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Unit V

The document discusses the characteristics and functions of instruction sets, detailing the elements of an instruction, types of operands, and various data types. It also covers pipelining in CPU instruction processing, including potential hazards such as structural, data, and control hazards, along with strategies to mitigate these issues. Additionally, it contrasts RISC and CISC architectures in terms of design decisions and instruction handling.

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607Aditi Patil
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10 views

Unit V

The document discusses the characteristics and functions of instruction sets, detailing the elements of an instruction, types of operands, and various data types. It also covers pipelining in CPU instruction processing, including potential hazards such as structural, data, and control hazards, along with strategies to mitigate these issues. Additionally, it contrasts RISC and CISC architectures in terms of design decisions and instruction handling.

Uploaded by

607Aditi Patil
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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UNIT V

Characteristics, Functions and


Pipelining of Instructions
Readings from – 12.3 and 12.4
What is an Instruction Set?

■ The complete collection of instructions


that are understood by a CPU
■ Machine Code
■ Binary
■ Usually represented by assembly codes
Elements of an Instruction
■ Operation code (Op code)
– Do this
■ Source Operand reference
– To this
■ Result Operand reference
– Put the answer here
■ Next Instruction Reference
– When you have done that, do this...
Instruction Cycle – State
Diagram

Instruction Types

■ Data processing
■ Data storage (main
memory) ■ Data movement
(I/O) ■ Program flow control
Types of
Operand ■ Addresses
■ Numbers
– Integer/floating point
■ Characters
– ASCII etc.
■ Logical Data
– Bits or flags
Pentium Data Types

■ 8 bit Byte
■ 16 bit word
■ 32 bit double word
■ 64 bit quad word
■ Addressing is by 8 bit unit
■ A 32 bit double word is read at addresses
divisible by 4
Specific Data Types
■ General - arbitrary binary contents
■ Integer - single binary value
■ Ordinal - unsigned integer
■ Unpacked BCD - One digit per byte ■
Packed BCD - 2 BCD digits per byte ■ Near
Pointer - 32 bit offset within segment ■ Bit
field
■ Byte String
■ Floating Point

Design Decisions (1)


■ Operation repertoire
– How many ops?
– What can they do?
– How complex are they?
■ Data types
■ Instruction formats
– Length of op code field
– Number of addresses
Design Decisions (2)

■ Registers
– Number of CPU registers available –
Which operations can be performed on
which registers?
■ Addressing modes
Pipelining
■ Fetch instruction
■ Decode instruction
■ Calculate operands (i.e. EAs)
■ Fetch operands
■ Execute instructions
■ Write result

■ Overlap these operations


Two Stage Instruction Pipeline
Timing Diagram –
Instruction Pipeline
The Effect of Branching
Six Stage
Instruction
Pipeline
Alternative Pipeline
Depiction

Pipeline Hazards
■ The situation that prevents the starting of
the next instruction in next cycle
■ They reduce the speedup of pipeline
Pipeline Hazards
■ Structural Hazard
– attempt to use the same resource by two or
more instructions
■ Data Hazard
– attempt to use data before it is ready
■ Control Hazard
– attempt to make branching decisions
before branch condition is evaluated
Structural Hazards – Memory

Time (clock cycles)


Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

I Ifetch DMem Reg


Load
n Reg
UL

s Ifetch DMem Reg


Instr 1
t r. Reg
UL

Ifetch DMem Reg


Instr 2
Or Instr 3
Reg
U

Ifetch DMem Reg


Reg
der UL

A
Structural Hazards – Memory

Time (clock cycles)


Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

I Ifetch DMem Reg


Load
n Reg
UL

s Ifetch DMem Reg


Instr 1
t r. Reg
UL

Ifetch DMem Reg


Instr 2
O Reg UL

r Stall Instr 3
der
Bubble Bubble Bubble Bubble
BubbleIfetch DMem Reg

Reg
UL

Types of Structural Hazards


■ Memory:
– Single port vs. multi-port memory
■ Floating point:
– Since many floating point instructions
require many cycles, it’s easy for them to
interfere with each other.
■ Starting up more of one type of instruction than
there are resources.

Data Hazards
■ RAW – Read after Write
Instr i ■ WAW – Write after Write
– j tries to write a source
before i writes it.
Instr j
– j tries to read a source before ■ WAR – Write after Read
i writes it. – j tries to write a source
before i reads it.
Control Hazards

■ When a branch is executed it may or it


may not change the PC
– If a branch is changing the PC to its target
address, than it is a taken branch
– If a branch doesn’t change the PC to its
target address, than it is a not taken
branch
Dealing with Branches

■ Multiple Streams
■ Prefetch Branch Target
■ Loop buffer
■ Branch prediction
■ Delayed branching
Multiple Streams

■ Have two pipelines


■ Prefetch each branch into a separate pipeline
■ Use appropriate pipeline

■ Leads to bus & register contention


■ Multiple branches lead to further pipelines
being needed
Prefetch Branch Target
■ Target of branch is prefetched in addition to
instructions following branch
■ Keep target until branch is executed
■ Used by IBM 360/91

Loop Buffer

■ Very fast memory


■ Maintained by fetch stage of pipeline ■
Check buffer before fetching from memory ■
Very good for small loops or jumps ■ c.f.
cache
■ Used by CRAY-1
Loop Buffer Diagram

Branch Prediction
■ Predict never taken
– Assume that jump will not happen
– Always fetch next instruction
■ Predict always taken
– Assume that jump will happen
– Always fetch target instruction
■ Predict by Opcode
– Some instructions are more likely to result in a jump than
others
– Can get up to 75% success
Branch Prediction

■ Taken/Not taken switch


– Based on previous history
– Good for loops
■ Delayed Branch
– Do not take jump until you have to
– Rearrange instructions
RISC vs. CISC

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