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16 views12 pages

Group 8 exp 7

Uploaded by

Miraj Hossain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AMERICAN INTERNATIONAL UNIVERSITY-

BANGLADESH
Faculty of Engineering

Lab Report

Experiment Title: Implementation of Asynchronous and synchronous counters


using flip-flops.

Date of Perform: 18 December 2024 Date of Submission: 08 January 2025


Course Title: Digital Logic and Circuits Laboratory
Course Code: Section: D
Semester: Fall 2024-25 Degree Program: BSc in EEE
Course Teacher: Bismoy Jahan

Declaration and Statement of Authorship:


1. I/we hold a copy of this Assignment/Case-Study, which can be produced if the original is lost/damaged.
2. This Assignment/Case-Study is my/our original work and no part of it has been copied from any other student’s work or from any other
source except where due acknowledgment is made.
3. No part of this Assignment/Case-Study has been written for me/us by any other person except where such collaboration has been authorized
by the concerned teacher and is clearly acknowledged in the assignment.
4. I/we have not previously submitted or currently submitting this work for any other course/unit.
5. This work may be reproduced, communicated, compared, and archived for the purpose of detecting plagiarism.
6. I/we give permission for a copy of my/our marked work to be retained by the Faculty Member for review by any internal/external
examiners.
7. I/we understand that Plagiarism is the presentation of the work, idea, or creation of another person as though it is your own. It is a form of cheating
and is a very serious academic offense that may lead to expulsion from the University. Plagiarized material can be drawn from, and presented in,
written, graphic and visual forms, including electronic data, and oral presentations. Plagiarism occurs when the origin of the source is not
appropriately cited.
8. I/we also understand that enabling plagiarism is the act of assisting or allowing another person to plagiarize or copy my/our work.

* Student(s) must complete all details except the faculty use part.
** Please submit all assignments to your course teacher or the office of the concerned teacher.

Group # 08

Sl No Name ID PROGRAM SIGNATURE


1 Miraj Hosain (Submitted By) 22-49183-3 BSc CSE
2 Md. Nafizur Nayem 22-49185-3 BSc CSE
3 Saikat Sarker Kabbo 22-48769-3 BSc CSE
4 Radia Noushin 22-46268-1 BSc CSE
5 Md Siddiqur Rahman Sadik 22-48358-3 BSc CSE
7
Experiment 7

Introduction:

Counters are arrangements of flip-flops designed to count clock pulses over a given interval. With NN
flip-flops, a counter can represent 2N2^N states, and if it cycles through KK states (K≤2NK \leq 2^N), it
is called a Mod-KK counter. Counters may provide individual outputs for each state or a single pulse for
every KK-th state. Counters are classified based on their clocking method like Asynchronous Counters:
The first flip-flop is triggered by the clock, and subsequent flip-flops are triggered by the output of the
preceding one. Synchronous Counters: All flip-flops are triggered simultaneously by the same clock
signal. The objective of this experiment is designing of the following counters using J-K Flip-Flops (IC
74LS76)
(a) n-bit Binary Asynchronous Counter
(b) n-bit Binary Synchronous Counter

Theory and Methodology:


Asynchronous counter
A three-bit asynchronous counter is shown in figure 9.1. The external clock is connected to
the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of
each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of
FF0. Because of the inherent propagation delay through a flip-flop, the transition of the input
clock pulse and a transition of the Q output of FF0 can never occur at the same time.
Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous
operation.
Figure 9.1 gives a three-bit counter capable of counting from 0 to 7. The clock inputs of the
three flip-flops are connected in cascade. The T input of each flip-flop is connected to a
constant 1, which means that the state of the flip-flop will be reversed (toggled) at each
positive edge of its clock. We are assuming that the purpose of this circuit is to count the
number of pulses that occur on the primary input called Clock. Thus, the clock input of the
first flip-flop is connected to the Clock line. The other two flip-flops have their clock inputs
driven by the Q output of the preceding flip-flop. Therefore, they toggle their state whenever
the preceding flip-flop changes its state from Q = 1toQ = 0, which results in a positive edge of
the Q signal.
Figure 9.1 shows a timing diagram for the counter. The value of Q0 toggles once each clock
cycle. The change takes place shortly after the positive edge of the Clock signal. The delay is
caused by the propagation delay through the flip-flop. Since the second flip-flop is clocked by
Q0, the value of Q1 changes shortly after the negative edge of the Q0 signal. This circuit is a
modulo-8 counter. Because it counts in the upward direction, we call it an up-counter.

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 1


7
Experiment 7

Figure 9.1: 3-bit Asynchronous counter and its timing diagram


In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).
The most important advantage of synchronous counters is that there is no cumulative time
delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency
for this counter will be significantly higher than for the corresponding ripple counter.

Table 9.1 shows the contents of a four-bit up-counter for eight consecutive clock cycles,
assuming that the count is initially 0. Observing the pattern of bits in each row of the table, it is
apparent that bit Q0 changes on each clock cycle. Bit Q1 changes only when Q0 = 1. Bit Q2
changes only when both Q1 and Q0 are equal to 1. In general, for an n-bit up-counter, a given
flip-flop changes its state only when all the preceding flip-flops are in the state Q = 1.

Figure 9.2a: A four-bit Synchronous Up Counter

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 2


Figure 9.2b: The timing diagram of a four-bit Synchronous Up Counter
There are 2 J-K Flip Flops in one IC. Here is the pin configuration of the IC 74LS76:

Figure 9.3: IC 74LS76

IC 7408 contains 4 AND gates in it. The pin configuration is shown below:

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 3


Fig 9.5: 3 bit Asynchronous Counter

Fig 9.6: 3 bit Synchronous Counter

Apparatus:

 IC 74LS76 (JK Flip Flop)


 IC 7408 (AND Gate)
 LED Lamps or Display
 Trainer Board
 Oscilloscope
 Connecting Wires

4
Simulation and Measurement:

3-bit Asynchronous Counter:

3-bit Synchronous Counter:

5
Questions answers:

4-bit Asynchronous Up-Counter :

6
7
4-bit Synchronous Up-Counter:

8
Bonus Mark Questions answers:

3-bit Asynchronous Down Counter:

9
Mod 10 Synchronous up counter:

10
Results and Discussion :

The key findings of this experiment reveal the differences in how synchronous and asynchronous counters
handle clock signals. In a synchronous counter, all flip-flops are triggered simultaneously by the same clock
signal. In contrast, in an asynchronous counter, each flip-flop is triggered by the output of the previous one.
The findings show that a 3-bit counter cycles through binary values from 000 to 111 (or 0 to 7 in decimal),
while a 4-bit counter cycles from 0000 to 1111 (or 0 to 15 in decimal). A Mod-10 counter, on the other
hand, counts from 0 to 9 in decimal. It was also observed that "Up Counters" start counting from 0, whereas
"Down Counters" count down to 0. The experiment's objective was successfully met by replacing a faulty
IC. The faulty IC caused the Hex display output to be unclear, but the correctness of the counter's operation
was verified using LEDs, ensuring the counting process was accurate.

Reference(s):
i) Thomas L. Floyd, “Digital Fundamentals”, Ninth Edition.
ii) AIUB Lab Manual.
iii) www.tutorialspoint.com

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