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3.error Detection and Correction

Error Detection and correction notes for Mumbai University B.Sc IT students

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0% found this document useful (0 votes)
6 views5 pages

3.error Detection and Correction

Error Detection and correction notes for Mumbai University B.Sc IT students

Uploaded by

uniqtainerr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ERROR DETECTION

Errors occurs when bits are transmitted over the computer


network, they are subject to get corrupted due to
interference and network problems. There are two types of
errors which are single-bit and burst error.
Single-bit error means that only 1 bit of a given data unit
(such as a byte, character, or packet) is changed from 1 to 0
or from 0 to 1. The term burst error means that 2 or more
bits in the data unit have changed from 1 to 0 or from 0 to 1.

In error detection, we are only looking to see if any error has


occurred. We are not even interested in the number of
corrupted bits or types of error. Errors in the received bits are
detected by means of Parity Check, Cyclic Redundancy Check
(CRC) and checksum. In all of these techniques, few extra bits
are sent along with actual data to confirm that bits received
at other end are same as they were sent. If, during the
comparison or counter-check, the receiver finds that the
received extra bits do not match the expected values then it
means that error has occurred.
1.Parity check:
One extra bit is sent along with the original bits to make
number of 1s either even in case of even parity, or odd in
case of odd parity, this extra bit is called as parity bit. There
are two common types of parity checks: even parity and odd
parity.
In even parity, the total number of 1s (including the parity
bit) in the frames must be even. If the frames already
contains an even number of 1s, the parity bit is set to 0. If the
frames has an odd number of 1s, the parity bit is set to 1, so
that the total number of 1s becomes even. In odd parity, the
total number of 1s (including the parity bit) in the frames
must be odd. If the frames already contain’s an odd number
of 1s, the parity bit is set to 0. If the frames have an even
number of 1s, the parity bit is set to 1, so that the total
number of 1s becomes odd. But when errors occur in more
than one bits then it’s very hard for the receiver to detect the
error.

2.Cyclic redundancy check:


This technique involves binary division of the data bits being
sent. To perform CRC error detection, the sender divides the
data frame by the divisor. The divisor is generated using
polynomials. The sender performs a polynomial division,
using the generator polynomial as the divisor and the entire
data frame as the dividend. This division results in a
remainder, which is typically the same length as the
generator polynomial/divisor. The calculated remainder (CRC)
is added to the end of the data frame. The entire frame,
including the original data and the CRC bits, is then
transmitted to the receiver. At the other end, the receiver
performs polynomial division operation on the received
frame using the same divisor. If the remainder contains all
zeros the data bits are accepted, otherwise it is considered as
error has occurred during transmission.

3.Checksum:
The process involves dividing the data into equally sized
segments and this segments are added one by one to get the
sum. This sum is complemented using 1s complement to get
the checksum. The entire frame, which now includes the data
and the checksum, is transmitted to the receiver. Upon
receiving the frame, the receiver performs the same
calculation i.e adding segments one by one (including the
added checksum). Then sum of these segments are
complemented using 1s complement and If the result is zero
then the data is accepted otherwise it is considered as error
has occurred during transmission and it is discarded.

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