American International University- Bangladesh (AIUB)

Faculty of Engineering (EEE)

Course Name: Digital Logic and Circuits Lab Course Code: EEE 2210

Semester: SUMMER 2023-2024 Sec: N

Experiment No 6
Experiment Name Construction of MOSFET Logic Gates

3 Submission 26/09/2024
Group No.
Date:

Sl. Student ID: Student Name:

1. 23-51706-2 MD. MAHABUBUR RAHAMAN SIAM
2. 23-51356-1 SHAHRIAR HASAN
3. 22-46052-1 MD. TANVIR RAHMAN MOLLA
4. 22-46948-1 MD. RIFAT CHOWDHURY FAMI
5. 23-51096-1 AHAMMED,MD SHAPARAN
6. 22-46277-1 H.M AHNAF ZAWAD

Submitted to:
MD. SHAORAN SAYEM
Title: Construction of MOSFET Logic Gates

Introduction:

We learned how Construction of MOSFET Logic Gates works. It signifies that the MOSFET can
be powered by the general-purpose logic IC's output voltage (5 V). The MOSFET cannot be
powered if the general-purpose logic IC does not have enough output current capabilities. With a
simple example of a Diode-Resistor Logic (DRL) AND gate and a Diode-Transistor Logic (DTL)
NAND gate, simple digital logic gates can be built by combining transistors and resistors.

Theory and Methodology:

MOSFET:
MAWS-feht is the correct pronunciation. Metal-oxide semiconductor field-effect transistor is an
acronym. These are utilized in a variety of situations when voltage conversion is required. To
create CPU, memory, and AGP voltages, for example, on your motherboard. Mosfets are typically
employed in groups of two. Three-phase power is indicated by the presence of six mosfets around
the CPU socket.

CMOS:
CMOS (complementary metal–oxide–semiconductor) is an integrated circuit fabrication method.
Microprocessors, microcontrollers, static RAM, and other digital logic circuits all utilise CMOS
technology. CMOS technology is also used for several analog circuits such as image sensors
(CMOS sensor), data converters, and highly integrated transceivers for many types of
communication. In 1963, Frank Wanlass received a patent on CMOS (US patent 3,356,858).
Complementary-symmetry metal–oxide–semiconductor is another name for CMOS (or
COSMOS). The term "complementary-symmetry" refers to how CMOS logic functions are often
implemented using complementary and symmetrical pairings of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs).

Figure1:CMOS inverter
High noise immunity and low static power consumption are two significant properties of CMOS
electronics. Because one of the pair's transistors is permanently off, the series combination only
drains substantial power while transitioning between on and off states. As a result, CMOS devices
produce less waste heat than other types of logic, such as transistor–transistor logic (TTL) or
NMOS logic, which typically have some standing current even when not in use. In addition,
CMOS enables for a high density of logic functions on a single chip. It was primarily for this
reason that CMOS became the most widely utilized technology for VLSI chips.
Here Some the advantages of CMOS over TTL are:
1. Because MOSFETs are voltage-controlled rather than current-controlled
semiconductors, CMOS gate inputs draw significantly less current than TTL inputs.
2. CMOS gates can operate over a far larger range of voltages than TTL gates:
typically, 3 to 15 volts against 4.75 to 5.25 volts for TTL gates.
3. CMOS transistors are smaller than NMOS transistors and have lower power
dissipation.
CMOS Logic:
CMOS transistors are smaller than NMOS transistors and have lower power dissipation. Thus,
they became the obvious choice of replacing NMOS transistors at the integrating circuit level
design in all applications. CMOS consists of one p-channel MOSFET or PMOS and one NMOS.
The two MOSFETs have been engineered to have similar properties. Thus, they are
complementary to each other. When OFF, their resistance is effectively infinite; when ON, their
channel resistance is quite low (around 200 Ω). Since the gate is essentially an open circuit it draws
no current and the output voltage will be equal to either ground or to the power supply voltage,
depending on which transistor is conducting.

NMOS Logic:

N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs (metal-oxide-

semiconductor field-effect transistors) to implement logic gates and other digital circuits. These
NMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion
layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals.
The n-channel is created by applying voltage to the third terminal, called the gate. Like other
MOSFETs, NMOS transistors have four modes of operation: cut-off (or subthreshold), triode,
saturation (sometimes called active), and velocity saturation.
Apparatus:
(1)10KΩresistor
(2) CMOS and Nmos
(3) Connecting wires.
(4)Trainer Board

Pre-Lab Homework:
1. Develop truth tables for a 2-input NAND and a 2-input NOR gate.
Ans: Truth table of 2 input NAND Gate
input1 input2 LED1
0 0 on(1)
0 1 on(1)
1 0 on(1)
1 1 off (0)
Truth table of 2-input NOR Gate
input1 input2 LED1
0 0 on(1)
0 1 off (0)
1 0 off (0)
1 1 off (0)
2. Explain with graphs the I-V characteristics of different types of MOSFET.
Ans:
MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form
an integral part of vast variety of electronic circuits.

3. Distinguish the similarities and differences between a MOSFET and FET.

Ans: differences between a MOSFET and
FET.

On the similarities side, MOSFETs and JFETs are both voltage-controlled transistors. A voltage at
the gate terminal of the transistor either turns the transistor on or off. They are unlike BJTs, which
are current-controlled.
Simulation and Measurement:

NMOS Inverter with Ohmic/ Resistive Load:

Figure 2: Simulation output of a NMOS Inverter with Ohmic/ Resistive Load

Truth table of NMOS inverter

input LED1
0 on(1)
1 off (0)

Figure 3: NMOS Inverter with Ohmic/ Resistive Load

NMOS Inverter with NMOS Enhancement Transistor load:

Figure 4: Simulation output of NMOS Inverter with NMOS Enhancement Transistor load
Truth table of NMOS inverter
input LED1
0 on(1)
1 off (0)

Figure 5: NMOS Inverter with NMOS Enhancement Transistor load

NMOS NAND Gate:

Figure 6 : Simulation output of the NMOS NAND Gate

Truth table of NMOS NAND Gate
input1 input2 LED1
0 0 on(1)
0 1 on(1)
1 0 on(1)
1 1 off (0)

Figure 7: NMOS NAND Gate

NMOS NOR Gate:

Figure 8: Simulation output of the NMOS NOR Gate

Truth table of NMOS NOR Gate

input1 input2 LED1
0 0 On (1)
0 1 off (0)
1 0 off (0)
1 1 off (0)

Figure 9: Simulation output of the NMOS NOR Gate

CMOS Inverter:

Figure 10: Simulation output of the CMOS Inverter

Truth table of CMOS inverter

input LED1
0 On (1)
1 off (0)

Figure 11: CMOS Inverter

CMOS NAND Gate:

Figure 12: Simulation output of the CMOS NAND Gate

Truth table of CMOS NAND Gate

input1 input2 LED1
0 0 On (1)
0 1 On (1)
1 0 On (1)
1 1 off (0)

Figure 13: CMOS NAND Gate

CMOS NOR Gate:

Figure 14: Simulation output of the CMOS NOR Gate

Truth table of NMOS NOR Gate

input1 input2 LED1
0 0 On (1)
0 1 off (0)
1 0 off (0)
1 1 off (0)

Figure 14: CMOS NOR Gate

Questions with answers for report writing:

Qs1. For, each of the above set-ups, describe in words what the data means. Did your results match
the expected ideal outputs? If not, explain why?

1. Ans: For inverter setup the output truth table interprets that if inputs HIGH, output will be
low and if input low, output will be high.
The NAND gate has an output that is normally at logic high and only goes to logic low
when all of its inputs are at logic high.
For NOR Gate, A HIGH output (1) results if both the inputs to the gate are LOW (0); if
one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation
of the OR operator.
Yes, the truth table clearly shows us that the results matched with the expected ideal
outputs.

Qs2. Implement logic function Vout = A+ BC+ DEF using: (a) NMOS (b) CMOS
2. Ans:
Discussion and conclusion:
The main objectives of this experiment were to be familiar with NMOS and CMOS logic to know
the how to design the inverter, NAND and NOR gate by NMOS and CMOS Mosfet. In the
hardware implementation part, we faced difficulties to implement the CMOS NOR Gate that’s
why it took a much extra time. Anyway, the overall outcome was excellent and matched the truth
table value. In the simulation part, we have used NI Multisim version -14.2. we successfully
assembled all of the components on the Multisim bread board without any faults. Successfully
we have confirmed to build the connection between the circuit wires without any problem. All
the simulation circuit were run and the output were matched with the theoretical knowledge. No
error was found in the output values. So, we can say that our hardware implementation was
verified by simulations result and truth table.

Reference:

1. Thomas L. Floyd, Digital Fundamentals, 9th Edition, 2006, Prentice Hall.

2. Link: http://www.techpowerup.com/articles/overclocking/voltmods/21
3. https://www.google.com/search?q=Construction+of+MOSFET+Logic+Gates+(P
art+I)&rlz=1C1GCEA_enBD903BD903&oq=Construction+of+MOSFET+Logic
+Gates+(Part+I)&aqs=chrome.0.69i59.1311j0j7&sourceid=chrome&ie=UTF-8
4. https://pages.jh.edu/aandreo1/216/Archives/2014/Handouts/POP_Ch3-4.pdf

5. https://www.google.com/search?q=cmosfet&rlz=1C1GCEA_enBD903BD903&o
q=cmosfet+&aqs=chrome..69i57j0i10i433j0i10i131i433j0i10l7.2865j0j7&source
id=chrome&ie=UTF-8