Lecture 2: Microprocessor Architecture

Architecture of 8086 Microprocessor: The 8086 microprocessor is an 8-bit/16-bit

microprocessor designed by Intel in the late 1970s. It is the first member of the x86 family of
microprocessors, which includes many popular CPUs used in personal computers.

The architecture of the 8086 microprocessor is based on a complex instruction set computer
(CISC) architecture, which means that it supports a wide range of instructions, many of which can
perform multiple operations in a single instruction. The 8086 microprocessor has a 20-bit address
bus, which can address up to 1 MB of memory, and a 16-bit data bus, which can transfer data
between the microprocessor and memory or I/O devices.

Bus Interface Unit (BIU): The bus interface unit interfaces 8086 with the external world. It
handles all the data transfer functions. The BIU performs read and write operations on data in the
memory and on the external devices connected to the ports of the microprocessor, and it also sends
out addresses. That means all external operations are performed by BIU.

Instruction Queue: The instruction queue holds the six bytes of instruction fetched from the code
memory by the BIU that are to be executed by the EU. The instruction queue contains registers
that work on FIFO (first-in-first-out) principle. Since EU and BIU are independent, whenever the
execution unit starts decoding and executing fetched instructions, the BIU fetches additional
instructions to the queue from the code memory for execution.

Again, when the execution unit starts executing fetched instructions in the queue, again the BIU
will add instructions to the queue at the same time. Since the fetching of instructions from the
memory and execution of instructions in the queue are done as the same time, both the operations
will overlap. This is called Pipelining which speeds up the execution by reducing CPU waiting
state time.
Segment Registers: The 8086 microprocessor has 1 Megabyte (220 bits = 1 Mb) of segmentized
memory divided into 16 logical segments. The maximum size of each segment is 64kb so that any
location within the segment can be accessed with a 16-bit logical address. At any given time, 8086
works with only four 64kb segments which are independent and separately addressable units. Each
segment is associated with segment registers that are 16 bits wide. The four registers related to
four segments are,

• Data Segment Register (DS) – It is used to point to the base address of the data register.
• Code Segment Register (CS) – It is used to point to the base address of the code register.
• Extra Segment Register (ES) – It holds the base address of the extra memory segment.
• Stack Segment Register (SS) – It holds the base address of the stack memory segment.

Instruction Pointer (IP): The instruction pointer is similar to the program counter in 8085 CPU.
The IP is updated by BIU so that it contains the offset (distance in byte from base address) of the
next instruction. That is IP points to the next instruction to be fetched from the code segment.

Execution Unit (EU): The execution unit tells the bus interface unit where to fetch instruction or
data from. It decodes the instruction and performs arithmetic and logical operations using the ALU.
This execution unit provides effective addresses of memory locations. Then, this address is added
to the base address provided by segment registers in the bus interface unit.

Central Processing Unit (CPU): A Central Processing Unit (CPU) is the primary component of
a computer that performs most of the processing inside a computer. It’s often referred to as the
‘brain’ of the computer, as it carries out instructions from a computer program by performing the
basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

• Control Unit (CU): Manages and coordinates all operations in the processor.
• Arithmetic Logic Unit (ALU): Depending upon the given instructions the ALU performs
operations like addition, subtraction, AND, OR, NOT, shifting of binary numbers, etc, on the
data.

General-Purpose Registers

These registers are used for general arithmetic, logic operations, data transfer, and addressing.

1. AX (Accumulator Register):
o Used for arithmetic operations, logic operations, and data transfer.
o Divided into AH (high byte) and AL (low byte).
2. BX (Base Register):
o Primarily used as a base pointer for memory access.
o Divided into BH (high byte) and BL (low byte).
3. CX (Count Register):
o Used as a counter in loop operations and for string operations.
o Divided into CH (high byte) and CL (low byte).
4. DX (Data Register):
o Used in I/O operations and for multiplication/division operations.
 o Divided into DH (high byte) and DL (low byte).

Segment Registers

These registers are used to address different segments in memory. Each segment can be up to
64KB.

1. CS (Code Segment):
o Points to the segment containing the executable code.
o Works with the IP (Instruction Pointer) to fetch instructions.
2. DS (Data Segment):
o Points to the segment containing data.
o Used to access variables and data structures.
3. SS (Stack Segment):
o Points to the segment containing the stack.
o Works with the SP (Stack Pointer) to manage function calls and local variables.
4. ES (Extra Segment):
o An additional segment register for data storage.
o Used in string operations to access additional data.

Pointer and Index Registers

These registers are used for memory addressing and operations on arrays and strings.

1. SP (Stack Pointer):
o Points to the top of the stack in the stack segment.
o Used for stack operations like PUSH and POP.
2. BP (Base Pointer):
o Primarily used to access parameters passed via the stack.
o Can also be used for general-purpose addressing.
3. SI (Source Index):
o Used as a source pointer in string operations.
o Can also be used for indexed addressing.
4. DI (Destination Index):
o Used as a destination pointer in string operations.
o Can also be used for indexed addressing.

Instruction Pointer and Flag Register

1. IP (Instruction Pointer):
o Points to the next instruction to be executed.
o Works with the CS register to fetch instructions from memory.
2. Flag Register:
o Contains status flags and control flags that indicate the status of the processor and
the outcome of operations.
 o Includes flags like Carry Flag (CF), Zero Flag (ZF), Sign Flag (SF), Overflow
Flag (OF), and others.

Bus in 8086 Microprocessor

A bus in the context of microprocessors is a communication system that transfers data between
different components of the computer, such as the CPU, memory, and peripheral devices. In the
8086 microprocessors, there are three main types of buses: the address bus, the data bus, and the
control bus.

1. Address Bus

• Function:
o The address bus is used to carry the address of the memory location or I/O port that the
CPU wants to read from or write to.
• Characteristics:
o The 8086 has a 20-bit address bus, allowing it to address up to 2^20 (1,048,576) memory
locations, equivalent to 1MB of memory.
o The address bus is unidirectional, meaning it only carries addresses from the CPU to the
memory or I/O devices.

2. Data Bus

• Function:
o The data bus is used to transfer actual data between the CPU, memory, and I/O devices.
• Characteristics:
o The 8086 has a 16-bit data bus, meaning it can transfer 16 bits of data at a time.
o The data bus is bidirectional, allowing data to flow both to and from the CPU.

3. Control Bus

• Function:
o The control bus carries control signals from the CPU to other components to manage and
coordinate various operations.
• Characteristics:
o The control bus includes various lines for specific control signals, such as Read/Write
signals, Interrupt signals, Clock signals, and more.
o These signals ensure that the correct operation is performed at the correct time, enabling
synchronization between the CPU and other components.

Operand: An operand is a value or memory location upon which an instruction operates. In the
context of the 8086 microprocessor, operands can be:

1. Immediate Operand:
o A constant value directly specified in the instruction.
o Example: MOV AX, 5 (here, 5 is the immediate operand).
 2. Register Operand:
o A register that contains the data.
o Example: MOV BX, AX (here, AX is the register operand).
3. Memory Operand:
o A memory location where data is stored.
o Example: MOV AX, [1234H] (here, [1234H] is the memory operand).

Flag: Flags are special indicators that represent the status of the processor or the outcome of
certain operations. The 8086 microprocessor has a set of flags that are stored in a special register
called the Flag Register. These flags are used to control operations and to indicate the status of
the CPU. The flag register is divided into status flags and control flags.

1. Status Flags:
o Carry Flag (CF): Indicates if there was a carry out or borrow into the most
significant bit during arithmetic operations.
▪ Set if an arithmetic operation generates a carry or borrow; otherwise,
cleared.
o Parity Flag (PF): Indicates if the number of set bits (1s) in the result is even.
▪ Set if the number of set bits is even; otherwise, cleared.
o Auxiliary Carry Flag (AF): Indicates if there was a carry or borrow from the
lower nibble (4 bits) to the higher nibble in a byte during arithmetic operations.
▪ Set if there is a carry/borrow; otherwise, cleared.
o Zero Flag (ZF): Indicates if the result of an operation is zero.
▪ Set if the result is zero; otherwise, cleared.
o Sign Flag (SF): Indicates the sign of the result of an operation.
▪ Set if the result is negative (most significant bit is 1); otherwise, cleared.
o Overflow Flag (OF): Indicates if there was an arithmetic overflow.
▪ Set if there is an overflow; otherwise, cleared.
2. Control Flags:
o Direction Flag (DF): Controls the direction of string operations.
▪ Set for decrementing the index registers; cleared for incrementing.
o Interrupt Flag (IF): Controls the enabling or disabling of interrupts.
▪ Set to enable interrupts; cleared to disable interrupts.
o Trap Flag (TF): Enables single-step execution for debugging.
▪ Set to enable single-step mode; cleared to disable.

Instruction Cycle of 8086 Microprocessor

The instruction cycle of the 8086 microprocessor is the process by which the CPU fetches,
decodes, and executes an instruction. This cycle can be broken down into three main stages:

1. Fetch Cycle:
o Objective: Retrieve the next instruction from memory.
o Steps:
 1. Fetch Instruction: The CPU places the address of the next instruction
(pointed to by the Instruction Pointer, IP) on the address bus.
2. Memory Read: The control bus signals a memory read operation.
3. Instruction Queue: The fetched instruction is placed into the instruction
queue (a prefetch queue), which helps speed up processing by overlapping
instruction fetch with execution.
2. Decode Cycle:
o Objective: Interpret the fetched instruction.
o Steps:
1. Instruction Decode: The control unit decodes the instruction in the
instruction decoder.
2. Identify Operands: Determine the required operands and addressing
modes.
3. Prepare for Execution: The necessary control signals are generated to
execute the instruction.
3. Execute Cycle:
o Objective: Perform the operation specified by the instruction.
o Steps:
1. ALU Operations: If the instruction involves arithmetic or logic
operations, the Arithmetic Logic Unit (ALU) performs these operations.
2. Memory Access: If the instruction requires reading from or writing to
memory, the address and data buses are used to transfer data.
3. I/O Operations: If the instruction involves I/O operations, the appropriate
I/O ports are accessed.
4. Update Registers: The results are stored in the specified registers or
memory locations.
5. Set Flags: Update the flag register based on the result of the operation.