Birla Institute of Technology and Science Pilani, Dubai Campus

Dubai International Academic City

CS/ECE/EEE/INSTR F215 DIGITAL ELECTRONICS

LABORATORY MANUAL
I Semester 2023-24

CYCLE I

Name:……………………..

ID No:……………….…….
Name & ID:…………………………………… Date: ……………………….

DIGITAL ELECTRONICS LABORATORY

List of Experiments

Cycle I

Exp. No Name of the Experiment

1 Familiarization with Hardware Lab Equipment

2 Familiarization with Software Tool and Environment

3 Implementation of Boolean Function

4 Adders and Subtractors

5 Decoders and Comparators

Appendix-I: Steps for doing Verilog simulation in Cadence

Name & ID:…………………………………… Date: ……………………….

EXPERIMENT-1
Familiarization of Hardware setup
Run 1: Understanding the trainer board (20 mins)
The power supply is a source of regulated DC power. It is used to power different ICs. It
is also used to provide logic level inputs to different digital circuits. Below are the tasks to
perform:
(a) Connection of inputs to output LEDs
(b) Manual clock to LEDs

Q: Why is it called multi-output supply?

A:

Q: Which amongst the outputs of the power supply would you choose for digital IC
based experiments? Why?
A:

Run 2: Understanding the CRO (20 Mins)

The CRO is the most useful and versatile electronic test equipment. It lets us see voltage
in a circuit as a function of time, triggering on a particular point of the waveform so that a
stationary display result. Below are the tasks to perform:
(a) Connect and see the test square waveform from CRO itself
(b) Connect and see the square wave from trainer board to CRO (vary frequency)

Q: Draw the test square waveform generate by CRO itself. What is the voltage and
frequency of this waveform?
A:
Name & ID:…………………………………… Date: ……………………….

Q: Generate a square wave of 5 V, 1 KHz TTL O/P from onboard function generator to
CRO. Calculate its time period and draw the waveform? Draw another wave form with 2
KHz frequency.
A:

Run 3: Understanding the IC data sheet of NOT Gate (20 mins)

Refer Not Gate IC Data Sheet
(a) Pin Diagram
(b) Voltage nominal +/- tolerance
(c) Logic low range
(d) Logic high range
(e) Gate delay
Name & ID:…………………………………… Date: ……………………….

Q: Write the IC no. of NOT Gate? Draw its Pin Diagram?

A:

Q: How much voltage is required to operate an IC and write the voltage tolerance?
A:

Q: Why do we connect VCC and Ground?

A:

Q: This IC is belonging to which family and What is the Logical low and high range of it?
A:

Run 4: Propagation delay of gates using NOT Gate (40 mins)

(a) Define propagation delay.
(b) Connect the six not gates of IC 7404 in cascade as shown below.
(c) Apply clock pulses to the input and observe it on X channel (CH1) of CRO.
(d) Observe the output of the last gate on the Y channel (CH2).
(e) Note down tPHL and tPLH.

Q: Define Propagation delay time?

A:
Name & ID:…………………………………… Date: ……………………….

Q: Draw the I/P and O/P wave form.

A:
Input and output:

Q: Note down the tPHL and tPLH and calculate the propagation delay of each gate?
A:
Input clock frequency:
tPHL: tPLH:
Average propagation delay (P.D) = (tPHL + tPLH)/2 =
Delay per gate = P.D/6

Assignment:
1. How do you test if a CRO is working or not?
Ans:

2. What is the meaning of the following IC packages type –SOIC and PDIP?
Ans:
Name & ID:…………………………………… Date: ……………………….

Test yourself
1. What is a sweep signal in a CRO and how is it relevant in triggering?
2. Where is a component tester located in the CRO and what are its applications?
3. What is significance of the ac/dc switch in the CRO?
4. What is the use of an external trigger in a pulse generator?
5. What is the cable that you use for connecting the CRO to signal point called?
6. What is the connector between the cable and the CRO called?
Name & ID:…………………………………… Date: ……………………….

NOT Gate IC Datasheet (IC 7404)

Name & ID:…………………………………… Date: ……………………….
Name & ID:…………………………………… Date: ……………………….

EXPERIMENT-2
Familiarization of software tool and environment

Run 1: Login to the Linux account and invoke cadence virtuoso (15 mins)
Aim: This section aims to provide detailed guide about how to invoke ‘Cadence Virtuoso’ from the
PCs in the Lab.
Step 1 Turn on the desktop machine and boot it into CentOS 7 by selecting the option as shown
in figure 1.1

Figure 1.1: First screen when computer boots up.

Step 2 Click on “Not Listed?” (Marked in red box at the bottom) as shown in figure 1.2 below to
enter login window.

Figure 1.2: Click on “Not Listed?” to enter your username and password.
Name & ID:…………………………………… Date: ……………………….

Step 3 Enter your username (figure 1.3a) and password (figure 1.3b). For username and
password please check your email or contact lab staff or faculty.

Figure 1.3a: Enter username and click next Figure 1.3b: Enter password and click Sign In.

Step 4 Then open a terminal by hovering your cursor towards top left, Click on Application,
Select System Tools then Terminal.

Figure 1.4: To open the terminal

Step 5 To start the Cadence Virtuoso, in the Terminal type virtuoso & (see Figure 1.5a) and
press enter.

Figure 1.5a: Type virtuoso & to launch the cadence software

Name & ID:…………………………………… Date: ……………………….

After typing the above command, a window will pop up after few seconds as shown below (figure
1.5b), maximize the window to full screen. Note you must see the statement like the one
highlighted in figure 1.5b.
“Virtuoso Framework License (111) was checked out successfully. Total checkout time was
0.02s.”

Figure 1.5b: Virtuoso pop up window with license successfully checked out message.

Important notes:
1. After you finish the simulations, always close the Virtuoso and all other cadence windows
properly.
2. Also close the terminal from where you typed virtuoso &.
3. After that always logout from your account properly by clicking your username and then
logout in top-right corner of the main screen.

NEVER SHUTDOWN THE PC ONLY LOGOUT FROM TOP RIGHT CORNER

Now you are ready to use Cadence Software.
Name & ID:…………………………………… Date: ……………………….

Run 2: Define logic gates and see the propagation delay (45 mins)

(a) Write Verilog code and testbench for NOT gate using gate level modeling and see the
waveforms.

Verilog HDL supports basic logic gates as predefined primitives. These primitives can be used to
simulate circuits. The various primitives are AND, NAND, NOR, OR, NOT, XOR and XNOR. At
the gate level of modeling, it can be observed that there is a one-one correspondence between
logic diagram and Verilog description.

Please refer the procedure Appendix-I for the first time to understand the software flow. Later
same procedure is to be followed.

//Verilog HDL for "DD_Lab", "NOTgate" "functional"

//Gate level modeling code for NOT gate
module NOTgate (z,a); //module is like a function in C programming here function name is NOTgate
//and in bracket inputs and output ports of function are defined.
input a; // 'a' is defined as one bit input Data type
output z; // 'b' is defined as one bit output Data type
not #1 (z,a); // not is inbuilt command for NOT gate, '#1' is one unit delay.
endmodule // endmodule is like closing the function

// Testbench for NOT gate (this is behavioral modeling)

module testbench_NOT;// Module of testbench usually does not have any input or output
reg p; // Data type 'reg' can store value and for input we need to apply some stimulus
wire q; // Data type 'wire' is required to connect two elements
initial // 'initial' statement only execute once
begin
#000 p=0; // at time 000 p is assigned value '0'
#100 p=1; // at time 100 p is assigned value '1'
#100 p=0; // at time 200 p is assigned value '0'
#100 p=1; // at time 300 p is assigned value '1'
#100 $stop; // to stop simulation after 400-time units
end // closing of initial begin
NOTgate U1(q,p); // Here we are connecting NOTgate module with testbench_NOT.
// 'NOTgate' is module name, 'U1' is instance name (defined by us).
// 'q' and 'p' are port association, note that proper sequence is to be followed.
endmodule
 Name & ID:…………………………………… Date: ……………………….

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
A:

(b) Use the above Verilog code of NOT gate as a block and create a series of six NOT gates
using structural modeling and see the output with and without delay by applying square
wave at the input of first NOT gate.

// Code for not gate chain

module not_chain (o1,o7);

output o7;
input o1;
wire o2,o3,o4,o5,o6;
notgate_gatelevel G1(o2,o1);
notgate_gatelevel G2(o3,o2);
notgate_gatelevel G3(o4,o3);
notgate_gatelevel G4(o5,o4);
notgate_gatelevel G5(o6,o5);
notgate_gatelevel G6(o7,o6);
endmodule

// Where module notgate_gatelevel is already defined in part (a) as below

module notgate_gatelevel (z,a );
input a;
output z;
not #1 (z,a);
endmodule
Name & ID:…………………………………… Date: ……………………….

// testbench for not gate chain

module not_chain_tb;
reg o1;
wire o7;
not_chain NC1(o1, o7);
initial begin
#10 o1 = 0;
#10 o1 = 1;
#10 $stop;
end
endmodule

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
A:

Run 3: Define logic gates using behavioral modeling on www.edaplayground.com (40

mins)

(a) Verilog code and testbench for 2 input OR gate behavioral modeling.
Name & ID:…………………………………… Date: ……………………….

//Testbench for 2 input OR gate for (a) //Behavioral modeling code for 2 input OR gate

module testbench_ORgate; module OR_2_behavioral (output reg Z, input E,F);

reg p,q; always @ (E or F) begin
wire r; if (E==0 & F==0) begin
initial #10 Z = 0;
begin end
$dumpfile ("dump.vcd"); else
$dumpvars (1, testbench_ORgate); #10 Z = 1;
#000 p = 0; q = 0; end
#100 p = 0; q = 1; endmodule
#100 p = 1; q = 0;
#100 p = 1; q = 1;
#100 $stop;
end
OR_2_behavioral U3(r,p,q);
endmodule

Q: Paste the Image of your EPWave window where you get the waveforms for the above code.
A:

Assignment: All assignments are to be submitted strictly before start of next lab session through
online only. Late assignments will not be entertained and will be awarded ‘0’ marks.
Copy-paste or type the unique URL of your assignment solution from website
www.edaplayground.com for assignment questions. Please note that do not copy someone else’s
link as any kind of unfair means will result in academic misconduct and will be treated accordingly.
All links for each user and each code are unique.
Name & ID:…………………………………… Date: ……………………….

(a) Write the single Verilog code and testbench for 3-input gates (NAND, EXOR) using gate
level modeling.

Ans: Link1:
: Paste the Image of your EPWave window

(b) Verilog code and testbench for finding 1’s complement of 8-bit binary number.

Ans: Link2:
: Paste the Image of your EPWave window

(c) Write the Verilog code and testbench for NOT gate using data flow modeling and see the
waveforms.
(Data flow modeling uses the continuous assignment statement assign. It also makes use
of operators, which act on operands to produce desired results.)

Ans: Link3:
: Paste the Image of your EPWave window

(a) Write the Verilog code and testbench for NOT gate using behavioral modeling and see the
waveforms.
(Behavioral modeling is used to model digital circuits at a functional and algorithmic level.
These descriptions support the use of if-else, case, loops and use the always construct to
implement the same. This modeling style is used for both combinational and sequential
circuits.)
Note: The statements inside an always block execute sequentially. Similarly, one can use
if-else and case constructs.

Ans: Link4:
: Paste the Image of your EPWave window

Self-Practice and self-evaluation

(a) Write the single Verilog code and testbench for 2-input gates (AND, OR, NAND, NOR,
EXOR, EXNOR) using data flow modeling.
(b) The Verilog description of a circuit is given below. Draw the equivalent circuit and identify
its functionality.
module circuit(f,a,b,c);
input a,b,c;
output f;
wire ab,bc,ca;
or or1 (ab,a,b);
or or2 (ac,a,c);
or or3 (bc,b,c);
and(f,ab,bc,ca);
endmodule
(c) Verilog code and testbench for finding 2’s complement of 8-bit binary number.
(d) Write the Verilog code and testbench for 3-input gates (AND, OR) using structural modeling
use two 2-input gates.
Name & ID:…………………………………… Date: ……………………….

Experiment No. 3
Implementation of Boolean Function
Hardware runs

IC pin diagrams
Name & ID:…………………………………… Date: ……………………….

Run 1: AND-OR implementation (30 mins)

Diagram

Truth Table

A B C P Q R X

0 0 0
0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

For the circuit diagram fill in the following details

No. of AND gates used: No. of AND gate IC used:
No. of NOT gates used: No. of NOT gate IC used:
No. of OR gates used: No. of OR gate IC used:
Total No. of ICs used:

Now wire up the above circuit using the required Nos. of ICs. (The pin out of the ICs is given
above). Feed inputs using toggle switches and observe the output on LEDs. Tabulate your
observations for all input combination.
Name & ID:…………………………………… Date: ……………………….

Run 2: Parity generator (20 Mins)

XOR gates are one of the most versatile gates and find a variety of applications. They are widely
used in comparators, parity checking and certain code conversions. We will implement circuits for
parity generation using XOR gates.
Construct a circuit using 2-input XOR gates to generate an odd parity bit and an even parity bit
depending upon a control bit L. If L=0 the circuit generates odd parity bit and if L=1 the circuit
generates even parity bit. Draw the circuit diagram below by using XOR gates.
Try and use wires of different colors to signal different functionalities.

Diagram

Q: How many XOR gates are used?

A:
Q: How many 7486 IC are used?
A:
Q: Can the circuit be implemented using only one 7486 IC?
A:

Q: Take few 6-input combinations and complete the below table.

Truth Table
A B C D L P

0 1 0 1 0

0 1 0 1 1
0 1 1 1 0

0 1 1 1 1

1 1 1 1 0

1 1 1 1 1
Name & ID:…………………………………… Date: ……………………….

Software runs
Run 3: Circuit implementation (20 Mins)
Verilog HDL supports basic logic gates as predefined primitives. These primitives can be used to
simulate circuits. The various primitives are AND, NAND, NOR, OR, NOT, XOR and XNOR. At
the gate level of modeling, it can be observed that there is a one-one correspondence between
logic diagram and Verilog description.
Implement the below circuit using Gate level modeling, write the code as well as its testbench.

Figure 3.1: Circuit for Gate level Verilog modeling

// Verilog code for the above circuit
module circuit(X, A,B,C); //module name followed by list of ports
input A,B,C; //input port declarations, by default wire
output X; //output port declarations, by default wire
wire P, Q, R; //wire declaration for intermediary wires
and a1(P,A,B); //instance name is not compulsory. output of gate is always mentioned first
not (Q,B);
and (R,Q,C);
or (X,R,P); //2 input OR gate
endmodule

// testbench for the above code

module stimulus;
reg A,B,C; //reg is data type that makes variable retain value
wire X; //same variable names can be used
initial //statements within initial block have sequential execution
begin
A=0; B=0; C=0;
#10 A=0; B=0; C=1; //#10 is 10ns delay
#10 A=0; B=1; C=0;
#10 A=0; B=1; C=1;
#10 A=1; B=0; C=0;
#10 A=1; B=0; C=1;
#10 A=1; B=1; C=0;
#10 A=1; B=1; C=1;
#10 $stop;
end
circuit mycircuit(X,A,B,C); //instantiating the design block taking care of port connection rules
endmodule
Name & ID:…………………………………… Date: ……………………….

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
A:

Run 4: Error detection and error correction codes (35 Mins)

1. Verilog code and testbench for generating even parity Hamming code for 4-bit data.
(Hint: P0 = D2^D1^D0, P1 = D3^D1^D0, P2 = D3^D2^D0)
A: Verilog Code-
Name & ID:…………………………………… Date: ……………………….

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
A:

Assignment All assignments are to be submitted strictly before start of next lab session through
online only. Late assignments will not be entertained and will be awarded ‘0’ marks.

Copy-paste or type the unique URL of your assignment solution from website
www.edaplayground.com for assignment questions. Please note that do not copy
someone else’s link as any kind of unfair means will result in academic misconduct and
will be treated accordingly. All links for each user and each code are unique.

1. Implement a NOT gate using one 2-input NAND gate only. Write its Verilog code also.
Ans: Link1:
: Paste the Image of your EPWave window

2. Verilog code and testbench using data flow modeling for Y = ABC + AB +AC.
Ans: Link2:
: Paste the Image of your EPWave window

3. Verilog code and testbench for detecting even parity error in 4 bit (3+1) binary number.

Ans: Link3:
: Paste the Image of your EPWave window

4. Write Verilog code and testbench for generating even parity bit for 4-bit binary number.
(Hint: you can use the structure of run-2 of this experiment also or y = A^B^C^D).

Ans: Link4:
: Paste the Image of your EPWave window
Name & ID:…………………………………… Date: ……………………….

Self-Practice and self-evaluation

1. Implement a NOT gate using one 2-input NOR gates only.
2. Name the universal gates. Why are they called ‘Universal’?
3. Why multiple variable XOR operation is called odd function? Write the canonical SOP form
of four variable odd function. Which operation would give rise to even function?
4. Prove that any function can be implemented using only XOR and AND gates.
5. Write one advantage and one disadvantage of gray code over binary code.
6. Verilog code and testbench for generating odd parity bit for 4-bit binary number.
7. Verilog code and testbench for detecting odd parity bit for 4 bit (3+1) binary number.
8. Verilog code and testbench for detecting error and its position in 7-bit input code.
9. Verilog code and testbench for 2 input OR gate using 2-input NAND gates using
structural modeling.
10. Verilog code and testbench for 2 input AND gate using 2-input NAND gates using
structural modeling.
11. Verilog code and testbench for 2 input XOR gate using 2-input NAND gates using
structural modeling.
12. Verilog code and testbench using structural modeling for Y = ABC + AB +AC.
13. Verilog code and testbench using data flow modeling for Y = (A+B+C).(A+B).(A+C)
Name & ID:…………………………………… Date: ……………………….

Appendix-I
Steps for doing Verilog simulation in Cadence
AIM: This section of the manual aims to describe detailed steps for performing Verilog simulations.
After opening the virtuoso as explained in section 1 follow the below steps. Skip steps 1-4 if you are
opening existing Verilog code for simulations second time.
Step 1: Go to File-> New-> Library to create new library (Figure 2.1). Here library is like a folder in
windows or directory in unix to save your various design files which you create over time.
Note that you need not to create new library every time, use previously created library from next time.

Figure 2.1: To create the library for first time.

Step 2 A new window will popup as shown below in Figure 2.2. Enter the library name as per your
convenience in the Library field on left side against Name, here I entered “DD_Lab”, you can write
anything. Note that library name should start with an alphabet. Select the fourth bullet “Do not need process
information” in Technology File field on right. Then click OK.

Figure 2.2: Enter library name and select the technology file field.
Name & ID:…………………………………… Date: ……………………….

Step 3 Go to File-> New-> Cellview to create new cell (figure 2.3). Here cellview is a new design you want
to create (like a file inside a folder).

Figure 2.3: To create new cellview

Step 4 A new window will pop up (Figure 2.4a).

• Select the library from drop down menu against Library field you created in step 2 or previously.
• Enter the design name against Cell field as per your choice (here for example “NOTgate” is
entered).
• No need to write anything in View field.
• Select the “Verilog” option from drop down menu against Type field.
• Select the “Text Editor” option against Open with field.
Then click OK

Figure 2.4a: Select the options in cellview window

Name & ID:…………………………………… Date: ……………………….

• Always select Session, whenever a new popup window opens of Next License (like Figure 2.4b)

Figure 2.4b: Select the Session in Next License window

Next time when you want to open the existing design, then you can skip steps 1-4 and directly go to
File-> Open then in the pop up window (like Figure 2.4c) select the library name (as here it was
DD_Lab) and cell from right side list (as here it is NOTgate, there could be many over time).

Figure 2.4c: For opening the existing design

Step 5 Another window will pop up after step 5 for writing the Verilog code (Figure 2.5)

Figure 2.5: Window for writing the Verilog code and testbench looks like this.
Name & ID:…………………………………… Date: ……………………….

Step 6 Next you can type Verilog code and testbench here in any of the modeling style you want (gate level
modeling, dataflow, behavioral modeling or structural modeling) click the save and check button on top
panel (Figure 2.6). Below is the sample Verilog code and testbench of NOT gate in gate level modeling
(for reference).
//Verilog HDL for "DD_Lab", "NOTgate" "functional"
//Gate level modeling code for NOT gate
module NOTgate (z,a); //module is like a function in C programming here function name is NOTgate
//and in bracket inputs and output ports of function are defined.
input a; // 'a' is defined as one bit input Data type
output z; // 'b' is defined as one bit output Data type
not #1 (z,a); // not is inbuilt command for NOT gate, '#1' is one unit delay.
endmodule // endmodule is like closing the function

// Testbench for NOT gate (this is behavioral modeling)

module testbench_NOT;// Module of testbench usually does not have any input or output
reg p; // Data type 'reg' can store value and for input we need to apply some stimulus
wire q; // Data type 'wire' is required to connect two elements
initial // 'initial' statement only execute once
begin
#000 p=0; // at time 000 p is assigned value '0'
#100 p=1; // at time 100 p is assigned value '1'
#100 p=0; // at time 200 p is assigned value '0'
#100 p=1; // at time 300 p is assigned value '1'
#100 $stop; // to stop simulation after 400-time units
end // closing of initial begin
NOTgate U1(q,p); // Here we are connecting NOTgate module with testbench_NOT.
// 'NOTgate' is module name, 'U1' is instance name (defined by us).
// 'q' and 'p' are port association, note that proper sequence is to be followed.
endmodule

Figure 2.6: Verilog code and testbench for Half Adder.

Name & ID:…………………………………… Date: ……………………….

Step 7 After you click save and check icon it will ask “Cellview Half_Adder symbol does not exist. Do you
want to create it?” as shown in Figure 2.7. If you want to create symbol then click yes, but at this point
click No.

Figure 2.7: Ask about creating symbol for cellview

Step 8 You can check for any error or warning message in View tab and click “Parser Log File”. If there
are any error messages rectify them in code and again click on saved and checked icon. Repeat this until
you got zero errors and zero warnings (sometimes we can ignore warning messages but it’s important to
read them as on later stage some warnings may cause problem).

Step 9 Once the code is saved and checked with no errors, go to Launch -> NC Verilog as shown in figure
2.9.

Figure 2.9: To launch the verilog simulator click NC-Verilog

Name & ID:…………………………………… Date: ……………………….

Step 10 After this the Virtuoso Verilog Environment for NC-Verilog Integration is launched as shown in
figure 2.12. Now click the top left icon “Initialize Design” (high-lighted in figure 2.10a).

Figure 2.10a: Verilog environment for NC-Verilog

This enables the Generate Netlist icon and Simulate icon. Click Generate Netlist icon on left and then
Simulate icon below it as highlighted in figure 2.12b.

Figure 2.10b: Click the generate netlist icon and then simulate as highlighted
Name & ID:…………………………………… Date: ……………………….

Step 11 After clicking on “simulate” icon, wait for 10-15 seconds for two new windows to launch.
This invokes Design Browser (figure 2.11a) and Console window (figure 2.11b).

Figure 2.11a: Design Browser 1- Simvision window

Figure 2.11b: Console - Simvision window

Name & ID:…………………………………… Date: ……………………….

Step 12: Click to expand the “test” and testbench_halfadder” under simulator in the Design Browser. Now
select the “U1” under testbench_NOT (why U1 under testbench_NOT? because U1 is your instance name
of ‘NOTgate’ inside module ‘testbench_NOT’ in the code above) to view the inputs and output from the
Verilog code in the Objects (see Figure 2.12). Now click on button to probe all these ports to the waveform
viewer in accordance with the inputs defined in the test bench of the Verilog code.

Figure 2.12: Design browser Console - Simvision window

Step 13 In the waveform window (as shown in figure 2.13a). Click the run button , if $stop is not given in
testbench then click the pause button next to it.

Figure 2.13a: Waveform window setting and play button

Name & ID:…………………………………… Date: ……………………….

Simulation runs for total 400ns as mentioned in testbench. Input value changes after every 100ns. The
cursor can be moved along the waveform to view the binary values of the inputs (a) and output (z) at a
particular instant of time as shown below in figure 1.13b)

Figure 2.13b: Waveform for NOT gate for varying input in testbench and its output as in design.

***********************