09 March 2024 21:15

➢ What is a system verilog constraint?

• constraints restrict the randomization or a random variable to a particular range(randomization distributions) during simulat ion or synthesis.
• constraints blocks specify a legal random values (which satisfy all the requirements) to a random variable with keyword rand.
• All the constraints block are in active state simultaneously , each block has its unique name.

➢ What are Directed tests and Randomized tests?

○ Verification engineers create verification plan for the design to target each test feature/scenario. In directed tests exhaustive testing is done(Time consuming).
○ In Complex designs has lot of scenarios and corner cases which are better verified by Randomized tests with less effort and time.

Example: If there is a pheripheral that needs its registers to be configured for AXI bus transaction, then we configure those registers differently to achieve a good
coverage. A test will configure the pheripheral registers with random values every time with a different seed thereby achieving different scenarios for every run
which is effective to exercise corner cases and spot any hidden bugs.

➢ What are System Verilog rand Variables ?

○ variables declared random using rand or randc keyword. the function randomize() (randomize(v1,v2) randomizes variable v1 and v2) is invoked as part of the
class object to randomize all the rand type variables. normal variables holds its default value.

○ Random variables values are uniformly distributed over the range, (Eg the variable data(Left figure) in the above code is 8-bit unsigned integer with a range
from 0 to 255) . If this variable is randomized without any constraints then any value it take with probabality (1/256).
○ when variables declared under randc then, the same value will repeat only after all the values have assigned atleast once. randc values are solved before other
random values.

➢ Some points about constraint.

• A variable may have multiple contraints but conflicts in constrants in multiple blocks leads to error. Some constraints are s electively turnedoff/on using
constraint_mode() method.
• constraints are placed either inside the class body definition or outside (external constraints), when constraints are place d outside a class's body they are accessed by
using the scope resolution operator ::

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Array Randomization: array randomization allows to randomize the elements of an array individually or collectively based on specified constraints.

Some Basic examples of constraints.

Write a constraint Write a constraint

1)cst 1 to generate a pattern 010203 5) cst3 to generate the random odd numbers between 10 to 30.
2)cst 2 divisible by 5
class abc;
class abc; rand bit [7:0]a;
rand int a[ ]; constraint cst3{a inside {[10:30]}; a%2==1;} //((a>9) &&(a<31))
rand bit [7:0]b; endclass

constraint cst1{a.size==6; foreach(a[i]) if(i%2==0) a[i]==0; Write a constraint for

else a[i]==(i+1)/2;} //pattern generation
6) 4 bit dynamic array with size between 15 to 20 and even numbers at
constraint cst2{b%5==0;} //divisible by 5
endclass
odd location and odd numbers at even location.

Write a constraint class abc;

rand bit [3:0]a[ ];
3) To generate the multiples of power 2
constraint cst4{a.size() inside[15:20];
class abc; foreach(a[i])
rand logic[7:0]a; if(i%2==0) a[i]%2==1;
rand logic [4:0]power; else if (i%2==1) a[i]%2==0;
}
constraint d1{a==2*power}
//alternate style constraint d1{a!=0; (a&(a-1))==0;} endclass
endclass

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 endclass
endclass Write a constraint to generate 10-digit phone number with first 3-digits(853)
class Ph;
Write a constraint rand int num[$];
4) To generate the generate the 5 unique real elements between 1.62 and 1.98 in
ascending order constraint cst4{num.size()==10;
class abc; foreach(num[i])
rand real a[5]; if(i==0) num[i]==8;
else if(i==1) num[i]==5;
constraint cst{ else if(i==2) num[i]==3;
foreach(a[i]) { else num[i] inside {[0:9]};}
a[i] inside {[1.62:1.98]}; endclass
if(i>0) a[i]>a[i-1]; //for ascending order
}
unique {a};} //for unique elements
endclass

module tb();
abc a1=new();

initial begin
a1.randomize();
$display("%0p", a1.a);
end

endmodule

➢ Explain some common ways of writing a system verilog constraints?

constraint expressions are written inside constraint block by some common methods described below.
• Simple expressions:
There can be only one relational operator (<, <=, >, >=) in an expression, (= not allowed, ==allowed).

Note: $sformatf() is the system task which allows to format the data into a string variable.

Example

string formatted_str;
int value=42;
formatted_str=$sformatf("The value is %0d",value); //This system task formats the integer value into the string variable(formatted_str) with message " The value is 42".

Example-(Use of inside operator)

• We can specify the range of values the variable(var1) can take each are equiprobable using inside operator.

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 Implication Operator
An implication operator (->) is used in constraint to establish the relation between two variables in constraint. If the expression in LHS is satisfied implies the RHS must
be satisfied but vicevarsa is need not be satisfied.

➢ Explain if-else and foreach constraint?

• This constraint provides an option to specify the else part of a conditional expression. If the conditional expression is tru e, then all the constraints specified in first
constraint set will be satisfied. Otherwise all of the constraints in the optional else part will be satisfied.
• Arrays can be constrained through foreach loop. The below example declares a static array with size 5, indexing from 0 to 4.

• Nested if-else blocks are allowed and multiple constraint statements require them to be enclosed in curly braces{ }.

Example: with foreach:

class abc;
rand bit [3:0] m1;
rand bit m2;

constraint c1{ if (m1 inside {[4'h5:4'hB]} ) m2==1;

else { if(m1==4'h1) m2==1;
else m2==0;
}
}

endclass

Write a constraint to create the random array of unique Integers with size between 10 and 16 whose values are in descending o rder.

class array_1;
rand unsigned int myarray[ ];

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constraint c_val{myarray.size inside {[10:16]};
foreach (myarray[i])
if(i>0) myarray[i-1]>myarray[i];
unique{my_array};}

endclass

Note: If constraint specified in the base class gets modified at the extended class by again specifying the constraint at the same name as that of the base class.

Multidimensional array: SV supports constraints which can be applied to multi-dimensional arrays aswell. The below example shows multi-dimensional array with a
packed structure.

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packed structure.

Array Reduction Iterative constraint:

Array reduction methods produce a single value from an unpacked array of integral values which can be used within a constrain t to allow the expression to be considered
during randomization.
Consider an example that an array of N elements to be randomized such that sum of all elements equal to some value. An array reduction operator can be used with the
with clause such that it iterates over each element of the array and include it in the constraint solver.

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Note: constraint_mode function is used to enable, disable and getting the status of whether the constraint is active or not.

Solve before constraint:

By default the rand variables are randomized with uniform probabality by the constraint solver, but by using solve before keyword the probabality of randomization will be
changed such that certain corner cases hits more effectively.
Example-1 (effect of solve before)
• The values of a and b are randomized without solve before(Left figure).
The probabality of a=1 and b=3 is (1/2).
• The values of a and b are randomized with solve before(Right figure). Here b is randomized earlier than a so the probabality of a=1 and b=3 is (1/4)
Note: randc variables are not allowed in solve before since they are always solved first.

class abc; class abc;

rand bit a; rand bit a;
rand bit [1:0]b; rand bit [1:0]b;

constraint c_ab1{a->b==3'h3;} constraint c_ab1{a->b==3'h3;

endclass solve b before a}

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 endclass solve b before a}

endclass

.
What is System verilog Static Constraint?
Static constraint can be shared across successive class instances. When a static constraint can be enabled/disabled by object handle(constraint_mode()) of its class , The mode
change with one handle of a class will reflect at all other objects of same type in static constraints this is not the case with non static constraints.

Example:
By default the constraints are dynamic in nature, In the below example
Static constraints share their status(active/inactive) across successive randomization but not incase of dynamic.

Practical examples for SV constraints:

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4.constraints Page 9
<Variable memory partitions, variable partitions with spaceinbetween, Partition for program and data>

Bus Protocol constraints:

Digital blocks communicate among each other using Bus protocols (Eg AMBA, AXI, wishbone etc…) the Protocol specific control signals are initiated at the master tell the
slave when the packet is valied, whether it is a read or write, and how many bytes of data is sent. The master also sends out an address followed by the data to be stored at that
address.

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 ➢ Explain Randomization methods in SV?
Random variables are declared as rand or randc inside a class are randomized using the builtin method randomize(), The method returns 1/0 for successful/unsuccessful
randomization.

Note: There are some callback functions defined in class and are automatically called by randomize() before and after computing the random values.
• pre_randomize() is called before computing the random values and post_randomize is called after computing the random values thus we can change the randomization
characteristics of the object.
• Both functions are not virtual but behave like virtual methods, If we manually try make them virtual lead to error.
• If randomize() fails then post-randomize() cant be activated variables retain their previous values.

➢ What are SV inline constraints ?

using with construct, users can declare inline constraints at the point where randomize() method is called. These additional constraints will be taken into account along
with the objects original constraints by the solver.

Note: There should not be any contradictory/overriding between original and inline constraint.

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Note: There should not be any contradictory/overriding between original and inline constraint.

➢ Explain the soft constraints in SV?

• By default constraints are Hard constraints where it is mandatory for the solver to always satisfy them else randomization fails. upon declaring the constraints as soft
gives some flexibility. if there are other contradicting constraints(either hard/soft constraint with higher priority). soft constraints are used t o specify default values and
distributions for random variables.
• Conflicting conditions in the soft constraints not leads to randomization failure.

Example(soft data>=4 is need not be strictly followed):

class abc; module tb();

rand bit [3:0]data; abc a1;

constraint c1{soft data>=4; data<=12;} initial begin

endclass a1=new;
repeat(3) begin
a1.randomize() with {data==2;};
end
end

endmodule

➢ Explain SV disable Constraints?

All constraints by default enabled and considered by the SV constraint solver during randomization. A disable constraint is n ot considered during randomization.
constraint can be enabled or disabled by constraint_mode().

Note: Disabling the constraint which is not actually exist leads to compile error

➢ Explain SV disable Randomization?

Randomization of class variables can be disabled using rand_mode method call.
rand_mode can be called both as a function and task. current state of the variables will be returned if it is called as a function.

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➢ Explain weighted randomcase in SV?
Sometimes we comeacross a scenarios where we need to pick one statement out of many. The randcase introduces a case statement that randomly selects one of its
branches. The case item expressions are positive integer values that represents a weights associated with each item.

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 Note: If a branch is assigned a 0 weight then that branch will not be taken, If all branches are assigned 0 weight then none of the branch taken at all(run time warning
gets popedup).

Seed in Constraint?

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