UNIT-IV

Interconnect, Memory Architecture and Arithmetic Circuits

Part-A

1. What is meant by data path circuits?

Data path circuits are meant for passing the data from one segment to other segment for
processing or storing. The data path is the core of processors, where all computations are
performed.

2. What is ripple carry adder?

If n bits are added, then we can get n-bit sum and carry of Cn. Ci= Carry in bit from the
previous column. N bit ripples carry adder needs n full adders with Ci+1 carry out bit.

3. What is meant by Carry Lookahead Adder (CLA)?

A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital logic. It
improves speed by reducing the amount of time required to determine carry bits. It calculates
one or more carry bits before the sum, which reduces the wait time to calculate the result of
the larger value bits.

4. What are accumulators?

Accumulator acts as a part of ALU and it is identified as register A. The result of an

operation performed in the ALU is stored in the accumulator. It is used to hold the data for
manipulation (arithmetic and logical).

5. Draw the circuit for 4 bit ripple carry adder.

6. What is meant by Barrel shifter?

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in
one clock cycle. It can be implemented as a sequence of multiplexers (MUX). The output of
one MUX is connected to the input of the next MUX in a way that depends on the shift
distance.
7. What is meant by booth multiplier?

Booth’s algorithm is an efficient hardware implementation of a digital circuit that multiplies

two binary numbers in two’s complement notation. Booth multiplication is a fastest technique
that allows for smaller, faster multiplication circuits, by recoding the numbers that are
multiplied.

8. What is meant by array multiplier?

Array multiplier uses an array of cells for calculation. Multiplier circuit is based on repeated
addition and shifting procedure. Each partial product is generated by the multiplication of the
multiplicand with one multiplier digit. N-1 adders are required where N is the number of
multiplier bits.

9. Define ROM. Give some examples.

ROM is a memory where code is written only one time.

Examples: washing machine, calculator, games etc.

10. What are advantage and disadvantages of programming ROM?

Advantage:

 Basic cell only consists of transistor.

 No need of connection to any of the supply voltage.

Disadvantage:

 It has pseudo nMOS

 It is ratioed logic
 Consumes static power.

11. Mention the application of Barrel shift register.

• A common usage of a barrel shifter is in the hardware implementation of floating- point

arithmetic.

• For a floating-point add or subtract operation, requires shifting the smaller number to the
right.

• This is done by using the barrel shifter to shift the smaller number to the right by the
difference, in one cycle.
12.What is Carry save adder?

In carry save adder, the carry does not propagate. So, it is faster than carry propagate adder. It
has three inputs and produces 2 outputs, carry-out is saved. It is not immediately used to find
the final sum value.

13.Write the delay equation for array multiplier.

The equation for array multiplier is

14. State radix-2 booth encoding table.

In radix-2 booth multiplication partial product generation is done based on encoding which is
as given by Table
15. Draw the graph between area Vs delay of carry lookahead and ripple carry adder
for 8 bit, 16 bit, 32 bit.

carry lookahead and ripple carry adder for 8 bit

carry lookahead and ripple carry adder for 16 bit

carry lookahead and ripple carry adder for 32 bit

16. What is FPGA ?

FPGA stands for field programmable gate array, which is the next generation in the
programmable logic devices. The word field refers to the ability of the gate arrays to be
programmed for a specific function by the end user. The word array indicates a series of
columns and rows of gates that can be programmed by the end user.

17. List the configurable elements in the FPGA architecture.

The FPGA architecture consists of three types of configurable elements:
1. A perimeter of Input/Output Blocks (IOBs).
2. A core array of Configurable Logic Blocks (CLBs).
3. Resources for interconnection.
18. What are the characteristics of FPGA?

 No mask layers are customized.

 Programming basic logic cells and interconnect.
 Core with regular array of programmable basic logic cells that implement
combinational and sequential logic.
 Matrix of programmable interconnect surrounds the basic logic cells Programmable
I/O cells surround the core.

19. What is Programmable Logic Array?

A programmable logic array (PLA) is a programmable device used to implement

combinational logic circuits. The PLA has a set of programmable AND planes, which link to
a programmable OR planes, which can then be conditionally complemented to produce an
output. This layout allows for a large number of logic functions to be synthesized in the sum
of products (sometimes product of sums) canonical forms.

20. Write the application of PLA.

 PLA is used to provide control over data path.

 PLA is used as a counter.
 PLA is used as a decoders.
 PLA is used as a BUS interface in programmed I/O.

Part-B

1. Draw the ripple carry adder & explain its operation.

2. Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the numbers of
adders. Discuss it over Wallace multiplier.

3. Explain FPGA Architecture and Applications.

4. Explain PLA and ROM.

5. Explain Comparators and Shift registers.

 UNIT-V

ASIC design and Testing

Part-A

1. List out the Implementation technologies in ASIC.

The implementation technologies used in ASIC are:

 TTL – Transistor Transistor Logic

 ECL – Emitter Coupled Logic
 MOS – Metal Oxide Semiconductor (NMOS, CMOS)

2. What are the types of ASICs?

The ASICs are classified as follows:

I. Full-Custom ASICs
II. Semi-custom ASICs

a. Standard-Cell–Based ASICs (CBIC)

b. Gate-Array–Based ASICs (MPGA)

 Channeled Gate Array

 Channel less Gate Array
 Structured Gate Array

III. Programmable ASICs

 Complex Programmable Logic Devices (CPLD)

 Field-Programmable Gate Arrays (FPGA)
3. What is needed for testing?

i. Physical defects are likely in manufacturing.

 Missing connections (opens)

 Bridged connections (shorts)
 Imperfect doping, processing steps
 Packaging
ii. Need to weed out bad die before assembly.
iii. Need to test during operation

 Electromagnetic interference, mechanical stress, electromigration, alpha particles.

4. What are different stages of testing on a chip?

 wafer level
 circuit level
 chip level
 board level
 field level
 logic level

5. What is meant by test program?

The tester requires a test program. This program is written in a high-level language that
supports a library of primitives for a particular tester.

6. Distinguish functionality test and manufacturing test.

S.No Functionality test Manufacturing test

1 Functionality test is to check whether Manufacturing test is to check is there any
logic block works with correct logic. defects occurred in circuit after fabrication
process.
2 It leads to imperfection of logic It leads to nodes to float, shorted to power
function. or ground.
3 It is done before the fabrication It is done after fabrication process.
process.

7. What is struck at fault?

If any input line is struck at logic ‘0’ or logic ‘1’ permanently called as struck at fault. If it
struck at logic ‘1’ then called as struck-at-1 or (SA1) and if it struck at logic ‘0’ then called as
struck-at-0 or (SA0).
8. What is struck open fault?

Due to defects while manufacturing leads to permanent disconnect of drain to source terminal
called as struck open fault.

9.What is bridging fault or short circuit fault?

Due to defects while manufacturing leads to shorting of inputs between themselves or

shorting of inputs to outputs(feedback) occurs called as bridging fault.

10. Define fault coverage?

Fault coverage is defined as ratio of the number of nodes detected as faults and total number
of nodes in the circuit.

Total no.of nodes in which fault identified

Fault coverage =
Total no.of nodes in circuit

11.What is meant by ATPG?

Automatic Test Pattern Generation (ATPG) – Block generates input patterns automatically by
itself for testing its own logic block and stores the output pattern and compare it with defined
pattern for error identification.

12.What are the 3 approaches in design for testability? (or) List out design required for
testing in CMOS chip design.

Three approaches in design for testability are

 Adhoc testing
 Scan based testing
 BIST- Built In Self Test

13.What is serial scan & parallel scan?

In serial scan based approaches, logic is connected to form a giant shift register called as a
scan chain spanning the whole chip.

In parallel scan based approaches, logic is split the chain into smaller segments. This can be
done on a module –by-module basis or completely automatically to some specified scan
length.
14.What is the aim of Adhoc test techniques?

Ad hoc test techniques are collections of ideas aimed at reducing the combinational
explosion of testing. They are only useful for small designs where scan, ATPG, and BIST are
not available. A complete scan-based testing methodology is recommended for all digital
circuits.

15.What is BIST or BILBO?

The Combination of scan technique with PRSG & signature analysis creates a structure called
as Built-in Logic Block Observer (BILBO).

16. What is observability and controllability?

The observability of a particular circuit node is the degree to which we can observe that node
at the outputs of an integrated circuit.

The measure of ease of forcing/setting a node to 0 or 1 by driving input pins of the chip is
called controllability.

17. Draw the Tap Access port (TAP) architecture.

18. What is Data Register (DR)?

The test data registers are used to set the inputs of modules to be tested and collect the results
of running tests.

19. What is boundary scan register?

The boundary scan register connects to all of the I/O circuitry. It internally consists of a shift
register for the scan chain and an additional bank of flip-flops to update the outputs in
parallel.
20. What are the advantages and disadvantages of BIST?

Advantages:

 Lower cost of test, since the need for external electrical testing using an ATE will be
 reduced, if not eliminated
 Better fault coverage, since special test structures can be incorporated onto the chips
 Shorter test times if the BIST can be designed to test more structures in parallel
 Easier customer support

Disadvantages:

 Additional silicon area and fab processing requirements for the BIST circuit
 Reduced access times
 Additional pin (and possibly bigger package size) requirements, since the BIST
circuitry need a way to interface with the outside world to be effective
 Possible issues with the correctness of BIST results, since the on-chip testing
hardware itself can fail.

Part-B

1. Explain the Fault models and Test coding.

2. Explain the ASIC Design Flow.

3. Explain the writing test benches in Verilog HDL

4. Explain the Automatic test pattern generation.

5.Explain the Design for testability. (Scan design: Test interface and boundary scan)