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course plan for dsd

course plan for dsd

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12 views

course plan for dsd

course plan for dsd

Uploaded by

malnaham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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121 20281115 (02208 Design of egal systems 02203 Design of digital systems (Fall 2023) Below you find a general description of the course, a description of the textbook and other course material, and a tentative lecture plan. 1. General description of the course About the course The course requires some background in: (1) digital electronics, including some experience using a hardware description language e.g. VHDL, Verilog or similar, (2) elementary computer architecture and (3) programming, The course is an upper level undergraduate course (for some students) or a graduate level course (for most students). In more detail, the course can be characterized as follows: + Afirst-level masters course for students enrolled in one of the following of DTUs M.Sc.-programs: Computer Systems Engineering, Electrical Engineering and Telecommunication. + Next level “up” for students enrolled in DTUs B.Sc. program in Electrical Engineering (who follow a bottom-up approach (courses 02138+39) + Next level “down” students enrolled in DTUs B.Sc. program in Software Technology (who follow a top down approach; course 02132) + Elective course for students B.Eng. program in Electrical Engineering (‘Diplom E") Overall course objectives: + To enable students to design large digital circuits in a systematic way and to implement these in FPGA technology using typical CAD tools (currently: VHDL and Xilinx Vivado). + To enable students to analyze and optimize the speed and area of a digital circuit. 8 covered: 1. Digital systems design: RTL-components and timing. Pipelining. FSM+Data path (FSMD), Time multiplexing. 2. The VHDL language: Language constructs. How to describe the intended circuitry in an efficient way. 3. Design methodology: Using VHDL, Top-down design flow, Simulation, Synthesis, FPGA technology, Tools: Xilinx Vivado. 4, A small project during the last half of the course. Some relatively small project that can be done within the semester. The design is taken all the way to a working FPGA implementation. Project (you pick one, A or B) bitps Aww. stu. dxleourses/02203) 8 121 20281115 (02208 Design of egal systems ‘A: Amin-heap circuit for dynamic pruning in Al accelerator * Used for dynamic pruning in neural networks (reduces power and computational complexity) ‘* Find the largest M elements in a stream of N elements (M<

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