dsPIC30F2011/2012/3012/3013

Data Sheet
High-Performance, 16-bit
Digital Signal Controllers

© 2008 Microchip Technology Inc. DS70139F

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS70139F-page ii © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
High-Performance, 16-bit Digital Signal Controllers
Peripheral Features:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • High-current sink/source I/O pins: 25 mA/25 mA
intended to be a complete reference • Three 16-bit timers/counters; optionally pair up
source. For more information on the CPU, 16-bit timers into 32-bit timer modules
peripherals, register descriptions and gen- • 16-bit Capture input functions
eral device functionality, refer to the • 16-bit Compare/PWM output functions
“dsPIC30F Family Reference Manual”
• 3-wire SPI modules (supports four Frame modes)
(DS70046). For more information on the
device instruction set and programming, • I2C™ module supports Multi-Master/Slave mode
refer to the “dsPIC30F/33F Programmer’s and 7-bit/10-bit addressing
Reference Manual” (DS70157). • Up to two addressable UART modules with FIFO
buffers
High-Performance Modified RISC CPU:
Analog Features:
• Modified Harvard architecture
• 12-bit Analog-to-Digital Converter (ADC) with:
• C compiler optimized instruction set architecture
- 200 ksps conversion rate
• Flexible addressing modes
- Up to 10 input channels
• 83 base instructions
- Conversion available during Sleep and Idle
• 24-bit wide instructions, 16-bit wide data path
• Programmable Low-Voltage Detection (PLVD)
• Up to 24 Kbytes on-chip Flash program space
• Programmable Brown-out Reset
• Up to 2 Kbytes of on-chip data RAM
• Up to 1 Kbytes of nonvolatile data EEPROM Special Microcontroller Features:
• 16 x 16-bit working register array
• Enhanced Flash program memory:
• Up to 30 MIPS operation:
- 10,000 erase/write cycle (min.) for
- DC to 40 MHz external clock input industrial temperature range, 100K (typical)
- 4 MHz - 10 MHz oscillator input with • Data EEPROM memory:
PLL active (4x, 8x, 16x)
- 100,000 erase/write cycle (min.) for
• Up to 21 interrupt sources: industrial temperature range, 1M (typical)
- 8 user-selectable priority levels • Self-reprogrammable under software control
- 3 external interrupt sources • Power-on Reset (POR), Power-up Timer (PWRT)
- 4 processor trap sources and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip
DSP Features: low-power RC oscillator for reliable operation
• Dual data fetch • Fail-Safe Clock Monitor operation:
• Modulo and Bit-Reversed modes - Detects clock failure and switches to on-chip
low-power RC oscillator
• Two 40-bit wide accumulators with optional
saturation logic • Programmable code protection
• 17-bit x 17-bit single-cycle hardware fractional/ • In-Circuit Serial Programming™ (ICSP™)
integer multiplier • Selectable Power Management modes:
• All DSP instructions are single cycle - Sleep, Idle and Alternate Clock modes
- Multiply-Accumulate (MAC) operation
• single-cycle ±16 shift
CMOS Technology:
• Low-power, high-speed Flash technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low-power consumption

© 2008 Microchip Technology Inc. DS70139F-page 3

dsPIC30F2011/2012/3012/3013
dsPIC30F2011/2012/3012/3013 Sensor Family
Program Memory Output

UART

I2C™
SRAM EEPROM Timer Input A/D 12-bit

SPI
Device Pins Comp/Std
Bytes Instructions Bytes Bytes 16-bit Cap 200 Ksps
PWM
dsPIC30F2011 18 12K 4K 1024 – 3 2 2 8 ch 1 1 1
dsPIC30F3012 18 24K 8K 2048 1024 3 2 2 8 ch 1 1 1
dsPIC30F2012 28 12K 4K 1024 – 3 2 2 10 ch 1 1 1
dsPIC30F3013 28 24K 8K 2048 1024 3 2 2 10 ch 2 1 1

DS70139F-page 4 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
Pin Diagrams

18-Pin PDIP and SOIC

MCLR 1 18 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 17 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 16 AN6/SCK1/INT0/OCFA/RB6

dsPIC30F2011
dsPIC30F3012
AN2/SS1/LVDIN/CN4/RB2 4 15 EMUD2/AN7/OC2/IC2/INT2/RB7
AN3/CN5/RB3 5 14 VDD
OSC1/CLKI 6 13 VSS
OSC2/CLKO/RC15 7 12 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 8 11 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 9 10 EMUC2/OC1/IC1/INT1/RD0

28-Pin PDIP and SOIC

MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 AN6/OCFA/RB6
AN2/SS1/LVDIN/CN4/RB2 4 25 EMUD2/AN7/RB7
AN3/CN5/RB3 5 24 AN8/OC1/RB8

dsPIC30F2012
AN4/CN6/RB4 6 23 AN9/OC2/RB9
AN5/CN7/RB5 7 22 CN17/RF4
VSS 8 21 CN18/RF5
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/RF3
VDD 13 16 SCK1/INT0/RF6
IC2/INT2/RD9 14 15 EMUC2/IC1/INT1/RD8

28-Pin SPDIP and SOIC

MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 AN6/OCFA/RB6
AN2/SS1/LVDIN/CN4/RB2 4 25 EMUD2/AN7/RB7
dsPIC30F3013

AN3/CN5/RB3 5 24 AN8/OC1/RB8
AN4/CN6/RB4 6 23 AN9/OC2/RB9
AN5/CN7/RB5 7 22 U2RX/CN17/RF4
VSS 8 21 U2TX/CN18/RF5
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/RF3
VDD 13 16 SCK1/INT0/RF6
IC2/INT2/RD9 14 15 EMUC2/IC1/INT1/RD8

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

© 2008 Microchip Technology Inc. DS70139F-page 5

dsPIC30F2011/2012/3012/3013
Pin Diagrams

28-Pin QFN

EMUD2/AN7/OC2/IC2/INT2/RB7
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1

AN6/SCK1/INT0/OCFA/RB6
MCLR
AVDD
AVSS

22
28
27
26

24
23
25
AN2/SS1/LVDIN/CN4/RB2 1 21 NC
AN3/CN5/RB3 2 20 NC
NC 3 19 NC
NC 4 dsPIC30F2011 18 NC
VSS 5 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO/RC15 7 15 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5
10
11

13
14
12
8
9

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUC2/OC1/IC1/INT1/RD0
VDD
NC

NC
EMUD1/SOSC1/T2CK/U1ATX/CN1/RC13

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139F-page 6 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
Pin Diagrams

28-Pin QFN

EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1

EMUD2/AN7/RB7
AN6/OCFA/RB6
MCLR
AVDD
AVSS

22
28
27
26
25
24
23
AN2/SS1/LVDIN/CN4/RB2 1 21 AN8/OC1/RB8
AN3/CN5/RB3 2 20 AN9/OC2/RB9
AN4/CN6/RB4 3 19 CN17/RF4
AN5/CN7/RB5 4 dsPIC30F2012 18 CN18/RF5
VSS 5 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO/RC15 7 15 PGC/EMUC/U1RX/SDI1/SDA/RF2
10

12
13
14
11
8
9
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

IC2/INT2/RD9
VDD

EMUC2/IC1/INT1/RD8

PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/INT0/RF6

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

© 2008 Microchip Technology Inc. DS70139F-page 7

dsPIC30F2011/2012/3012/3013
Pin Diagram

44-Pin QFN

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC2/OC1/IC1/INT1/RD0

VDD
NC
NC
NC
NC

NC
NC
44 43 42 41 40 39 38 37 36 35 34
PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 1 33 OSC2/CLKO/RC15
VSS 2 32 OSC1/CLKI
NC 3 31 VSS
VDD 4 30 VSS
NC 5 29 NC
NC 6 dsPIC30F3012 28 NC
NC 7 27 NC
NC 8 26 NC
NC 9 25 AN3/CN5/RB3
NC 10 24 NC
NC 11 23 AN2/SS1/LVDIN/CN4/RB2
12 13 14 15 16 17 18 19 20 21 22
EMUD2/AN7/OC2/IC2/INT2/RB7

AVSS
AVDD
NC

NC

MCLR
AN6/SCK1/INT0/OCFA/RB6

EMUD3/AN0/VREF+/CN2/RB0

NC
NC
EMUC3/AN1/VREF-/CN3/RB1

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139F-page 8 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
Pin Diagrams

44-Pin QFN

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PGD/EMUD/U1TX/SDO1/SCL/RF3

EMUC2/IC1/INT1/RD8
SCK1/INT0/RF6

IC2/INT2/RD9
VDD
NC
NC
NC
NC
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
VSS 2 32 OSC1/CLKI
NC 3 31 VSS
VDD 4 30 VSS
NC 5 29 NC
NC 6 dsPIC30F3013 28 NC
U2TX/CN18/RF5 7 27 AN5/CN7/RB5
NC 8 26 AN4/CN6/RB4
U2RX/CN17/RF4 9 25 AN3/CN5/RB3
AN9/OC2/RB9 10 24 NC
AN8/OC1/RB8 11 23 AN2/SS1/LVDIN/CN4/RB2
12
13
14
15
16
17
18
19
20
21
22
EMUD2/AN7/RB7

AN6/OCFA/RB6

EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AVSS
AVDD
NC

NC

MCLR

NC
NC

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

© 2008 Microchip Technology Inc. DS70139F-page 9

dsPIC30F2011/2012/3012/3013
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 CPU Architecture Overview........................................................................................................................................................ 19
3.0 Memory Organization ................................................................................................................................................................. 29
4.0 Address Generator Units ............................................................................................................................................................ 43
5.0 Flash Program Memory .............................................................................................................................................................. 49
6.0 Data EEPROM Memory ............................................................................................................................................................. 55
7.0 I/O Ports ..................................................................................................................................................................................... 59
8.0 Interrupts .................................................................................................................................................................................... 65
9.0 Timer1 Module ........................................................................................................................................................................... 73
10.0 Timer2/3 Module ........................................................................................................................................................................ 77
11.0 Input Capture Module................................................................................................................................................................. 83
12.0 Output Compare Module ............................................................................................................................................................ 87
13.0 SPI™ Module ............................................................................................................................................................................. 91
14.0 I2C™ Module ............................................................................................................................................................................. 95
15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 103
16.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 111
17.0 System Integration ................................................................................................................................................................... 121
18.0 Instruction Set Summary .......................................................................................................................................................... 135
19.0 Development Support............................................................................................................................................................... 143
20.0 Electrical Characteristics .......................................................................................................................................................... 147
21.0 Packaging Information.............................................................................................................................................................. 185
Index .................................................................................................................................................................................................. 197
The Microchip Web Site ..................................................................................................................................................................... 203
Customer Change Notification Service .............................................................................................................................................. 203
Customer Support .............................................................................................................................................................................. 203
Reader Response .............................................................................................................................................................................. 204
Product Identification System............................................................................................................................................................. 205

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70139F-page 10 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
This data sheet contains information specific to the
dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and
dsPIC30F3013 Digital Signal Controllers (DSC). These
devices contain extensive Digital Signal Processor
(DSP) functionality within a high-performance 16-bit
microcontroller (MCU) architecture.
The following block diagrams depict the architecture for
these devices:
• Figure 1-1 illustrates the dsPIC30F2011
• Figure 1-2 illustrates the dsPIC30F2012
• Figure 1-3 illustrates the dsPIC30F3012
• Figure 1-4 illustrates the dsPIC30F3013
Following the block diagrams, Table 1-1 relates the I/O
functions to pinout information.

© 2008 Microchip Technology Inc. DS70139F-page 11

dsPIC30F2011/2012/3012/3013
FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM

Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(512 bytes) (512 bytes)
Address Address 16
24 Latch Latch
16 16 16
EMUD3/AN0/VREF+/CN2/RB0
24 X RAGU EMUC3/AN1/VREF-/CN3/RB1
Y AGU
PCU PCH PCL X WAGU AN2/SS1/LVDIN/CN4/RB2
Program Counter AN3/CN5/RB3
Address Latch Stack Loop PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4
Control Control
Program Memory Logic Logic PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5
(12 Kbytes) AN6/SCK1/INT0/OCFA/RB6
EMUD2/AN7/OC2/IC2/INT2/RB7
Data Latch
Effective Address PORTB
16

ROM Latch 16
24

IR EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
16 16 OSC2/CLKO/RC15
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode & 16 16
Control

DSP Divide
Power-up Engine Unit
Timer EMUC2/OC1/IC1/INT1/RD0

OSC1/CLKI Timing Oscillator

Generation Start-up Timer
POR/BOR ALU<16>
Reset
Watchdog 16 16 PORTD
MCLR
Timer
Low-Voltage
VDD, VSS Detect
AVDD, AVSS

Input Output
12-bit ADC Capture Compare I2C™
Module Module

Timers SPI1 UART1

DS70139F-page 12 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM

Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(512 bytes) (512 bytes)
Address Address 16
24 Latch Latch
16 16 16
EMUD3/AN0/VREF+/CN2/RB0
24 X RAGU EMUC3/AN1/VREF-/CN3/RB1
Y AGU
PCU PCH PCL X WAGU AN2/SS1/LVDIN/CN4/RB2
Program Counter AN3/CN5/RB3
Address Latch Stack Loop AN4/CN6/RB4
Control Control
Logic Logic AN5/CN7/RB5
Program Memory
(12 Kbytes) AN6/OCFA/RB6
EMUD2/AN7/RB7
Data Latch AN8/OC1/RB8
Effective Address AN9/OC2/RB9
16
PORTB

ROM Latch 16
24

IR EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
16 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
16
OSC2/CLKO/RC15
16 x 16
W Reg Array PORTC
Decode
Instruction
Decode & 16 16
Control

DSP Divide
Power-up Engine Unit
Timer
Timing Oscillator EMUC2/IC1/INT1/RD8
OSC1/CLKI
Generation Start-up Timer IC2/INT2/RD9
POR/BOR ALU<16>
Reset
PORTD
Watchdog 16 16
MCLR
Timer
Low-Voltage
VDD, VSS Detect
AVDD, AVSS

Input Output
12-bit ADC Capture Compare I2C™
Module Module
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
CN17/RF4
CN18/RF5
SCK1/INT0/RF6
Timers SPI1 UART1
PORTF

© 2008 Microchip Technology Inc. DS70139F-page 13

dsPIC30F2011/2012/3012/3013
FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM

Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(1 Kbytes) (1 Kbytes)
Address Address 16
24 Latch Latch
16 16 16
EMUD3/AN0/VREF+/CN2/RB0
24 X RAGU EMUC3/AN1/VREF-/CN3/RB1
Y AGU
PCU PCH PCL X WAGU AN2/SS1/LVDIN/CN4/RB2
Program Counter AN3/CN5/RB3
Address Latch Stack Loop PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4
Control Control
Program Memory Logic Logic PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5
(24 Kbytes) AN6/SCK1/INT0/OCFA/RB6
EMUD2/AN7/OC2/IC2/INT2/RB7
Data EEPROM
(1 Kbytes) Effective Address PORTB
Data Latch 16

ROM Latch 16
24

IR EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
16 16 OSC2/CLKO/RC15
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode & 16 16
Control

DSP Divide
Power-up Engine Unit
Timer EMUC2/OC1/IC1/INT1/RD0

OSC1/CLKI Timing Oscillator

Generation Start-up Timer
POR/BOR ALU<16>
Reset
Watchdog 16 16 PORTD
MCLR
Timer
Low-Voltage
VDD, VSS Detect
AVDD, AVSS

Input Output
12-bit ADC Capture Compare I2C™
Module Module

Timers SPI1 UART1

DS70139F-page 14 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM

Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(1 Kbytes) (1 Kbytes)
Address Address 16
24 Latch Latch
16 16 16
EMUD3/AN0/VREF+/CN2/RB0
24 X RAGU EMUC3/AN1/VREF-/CN3/RB1
Y AGU
PCU PCH PCL X WAGU AN2/SS1/LVDIN/CN4/RB2
Address Latch Program Counter AN3/CN5/RB3
Program Memory Stack Loop AN4/CN6/RB4
Control Control
(24 Kbytes) Logic Logic AN5/CN7/RB5
AN6/OCFA/RB6
Data EEPROM
(1 Kbytes) EMUD2/AN7/RB7
AN8/OC1/RB8
Data Latch Effective Address AN9/OC2/RB9
16
PORTB

ROM Latch 16
24

IR EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
16 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
16
OSC2/CLKO/RC15
16 x 16
W Reg Array PORTC
Decode
Instruction
Decode & 16 16
Control

DSP Divide
Power-up Engine Unit
Timer
Timing Oscillator EMUC2/IC1/INT1/RD8
OSC1/CLKI
Generation Start-up Timer IC2/INT2/RD9
POR/BOR ALU<16>
Reset
PORTD
Watchdog 16 16
MCLR
Timer
Low-Voltage
VDD, VSS Detect
AVDD, AVSS

Input Output
12-bit ADC Capture Compare I2C™
Module Module
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
SCK1/INT0/RF6
Timers SPI1 UART1,
UART2
PORTF

© 2008 Microchip Technology Inc. DS70139F-page 15

dsPIC30F2011/2012/3012/3013
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Buffer
Pin Name Description
Type Type
AN0 - AN9 I Analog Analog input channels.
AVDD P P Positive supply for analog module.
AVSS P P Ground reference for analog module.
CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin
function.
CLKO O — Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with OSC2 pin function.
CN0 - CN7 I ST Input change notification inputs.
Can be software programmed for internal weak pull-ups on all
inputs.
EMUD I/O ST ICD Primary Communication Channel data input/output pin.
EMUC I/O ST ICD Primary Communication Channel clock input/output pin.
EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin.
EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin.
EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin.
EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin.
EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin.
EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin.
IC1 - IC2 I ST Capture inputs 1 through 2.
INT0 I ST External interrupt 0.
INT1 I ST External interrupt 1.
INT2 I ST External interrupt 2.
LVDIN I Analog Low-Voltage Detect Reference Voltage Input pin.
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This
pin is an active-low Reset to the device.
OC1-OC2 O — Compare outputs 1 through 2.
OCFA I ST Compare Fault A input.
OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes.
PGD I/O ST In-Circuit Serial Programming™ data input/output pin.
PGC I ST In-Circuit Serial Programming clock input pin.
RB0 - RB9 I/O ST PORTB is a bidirectional I/O port.
RC13 - RC15 I/O ST PORTC is a bidirectional I/O port.
RD0, RD8 - RD9 I/O ST PORTD is a bidirectional I/O port.
RF2 - RF5 I/O ST PORTF is a bidirectional I/O port.
SCK1 I/O ST Synchronous serial clock input/output for SPI1.
SDI1 I ST SPI1 Data In.
SDO1 O — SPI1 Data Out.
SS1 I ST SPI1 Slave Synchronization.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

DS70139F-page 16 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
Pin Name Description
Type Type
SCL I/O ST Synchronous serial clock input/output for I2C™.
SDA I/O ST Synchronous serial data input/output for I2C.
SOSCO O — 32 kHz low-power oscillator crystal output.
SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
T1CK I ST Timer1 external clock input.
T2CK I ST Timer2 external clock input.
U1RX I ST UART1 Receive.
U1TX O — UART1 Transmit.
U1ARX I ST UART1 Alternate Receive.
U1ATX O — UART1 Alternate Transmit.
U2RX I ST UART2 Receive.
U2TX O — UART2 Transmit.
VDD P — Positive supply for logic and I/O pins.
VSS P — Ground reference for logic and I/O pins.
VREF+ I Analog Analog Voltage Reference (High) input.
VREF- I Analog Analog Voltage Reference (Low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

© 2008 Microchip Technology Inc. DS70139F-page 17

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 18 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
2.0 CPU ARCHITECTURE Two ways to access data in program memory are:
OVERVIEW • The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of
Note: This data sheet summarizes features of program space at any 16K program word
this group of dsPIC30F devices and is not boundary, defined by the 8-bit Program Space
intended to be a complete reference Visibility Page (PSVPAG) register. Thus any
source. For more information on the CPU, instruction can access program space as if it were
peripherals, register descriptions and data space, with a limitation that the access
general device functionality, refer to the requires an additional cycle. Only the lower 16
“dsPIC30F Family Reference Manual” bits of each instruction word can be accessed
(DS70046). For more information on the using this method.
device instruction set and programming, • Linear indirect access of 32K word pages within
refer to the “dsPIC30F/33F Programmer’s program space is also possible using any working
Reference Manual” (DS70157). register, via table read and write instructions.
This section is an overview of the CPU architecture of Table read and write instructions can be used to
the dsPIC30F. The core has a 24-bit instruction word. access all 24 bits of an instruction word.
The Program Counter (PC) is 23 bits wide with the Overhead-free circular buffers (Modulo Addressing)
Least Significant bit (LSb) always clear (see are supported in both X and Y address spaces. This is
Section 3.1 “Program Address Space”). The Most primarily intended to remove the loop overhead for
Significant bit (MSb) is ignored during normal program DSP algorithms.
execution, except for certain specialized instructions. The X AGU also supports Bit-Reversed Addressing on
Thus, the PC can address up to 4M instruction words destination effective addresses to greatly simplify input
of user program space. An instruction prefetch or output data reordering for radix-2 FFT algorithms.
mechanism helps maintain throughput. Program loop Refer to Section 4.0 “Address Generator Units” for
constructs, free from loop count management details on Modulo and Bit-Reversed Addressing.
overhead, are supported using the DO and REPEAT
instructions, both of which are interruptible at any point. The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
2.1 Core Overview
modes. Instructions are associated with pre-defined
The working register array consists of 16 x 16-bit addressing modes, depending upon their functional
registers, each of which can act as data, address or requirements.
offset registers. One working register (W15) operates For most instructions, the core is capable of executing
as a Software Stack Pointer for interrupts and calls. a data (or program data) memory read, a working
The data space is 64 Kbytes (32K words) and is split register (data) read, a data memory write and a
into two blocks, referred to as X and Y data memory. program (instruction) memory read per instruction
Each block has its own independent Address Genera- cycle. As a result, 3 operand instructions are
tion Unit (AGU). Most instructions operate solely supported, allowing C = A+B operations to be exe-
through the X memory, AGU, which provides the cuted in a single cycle.
appearance of a single unified data space. The A DSP engine has been included to significantly
Multiply-Accumulate (MAC) class of dual source DSP enhance the core arithmetic capability and throughput.
instructions operate through both the X and Y AGUs, It features a high-speed 17-bit by 17-bit multiplier, a
splitting the data address space into two parts (see 40-bit ALU, two 40-bit saturating accumulators and a
Section 3.2 “Data Address Space”). The X and Y 40-bit bidirectional barrel shifter. Data in the accumula-
data space boundary is device specific and cannot be tor or any working register can be shifted up to 15 bits
altered by the user. Each data word consists of 2 bytes right, or 16 bits left in a single cycle. The DSP instruc-
and most instructions can address data either as words tions operate seamlessly with all other instructions and
or bytes. have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear is for all others. This has been
achieved in a transparent and flexible manner, by ded-
icating certain working registers to each address space
for the MAC class of instructions.

© 2008 Microchip Technology Inc. DS70139F-page 19

dsPIC30F2011/2012/3012/3013
The core does not support a multi-stage instruction 2.2.1 SOFTWARE STACK POINTER/
pipeline. However, a single-stage instruction prefetch FRAME POINTER
mechanism is used, which accesses and partially
The dsPIC® DSC devices contain a software stack.
decodes instructions a cycle ahead of execution, in
W15 is the dedicated Software Stack Pointer (SP),
order to maximize available execution time. Most
which is automatically modified by exception process-
instructions execute in a single cycle with certain
ing and subroutine calls and returns. However, W15
exceptions.
can be referenced by any instruction in the same man-
The core features a vectored exception processing ner as all other W registers. This simplifies the reading,
structure for traps and interrupts, with 62 independent writing and manipulation of the Stack Pointer (e.g., cre-
vectors. The exceptions consist of up to 8 traps (of ating stack frames).
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between Note: In order to protect against misaligned
1 and 7 (1 being the lowest priority and 7 being the stack accesses, W15<0> is always clear.
highest), in conjunction with a predetermined ‘natural W15 is initialized to 0x0800 during a Reset. The user
order’. Traps have fixed priorities ranging from 8 to 15. may reprogram the SP during initialization to any
location within data space.
2.2 Programmer’s Model W14 has been dedicated as a Stack Frame Pointer, as
The programmer’s model is shown in Figure 2-1 and defined by the LNK and ULNK instructions. However,
consists of 16 x 16-bit working registers (W0 through W14 can be referenced by any instruction in the same
W15), 2 x 40-bit accumulators (ACCA and ACCB), manner as all other W registers.
STATUS register (SR), Data Table Page register
2.2.2 STATUS REGISTER
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART, The dsPIC DSC core has a 16-bit STATUS register
DOEND, DCOUNT and RCOUNT) and Program Coun- (SR), the LSB of which is referred to as the SR Low
ter (PC). The working registers can act as data, byte (SRL) and the MSB as the SR High byte (SRH).
address or offset registers. All registers are memory See Figure 2-1 for SR layout.
mapped. W0 acts as the W register for file register SRL contains all the MCU ALU operation Status flags
addressing. (including the Z bit), as well as the CPU Interrupt Prior-
Some of these registers have a shadow register asso- ity Level Status bits, IPL<2:0>, and the Repeat Active
ciated with each of them, as shown in Figure 2-1. The Status bit, RA. During exception processing, SRL is
shadow register is used as a temporary holding register concatenated with the MSB of the PC to form a com-
and can transfer its contents to or from its host register plete word value which is then stacked.
upon the occurrence of an event. None of the shadow The upper byte of the STATUS register contains the
registers are accessible directly. The following rules DSP Adder/Subtracter Status bits, the DO Loop Active
apply for transfer of registers into and out of shadows. bit (DA) and the Digit Carry (DC) Status bit.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits 2.2.3 PROGRAM COUNTER
only) are transferred. The program counter is 23 bits wide; bit 0 is always
• DO instruction clear. Therefore, the PC can address up to 4M
DOSTART, DOEND, DCOUNT shadows are instruction words.
pushed on loop start and popped on loop end.
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSB) can be manipulated
through byte-wide data memory space accesses.

DS70139F-page 20 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 2-1: PROGRAMMER’S MODEL

D15 D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer

SPLIM Stack Pointer Limit Register

AD39 AD31 AD15 AD0

DSP ACCA
Accumulators ACCB

PC22 PC0
0 Program Counter

7 0
TABPAG
TBLPAG Data Table Page Address

7 0
PSVPAG Program Space Visibility Page Address

15 0
RCOUNT REPEAT Loop Counter

15 0
DCOUNT DO Loop Counter

22 0
DOSTART DO Loop Start Address

22
DOEND DO Loop End Address

15 0
CORCON Core Configuration Register

OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS register

SRH SRL

© 2008 Microchip Technology Inc. DS70139F-page 21

dsPIC30F2011/2012/3012/3013
2.3 Divide Support The divide instructions must be executed within a
REPEAT loop. Any other form of execution
The dsPIC DSC devices feature a 16/16-bit signed (e.g., a series of discrete divide instructions) will not
fractional divide operation, as well as 32/16-bit and function correctly because the instruction flow depends
16/16-bit signed and unsigned integer divide opera- on RCOUNT. The divide instruction does not
tions, in the form of single instruction iterative divides. automatically set up the RCOUNT value and it must,
The following instructions and data sizes are therefore, be explicitly and correctly specified in the
supported: REPEAT instruction, as shown in Table 2-1 (REPEAT
1. DIVF - 16/16 signed fractional divide executes the target instruction {operand value+1}
2. DIV.sd - 32/16 signed divide times). The REPEAT loop count must be setup for 18
iterations of the DIV/DIVF instruction. Thus, a
3. DIV.ud - 32/16 unsigned divide
complete divide operation requires 19 cycles.
4. DIV.s - 16/16 signed divide
5. DIV.u - 16/16 unsigned divide Note: The divide flow is interruptible. However,
the user needs to save the context as
The 16/16 divides are similar to the 32/16 (same number appropriate.
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function
DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1
DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.s Signed divide: Wm/Wn → W0; Rem → W1
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1

DS70139F-page 22 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
2.4 DSP Engine The DSP engine has various options selected through
various bits in the CPU Core Configuration register
The DSP engine consists of a high-speed 17-bit x (CORCON), as listed below:
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round 1. Fractional or integer DSP multiply (IF).
and saturation logic). 2. Signed or unsigned DSP multiply (US).
The DSP engine also has the capability to perform 3. Conventional or convergent rounding (RND).
inherent accumulator-to-accumulator operations, 4. Automatic saturation on/off for ACCA (SATA).
which require no additional data. These instructions are 5. Automatic saturation on/off for ACCB (SATB).
ADD, SUB and NEG. 6. Automatic saturation on/off for writes to data
The dsPIC30F is a single-cycle instruction flow memory (SATDW).
architecture, therefore, concurrent operation of the 7. Accumulator Saturation mode selection
DSP engine with MCU instruction flow is not possible. (ACCSAT).
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction Note: For CORCON layout, see Table 3-3.
(e.g., ED, EDAC). See Table 2-2. A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2: DSP INSTRUCTION SUMMARY
Instruction Algebraic Operation ACC WB?
CLR A=0 Yes
ED A = (x – y)2 No
EDAC A = A + (x – y)2 No
MAC A = A + (x * y) Yes
MAC A = A + x2 No
MOVSAC No change in A Yes
MPY A=x*y No
MPY.N A=–x*y No
MSC A=A–x*y Yes

© 2008 Microchip Technology Inc. DS70139F-page 23

dsPIC30F2011/2012/3012/3013
FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder

Negate

40 40 40

Barrel
16
Shifter

X Data Bus
40

Sign-Extend
Y Data Bus

32 16
Zero Backfill
32
33

17-bit
Multiplier/Scaler

16 16

To/From W Array

DS70139F-page 24 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtracter, Overflow and
The 17 x 17-bit multiplier is capable of signed or Saturation
unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional
scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement
integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the
into the 17th bit of the multiplier input value. Signed carry/borrow input is active high and the other input is
operands are sign-extended into the 17th bit of the true data (not complemented), whereas in the case of
multiplier input value. The output of the 17 x 17-bit subtraction, the carry/borrow input is active low and the
multiplier/scaler is a 33-bit value which is other input is complemented. The adder/subtracter
sign-extended to 40 bits. Integer data is inherently generates overflow Status bits SA/SB and OA/OB,
represented as a signed two’s complement value, which are latched and reflected in the STATUS register:
where the MSB is defined as a sign bit. Generally
• Overflow from bit 39: this is a catastrophic
speaking, the range of an N-bit two’s complement
overflow in which the sign of the accumulator is
integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
destroyed.
range is -32768 (0x8000) to 32767 (0x7FFF) including
‘0’. For a 32-bit integer, the data range is • Overflow into guard bits 32 through 39: this is a
-2,147,483,648 (0x8000 0000) to 2,147,483,645 recoverable overflow. This bit is set whenever all
(0x7FFF FFFF). the guard bits are not identical to each other.

When the multiplier is configured for fractional The adder has an additional saturation block which
multiplication, the data is represented as a two’s controls accumulator data saturation if selected. It uses
complement fraction, where the MSB is defined as a the result of the adder, the overflow Status bits
sign bit and the radix point is implied to lie just after the described above, and the SATA/B (CORCON<7:6>)
sign bit (QX format). The range of an N-bit two’s and ACCSAT (CORCON<4>) mode control bits to
complement fraction with this implied radix point is -1.0 determine when and to what value to saturate.
to (1 – 21-N). For a 16-bit fraction, the Q15 data range Six STATUS register bits have been provided to
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’ support saturation and overflow. They are:
and has a precision of 3.01518x10-5. In Fractional 1. OA:
mode, the 16x16 multiply operation generates a 1.31 ACCA overflowed into guard bits
product, which has a precision of 4.65661 x 10-10.
2. OB:
The same multiplier is used to support the MCU ACCB overflowed into guard bits
multiply instructions, which include integer 16-bit 3. SA:
signed, unsigned and mixed sign multiplies. ACCA saturated (bit 31 overflow and saturation)
The MUL instruction can be directed to use byte or or
word-sized operands. Byte operands direct a 16-bit ACCA overflowed into guard bits and saturated
result. Word operands direct a 32-bit result to the (bit 39 overflow and saturation)
specified register(s) in the W array. 4. SB:
ACCB saturated (bit 31 overflow and saturation)
2.4.2 DATA ACCUMULATORS AND or
ADDER/SUBTRACTER ACCB overflowed into guard bits and saturated
The data accumulator consists of a 40-bit (bit 39 overflow and saturation)
adder/subtracter with automatic sign extension logic. It 5. OAB:
can select one of two accumulators (A or B) as its Logical OR of OA and OB
pre-accumulation source and post-accumulation 6. SAB:
destination. For the ADD and LAC instructions, the data Logical OR of SA and SB
to be accumulated or loaded can be optionally scaled
The OA and OB bits are modified each time data
via the barrel shifter prior to accumulation.
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the
corresponding overflow trap flag enable bit (OVATE,
OVBTE) in the INTCON1 register (refer to Section 8.0
“Interrupts”) is set. This allows the user to take
immediate action, for example, to correct system gain.

© 2008 Microchip Technology Inc. DS70139F-page 25

dsPIC30F2011/2012/3012/3013
The SA and SB bits are modified each time data 2.4.2.2 Accumulator ‘Write-Back’
passes through the adder/subtracter but can only be
The MAC class of instructions (with the exception of
cleared by the user. When set, they indicate that the
MPY, MPY.N, ED and EDAC) can optionally write a
accumulator has overflowed its maximum range (bit 31
rounded version of the high word (bits 31 through 16)
for 32-bit saturation or bit 39 for 40-bit saturation) and
of the accumulator that is not targeted by the instruction
will be saturated if saturation is enabled. When satura-
into data space memory. The write is performed across
tion is not enabled, SA and SB default to bit 39 overflow
the X bus into combined X and Y address space. The
and thus indicate that a catastrophic overflow has
following addressing modes are supported:
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits generate an arithmetic warning trap 1. W13, Register Direct:
when saturation is disabled. The rounded contents of the non-target
accumulator are written into W13 as a 1.15
The overflow and saturation Status bits can optionally
fraction.
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA 2. [W13]+=2, Register Indirect with Post-Increment:
and SB (in bit SAB). This allows programmers to check The rounded contents of the non-target
one bit in the STATUS register to determine if either accumulator are written into the address pointed
accumulator has overflowed, or one bit to determine if to by W13 as a 1.15 fraction. W13 is then
either accumulator has saturated. This would be useful incremented by 2 (for a word write).
for complex number arithmetic which typically uses
2.4.2.3 Round Logic
both the accumulators.
The round logic is a combinational block which
The device supports three saturation and overflow
performs a conventional (biased) or convergent
modes:
(unbiased) round function during an accumulator write
1. Bit 39 Overflow and Saturation: (store). The Round mode is determined by the state of
When bit 39 overflow and saturation occurs, the the RND bit in the CORCON register. It generates a
saturation logic loads the maximally positive 9.31 16-bit, 1.15 data value, which is passed to the data
(0x7FFFFFFFFF) or maximally negative 9.31 space write saturation logic. If rounding is not indicated
value (0x8000000000) into the target accumula- by the instruction, a truncated 1.15 data value is stored
tor. The SA or SB bit is set and remains set until and the least significant word (lsw) is simply discarded.
cleared by the user. This is referred to as ‘super
Conventional rounding takes bit 15 of the accumulator,
saturation’ and provides protection against erro-
zero-extends it and adds it to the ACCxH word (bits 16
neous data or unexpected algorithm problems
through 31 of the accumulator). If the ACCxL word
(e.g., gain calculations).
(bits 0 through 15 of the accumulator) is between
2. Bit 31 Overflow and Saturation: 0x8000 and 0xFFFF (0x8000 included), ACCxH is
When bit 31 overflow and saturation occurs, the incremented. If ACCxL is between 0x0000 and 0x7FFF,
saturation logic then loads the maximally posi- ACCxH is left unchanged. A consequence of this
tive 1.31 value (0x007FFFFFFF) or maximally algorithm is that over a succession of random rounding
negative 1.31 value (0x0080000000) into the operations, the value tends to be biased slightly
target accumulator. The SA or SB bit is set and positive.
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are Convergent (or unbiased) rounding operates in the
not used, so the OA, OB or OAB bits are never same manner as conventional rounding, except when
set. ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
3. Bit 39 Catastrophic Overflow:
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
The bit 39 overflow Status bit from the adder is
modified. Assuming that bit 16 is effectively random in
used to set the SA or SB bit which remains set
nature, this scheme will remove any rounding bias that
until cleared by the user. No saturation operation
may accumulate.
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in The SAC and SAC.R instructions store either a
the INTCON1 register is set, a catastrophic truncated (SAC) or rounded (SAC.R) version of the
overflow can initiate a trap exception. contents of the target accumulator to data memory via
the X bus (subject to data saturation, see
Section 2.4.2.4 “Data Space Write Saturation”).
Note that for the MAC class of instructions, the
accumulator write-back operation functions in the
same manner, addressing combined MCU (X and Y)
data space though the X bus. For this class of
instructions, the data is always subject to rounding.

DS70139F-page 26 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data The barrel shifter is capable of performing up to 16-bit
space may also be saturated but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts
contents of the source accumulator. The data space in a single cycle. The source can be either of the two
write saturation logic block accepts a 16-bit, 1.15 DSP accumulators, or the X bus (to support multi-bit
fractional value from the round logic block as its input, shifts of register or memory data).
together with overflow status from the original source The shifter requires a signed binary value to determine
(accumulator) and the 16-bit round adder. These are both the magnitude (number of bits) and direction of the
combined and used to select the appropriate 1.15 shift operation. A positive value shifts the operand right.
fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’
memory. does not modify the operand.
If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a
(after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result
adjusted accordingly. For input data greater than for MCU shift operations. Data from the X bus is
0x007FFF, data written to memory is forced to the presented to the barrel shifter between bit positions 16
maximum positive 1.15 value, 0x7FFF. For input data to 31 for right shifts, and bit positions 0 to 16 for left
less than 0xFF8000, data written to memory is forced shifts.
to the maximum negative 1.15 value, 0x8000. The MSb
of the source (bit 39) is used to determine the sign of
the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.

© 2008 Microchip Technology Inc. DS70139F-page 27

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 28 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
3.0 MEMORY ORGANIZATION Program memory is addressable by a 24-bit value from
either the 23-bit PC, table instruction Effective Address
Note: This data sheet summarizes features of (EA), or data space EA, when program space is
this group of dsPIC30F devices and is not mapped into data space as defined by Table 3-1. Note
intended to be a complete reference that the program space address is incremented by two
source. For more information on the CPU, between successive program words in order to provide
peripherals, register descriptions and compatibility with data space addressing.
general device functionality, refer to the User program space access is restricted to the lower
“dsPIC30F Family Reference Manual” 4M instruction word address range (0x000000 to
(DS70046). For more information on the 0x7FFFFE) for all accesses other than TBLRD/TBLWT,
device instruction set and programming, which uses TBLPAG<7> to determine user or configu-
refer to the “dsPIC30F/33F Programmer’s ration space access. In Table 3-1, Program Space
Reference Manual” (DS70157). Address Construction, bit 23 allows access to the
Device ID, the User ID and the Configuration bits.
3.1 Program Address Space Otherwise, bit 23 is always clear.
The program address space is 4M instruction words.
The program space memory map for the
dsPI30F2011/2012 is shown in Figure 3-1. The pro-
gram space memory map for the dsPI30F3012/3013 is
shown in Figure 3-2.

© 2008 Microchip Technology Inc. DS70139F-page 29

dsPIC30F2011/2012/3012/3013
FIGURE 3-1: dsPIC30F2011/2012 FIGURE 3-2: dsPIC30F3012/3013
PROGRAM SPACE PROGRAM SPACE
MEMORY MAP MEMORY MAP

Reset - GOTO Instruction 000000 Reset - GOTO Instruction 000000

Reset - Target Address 000002 Reset - Target Address 000002
000004 000004

Interrupt Vector Table Interrupt Vector Table

Vector Tables Vector Tables

00007E 00007E
Reserved 000080 Reserved 000080
000084

Alternate Vector Table Alternate Vector Table

User Memory

User Memory
000084
0000FE 0000FE
Space

Space
User Flash 000100 User Flash 000100
Program Memory Program Memory
(4K instructions) (8K instructions)
001FFE 003FFE
002000 004000
Reserved
(Read ‘0’s)
Reserved 7FFBFE
(Read ‘0’s) 7FFC00
Data EEPROM
(1 Kbyte)
7FFFFE 7FFFFE
800000 800000

Reserved Reserved
Configuration Memory

Configuration Memory

8005BE 8005BE
Space

Space

8005C0 8005C0
UNITID (32 instr.) UNITID (32 instr.)
8005FE 8005FE
800600 800600
Reserved Reserved
F7FFFE F7FFFE
Device Configuration F80000 Device Configuration F80000
Registers F8000E Registers F8000E
F80010 F80010

Reserved Reserved

FEFFFE FEFFFE
DEVID (2) FF0000 DEVID (2) FF0000
FFFFFE FFFFFE

DS70139F-page 30 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(TBLPAG<7> = 0)
TBLRD/TBLWT Configuration TBLPAG<7:0> Data EA<15:0>
(TBLPAG<7> = 1)
Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits
Using
Program 0 Program Counter 0
Counter

Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits

EA

Using 1/0 TBLPAG Reg

Table
Instruction
8 bits 16 bits

User/
Configuration Byte
Space 24-bit EA
Select
Select

Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory.

© 2008 Microchip Technology Inc. DS70139F-page 31

dsPIC30F2011/2012/3012/3013
3.1.1 DATA ACCESS FROM PROGRAM A set of table instructions are provided to move byte or
MEMORY USING TABLE word-sized data to and from program space. See
INSTRUCTIONS Figure 3-4 and Figure 3-5.
This architecture fetches 24-bit wide program memory. 1. TBLRDL: Table Read Low
Consequently, instructions are always aligned. Word: Read the LS Word of the program address;
However, as the architecture is modified Harvard, data P<15:0> maps to D<15:0>.
can also be present in program space. Byte: Read one of the LSB of the program
address;
There are two methods by which program space can P<7:0> maps to the destination byte when byte
be accessed: via special table instructions, or through select = 0;
the remapping of a 16K word program space page into P<15:8> maps to the destination byte when byte
the upper half of data space (see Section 3.1.2 “Data select = 1.
Access from Program Memory Using Program
2. TBLWTL: Table Write Low (refer to Section 5.0
Space Visibility”). The TBLRDL and TBLWTL
“Flash Program Memory” for details on Flash
instructions offer a direct method of reading or writing
Programming)
the lsw of any address within program space, without
going through data space. The TBLRDH and TBLWTH 3. TBLRDH: Table Read High
instructions are the only method whereby the upper 8 Word: Read the MS Word of the program address;
bits of a program space word can be accessed as data. P<23:16> maps to D<7:0>; D<15:8> will always
be = 0.
The PC is incremented by two for each successive Byte: Read one of the MSB of the program
24-bit program word. This allows program memory address;
addresses to directly map to data space addresses. P<23:16> maps to the destination byte when
Program memory can thus be regarded as two 16-bit byte select = 0;
word wide address spaces, residing side by side, each The destination byte will always be = 0 when
with the same address range. TBLRDL and TBLWTL byte select = 1.
access the space which contains the lsw, and TBLRDH
4. TBLWTH: Table Write High (refer to Section 5.0
and TBLWTH access the space which contains the
“Flash Program Memory” for details on Flash
MSB.
Programming)
Figure 3-3 shows how the EA is created for table
operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (lsw)

PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000

TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
TBLRDL.B (Wn<0> = 1)
(read as ‘0’)

DS70139F-page 32 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB)

TBLRDH.W

PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000

TBLRDH.B (Wn<0> = 0)

Program Memory
‘Phantom’ Byte
(read as ‘0’) TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each
MEMORY USING PROGRAM SPACE program memory word, the LS 15 bits of data space
VISIBILITY addresses directly map to the LS 15 bits in the
corresponding program space addresses. The
The upper 32 Kbytes of data space may optionally be remaining bits are provided by the Program Space
mapped into any 16K word program space page. This Visibility Page register, PSVPAG<7:0>, as shown in
provides transparent access of stored constant data Figure 3-6.
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the MSb of the data space EA is set and program For instructions that use PSV which are executed
space visibility is enabled by setting the PSV bit in the outside a REPEAT loop:
Core Control register (CORCON). The functions of • The following instructions require one instruction
CORCON are discussed in Section 2.4 “DSP cycle in addition to the specified execution time:
Engine”.
- MAC class of instructions with data operand
Data accesses to this area add an additional cycle to prefetch
the instruction being executed, since two program - MOV instructions
memory fetches are required.
- MOV.D instructions
Note that the upper half of addressable data space is • All other instructions require two instruction cycles
always part of the X data space. Therefore, when a in addition to the specified execution time of the
DSP operation uses program space mapping to access instruction.
this memory region, Y data space should typically
contain state (variable) data for DSP operations, For instructions that use PSV which are executed
whereas X data space should typically contain inside a REPEAT loop:
coefficient (constant) data. • The following instances require two instruction
Although each data space address, 0x8000 and higher, cycles in addition to the specified execution time
maps directly into a corresponding program memory of the instruction:
address (see Figure 3-6), only the lower 16 bits of the - Execution in the first iteration
24-bit program word are used to contain the data. The - Execution in the last iteration
upper 8 bits should be programmed to force an illegal - Execution prior to exiting the loop due to an
instruction to maintain machine robustness. Refer to interrupt
the “dsPIC30F/33F Programmer’s Reference Manual”
- Execution upon re-entering the loop after an
(DS70157) for details on instruction encoding.
interrupt is serviced
• Any other iteration of the REPEAT loop allow the
instruction accessing data, using PSV, to execute
in a single cycle.

© 2008 Microchip Technology Inc. DS70139F-page 33

dsPIC30F2011/2012/3012/3013
FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space Program Space

0x0000 0x000000

15 PSVPAG(1)
EA<15> = 0 0x00
8

Data 16
Space 0x8000
15 23 15 0
EA Address
EA<15> = 1 Concatenation 23 0x001200
15

Upper Half of Data

Space is Mapped
into Program Space
0xFFFF 0x001FFF

Data Read
BSET CORCON,#2 ; Set PSV bit
MOV #0x0, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x9200, W0 ; Access program memory location
; using a data space access

Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address.

DS70139F-page 34 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
3.2 Data Address Space When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
The core has two data spaces. The data spaces can be 64-Kbyte data address space (including all Y
considered either separate (for some DSP addresses). When executing one of the MAC class of
instructions), or as one unified linear address range (for instructions, the X block consists of the 64-Kbyte data
MCU instructions). The data spaces are accessed address space, excluding the Y address block (for data
using two Address Generation Units (AGUs) and reads only). In other words, all other instructions regard
separate data paths. the entire data memory as one composite address
space. The MAC class instructions extract the
3.2.1 DATA SPACE MEMORY MAP Y address space from data space and address it using
The data space memory is split into two blocks, X and EAs sourced from W10 and W11. The remaining X data
Y data space. A key element of this architecture is that space is addressed using W8 and W9. Both address
Y space is a subset of X space, and is fully contained spaces are concurrently accessed only with the MAC
within X space. In order to provide an apparent Linear class instructions.
Addressing space, X and Y spaces have contiguous The data space memory map for the dsPIC30F2011
addresses. and dsPIC30F2012 is shown in Figure 3-7. The data
space memory map for the dsPIC30F3012 and
dsPIC30F3013 is shown in Figure 3-8.

FIGURE 3-7: dsPIC30F2011/2012 DATA SPACE MEMORY MAP

MSB LSB
Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte
SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
X Data RAM (X) 8 Kbyte
0x09FF 0x09FE Near
1 Kbyte 0x0A01 0x0A00 Data
SRAM Space Y Data RAM (Y) Space
0x0BFF 0x0BFE
0x0C01 0x0C00

0x1FFF 0x1FFE

0x8001 0x8000

Optionally X Data
Mapped Unimplemented (X)
into Program
Memory

0xFFFF 0xFFFE

© 2008 Microchip Technology Inc. DS70139F-page 35

dsPIC30F2011/2012/3012/3013
FIGURE 3-8: dsPIC30F3012/3013 DATA SPACE MEMORY MAP

MSB LSB
Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte
SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
X Data RAM (X) 8 Kbyte
2 Kbyte 0x0BFF 0x0BFE Near
0x0C01 0x0C00 Data
SRAM Space Space
Y Data RAM (Y)
0x0FFF 0x0FFE
0x1001 0x1000

0x1FFF 0x1FFE

0x8001 0x8000

Optionally X Data
Mapped Unimplemented (X)
into Program
Memory

0xFFFF 0xFFFE

DS70139F-page 36 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE SFR SPACE

X SPACE
UNUSED

(Y SPACE) Y SPACE UNUSED

X SPACE

X SPACE
UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops (Read)

MAC Class Ops (Write)

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

© 2008 Microchip Technology Inc. DS70139F-page 37

dsPIC30F2011/2012/3012/3013
3.2.2 DATA SPACES 3.2.3 DATA SPACE WIDTH
The X data space is used by all instructions and sup- The core data width is 16 bits. All internal registers are
ports all addressing modes. There are separate read organized as 16-bit wide words. Data space memory is
and write data buses. The X read data bus is the return organized in byte addressable, 16-bit wide blocks.
data path for all instructions that view data space as
combined X and Y address space. It is also the X 3.2.4 DATA ALIGNMENT
address space data path for the dual operand read To help maintain backward compatibility with
instructions (MAC class). The X write data bus is the PIC® MCU devices and improve data space memory
only write path to data space for all instructions. usage efficiency, the dsPIC30F instruction set supports
The X data space also supports Modulo Addressing for both word and byte operations. Data is aligned in data
all instructions, subject to Addressing mode restric- memory and registers as words, but all data space EAs
tions. Bit-Reversed Addressing is only supported for resolve to bytes. Data byte reads read the complete
writes to X data space. word that contains the byte, using the LSb of any EA to
determine which byte to select. The selected byte is
The Y data space is used in concert with the X data
placed onto the LSB of the X data path (no byte
space by the MAC class of instructions (CLR, ED,
accesses are possible from the Y data path as the MAC
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
class of instruction can only fetch words). That is, data
provide two concurrent data read paths. No writes
memory and registers are organized as two parallel
occur across the Y bus. This class of instructions
byte wide entities with shared (word) address decode
dedicates two W register pointers, W10 and W11, to
but separate write lines. Data byte writes only write to
always address Y data space, independent of X data
the corresponding side of the array or register which
space, whereas W8 and W9 always address X data
matches the byte address.
space. Note that during accumulator write back, the
data address space is considered a combination of X As a consequence of this byte accessibility, all Effective
and Y data spaces, so the write occurs across the X Address calculations (including those generated by the
bus. Consequently, the write can be to any address in DSP operations which are restricted to word-sized
the entire data space. data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
The Y data space can only be used for the data
Post-Modified Register Indirect Addressing mode
prefetch operation associated with the MAC class of
[Ws++] results in a value of Ws + 1 for byte operations
instructions. It also supports Modulo Addressing for
and Ws + 2 for word operations.
automated circular buffers. Of course, all other
instructions can access the Y data address space All word accesses must be aligned to an even address.
through the X data path as part of the composite linear Misaligned word data fetches are not supported, so
space. care should be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
The boundary between the X and Y data spaces is
a misaligned read or write be attempted, an address
defined as shown in Figure 3-8 and is not user
error trap is generated. If the error occurred on a read,
programmable. Should an EA point to data outside its
the instruction underway is completed, whereas if it
own assigned address space, or to a location outside
occurred on a write, the instruction is executed, but the
physical memory, an all zero word/byte is returned. For
write does not occur. In either case, a trap is then
example, although Y address space is visible by all
executed, allowing the system and/or user to examine
non-MAC instructions using any addressing mode, an
the machine state prior to execution of the address
attempt by a MAC instruction to fetch data from that
fault.
space using W8 or W9 (X space pointers)
returns 0x0000.
FIGURE 3-10: DATA ALIGNMENT
TABLE 3-2: EFFECT OF INVALID MSB LSB
15 87 0
MEMORY ACCESSES
0001 Byte 1 Byte 0 0000
Attempted Operation Data Returned
0003 Byte 3 Byte 2 0002
EA = an unimplemented address 0x0000
W8 or W9 used to access Y data 0x0000 0005 Byte 5 Byte 4 0004
space in a MAC instruction
W10 or W11 used to access X 0x0000
data space in a MAC instruction
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.

DS70139F-page 38 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
All byte loads into any W register are loaded into the There is a Stack Pointer Limit register (SPLIM)
LSB. The MSB is not modified. associated with the Stack Pointer. SPLIM is
A Sign-Extend (SE) instruction is provided to allow uninitialized at Reset. As is the case for the Stack
users to translate 8-bit signed data to 16-bit signed Pointer, SPLIM<0> is forced to ‘0’ because all stack
values. Alternatively, for 16-bit unsigned data, users operations must be word aligned. Whenever an
can clear the MSB of any W register by executing a Effective Address (EA) is generated using W15 as a
Zero-Extend (ZE) instruction on the appropriate source or destination pointer, the address thus
address. generated is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
Although most instructions are capable of operating on ister are equal, and a push operation is performed, a
word or byte data sizes, it should be noted that some stack error trap does not occur. The stack error trap
instructions, including the DSP instructions, operate occurs on a subsequent push operation. Thus, for
only on words. example, if it is desirable to cause a stack error trap
when the stack grows beyond address 0x2000 in RAM,
3.2.5 NEAR DATA SPACE initialize the SPLIM with the value, 0x1FFE.
An 8-Kbyte near data space is reserved in X address Similarly, a Stack Pointer underflow (stack error) trap is
memory space between 0x0000 and 0x1FFF, which is generated when the Stack Pointer address is found to
directly addressable via a 13-bit absolute address field be less than 0x0800, thus preventing the stack from
within all memory direct instructions. The remaining X interfering with the Special Function Register (SFR)
address space and all of the Y address space is space.
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which A write to the SPLIM register should not be immediately
support memory direct addressing with a 16-bit followed by an indirect read operation using W15.
address field.

3.2.6 SOFTWARE STACK

The dsPIC DSC devices contain a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes, as shown in
Figure 3-11. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note: A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.

FIGURE 3-11: CALL STACK FRAME

0x0000 15 0
Stack Grows Towards
Higher Address

PC<15:0> W15 (before CALL)

000000000 PC<22:16>
<Free Word> W15 (after CALL)

POP : [--W15]
PUSH : [W15++]

© 2008 Microchip Technology Inc. DS70139F-page 39

 TABLE 3-3: CORE REGISTER MAP
DS70139F-page 40

dsPIC30F2011/2012/3012/3013
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)

W0 0000 W0/WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000
TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000
© 2008 Microchip Technology Inc.

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
 TABLE 3-3: CORE REGISTER MAP (CONTINUED)
© 2008 Microchip Technology Inc.

Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013
DS70139F-page 41
dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 42 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
Note: This data sheet summarizes features of
(f) to directly address data present in the first 8192
this group of dsPIC30F devices and is not
bytes of data memory (near data space). Most file
intended to be a complete reference
register instructions employ a working register, W0,
source. For more information on the CPU,
which is denoted as WREG in these instructions. The
peripherals, register descriptions and
destination is typically either the same file register or
general device functionality, refer to the
WREG (with the exception of the MUL instruction),
“dsPIC30F Family Reference Manual”
which writes the result to a register or register pair. The
(DS70046). For more information on the
MOV instruction allows additional flexibility and can
device instruction set and programming,
access the entire data space during file register
refer to the “dsPIC30F/33F Programmer’s
operation.
Reference Manual” (DS70157).
The dsPIC DSC core contains two independent 4.1.2 MCU INSTRUCTIONS
address generator units: the X AGU and Y AGU. The Y The three-operand MCU instructions are of the form:
AGU supports word-sized data reads for the DSP MAC
Operand 3 = Operand 1 <function> Operand 2
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing: where Operand 1 is always a working register (i.e., the
addressing mode can only be register direct), which is
• Linear Addressing
referred to as Wb. Operand 2 can be a W register,
• Modulo (Circular) Addressing fetched from data memory or a 5-bit literal. The result
• Bit-Reversed Addressing location can be either a W register or an address
Linear and Modulo Data Addressing modes can be location. The following addressing modes are
applied to data space or program space. Bit-Reversed supported by MCU instructions:
Addressing is only applicable to data space addresses. • Register Direct
• Register Indirect
4.1 Instruction Addressing Modes • Register Indirect Post-modified
• Register Indirect Pre-modified
The addressing modes in Table 4-1 form the basis of • 5-bit or 10-bit Literal
the addressing modes optimized to support the specific
features of individual instructions. The addressing Note: Not all instructions support all the
modes provided in the MAC class of instructions are addressing modes given above. Individual
somewhat different from those in the other instruction instructions may support different subsets
types. of these addressing modes.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description
File Register Direct The address of the File register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

© 2008 Microchip Technology Inc. DS70139F-page 43

dsPIC30F2011/2012/3012/3013
4.1.3 MOVE AND ACCUMULATOR In summary, the following addressing modes are
INSTRUCTIONS supported by the MAC class of instructions:
Move instructions and the DSP accumulator class of • Register Indirect
instructions provide a greater degree of addressing • Register Indirect Post-modified by 2
flexibility than other instructions. In addition to the • Register Indirect Post-modified by 4
addressing modes supported by most MCU • Register Indirect Post-modified by 6
instructions, move and accumulator instructions also • Register Indirect with Register Offset (Indexed)
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed 4.1.5 OTHER INSTRUCTIONS
mode. Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
Note: For the MOV instructions, the addressing
For example, BRA (branch) instructions use 16-bit
mode specified in the instruction can differ
signed literals to specify the branch destination directly,
for the source and destination EA.
whereas the DISI instruction uses a 14-bit unsigned
However, the 4-bit Wb (register offset)
literal field. In some instructions, such as ADD Acc, the
field is shared between both source and
source of an operand or result is implied by the opcode
destination (but typically only used by
itself. Certain operations, such as NOP, do not have any
one).
operands.
In summary, the following addressing modes are
supported by move and accumulator instructions: 4.2 Modulo Addressing
• Register Direct
• Register Indirect Modulo Addressing is a method of providing an
• Register Indirect Post-modified automated means to support circular data buffers using
• Register Indirect Pre-modified hardware. The objective is to remove the need for
• Register Indirect with Register Offset (Indexed) software to perform data address boundary checks
• Register Indirect with Literal Offset when executing tightly looped code, as is typical in
• 8-bit Literal many DSP algorithms.
• 16-bit Literal Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
Note: Not all instructions support all the essentially the same for both). One circular buffer can
addressing modes given above. Individual be supported in each of the X (which also provides the
instructions may support different subsets pointers into program space) and Y data spaces.
of these addressing modes. Modulo Addressing can operate on any W register
pointer. However, it is not advisable to use W14 or W15
4.1.4 MAC INSTRUCTIONS
for Modulo Addressing since these two registers are
The dual source operand DSP instructions (CLR, ED, used as the Stack Frame Pointer and Stack Pointer,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also respectively.
referred to as MAC instructions, utilize a simplified set of
In general, any particular circular buffer can only be
addressing modes to allow the user to effectively
configured to operate in one direction, as there are
manipulate the data pointers through register indirect
certain restrictions on the buffer Start address
tables.
(for incrementing buffers), or end address
The two source operand prefetch registers must belong (for decrementing buffers) based upon the direction of
to the set {W8, W9, W10, W11}. For data reads, W8 the buffer.
and W9 are always directed to the X RAGU. W10 and
The only exception to the usage restrictions is for
W11 are always directed to the Y AGU. The effective
buffers that have a power-of-2 length. As these buffers
addresses generated (before and after modification)
satisfy the Start and the end address criteria, they can
must, therefore, be valid addresses within X data space
operate in a Bidirectional mode (i.e., address boundary
for W8 and W9 and Y data space for W10 and W11.
checks are performed on both the lower and upper
Note: Register Indirect with Register Offset address boundaries).
addressing is only available for W9 (in X
space) and W11 (in Y space).

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 dsPIC30F2011/2012/3012/3013
4.2.1 START AND END ADDRESS 4.2.2 W ADDRESS REGISTER
The Modulo Addressing scheme requires that a SELECTION
starting and an ending address be specified and loaded The Modulo and Bit-Reversed Addressing Control
into the 16-bit Modulo Buffer Address registers: register, MODCON<15:0>, contains enable flags as
XMODSRT, XMODEND, YMODSRT and YMODEND well as a W register field to specify the W address
(see Table 3-3). registers. The XWM and YWM fields select which
registers operate with Modulo Addressing.
Note: Y space Modulo Addressing EA
If XWM = 15, X RAGU and X WAGU Modulo
calculations assume word-sized data (LSb
Addressing is disabled. Similarly, if YWM = 15, Y AGU
of every EA is always clear).
Modulo Addressing is disabled.
The length of a circular buffer is not directly specified. It
The X Address Space Pointer W register (XWM), to
is determined by the difference between the
which Modulo Addressing is to be applied, is stored in
corresponding Start and end addresses. The maximum
MODCON<3:0> (see Table 3-3). Modulo Addressing is
possible length of the circular buffer is 32K words
enabled for X data space when XWM is set to any value
(64 Kbytes).
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other
than ‘15’ and the YMODEN bit is set at
MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Byte
Address MOV #0x1100,W0
MOV W0,XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
0x1100 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0,[W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
0x1163

Start Addr = 0x1100

End Addr = 0x1163
Length = 0x0032 words

© 2008 Microchip Technology Inc. DS70139F-page 45

dsPIC30F2011/2012/3012/3013
4.2.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes,
APPLICABILITY then the last ‘N’ bits of the data buffer Start address
must be zeros.
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W XB<14:0> is the bit-reversed address modifier or ‘pivot
register. It is important to realize that the address point’ which is typically a constant. In the case of an
boundaries check for addresses less than, or greater FFT computation, its value is equal to half of the FFT
than the upper (for incrementing buffers), and lower (for data buffer size.
decrementing buffers) boundary addresses (not just Note: All bit-reversed EA calculations assume
equal to). Address changes may, therefore, jump word-sized data (LSb of every EA is
beyond boundaries and still be adjusted correctly. always clear). The XB value is scaled
Note: The modulo corrected Effective Address is accordingly to generate compatible (byte)
written back to the register only when addresses.
Pre-Modify or Post-Modify Addressing When enabled, Bit-Reversed Addressing is only
mode is used to compute the Effective executed for register indirect with pre-increment or
Address. When an address offset post-increment addressing and word-sized data writes.
(e.g., [W7+W2]) is used, Modulo address It does not function for any other addressing mode or
correction is performed, but the contents for byte-sized data. Normal addresses are generated
of the register remain unchanged. instead. When Bit-Reversed Addressing is active, the
W address pointer is always added to the address
4.3 Bit-Reversed Addressing modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In
Bit-Reversed Addressing is intended to simplify data addition, as word-sized data is a requirement, the LSb
re-ordering for radix-2 FFT algorithms. It is supported of the EA is ignored (and always clear).
by the X AGU for data writes only.
Note: Modulo Addressing and Bit-Reversed
The modifier, which may be a constant value or register
Addressing should not be enabled
contents, is regarded as having its bit order reversed. The
together. In the event that the user attempts
address source and destination are kept in normal order.
to do this, Bit-Reversed Addressing
Thus, the only operand requiring reversal is the modifier.
assumes priority when active for the X
4.3.1 BIT-REVERSED ADDRESSING WAGU, and X WAGU Modulo Addressing
is disabled. However, Modulo Addressing
IMPLEMENTATION
continues to function in the X RAGU.
Bit-Reversed Addressing is enabled when:
If Bit-Reversed Addressing has already been enabled
• BWM (W register selection) in the MODCON reg- by setting the BREN (XBREV<15>) bit, then a write to
ister is any value other than ‘15’ (the stack cannot the XBREV register should not be immediately followed
be accessed using Bit-Reversed Addressing) and by an indirect read operation using the W register that
• the BREN bit is set in the XBREV register and has been designated as the bit-reversed pointer.
• the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.

DS70139F-page 46 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0

Bit-Reversed Address

Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value
1024 0x0200
512 0x0100
256 0x0080
128 0x0040
64 0x0020
32 0x0010
16 0x0008
8 0x0004
4 0x0002
2 0x0001

© 2008 Microchip Technology Inc. DS70139F-page 47

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NOTES:

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 dsPIC30F2011/2012/3012/3013
5.0 FLASH PROGRAM MEMORY 5.2 Run-Time Self-Programming
(RTSP)
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not RTSP is accomplished using TBLRD (table read) and
intended to be a complete reference TBLWT (table write) instructions.
source. For more information on the CPU, With RTSP, the user may erase program memory, 32
peripherals, register descriptions and instructions (96 bytes) at a time and can write program
general device functionality, refer to the memory data, 32 instructions (96 bytes) at a time.
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
5.3 Table Instruction Operation
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s Summary
Reference Manual” (DS70157). The TBLRDL and the TBLWTL instructions are used to
The dsPIC30F family of devices contains internal read or write to bits<15:0> of program memory.
program Flash memory for executing user code. There TBLRDL and TBLWTL can access program memory in
are two methods by which the user can program this Word or Byte mode.
memory: The TBLRDH and TBLWTH instructions are used to read
1. Run-Time Self-Programming (RTSP) or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
2. In-Circuit Serial Programming™ (ICSP™)
Byte mode.

5.1 In-Circuit Serial Programming A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the Effective
(ICSP) Address (EA) from a W register specified in the table
dsPIC30F devices can be serially programmed while in instruction, as shown in Figure 5-1.
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.

FIGURE 5-1: ADDRESSING FOR TABLE AND NVM REGISTERS

24 bits
Using
Program 0 Program Counter 0
Counter

NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits

Working Reg EA

Using 1/0 TBLPAG Reg

Table
Instruction 8 bits 16 bits

Byte
User/Configuration Select
Space Select 24-bit EA

© 2008 Microchip Technology Inc. DS70139F-page 49

dsPIC30F2011/2012/3012/3013
5.4 RTSP Operation 5.5 Control Registers
The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program
into rows and panels. Each row consists of 32 Flash memory are:
instructions or 96 bytes. Each panel consists of 128 • NVMCON
rows or 4K x 24 instructions. RTSP allows the user to • NVMADR
erase one row (32 instructions) at a time and to • NVMADRU
program four instructions at one time. RTSP may be • NVMKEY
used to program multiple program memory panels, but
the Table Pointer must be changed at each panel 5.5.1 NVMCON REGISTER
boundary.
The NVMCON register controls which blocks are to be
Each panel of program memory contains write latches erased, which memory type is to be programmed, and
that hold 32 instructions of programming data. Prior to start of the programming cycle.
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be 5.5.2 NVMADR REGISTER
programmed into the panel is loaded in sequential
The NVMADR register is used to hold the lower two
order into the write latches; instruction 0, instruction 1,
bytes of the Effective Address. The NVMADR register
etc. The instruction words loaded must always be from
captures the EA<15:0> of the last table instruction that
a 32 address boundary.
has been executed and selects the row to write.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions 5.5.3 NVMADRU REGISTER
to load the write latches. Programming is performed by
The NVMADRU register is used to hold the upper byte
setting the special bits in the NVMCON register. 32
of the Effective Address. The NVMADRU register cap-
TBLWTL and four TBLWTH instructions are required to
tures the EA<23:16> of the last table instruction that
load the 32 instructions. If multiple panel programming
has been executed.
is required, the Table Pointer needs to be changed and
the next set of multiple write latches written. 5.5.4 NVMKEY REGISTER
All of the table write operations are single-word writes NVMKEY is a write-only register that is used for write
(2 instruction cycles), because only the table latches protection. To start a programming or an erase
are written. A programming cycle is required for sequence, the user must consecutively write 0x55 and
programming each row. 0xAA to the NVMKEY register. Refer to Section 5.6
The Flash Program Memory is readable, writable and “Programming Operations” for further details.
erasable during normal operation over the entire VDD
Note: The user can also directly write to the
range.
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.

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 dsPIC30F2011/2012/3012/3013
5.6 Programming Operations 4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
A complete programming sequence is necessary for latches.
programming or erasing the internal Flash in RTSP
5. Program 32 instruction words into program
mode. A programming operation is nominally 2 msec in
Flash.
duration and the processor stalls (waits) until the
operation is finished. Setting the WR bit a) Set up NVMCON register for multi-word,
(NVMCON<15>) starts the operation and the WR bit is program Flash, program, and set WREN
automatically cleared when the operation is finished. bit.
b) Write ‘0x55’ to NVMKEY.
5.6.1 PROGRAMMING ALGORITHM FOR c) Write ‘0xAA’ to NVMKEY.
PROGRAM FLASH d) Set the WR bit. This begins program cycle.
The user can erase or program one row of program e) CPU stalls for duration of the program cycle.
Flash memory at a time. The general process is: f) The WR bit is cleared by the hardware
1. Read one row of program Flash (32 instruction when program cycle ends.
words) and store into data RAM as a data 6. Repeat steps 1 through 5 as needed to program
“image”. desired amount of program Flash memory.
2. Update the data image with the desired new
data. 5.6.2 ERASING A ROW OF PROGRAM
3. Erase program Flash row. MEMORY
a) Set up NVMCON register for multi-word, Example 5-1 shows a code sequence that can be used
program Flash, erase, and set WREN bit. to erase a row (32 instructions) of program memory.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write ‘0x55’ to NVMKEY.
d) Write ‘0xAA’ to NVMKEY.
e) Set the WR bit. This begins erase cycle.
f) CPU stalls for the duration of the erase cycle.
g) The WR bit is cleared when erase cycle
ends.

EXAMPLE 5-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV #0x4041,W0 ;
MOV W0,NVMCON ; Init NVMCON SFR
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR),W0 ;
MOV W0,NVMADRU ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer
MOV W0, NVMADR ; Initialize NVMADR SFR
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

© 2008 Microchip Technology Inc. DS70139F-page 51

dsPIC30F2011/2012/3012/3013
5.6.3 LOADING WRITE LATCHES 5.6.4 INITIATING THE PROGRAMMING
Example 5-2 shows a sequence of instructions that SEQUENCE
can be used to load the 96 bytes of write latches. 32 For protection, the write initiate sequence for NVMKEY
TBLWTL and 32 TBLWTH instructions are needed to must be used to allow any erase or program operation
load the write latches selected by the Table Pointer. to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs as shown in Example 5-3.

EXAMPLE 5-2: LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000,W0 ;
MOV W0,TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000,W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0,W2 ;
MOV #HIGH_BYTE_0,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1,W2 ;
MOV #HIGH_BYTE_1,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2,W2 ;
MOV #HIGH_BYTE_2,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
; 31st_program_word
MOV #LOW_WORD_31,W2 ;
MOV #HIGH_BYTE_31,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 5-2, the contents of the upper byte of W3 has no effect.

EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

DS70139F-page 52 © 2008 Microchip Technology Inc.

 TABLE 5-1: NVM REGISTER MAP
© 2008 Microchip Technology Inc.

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013
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NOTES:

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6.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is
Note: This data sheet summarizes features of responsible for waiting for the appropriate duration of
this group of dsPIC30F devices and is not time before initiating another data EEPROM write/
intended to be a complete reference erase operation. Attempting to read the data EEPROM
source. For more information on the CPU, while a programming or erase operation is in progress
peripherals, register descriptions and results in unspecified data.
general device functionality, refer to the Control bit WR initiates write operations similar to
“dsPIC30F Family Reference Manual” program Flash writes. This bit cannot be cleared, only
(DS70046). For more information on the set, in software. They are cleared in hardware at the
device instruction set and programming, completion of the write operation. The inability to clear
refer to the “dsPIC30F/33F Programmer’s the WR bit in software prevents the accidental or
Reference Manual” (DS70157). premature termination of a write operation.
The data EEPROM memory is readable and writable The WREN bit, when set, allows a write operation. On
during normal operation over the entire VDD range. The power-up, the WREN bit is clear. The WRERR bit is set
data EEPROM memory is directly mapped in the when a write operation is interrupted by a MCLR Reset
program memory address space. or a WDT Time-out Reset during normal operation. In
The four SFRs used to read and write the program these situations, following Reset, the user can check
Flash memory are used to access data EEPROM the WRERR bit and rewrite the location. The address
memory, as well. As described in Section 5.5 “Control register NVMADR remains unchanged.
Registers”, these registers are: Note: Interrupt flag bit NVMIF in the IFS0
• NVMCON register is set when write is complete. It
• NVMADR must be cleared in software.
• NVMADRU
• NVMKEY
6.1 Reading the Data EEPROM
The EEPROM data memory allows read and write of A TBLRD instruction reads a word at the current
single words and 16-word blocks. When interfacing to program word address. This example uses W0 as a
data memory, NVMADR, in conjunction with the pointer to data EEPROM. The result is placed in
NVMADRU register, are used to address the register W4 as shown in Example 6-1.
EEPROM location being accessed. TBLRDL and
TBLWTL instructions are used to read and write data EXAMPLE 6-1: DATA EEPROM READ
EEPROM. The dsPIC30F devices have up to 8 Kbytes
MOV #LOW_ADDR_WORD,W0 ; Init Pointer
(4K words) of data EEPROM with an address range MOV #HIGH_ADDR_WORD,W1
from 0x7FF000 to 0x7FFFFE. MOV W1,TBLPAG
A word write operation should be preceded by an erase TBLRDL [ W0 ], W4 ; read data EEPROM
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
varies with voltage and temperature.

© 2008 Microchip Technology Inc. DS70139F-page 55

dsPIC30F2011/2012/3012/3013
6.2 Erasing Data EEPROM
6.2.1 ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially point
to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM and
set the WR and WREN bits in the NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 6-2.

EXAMPLE 6-2: DATA EEPROM BLOCK ERASE

; Select data EEPROM block, WR, WREN bits
MOV #0x4045,W0
MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

6.2.2 ERASING A WORD OF DATA

EEPROM
The NVMADRU and NVMADR registers must point to
the block. Select WR a block of data Flash and set the
WR and WREN bits in the NVMCON register. Setting the
WR bit initiates the erase, as shown in Example 6-3.

EXAMPLE 6-3: DATA EEPROM WORD ERASE

; Select data EEPROM word, WR, WREN bits
MOV #0x4044,W0
MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

DS70139F-page 56 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
6.3 Writing to the Data EEPROM The write does not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly
sequence must be followed: recommended that interrupts be disabled during this
1. Erase data EEPROM word. code segment.
a) Select word, data EEPROM erase, and set Additionally, the WREN bit in NVMCON must be set to
WREN bit in NVMCON register. enable writes. This mechanism prevents accidental
b) Write address of word to be erased into writes to data EEPROM due to unexpected code
NVMADR. execution. The WREN bit should be kept clear at all
c) Enable NVM interrupt (optional). times except when updating the EEPROM. The WREN
bit is not cleared by hardware.
d) Write ‘0x55’ to NVMKEY.
e) Write ‘0xAA’ to NVMKEY. After a write sequence has been initiated, clearing the
WREN bit does not affect the current write cycle. The
f) Set the WR bit. This begins erase cycle.
WR bit is inhibited from being set unless the WREN bit
g) Either poll NVMIF bit or wait for NVMIF is set. The WREN bit must be set on a previous
interrupt. instruction. Both WR and WREN cannot be set with the
h) The WR bit is cleared when the erase cycle same instruction.
ends.
At the completion of the write cycle, the WR bit is
2. Write data word into data EEPROM write cleared in hardware and the Nonvolatile Memory Write
latches. Complete Interrupt Flag bit (NVMIF) is set. The user
3. Program 1 data word into data EEPROM. may either enable this interrupt or poll this bit. NVMIF
a) Select word, data EEPROM program, and must be cleared by software.
set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional). 6.3.1 WRITING A WORD OF DATA
c) Write ‘0x55’ to NVMKEY. EEPROM
d) Write ‘0xAA’ to NVMKEY. Once the user has erased the word to be programmed,
e) Set the WR bit. This begins program cycle. then a table write instruction is used to write one write
latch, as shown in Example 6-4.
f) Either poll NVMIF bit or wait for NVM
interrupt. 6.3.2 WRITING A BLOCK OF DATA
g) The WR bit is cleared when the write cycle EEPROM
ends.
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.

EXAMPLE 6-4: DATA EEPROM WORD WRITE

; Point to data memory
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #LOW(WORD),W2 ; Get data
TBLWTL W2,[ W0] ; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV #0x4004,W0
MOV W0,NVMCON

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

© 2008 Microchip Technology Inc. DS70139F-page 57

dsPIC30F2011/2012/3012/3013
EXAMPLE 6-5: DATA EEPROM BLOCK WRITE
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #data1,W2 ; Get 1st data
TBLWTL W2,[ W0]++ ; write data
MOV #data2,W2 ; Get 2nd data
TBLWTL W2,[ W0]++ ; write data
MOV #data3,W2 ; Get 3rd data
TBLWTL W2,[ W0]++ ; write data
MOV #data4,W2 ; Get 4th data
TBLWTL W2,[ W0]++ ; write data
MOV #data5,W2 ; Get 5th data
TBLWTL W2,[ W0]++ ; write data
MOV #data6,W2 ; Get 6th data
TBLWTL W2,[ W0]++ ; write data
MOV #data7,W2 ; Get 7th data
TBLWTL W2,[ W0]++ ; write data
MOV #data8,W2 ; Get 8th data
TBLWTL W2,[ W0]++ ; write data
MOV #data9,W2 ; Get 9th data
TBLWTL W2,[ W0]++ ; write data
MOV #data10,W2 ; Get 10th data
TBLWTL W2,[ W0]++ ; write data
MOV #data11,W2 ; Get 11th data
TBLWTL W2,[ W0]++ ; write data
MOV #data12,W2 ; Get 12th data
TBLWTL W2,[ W0]++ ; write data
MOV #data13,W2 ; Get 13th data
TBLWTL W2,[ W0]++ ; write data
MOV #data14,W2 ; Get 14th data
TBLWTL W2,[ W0]++ ; write data
MOV #data15,W2 ; Get 15th data
TBLWTL W2,[ W0]++ ; write data
MOV #data16,W2 ; Get 16th data
TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.
MOV #0x400A,W0 ; Select data EEPROM for multi word op
MOV W0,NVMCON ; Operate Key to allow program operation
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start write cycle
NOP
NOP

6.4 Write Verify 6.5 Protection Against Spurious Write

Depending on the application, good programming There are conditions when the device may not want to
practice may dictate that the value written to the mem- write to the data EEPROM memory. To protect against
ory should be verified against the original value. This spurious EEPROM writes, various mechanisms have
should be used in applications where excessive writes been built-in. On power-up, the WREN bit is cleared;
can stress bits near the specification limit. also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.

DS70139F-page 58 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
7.0 I/O PORTS Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
Note: This data sheet summarizes features of port pins, write the latch (LATx).
this group of dsPIC30F devices and is not Any bit and its associated data and Control registers
intended to be a complete reference that are not valid for a particular device are disabled.
source. For more information on the CPU, That means the corresponding LATx and TRISx
peripherals, register descriptions and registers and the port pin read as zeros.
general device functionality, refer to the
“dsPIC30F Family Reference Manual” When a pin is shared with another peripheral or
(DS70046). function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
All of the device pins (except VDD, VSS, MCLR and there is no other competing source of outputs.
OSC1/CLKI) are shared between the peripherals and
A parallel I/O (PIO) port that shares a pin with a
the parallel I/O ports.
peripheral is, in general, subservient to the peripheral.
All I/O input ports feature Schmitt Trigger inputs for The peripheral’s output buffer data and control signals
improved noise immunity. are provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
7.1 Parallel I/O (PIO) Ports has ownership of the output data and control signals of
the I/O pad cell. Figure 7-1 shows how ports are shared
When a peripheral is enabled and the peripheral is with other peripherals and the associated I/O cell (pad)
actively driving an associated pin, the use of the pin as to which they are connected.
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit The format of the registers for the shared ports,
is disabled. If a peripheral is enabled, but the peripheral (PORTB, PORTC, PORTD and PORTF) are shown in
is not actively driving a pin, that pin can be driven by a Table 7-1 through Table 7-6.
port. Note: The actual bits in use vary between
All port pins have three registers directly associated devices.
with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.

FIGURE 7-1: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Peripheral Module Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O Cell
Peripheral Output Enable
1 Output Enable
Peripheral Output Data 0

1
PIO Module Output Data
0
Read TRIS

Data Bus I/O Pad

D Q

WR TRIS CK
TRIS Latch

D Q
WR LAT +
WR Port CK
Data Latch

Read LAT
Input Data

Read Port

© 2008 Microchip Technology Inc. DS70139F-page 59

dsPIC30F2011/2012/3012/3013
7.2 Configuring Analog Port Pins 7.2.1 I/O PORT WRITE/READ TIMING
The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port
operation of the A/D port pins. The port pins that are direction change or port write operation and a read
desired as analog inputs must have their operation of the same port. Typically this instruction
corresponding TRIS bit set (input). If the TRIS bit is would be a NOP.
cleared (output), the digital output level (VOH or VOL) is
converted. EXAMPLE 7-1: PORT WRITE/READ
When the PORT register is read, all pins configured as EXAMPLE
analog input channels are read as cleared (a low level). MOV #0xF0, W0; Configure PORTB<7:4>
; as inputs
Pins configured as digital inputs will not convert an
MOV W0, TRISB; and PORTB<3:0> as outputs
analog input. Analog levels on any pin that is defined as
NOP ; additional instruction cycle
a digital input (including the ANx pins) may cause the btss PORTB, #7; bit test RB7 and skip if set
input buffer to consume the current that exceeds
device specifications.

DS70139F-page 60 © 2008 Microchip Technology Inc.

 TABLE 7-1: PORTB REGISTER MAP FOR dsPIC30F2011/3012
© 2008 Microchip Technology Inc.

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISB 02C6 — — — — — — — — TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 1111 1111
PORTB 02C8 — — — — — — — — RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB — — — — — — — — LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’

TABLE 7-2: PORTB REGISTER MAP FOR dsPIC30F2012/3013

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISB 02C6 — — — — — — TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0011 1111 1111
PORTB 02C8 — — — — — — RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

dsPIC30F2011/2012/3012/3013
LATB 02CB — — — — — — LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’

TABLE 7-3: PORTC REGISTER MAP FOR dsPIC30F2011/2012/3012/3013

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000

PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’

TABLE 7-4: PORTD REGISTER MAP FOR dsPIC30F2011/3012

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISD 02D2 — — — — — — — — — — — — — — — TRISD0 0000 0000 0000 0001

PORTD 02D4 — — — — — — — — — — — — — — — RD0 0000 0000 0000 0000
LATD 02D6 — — — — — — — — — — — — — — — LATD0 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
DS70139F-page 61
 TABLE 7-5: PORTD REGISTER MAP FOR dsPIC30F2012/3013
DS70139F-page 62

dsPIC30F2011/2012/3012/3013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISD 02D2 — — — — — — TRISD9 TRISD8 — — — — — — — — 0000 0011 0000 0000

PORTD 02D4 — — — — — — RD9 RD8 — — — — — — — — 0000 0000 0000 0000
LATD 02D6 — — — — — — LATD9 LATD8 — — — — — — — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’

TABLE 7-6: PORTF REGISTER MAP FOR dsPIC30F2012/3013

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

TRISF 02DE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 0000 0000 0111 1100
PORTF 02E0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 — — 0000 0000 0000 0000
LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: The dsPIC30F2011/3012 devices do not have TRISF, PORTF, or LATF.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
7.3 Input Change Notification Module
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor, in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in Sleep mode,
when the clocks are disabled. There are up to 10
external signals (CN0 through CN7, CN17 and CN18)
that may be selected (enabled) for generating an
interrupt request on a change of state.

TABLE 7-7: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2011/3012 (BITS 7-0)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’

TABLE 7-8: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2012/3013 (BITS 7-0)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 — — — — — CN18IE CN17IE — 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 — — — — — CN18PUE CN17PUE — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

© 2008 Microchip Technology Inc. DS70139F-page 63

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 64 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
8.0 INTERRUPTS • INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
Note: This data sheet summarizes features of these two registers. INTCON1 contains the
this group of dsPIC30F devices and is not control and status flags for the processor
intended to be a complete reference exceptions. The INTCON2 register controls the
source. For more information on the CPU, external interrupt request signal behavior and the
peripherals, register descriptions and use of the alternate vector table.
general device functionality, refer to the Note: Interrupt flag bits get set when an interrupt
“dsPIC30F Family Reference Manual” condition occurs, regardless of the state of
(DS70046). For more information on the its corresponding enable bit. User
device instruction set and programming, software should ensure the appropriate
refer to the “dsPIC30F/33F Programmer’s interrupt flag bits are clear prior to
Reference Manual” (DS70157). enabling an interrupt.
The dsPIC30F sensor family has up to 21 interrupt All interrupt sources can be user assigned to one of 7
sources and 4 processor exceptions (traps) which must priority levels, 1 through 7, via the IPCx registers. Each
be arbitrated based on a priority scheme. interrupt source is associated with an interrupt vector,
The CPU is responsible for reading the Interrupt Vector as shown in Table 8-1. Levels 7 and 1 represent the
Table (IVT) and transferring the address contained in highest and lowest maskable priorities, respectively.
the interrupt vector to the program counter. The Note: Assigning a priority level of ‘0’ to an
interrupt vector is transferred from the program data interrupt source is equivalent to disabling
bus into the program counter via a 24-bit wide that interrupt.
multiplexer on the input of the program counter.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
The Interrupt Vector Table (IVT) and Alternate Interrupt interrupts is prevented. Thus, if an interrupt is currently
Vector Table (AIVT) are placed near the beginning of being serviced, processing of a new interrupt is
program memory (0x000004). The IVT and AIVT are prevented even if the new interrupt is of higher priority
shown in Figure 8-1. than the one currently being serviced.
The interrupt controller is responsible for
Note: The IPL bits become read-only whenever
pre-processing the interrupts and processor
the NSTDIS bit has been set to ‘1’.
exceptions before they are presented to the processor
core. The peripheral interrupts and traps are enabled, Certain interrupts have specialized control bits for
prioritized and controlled using centralized Special features like edge or level triggered interrupts,
Function Registers: interrupt-on-change, etc. Control of these features
remains within the peripheral module which generates
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
the interrupt.
All interrupt request flags are maintained in these
three registers. The flags are set by their The DISI instruction can be used to disable the
respective peripherals or external signals and processing of interrupts of priorities 6 and lower for a
they are cleared via software. certain number of instructions, during which the DISI bit
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0> (INTCON2<14>) remains set.
All interrupt enable control bits are maintained in When an interrupt is serviced, the PC is loaded with the
these three registers. These control bits are used address stored in the vector location in program
to individually enable interrupts from the memory that corresponds to the interrupt. There are 63
peripherals or external signals. different vectors within the IVT (refer to Table 8-1).
• IPC0<15:0>... IPC10<7:0> These vectors are contained in locations 0x000004
The user assignable priority level associated with through 0x0000FE of program memory (refer to
each of these 41 interrupts is held centrally in Table 8-1). These locations contain 24-bit addresses,
these eleven registers. and in order to preserve robustness, an address error
• IPL<3:0> trap takes place if the PC attempts to fetch any of these
The current CPU priority level is explicitly stored words during normal execution. This prevents
in the IPL bits. IPL<3> is present in the CORCON execution of random data as a result of accidentally
register, whereas IPL<2:0> are present in the decrementing a PC into vector space, accidentally
STATUS register (SR) in the processor core. mapping a data space address into vector space, or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space also generates an
address error trap.

© 2008 Microchip Technology Inc. DS70139F-page 65

dsPIC30F2011/2012/3012/3013
8.1 Interrupt Priority TABLE 8-1: INTERRUPT VECTOR TABLE
The user-assignable interrupt priority (IP<2:0>) bits for INT Vector
Interrupt Source
each individual interrupt source are located in the Number Number
LS 3 bits of each nibble within the IPCx register(s). Bit Highest Natural Order Priority
3 of each nibble is not used and is read as a ‘0’. These 0 8 INT0 — External Interrupt 0
bits define the priority level assigned to a particular 1 9 IC1 — Input Capture 1
interrupt by the user.
2 10 OC1 — Output Compare 1
Note: The user-assignable priority levels start at 3 11 T1 — Timer 1
0 as the lowest priority and level 7 as the 4 12 IC2 — Input Capture 2
highest priority. 5 13 OC2 — Output Compare 2
Natural Order Priority is determined by the position of 6 14 T2 — Timer 2
an interrupt in the vector table, and only affects 7 15 T3 — Timer 3
interrupt operation when multiple interrupts with the 8 16 SPI1
same user-assigned priority become pending at the
9 17 U1RX — UART1 Receiver
same time.
10 18 U1TX — UART1 Transmitter
Table 8-1 lists the interrupt numbers and interrupt 11 19 ADC — ADC Convert Done
sources for the dsPIC30F2011/2012/3012/3013
12 20 NVM — NVM Write Complete
devices and their associated vector numbers.
13 21 SI2C — I2C™ Slave Interrupt
Note 1: The natural order priority scheme has 0 14 22 MI2C — I2C Master Interrupt
as the highest priority and 53 as the 15 23 Input Change Interrupt
lowest priority.
16 24 INT1 — External Interrupt 1
2: The natural order priority number is the 17-22 25-30 Reserved
same as the INT number.
23 31 INT2 — External Interrupt 2
The ability for the user to assign every interrupt to one 24 32 U2RX* — UART2 Receiver
of seven priority levels means that the user can assign 25 33 U2TX* — UART2 Transmitter
a very high overall priority level to an interrupt with a
26-41 34-49 Reserved
low natural order priority. For example, the PLVD
42 50 LVD — Low-Voltage Detect
(Low Voltage Detect) can be given a priority of 7. The
INT0 (External Interrupt 0) may be assigned to priority 43-53 51-61 Reserved
level 1, thus giving it a very low effective priority. Lowest Natural Order Priority
* Only the dsPIC30F3013 has UART2 and the U2RX,
U2TX interrupts. These locations are reserved for
the dsPIC30F2011/2012/3012.

DS70139F-page 66 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
8.2 Reset Sequence 8.3 Traps
A Reset is not a true exception because the interrupt Traps can be considered as non-maskable interrupts
controller is not involved in the Reset process. The indicating a software or hardware error, which adhere
processor initializes its registers in response to a Reset to a predefined priority as shown in Figure 8-1. They
which forces the PC to zero. The processor then begins are intended to provide the user a means to correct
program execution at location 0x000000. A GOTO erroneous operation during debug and when operating
instruction is stored in the first program memory within the application.
location immediately followed by the address target for
Note: If the user does not intend to take
the GOTO instruction. The processor executes the GOTO
corrective action in the event of a trap
to the specified address and then begins operation at
error condition, these vectors must be
the specified target (start) address.
loaded with the address of a default
8.2.1 RESET SOURCES handler that contains the RESET instruc-
tion. If, on the other hand, one of the vec-
In addition to external Reset and Power-on Reset tors containing an invalid address is
(POR), there are 6 sources of error conditions which called, an address error trap is generated.
‘trap’ to the Reset vector.
Note that many of these trap conditions can only be
• Watchdog Time-out: detected when they occur. Consequently, the
The watchdog has timed out, indicating that the questionable instruction is allowed to complete prior to
processor is no longer executing the correct flow trap exception processing. If the user chooses to
of code. recover from the error, the result of the erroneous
• Uninitialized W Register Trap: action that caused the trap may have to be corrected.
An attempt to use an uninitialized W register as
There are 8 fixed priority levels for traps: Level 8
an Address Pointer causes a Reset.
through Level 15, which implies that the IPL3 is always
• Illegal Instruction Trap: set during processing of a trap.
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a If the user is not currently executing a trap, and he sets
fetch of an illegal instruction does not result in an the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
illegal instruction trap if that instruction is flushed interrupts are disabled, but traps can still be processed.
prior to execution due to a flow change.
8.3.1 TRAP SOURCES
• Brown-out Reset (BOR):
A momentary dip in the power supply to the The following traps are provided with increasing
device has been detected which may result in priority. However, since all traps can be nested, priority
malfunction. has little effect.
• Trap Lockout:
Math Error Trap:
Occurrence of multiple trap conditions
simultaneously causes a Reset. The math error trap executes under the following three
circumstances:
1. If an attempt is made to divide by zero, the
divide operation is aborted on a cycle boundary
and the trap is taken.
2. If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3. If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled.
4. If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap occurs.

© 2008 Microchip Technology Inc. DS70139F-page 67

dsPIC30F2011/2012/3012/3013
Address Error Trap: Stack Error Trap:
This trap is initiated when any of the following This trap is initiated under the following conditions:
circumstances occurs: • The Stack Pointer is loaded with a value which is
• A misaligned data word access is attempted. greater than the (user programmable) limit value
• A data fetch from our unimplemented data written into the SPLIM register (stack overflow).
memory location is attempted. • The Stack Pointer is loaded with a value which is
• A data access of an unimplemented program less than 0x0800 (simple stack underflow).
memory location is attempted.
Oscillator Fail Trap:
• An instruction fetch from vector space is
attempted. This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
Note: In the MAC class of instructions, wherein
the data space is split into X and Y data
8.3.2 HARD AND SOFT TRAPS
space, unimplemented X space includes
all of Y space, and unimplemented Y It is possible that multiple traps can become active
space includes all of X space. within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
5. Execution of a “BRA #literal” instruction or a
fixed priority shown in Figure 8-2 is implemented,
“GOTO #literal” instruction, where literal
which may require the user to check if other traps are
is an unimplemented program memory address.
pending, in order to completely correct the Fault.
6. Executing instructions after modifying the PC to
point the unimplemented program memory Soft traps include exceptions of priority level 8 through
addresses. The PC may be modified by loading level 11, inclusive. The arithmetic error trap (level 11)
a value into the stack and executing a RETURN falls into this category of traps.
instruction. Hard traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type can continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict occurs.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.

DS70139F-page 68 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 8-1: TRAP VECTORS FIGURE 8-2: INTERRUPT STACK
FRAME
Reset - GOTO Instruction 0x000000
Reset - GOTO Address 0x000002 0x0000 15 0
Reserved 0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector

Stack Grows Towards

Stack Error Trap Vector
Decreasing

Math Error Trap Vector

Higher Address
Priority

IVT Reserved Vector

Reserved Vector
Reserved Vector
Interrupt 0 Vector 0x000014 PC<15:0> W15 (before CALL)
Interrupt 1 Vector SRL IPL3 PC<22:16>
—
— <Free Word> W15 (after CALL)
—
Interrupt 52 Vector
Interrupt 53 Vector 0x00007E POP : [--W15]
Reserved 0x000080
Reserved 0x000082 PUSH: [W15++]
Reserved 0x000084
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
AIVT Reserved Vector Note 1: The user can always lower the priority
Reserved Vector level by writing a new value into SR. The
Reserved Vector
Interrupt 0 Vector 0x000094 Interrupt Service Routine must clear the
Interrupt 1 Vector interrupt flag bits in the IFSx register
—
— before lowering the processor interrupt
— priority, in order to avoid recursive
Interrupt 52 Vector
Interrupt 53 Vector 0x0000FE interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being
8.4 Interrupt Sequence processed. It is set only during execution
of traps.
All interrupt event flags are sampled in the beginning of
The RETFIE (return from interrupt) instruction unstacks
each instruction cycle by the IFSx registers. A pending
the program counter and STATUS registers to return
Interrupt Request (IRQ) is indicated by the flag bit
the processor to its state prior to the interrupt
being equal to a ‘1’ in an IFSx register. The IRQ causes
sequence.
an interrupt to occur if the corresponding bit in the
Interrupt Enable (IECx) register is set. For the
remainder of the instruction cycle, the priorities of all 8.5 Alternate Vector Table
pending interrupt requests are evaluated. In program memory, the Interrupt Vector Table (IVT) is
If there is a pending IRQ with a priority level greater followed by the Alternate Interrupt Vector Table (AIVT),
than the current processor priority level in the IPL bits, as shown in Figure 8-1. Access to the alternate vector
the processor is interrupted. table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and
The processor then stacks the current program counter exception processes use the alternate vectors instead
and the low byte of the processor STATUS register of the default vectors. The alternate vectors are
(SRL), as shown in Figure 8-2. The low byte of the organized in the same manner as the default vectors.
STATUS register contains the processor priority level at The AIVT supports emulation and debugging efforts by
the time prior to the beginning of the interrupt cycle. providing a means to switch between an application
The processor then loads the priority level for this and a support environment without requiring the
internsrupt into the STATUS register. This action interrupt vectors to be reprogrammed. This feature also
disables all lower priority interrupts until the completion enables switching between applications for evaluation
of the Interrupt Service Routine. of different software algorithms at run time.
If the AIVT is not required, the program memory
allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.

© 2008 Microchip Technology Inc. DS70139F-page 69

dsPIC30F2011/2012/3012/3013
8.6 Fast Context Saving 8.7 External Interrupt Requests
A context saving option is available using shadow The interrupt controller supports three external
registers. Shadow registers are provided for the DC, N, interrupt request signals, INT0-INT2. These inputs are
OV, Z and C bits in SR, and the registers W0 through edge sensitive; they require a low-to-high or a
W3. The shadows are only one level deep. The shadow high-to-low transition to generate an interrupt request.
registers are accessible using the PUSH.S and POP.S The INTCON2 register has three bits, INT0EP-INT2EP,
instructions only. that select the polarity of the edge detection circuitry.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current 8.8 Wake-up from Sleep and Idle
value of the aforementioned registers into their
respective shadow registers. The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
If an ISR of a certain priority uses the PUSH.S and Idle mode is active when the interrupt is generated.
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc- If an enabled interrupt request of sufficient priority is
tions. Users must save the key registers in software received by the interrupt controller, then the standard
during a lower priority interrupt if the higher priority ISR interrupt request is presented to the processor. At the
uses fast context saving. same time, the processor wakes up from Sleep or Idle
and begins execution of the Interrupt Service Routine
(ISR) needed to process the interrupt request.

DS70139F-page 70 © 2008 Microchip Technology Inc.

 TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP
© 2008 Microchip Technology Inc.

SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 — — — — — — — — INT2IF — — — — — — INT1IF 0000 0000 0000 0000
IFS2 0088 — — — — — LVDIF — — — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E — — — — — — — — INT2IE — — — — — — INT1IE 0000 0000 0000 0000
IEC2 0090 — — — — — LVDIE — — — — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

dsPIC30F2011/2012/3012/3013
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0000 0000 0000 0100
IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0000 0000 0000
IPC6 00A0 — — — — — — — — — 1 0 0 — 1 0 0 0000 0000 0100 0100
IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC10 00A8 — — — — — LVDIP<2:0> — — — — — — — — 0000 0100 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70139F-page 71
 TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP
DS70139F-page 72

dsPIC30F2011/2012/3012/3013
SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 — — — — — — U2TXIF U2RXIF INT2IF — — — — — — INT1IF 0000 0000 0000 0000
IFS2 0088 — — — — — LVDIF — — — — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E — — — — — U2TXIE U2RXIE INT2IE — — — — — — INT1IE 0000 0000 0000 0000
IEC2 0090 — — — — — LVDIE — — — — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0000 0000 0000 0100
IPC5 009E — INT2IP<2:0> — — — — — — — — — 0100 0000 0000 0000
IPC6 00A0 — — — — — — — — — U2TXIP<2:0> — U2RXIP<2:0> 0000 0000 0100 0100
IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC10 00A8 — — — — — LVDIP<2:0> — — — — — — — — 0000 0100 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
9.0 TIMER1 MODULE These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
Note: This data sheet summarizes features of presents a block diagram of the 16-bit timer module.
this group of dsPIC30F devices and is not 16-bit Timer Mode: In the 16-bit Timer mode, the timer
intended to be a complete reference increments on every instruction cycle up to a match
source. For more information on the CPU, value preloaded into the Period register PR1, then
peripherals, register descriptions and resets to ‘0’ and continues to count.
general device functionality, refer to the
“dsPIC30F Family Reference Manual” When the CPU goes into the Idle mode, the timer stops
(DS70046). incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer module logic resumes the incre-
This section describes the 16-bit general purpose menting sequence on termination of CPU Idle mode.
Timer1 module and associated operational modes.
16-bit Synchronous Counter Mode: In the 16-bit
Figure 9-1 depicts the simplified block diagram of the
Synchronous Counter mode, the timer increments on
16-bit Timer1 module. The following sections provide
the rising edge of the applied external clock signal
detailed descriptions including setup and Control
which is synchronized with the internal phase clocks.
registers, along with associated block diagrams for the
The timer counts up to a match value preloaded in PR1,
operational modes of the timers.
then resets to ‘0’ and continues.
The Timer1 module is a 16-bit timer that serves as the
When the CPU goes into the Idle mode, the timer stops
time counter for the real-time clock or operates as a
incrementing unless the respective TSIDL bit = 0. If
free-running interval timer/counter. The 16-bit timer has
TSIDL = 1, the timer module logic resumes the
the following modes:
incrementing sequence upon termination of the CPU
• 16-bit Timer Idle mode.
• 16-bit Synchronous Counter
16-bit Asynchronous Counter Mode: In the 16-bit
• 16-bit Asynchronous Counter Asynchronous Counter mode, the timer increments on
These operational characteristics are supported: every rising edge of the applied external clock signal.
• Timer gate operation The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep When the timer is configured for the Asynchronous
modes mode of operation and the CPU goes into the Idle
• Interrupt on 16-bit Period register match or falling mode, the timer stops incrementing if TSIDL = 1.
edge of external gate signal

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

PR1

Equal
Comparator x 16 TSYNC

1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
TGATE

Q CK
TCS

TGATE TCKPS<1:0>
SOSCO/ TON 2
T1CK 1x

Gate Prescaler
LPOSCEN 1, 8, 64, 256
Sync 01

SOSCI
TCY 00

© 2008 Microchip Technology Inc. DS70139F-page 73

dsPIC30F2011/2012/3012/3013
9.1 Timer Gate Operation 9.4 Timer Interrupt
The 16-bit timer can be placed in the Gated Time The 16-bit timer has the ability to generate an
Accumulation mode. This mode allows the internal TCY interrupt-on-period match. When the timer count
to increment the respective timer when the gate input matches the Period register, the T1IF bit is asserted and
signal (T1CK pin) is asserted high. Control bit, an interrupt is generated, if enabled. The T1IF bit must be
TGATE (T1CON<6>), must be set to enable this mode. cleared in software. The timer interrupt flag, T1IF, is
The timer must be enabled (TON = 1) and the timer located in the IFS0 Control register in the interrupt
clock source set to internal (TCS = 0). controller.
When the CPU goes into Idle mode, the timer stops When the Gated Time Accumulation mode is enabled,
incrementing unless TSIDL = 0. If TSIDL = 1, the timer an interrupt is also generated on the falling edge of the
resumes the incrementing sequence upon termination gate signal (at the end of the accumulation cycle).
of the CPU Idle mode. Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T1IE. The timer
9.2 Timer Prescaler interrupt enable bit is located in the IEC0 Control
register in the interrupt controller.
The input clock (FOSC/4 or external clock) to the 16-bit
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits, TCKPS<1:0> (T1CON<5:4>). 9.5 Real-Time Clock
The prescaler counter is cleared when any of the Timer1, when operating in Real-Time Clock (RTC)
following occurs: mode, provides time of day and event time-stamping
• a write to the TMR1 register capabilities. Key operational features of the RTC are:
• a write to the T1CON register • Operation from 32 kHz LP oscillator
• device Reset, such as POR and BOR • 8-bit prescaler
However, if the timer is disabled (TON = 0), then the • Low power
timer prescaler cannot be reset since the prescaler • Real-Time Clock interrupts
clock is halted.
These operating modes are determined by setting the
TMR1 is not cleared when T1CON is written. It is appropriate bit(s) in the T1CON Control register.
cleared by writing to the TMR1 register.
FIGURE 9-2: RECOMMENDED
9.3 Timer Operation During Sleep COMPONENTS FOR
Mode TIMER1 LP OSCILLATOR
The timer operates during CPU Sleep mode, if: RTC
• The timer module is enabled (TON = 1), and C1
• The timer clock source is selected as external
SOSCI
(TCS = 1), and
• The TSYNC bit (T1CON<2>) is asserted to a logic 32.768 kHz dsPIC30FXXXX
‘0’ which defines the external clock source as XTAL
asynchronous. SOSCO
When all three conditions are true, the timer continues C2 R
to count up to the Period register and be reset to
0x0000.
When a match between the timer and the Period C1 = C2 = 18 pF; R = 100K
register occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.

DS70139F-page 74 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
9.5.1 RTC OSCILLATOR OPERATION 9.5.2 RTC INTERRUPTS
When the TON = 1, TCS = 1 and TGATE = 0, the timer When an interrupt event occurs, the respective interrupt
increments on the rising edge of the 32 kHz LP oscilla- flag, T1IF, is asserted and an interrupt is generated if
tor output signal, up to the value specified in the Period enabled. The T1IF bit must be cleared in software. The
register and is then reset to ‘0’. respective Timer interrupt flag, T1IF, is located in the
The TSYNC bit must be asserted to a logic ‘0’ IFS0 register in the interrupt controller.
(Asynchronous mode) for correct operation. Enabling an interrupt is accomplished via the
Enabling LPOSCEN (OSCCON<1>) disables the respective timer interrupt enable bit, T1IE. The timer
normal Timer and Counter modes and enables a timer interrupt enable bit is located in the IEC0 Control
carry-out wake-up event. register in the interrupt controller.

When the CPU enters Sleep mode, the RTC continues

to operate, provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.

© 2008 Microchip Technology Inc. DS70139F-page 75

 TABLE 9-1: TIMER1 REGISTER MAP
DS70139F-page 76

dsPIC30F2011/2012/3012/3013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu

PR1 0102 Period Register 1 1111 1111 1111 1111
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the ls word
and Timer3 is the ms word of the 32-bit timer.
Note: This data sheet summarizes features of
Note: For 32-bit timer operation, T3CON control
this group of dsPIC30F devices and is not
bits are ignored. Only T2CON control bits
intended to be a complete reference
are used for setup and control. Timer2
source. For more information on the CPU,
clock and gate inputs are utilized for the
peripherals, register descriptions and
32-bit timer module, but an interrupt is
general device functionality, refer to the
generated with the Timer3 interrupt flag
“dsPIC30F Family Reference Manual
(T3IF) and the interrupt is enabled with the
“(DS70046).
Timer3 interrupt enable bit (T3IE).
This section describes the 32-bit general purpose 16-bit Timer Mode: In the 16-bit mode, Timer2 and
Timer module (Timer2/3) and associated Operational Timer3 can be configured as two independent 16-bit
modes. Figure 10-1 depicts the simplified block timers. Each timer can be set up in either 16-bit Timer
diagram of the 32-bit Timer2/3 module. Figure 10-2 mode or 16-bit Synchronous Counter mode. See
and Figure 10-3 show Timer2/3 configured as two Section 9.0 “Timer1 Module” for details on these two
independent 16-bit timers, Timer2 and Timer3, operating modes.
respectively.
The only functional difference between Timer2 and
The Timer2/3 module is a 32-bit timer (which can be Timer3 is that Timer2 provides synchronization of the
configured as two 16-bit timers) with selectable clock prescaler output. This is useful for high frequency
operating modes. These timers are utilized by other external clock inputs.
peripheral modules, such as:
32-bit Timer Mode: In the 32-bit Timer mode, the timer
• Input Capture increments on every instruction cycle, up to a match
• Output Compare/Simple PWM value preloaded into the combined 32-bit Period
The following sections provide a detailed description, register PR3/PR2, then resets to ‘0’ and continues to
including setup and Control registers, along with count.
associated block diagrams for the operational modes of For synchronous 32-bit reads of the Timer2/Timer3
the timers. pair, reading the ls word (TMR2 register) causes the ms
The 32-bit timer has the following modes: word to be read and latched into a 16-bit holding
register, termed TMR3HLD.
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except For synchronous 32-bit writes, the holding register
Asynchronous Counter mode) (TMR3HLD) must first be written to. When followed by
• Single 32-bit timer operation a write to the TMR2 register, the contents of TMR3HLD
is transferred and latched into the MSB of the 32-bit
• Single 32-bit synchronous counter
timer (TMR3).
Further, the following operational characteristics are
32-bit Synchronous Counter Mode: In the 32-bit
supported:
Synchronous Counter mode, the timer increments on
• ADC event trigger the rising edge of the applied external clock signal
• Timer gate operation which is synchronized with the internal phase clocks.
• Selectable prescaler settings The timer counts up to a match value preloaded in the
combined 32-bit period register, PR3/PR2, then resets
• Timer operation during Idle and Sleep modes
to ‘0’ and continues.
• Interrupt on a 32-bit period register match
When the timer is configured for the Synchronous
These operating modes are determined by setting the Counter mode of operation and the CPU goes into the
appropriate bit(s) in the 16-bit T2CON and T3CON Idle mode, the timer stops incrementing unless the
SFRs. TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic resumes the incrementing sequence
upon termination of the CPU Idle mode.

© 2008 Microchip Technology Inc. DS70139F-page 77

dsPIC30F2011/2012/3012/3013
FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>

TMR3HLD
16
16
Write TMR2
Read TMR2

16

Reset
TMR3 TMR2 Sync

MSB LSB
ADC Event Trigger
Comparator x 32
Equal

PR3 PR2

0
T3IF
Event Flag
1 Q D TGATE (T2CON<6>)
Q CK
TGATE
(T2CON<6>)

TGATE
TCS

TCKPS<1:0>
TON 2
T2CK 1x

Gate Prescaler
Sync 01 1, 8, 64, 256

TCY 00

Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.

DS70139F-page 78 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM

PR2

Equal
Comparator x 16

TMR2 Sync
Reset

0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE

TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1x

Gate Prescaler
Sync 01 1, 8, 64, 256

TCY 00

FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM

PR3

ADC Event Trigger Equal

Comparator x 16

TMR3
Reset

0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS

TCKPS<1:0>
TON 2
T3CK Sync 1x

Prescaler
01 1, 8, 64, 256

TCY 00

© 2008 Microchip Technology Inc. DS70139F-page 79

dsPIC30F2011/2012/3012/3013
10.1 Timer Gate Operation 10.4 Timer Operation During Sleep
The 32-bit timer can be placed in the Gated Time
Mode
Accumulation mode. This mode allows the internal TCY The timer does not operate during CPU Sleep mode
to increment the respective timer when the gate input because the internal clocks are disabled.
signal (T2CK pin) is asserted high. Control bit, TGATE
(T2CON<6>), must be set to enable this mode. When 10.5 Timer Interrupt
in this mode, Timer2 is the originating clock source.
The TGATE setting is ignored for Timer3. The timer The 32-bit timer module can generate an
must be enabled (TON = 1) and the timer clock source interrupt-on-period match or on the falling edge of the
set to internal (TCS = 0). external gate signal. When the 32-bit timer count
The falling edge of the external signal terminates the matches the respective 32-bit period register, or the
count operation but does not reset the timer. The user falling edge of the external “gate” signal is detected, the
must reset the timer in order to start counting from zero. T3IF bit (IFS0<7>) is asserted and an interrupt is
generated if enabled. In this mode, the T3IF interrupt
flag is used as the source of the interrupt. The T3IF bit
10.2 ADC Event Trigger must be cleared in software.
When a match occurs between the 32-bit timer Enabling an interrupt is accomplished via the
(TMR3/TMR2) and the 32-bit combined period register respective timer interrupt enable bit, T3IE (IEC0<7>).
(PR3/PR2), or between the 16-bit timer TMR3 and the
16-bit period register PR3, a special ADC trigger event
signal is generated by Timer3.

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits, TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler
operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• a write to the T2CON/T3CON register
• device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.

DS70139F-page 80 © 2008 Microchip Technology Inc.

 TABLE 10-1: TIMER2/3 REGISTER MAP
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu
TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu
PR2 010C Period Register 2 1111 1111 1111 1111
PR3 010E Period Register 3 1111 1111 1111 1111
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013
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dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 82 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
11.0 INPUT CAPTURE MODULE • Interrupt on input capture event
These operating modes are determined by setting the
Note: This data sheet summarizes features of appropriate bits in the IC1CON and IC2CON registers.
this group of dsPIC30F devices and is not The dsPIC30F2011/2012/3012/3013 devices have two
intended to be a complete reference capture channels.
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
11.1 Simple Capture Event Mode
“dsPIC30F Family Reference Manual” The simple capture events in the dsPIC30F product
(DS70046). family are:
This section describes the input capture module and • Capture every falling edge
associated operational modes. The features provided • Capture every rising edge
by this module are useful in applications requiring • Capture every 4th rising edge
frequency (period) and pulse measurement. • Capture every 16th rising edge
Figure 11-1 depicts a block diagram of the input • Capture every rising and falling edge
capture module. Input capture is useful for such modes These simple Input Capture modes are configured by
as: setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).
• Frequency/Period/Pulse Measurements
11.1.1 CAPTURE PRESCALER
• Additional Sources of External Interrupts
There are four input capture prescaler settings
Important operational features of the input capture specified by bits ICM<2:0> (ICxCON<2:0>). Whenever
module are: the capture channel is turned off, the prescaler counter
• Simple Capture Event mode is cleared. In addition, any Reset clears the prescaler
• Timer2 and Timer3 mode selection counter.

FIGURE 11-1: INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module T2_CNT T3_CNT

16 16

ICTMR
ICx pin 1 0
Prescaler Clock Edge FIFO
1, 4, 16 Synchronizer Detection R/W
Logic Logic

3 ICM<2:0>
Mode Select ICxBUF

ICBNE, ICOV

ICI<1:0>
Interrupt
ICxCON Logic

Data Bus Set Flag

ICxIF

Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture
channel (1 or 2).

© 2008 Microchip Technology Inc. DS70139F-page 83

dsPIC30F2011/2012/3012/3013
11.1.2 CAPTURE BUFFER OPERATION 11.2 Input Capture Operation During
Each capture channel has an associated FIFO buffer Sleep and Idle Modes
which is four 16-bit words deep. There are two status
An input capture event generates a device wake-up or
flags which provide status on the FIFO buffer:
interrupt, if enabled, if the device is in CPU Idle or Sleep
• ICBNE — Input Capture Buffer Not Empty mode.
• ICOV — Input Capture Overflow Independent of the timer being enabled, the input
The ICBNE is set on the first input capture event and capture module wakes up from the CPU Sleep or Idle
remains set until all capture events have been read mode when a capture event occurs if ICM<2:0> = 111
from the FIFO. As each word is read from the FIFO, the and the interrupt enable bit is asserted. The same
remaining words are advanced by one position within wake-up can generate an interrupt if the conditions for
the buffer. processing the interrupt have been satisfied.
The wake-up feature is useful as a method of adding
In the event that the FIFO is full with four capture
extra external pin interrupts.
events, and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition occurs and the ICOV
11.2.1 INPUT CAPTURE IN CPU SLEEP
bit is set to a logic ‘1’. The fifth capture event is lost and
MODE
is not stored in the FIFO. No additional events are
captured until all four events have been read from the CPU Sleep mode allows input capture module
buffer. operation with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable and the input
If a FIFO read is performed after the last read and no
capture module can only function as an external
new capture event has been received, the read will
interrupt source.
yield indeterminate results.
The capture module must be configured for interrupt
11.1.3 TIMER2 AND TIMER3 SELECTION only on rising edge (ICM<2:0> = 111) in order for the
MODE input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
The input capture module consists of up to 8 input
not applicable in this mode.
capture channels. Each channel can select between
one of two timers for the time base, Timer2 or Timer3.
11.2.2 INPUT CAPTURE IN CPU IDLE
Selection of the timer resource is accomplished MODE
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
CPU Idle mode allows input capture module operation
default timer resource available for the input capture
with full functionality. In the CPU Idle mode, the Interrupt
module.
mode selected by the ICI<1:0> bits is applicable, as well
11.1.4 HALL SENSOR MODE as the 4:1 and 16:1 capture prescale settings which are
defined by control bits ICM<2:0>. This mode requires
When the input capture module is set for capture on the selected timer to be enabled. Moreover, the ICSIDL
every edge, rising and falling, ICM<2:0> = 001, the bit must be asserted to a logic ‘0’.
following operations are performed by the input capture
logic: If the input capture module is defined as
ICM<2:0> = 111 in CPU Idle mode, the input capture
• The input capture interrupt flag is set on every pin serves only as an external interrupt pin.
edge, rising and falling.
• The interrupt on Capture mode setting bits, 11.3 Input Capture Interrupts
ICI<1:0>, is ignored since every capture
generates an interrupt. The input capture channels have the ability to generate
• A capture overflow condition is not generated in an interrupt based on the selected number of capture
this mode. events. The selection number is set by control
bits, ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx register.
Enabling an interrupt is accomplished via the
respective capture channel interrupt enable (ICxIE) bit.
The capture interrupt enable bit is located in the
corresponding IEC Control register.

DS70139F-page 84 © 2008 Microchip Technology Inc.

 TABLE 11-1: INPUT CAPTURE REGISTER MAP
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu
IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013
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NOTES:

DS70139F-page 86 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
12.0 OUTPUT COMPARE MODULE Figure 12-1 depicts a block diagram of the output
compare module.
Note: This data sheet summarizes features of The key operational features of the output compare
this group of dsPIC30F devices and is not module include:
intended to be a complete reference
source. For more information on the CPU, • Timer2 and Timer3 Selection mode
peripherals, register descriptions and • Simple Output Compare Match mode
general device functionality, refer to the • Dual Output Compare Match mode
“dsPIC30F Family Reference Manual” • Simple PWM mode
(DS70046). • Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
This section describes the output compare module and
These operating modes are determined by setting the
associated operational modes. The features provided
appropriate bits in the 16-bit OC1CON and OC2CON
by this module are useful in applications requiring
registers. The dsPIC30F2011/2012/3012/3013 devices
operational modes, such as:
have 2 compare channels.
• Generation of Variable Width Output Pulses
OCxRS and OCxR in Figure 12-1 represent the Dual
• Power Factor Correction

FIGURE 12-1: OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR Output S Q
Logic R
OCx
Output
3
Enable
OCM<2:0>
Comparator Mode Select

OCTSEL OCFA
0 1 0 1 (for x = 1, 2, 3 or 4)

From GP
Timer Module

TMR2<15:0 TMR3<15:0> T2P2_MATCH T3P3_MATCH

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channel (1 or 2).

© 2008 Microchip Technology Inc. DS70139F-page 87

dsPIC30F2011/2012/3012/3013
12.1 Timer2 and Timer3 Selection Mode 12.3.2 CONTINUOUS PULSE MODE
Each output compare channel can select between one For the user to configure the module for the generation
of two 16-bit timers, Timer2 or Timer3. of a continuous stream of output pulses, the following
steps are required:
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource • Determine instruction cycle time TCY.
for the output compare module. • Calculate desired pulse value based on TCY.
• Calculate timer to start pulse width from timer start
12.2 Simple Output Compare Match value of 0x0000.
Mode • Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
When control bits OCM<2:0> (OCxCON<2:0>) = 001, Compare registers, respectively.
010 or 011, the selected output compare channel is
• Set Timer Period register to value equal to or
configured for one of three simple Output Compare
greater than value in OCxRS Compare register.
Match modes:
• Set OCM<2:0> = 101.
• Compare forces I/O pin low
• Enable timer, TON (TxCON<15>) = 1.
• Compare forces I/O pin high
• Compare toggles I/O pin
12.4 Simple PWM Mode
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the When control bits OCM<2:0> (OCxCON<2:0>) = 110
selected incrementing timer count. When a compare or 111, the selected output compare channel is
occurs, one of these Compare Match modes occurs. If configured for the PWM mode of operation. When
the counter resets to zero before reaching the value in configured for the PWM mode of operation, OCxR is
OCxR, the state of the OCx pin remains unchanged. the main latch (read-only) and OCxRS is the secondary
latch. This enables glitchless PWM transitions.
12.3 Dual Output Compare Match Mode The user must perform the following steps in order to
configure the output compare module for PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 100
operation:
or 101, the selected output compare channel is
configured for one of two Dual Output Compare modes, 1. Set the PWM period by writing to the appropriate
which are: period register.
• Single Output Pulse mode 2. Set the PWM duty cycle by writing to the OCxRS
register.
• Continuous Output Pulse mode
3. Configure the output compare module for PWM
12.3.1 SINGLE PULSE MODE operation.
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation
Timer, TON (TxCON<15>) = 1.
of a single output pulse, the following steps are
required (assuming timer is off):
12.4.1 INPUT PIN FAULT PROTECTION
• Determine instruction cycle time TCY. FOR PWM
• Calculate desired pulse width value based on TCY. When control bits OCM<2:0> (OCxCON<2:0>) = 111,
• Calculate time to start pulse from timer start value the selected output compare channel is again
of 0x0000. configured for the PWM mode of operation with the
• Write pulse width start and stop times into OCxR additional feature of input Fault protection. While in this
and OCxRS Compare registers (x denotes mode, if a logic ‘0’ is detected on the OCFA/B pin, the
channel 1, 2, ...,N). respective PWM output pin is placed in the high
• Set Timer Period register to value equal to or impedance input state. The OCFLT bit (OCxCON<4>)
greater than value in OCxRS Compare register. indicates whether a Fault condition has occurred. This
• Set OCM<2:0> = 100. state is maintained until both of the following events
have occurred:
• Enable timer, TON (TxCON<15>) = 1.
• The external Fault condition has been removed.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100. • The PWM mode has been re-enabled by writing
to the appropriate control bits.

DS70139F-page 88 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
12.4.2 PWM PERIOD When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
The PWM period is specified by writing to the PRx
the next increment cycle:
register. The PWM period can be calculated using
Equation 12-1. • TMRx is cleared.
• The OCx pin is set.
EQUATION 12-1: - Exception 1: If PWM duty cycle is 0x0000,
the OCx pin remains low.
PWM period = [(PRx) + 1] • 4 • TOSC •
(TMRx prescale value) - Exception 2: If duty cycle is greater than PRx,
the pin remains high.
• The PWM duty cycle is latched from OCxRS into
PWM frequency is defined as 1/[PWM period]. OCxR.
• The corresponding timer interrupt flag is set.
See Figure 12-2 for key PWM period comparisons.
Timer3 is referred to in Figure 12-2 for clarity.

FIGURE 12-2: PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3
TMR3 = PR3 T3IF = 1
T3IF = 1 (Interrupt Flag)
(Interrupt Flag) OCxR = OCxRS
OCxR = OCxRS
TMR3 = Duty Cycle TMR3 = Duty Cycle
(OCxR) (OCxR)

12.5 Output Compare Operation During 12.7 Output Compare Interrupts

CPU Sleep Mode The output compare channels have the ability to
When the CPU enters Sleep mode, all internal clocks generate an interrupt on a compare match, for
are stopped. Therefore, when the CPU enters the whichever Match mode has been selected.
Sleep state, the output compare channel drives the pin For all modes except the PWM mode, when a compare
to the active state that was observed prior to entering event occurs, the respective interrupt flag (OCxIF) is
the CPU Sleep state. asserted and an interrupt is generated if enabled. The
For example, if the pin was high when the CPU entered OCxIF bit is located in the corresponding IFS register
the Sleep state, the pin remains high. Likewise, if the and must be cleared in software. The interrupt is
pin was low when the CPU entered the Sleep state, the enabled via the respective compare interrupt enable
pin remains low. In either case, the output compare (OCxIE) bit located in the corresponding IEC Control
module resumes operation when the device wakes up. register.
For the PWM mode, when an event occurs, the
12.6 Output Compare Operation During respective timer interrupt flag (T2IF or T3IF) is asserted
CPU Idle Mode and an interrupt is generated if enabled. The IF bit is
located in the IFS0 register and must be cleared in
When the CPU enters the Idle mode, the output software. The interrupt is enabled via the respective
compare module can operate with full functionality. timer interrupt enable bit (T2IE or T3IE) located in the
The output compare channel operates during the CPU IEC0 Control register. The output compare interrupt
Idle mode if the OCSIDL bit (OCxCON<13>) is at logic flag is never set during the PWM mode of operation.
‘0’ and the selected time base (Timer2 or Timer3) is
enabled and the TSIDL bit of the selected timer is set
to logic ‘0’.

© 2008 Microchip Technology Inc. DS70139F-page 89

 TABLE 12-1: OUTPUT COMPARE REGISTER MAP
DS70139F-page 90

dsPIC30F2011/2012/3012/3013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
13.0 SPI™ MODULE Transmit writes are also double-buffered. The user
writes to SPI1BUF. When the master or slave transfer
Note: This data sheet summarizes features of is completed, the contents of the shift register
this group of dsPIC30F devices and is not (SPI1SR) are moved to the receive buffer. If any
intended to be a complete reference transmit data has been written to the buffer register, the
source. For more information on the CPU, contents of the transmit buffer are moved to SPI1SR.
peripherals, register descriptions and The received data is thus placed in SPI1BUF and the
general device functionality, refer to the transmit data in SPI1SR is ready for the next transfer.
“dsPIC30F Family Reference Manual”
Note: Both the transmit buffer (SPI1TXB) and
(DS70046).
the receive buffer (SPI1RXB) are mapped
The Serial Peripheral Interface (SPI™) module is a to the same register address, SPI1BUF.
synchronous serial interface. It is useful for
communicating with other peripheral devices, such as
EEPROMs, shift registers, display drivers and A/D
converters, or other microcontrollers. It is compatible
with Motorola's SPI and SIOP interfaces. The
dsPIC30F2011/2012/3012/3013 devices feature one
SPI module, SPI1.

13.1 Operating Function Description

Figure 13-1 is a simplified block diagram of the SPI
module, which consists of a 16-bit shift register,
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. Control register SPI1CON (not
shown) configures the module. Additionally, status
register SPI1STAT (not shown) indicates various status
conditions.
Note: See “dsPIC30F Family Reference
Manual” (DS70046) for detailed
information on the control and status
registers.
Four I/O pins comprise the serial interface:
• SDI1 (serial data input)
• SDO1 (serial data output)
• SCK1 (shift clock input or output)
• SS1 (active-low slave select).
In Master mode operation, SCK1 is a clock output. In
Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPI1SR to SDO1 pin and
simultaneously shift in data from SDI1 pin. An interrupt
is generated when the transfer is complete and the
interrupt flag bit (SPI1IF) is set. This interrupt can be
disabled through the interrupt enable bit, SPI1IE.
The receive operation is double-buffered. When a
complete byte is received, it is transferred from SPI1SR
to SPI1BUF.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF is not
completed and the new data is lost. The module will not
respond to SCL transitions while SPIROV is ‘1’, effec-
tively disabling the module until SPI1BUF is read by
user software.

© 2008 Microchip Technology Inc. DS70139F-page 91

dsPIC30F2011/2012/3012/3013
FIGURE 13-1: SPI BLOCK DIAGRAM

Internal
Data Bus
Read Write

SPIxBUF SPIxBUF

Receive Transmit

SPI1SR
SDI1 bit 0

SDO1 Shift
Clock
SS & FSYNC Clock Edge
Control Select
Control
SS1
Secondary Primary
Prescaler Prescaler FCY
1:1 – 1:8 1, 4, 16, 64
SCK1
Enable Master Clock

Figure 13-2 depicts the a master/slave connection 13.1.2 SDO1 DISABLE

between two processors. In Master mode, the clock is
A control bit, DISSDO, is provided to the SPI1CON
generated by prescaling the system clock. Data is
register to allow the SDO1 output to be disabled. This
transmitted as soon as a value is written to SPI1BUF.
will allow the SPI module to be connected in an input
The interrupt is generated at the middle of the transfer
only configuration. SDO1 can also be used for general
of the last bit.
purpose I/O.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the 13.2 Framed SPI Support
interrupt is generated when the last bit is latched. If
SS1 control is enabled, then transmission and The module supports a basic framed SPI protocol in
reception are enabled only when SS1 = low. The SDO1 Master or Slave mode. The control bit, FRMEN,
output will be disabled in SS1 mode with SS1 high. enables framed SPI support and causes the SS1 pin to
perform the Frame Synchronization Pulse (FSYNC)
The clock provided to the module is (FOSC/4). This
function. The control bit, SPIFSD, determines whether
clock is then prescaled by the primary (PPRE<1:0>)
the SS1 pin is an input or an output (i.e., whether the
and the secondary (SPRE<2:0>) prescale factors. The
module receives or generates the Frame
CKE bit determines whether transmit occurs on
Synchronization Pulse). The frame pulse is an
transition from active clock state to Idle clock state, or
active-high pulse for a single SPI clock cycle. When
vice versa. The CKP bit selects the Idle state (high or
Frame Synchronization is enabled, the data
low) for the clock.
transmission starts only on the subsequent transmit
13.1.1 WORD AND BYTE edge of the SPI clock.
COMMUNICATION
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPI1SR
for 8-bit operation, and data is transmitted out of bit 15
of the SPI1SR for 16-bit operation. In both modes, data
is shifted into bit 0 of the SPI1SR.

DS70139F-page 92 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 13-2: SPI MASTER/SLAVE CONNECTION

SPI Master SPI Slave

SDO1 SDI1

Serial Input Buffer Serial Input Buffer

(SPI1BUF) (SPI1BUF)

Shift Register SDI1 SDO1 Shift Register

(SPI1SR) (SPI1SR)

MSb LSb MSb LSb

Serial Clock
SCK1 SCK1
PROCESSOR 1 PROCESSOR 2

13.3 Slave Select Synchronization 13.5 SPI Operation During CPU Idle
The SS1 pin allows a Synchronous Slave mode. The
Mode
SPI must be configured in SPI Slave mode with SS1 When the device enters Idle mode, all clock sources
pin control enabled (SSEN = 1). When the SS1 pin is remain functional. The SPISIDL bit (SPI1STAT<13>)
low, transmission and reception are enabled and the selects if the SPI module will stop or continue on idle. If
SDOx pin is driven. When SS1 pin goes high, the SPISIDL = 0, the module will continue to operate when
SDOx pin is no longer driven. Also, the SPI module is the CPU enters Idle mode. If SPISIDL = 1, the module
resynchronized, and all counters/control circuitry are will stop when the CPU enters Idle mode.
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb
even if SS1 had been de-asserted in the middle of a
transmit/receive.

13.4 SPI Operation During CPU Sleep

Mode
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.

© 2008 Microchip Technology Inc. DS70139F-page 93

 TABLE 13-1: SPI1 REGISTER MAP
DS70139F-page 94

dsPIC30F2011/2012/3012/3013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
14.0 I2C™ MODULE 14.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • I2C slave operation with 7-bit address
intended to be a complete reference • I2C slave operation with 10-bit address
source. For more information on the CPU, • I2C master operation with 7 or 10-bit address
peripherals, register descriptions and See the I2C programmer’s model (Figure 14-1).
general device functionality, refer to the
“dsPIC30F Family Reference Manual” 14.1.2 PIN CONFIGURATION IN I2C MODE
(DS70046).
I2C has a 2-pin interface: the SCL pin is clock and the
2 SDA pin is data.
The Inter-Integrated Circuit (I C ) module provides
TM

complete hardware support for both Slave and

Multi-Master modes of the I2C serial communication 14.1.3 I2C REGISTERS
standard, with a 16-bit interface. I2CCON and I2CSTAT are control and status registers,
This module offers the following key features: respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
• I2C interface supporting both master and slave
The remaining bits of the I2CSTAT are read/write.
operation.
• I2C Slave mode supports 7 and 10-bit address. I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
• I2C Master mode supports 7 and 10-bit address.
bytes are written, or from which data bytes are read.
• I2C port allows bidirectional transfers between I2CRCV is the receive buffer as shown in Figure 14-1.
master and slaves. I2CTRN is the transmit register to which bytes are
• Serial clock synchronization for I2C port can be written during a transmit operation, as shown in
used as a handshake mechanism to suspend and Figure 14-2.
resume serial transfer (SCLREL control).
The I2CADD register holds the slave address. A Status
• I2C supports multi-master operation; detects bus bit, ADD10, indicates 10-bit Address mode. The
collision and will arbitrate accordingly. I2CBRG acts as the Baud Rate Generator reload
value.
14.1 Operating Function Description In receive operations, I2CRSR and I2CRCV together
The hardware fully implements all the master and slave form a double-buffered receiver. When I2CRSR
functions of the I2C Standard and Fast mode receives a complete byte, it is transferred to I2CRCV
specifications, as well as 7 and 10-bit addressing. and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus. Note: Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.

FIGURE 14-1: PROGRAMMER’S MODEL

I2CRCV (8 bits)
Bit 7 Bit 0

I2CTRN (8 bits)
Bit 7 Bit 0
I2CBRG (9 bits)
Bit 8 Bit 0
I2CCON (16 bits)
Bit 15 Bit 0
I2CSTAT (16 bits)
Bit 15 Bit 0
I2CADD (10 bits)
Bit 9 Bit 0

© 2008 Microchip Technology Inc. DS70139F-page 95

dsPIC30F2011/2012/3012/3013
FIGURE 14-2: I2C™ BLOCK DIAGRAM

Internal
Data Bus

I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB

SDA Addr_Match
Match Detect

Write

I2CADD

Read

Start and
Stop bit Detect
Write

I2CSTAT
Start, Restart,
Stop bit Generate
Read
Control Logic

Collision
Detect
Write
I2CCON

Acknowledge
Read
Generation

Clock
Stretching Write

I2CTRN
LSB
Shift Read
Clock

Reload
Control Write

BRG Down I2CBRG

Counter Read
FCY

DS70139F-page 96 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
14.2 I2C Module Addresses 14.3.2 SLAVE RECEPTION
The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address
addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set,
interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the
address is received, it is compared to the 7 LSb of the ninth clock.
I2CADD register.
If the RBF flag is set, indicating that I2CRCV is still
If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then
10-bit address. When an address is received, it will be ACK is not sent; however, the interrupt pulse is
compared with the binary value ‘11110 A9 A8’ (where generated. In the case of an overflow, the contents of
A9 and A8 are two Most Significant bits of I2CADD). If the I2CRSR are not loaded into the I2CRCV.
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
Note: The I2CRCV will be loaded if the I2COV
in the 10-bit addressing protocol.
bit = 1 and the RBF flag = 0. In this case,
The 7-bit I2C Slave Addresses supported by the a read of the I2CRCV was performed but
dsPIC30F are shown in Table 14-1. the user did not clear the state of the
I2COV bit before the next receive
TABLE 14-1: 7-BIT I2C™ SLAVE occurred. The acknowledgement is not
ADDRESSES sent (ACK = 1) and the I2CRCV is
0x00 General call address or start byte updated.

0x01-0x03 Reserved
0x04-0x07 Hs-mode Master codes
14.4 I2C 10-bit Slave Mode Operation
0x04-0x77 Valid 7-bit addresses In 10-bit mode, the basic receive and transmit
0x78-0x7b Valid 10-bit addresses (lower 7 operations are the same as in the 7-bit mode. However,
bits) the criteria for address match is more complex.

0x7c-0x7f Reserved The I2C specification dictates that a slave must be

addressed for a write operation with two address bytes
following a Start bit.
14.3 I2C 7-bit Slave Mode Operation
The A10M bit is a control bit that signifies that the
Once enabled (I2CEN = 1), the slave module will wait address in I2CADD is a 10-bit address rather than a 7-bit
for a Start bit to occur (i.e., the I2C module is ‘Idle’). address. The address detection protocol for the first byte
Following the detection of a Start bit, 8 bits are shifted of a message address is identical for 7-bit and 10-bit
into I2CRSR and the address is compared against messages, but the bits being compared are different.
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
I2CADD holds the entire 10-bit address. Upon
are compared against I2CRSR<7:1> and I2CRSR<0>
receiving an address following a Start bit, I2CRSR
is the R_W bit. All incoming bits are sampled on the ris-
<7:3> is compared against a literal ‘11110’ (the default
ing edge of SCL.
10-bit address) and I2CRSR<2:1> are compared
If an address match occurs, an acknowledgement will against I2CADD<9:8>. If a match occurs and if
be sent, and the slave event interrupt flag (SI2CIF) is R_W = 0, the interrupt pulse is sent. The ADD10 bit will
set on the falling edge of the ninth (ACK) bit. The be cleared to indicate a partial address match. If a
address match does not affect the contents of the match fails or R_W = 1, the ADD10 bit is cleared and
I2CRCV buffer or the RBF bit. the module returns to the Idle state.

14.3.1 SLAVE TRANSMISSION The low byte of the address is then received and
compared with I2CADD<7:0>. If an address match
If the R_W bit received is a ‘1’, then the serial port will occurs, the interrupt pulse is generated and the ADD10
go into Transmit mode. It will send ACK on the ninth bit bit is set, indicating a complete 10-bit address match. If
and then hold SCL to ‘0’ until the CPU responds by an address match did not occur, the ADD10 bit is
writing to I2CTRN. SCL is released by setting the cleared and the module returns to the Idle state.
SCLREL bit, and 8 bits of data are shifted out. Data bits
are shifted out on the falling edge of SCL, such that
SDA is valid during SCL high. The interrupt pulse is
sent on the falling edge of the ninth clock pulse,
regardless of the status of the ACK received from the
master.

© 2008 Microchip Technology Inc. DS70139F-page 97

dsPIC30F2011/2012/3012/3013
14.4.1 10-BIT MODE SLAVE Clock stretching takes place following the ninth clock of
TRANSMISSION the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
Once a slave is addressed in this fashion with the full
set, the SCLREL bit is automatically cleared, forcing
10-bit address (we will refer to this state as
the SCL output to be held low. The user’s ISR must set
“PRIOR_ADDR_MATCH”), the master can begin
the SCLREL bit before reception is allowed to continue.
sending data bytes for a slave reception operation.
By holding the SCL line low, the user has time to
service the ISR and read the contents of the I2CRCV
14.4.2 10-BIT MODE SLAVE RECEPTION
before the master device can initiate another receive
Once addressed, the master can generate a Repeated sequence. This will prevent buffer overruns from
Start, reset the high byte of the address and set the occurring.
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation. Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
14.5 Automatic Clock Stretch falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
In the Slave modes, the module can synchronize buffer
stretching will not occur.
reads and write to the master device by clock stretching.
2: The SCLREL bit can be set in software
14.5.1 TRANSMIT CLOCK STRETCHING regardless of the state of the RBF bit. The
Both 10-bit and 7-bit Transmit modes implement clock user should be careful to clear the RBF bit
stretching by asserting the SCLREL bit after the falling in the ISR before the next receive
edge of the ninth clock, if the TBF bit is cleared, sequence in order to prevent an overflow
indicating the buffer is empty. condition.

In Slave Transmit modes, clock stretching is always 14.5.4 CLOCK STRETCHING DURING
performed irrespective of the STREN bit. 10-BIT ADDRESSING (STREN = 1)
Clock synchronization takes place following the ninth Clock stretching takes place automatically during the
clock of the transmit sequence. If the device samples addressing sequence. Because this module has a
an ACK on the falling edge of the ninth clock and if the register for the entire address, it is not necessary for
TBF bit is still clear, then the SCLREL bit is the protocol to wait for the address to be updated.
automatically cleared. The SCLREL being cleared to
After the address phase is complete, clock stretching
‘0’ will assert the SCL line low. The user’s ISR must set
will occur on each data receive or transmit sequence as
the SCLREL bit before transmission is allowed to
was described earlier.
continue. By holding the SCL line low, the user has time
to service the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit 14.6 Software Controlled Clock
sequence. Stretching (STREN = 1)
Note 1: If the user loads the contents of I2CTRN, When the STREN bit is ‘1’, the SCLREL bit may be
setting the TBF bit before the falling edge cleared by software to allow software to control the
of the ninth clock, the SCLREL bit will not clock stretching. The logic will synchronize writes to the
be cleared and clock stretching will not SCLREL bit with the SCL clock. Clearing the SCLREL
occur. bit will not assert the SCL output until the module
2: The SCLREL bit can be set in software, detects a falling edge on the SCL output and SCL is
regardless of the state of the TBF bit. sampled low. If the SCLREL bit is cleared by the user
while the SCL line has been sampled low, the SCL
14.5.2 RECEIVE CLOCK STRETCHING output will be asserted (held low). The SCL output will
remain low until the SCLREL bit is set, and all other
The STREN bit in the I2CCON register can be used to devices on the I2C bus have de-asserted SCL. This
enable clock stretching in Slave Receive mode. When ensures that a write to the SCLREL bit will not violate
the STREN bit is set, the SCL pin will be held low at the the minimum high time requirement for SCL.
end of each data receive sequence.
If the STREN bit is ‘0’, a software write to the SCLREL
14.5.3 CLOCK STRETCHING DURING bit will be disregarded and have no effect on the
7-BIT ADDRESSING (STREN = 1) SCLREL bit.
When the STREN bit is set in Slave Receive mode, the
SCL line is held low when the buffer register is full. The
method for stretching the SCL output is the same for
both 7 and 10-bit addressing modes.

DS70139F-page 98 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
14.7 Interrupts 14.11 I2C Master Support
The I2C module generates two interrupt flags, MI2CIF As a master device, six operations are supported:
(I2C Master Interrupt Flag) and SI2CIF (I2C Slave • Assert a Start condition on SDA and SCL.
Interrupt Flag). The MI2CIF interrupt flag is activated
• Assert a Restart condition on SDA and SCL.
on completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message • Write to the I2CTRN register initiating
directed to the slave. transmission of data/address.
• Generate a Stop condition on SDA and SCL.
14.8 Slope Control • Configure the I2C port to receive data.
2 • Generate an ACK condition at the end of a
The I C standard requires slope control on the SDA
received byte of data.
and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate
control if desired. It is necessary to disable the slew 14.12 I2C Master Operation
rate control for 1 MHz mode. The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
14.9 IPMI Support ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
The control bit, IPMIEN, enables the module to support
the beginning of the next serial transfer, the I2C bus will
Intelligent Peripheral Management Interface (IPMI).
not be released.
When this bit is set, the module accepts and acts upon
all addresses. In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
14.10 General Call Address Support first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
The general call address can address all devices. this case, the data direction bit (R_W) is logic ‘0’. Serial
When this address is used, all devices should, in data is transmitted 8 bits at a time. After each byte is
theory, respond with an acknowledgement. transmitted, an ACK bit is received. Start and Stop
The general call address is one of eight addresses conditions are output to indicate the beginning and the
reserved for specific purposes by the I2C protocol. It end of a serial transfer.
consists of all ‘0’s with R_W = 0. In Master Receive mode, the first byte transmitted
The general call address is recognized when the contains the slave address of the transmitting device
General Call Enable (GCEN) bit is set (7 bits) and the data direction bit. In this case, the data
(I2CCON<7> = 1). Following a Start bit detection, 8 bits direction bit (R_W) is logic ‘1’. Thus, the first byte
are shifted into I2CRSR and the address is compared transmitted is a 7-bit slave address, followed by a ‘1’ to
with I2CADD, and is also compared with the general indicate receive bit. Serial data is received via SDA
call address which is fixed in hardware. while SCL outputs the serial clock. Serial data is
received 8 bits at a time. After each byte is received, an
If a general call address match occurs, the I2CRSR is ACK bit is transmitted. Start and Stop conditions
transferred to the I2CRCV after the eighth clock, the RBF indicate the beginning and end of transmission.
flag is set and on the falling edge of the ninth bit (ACK
bit), the master event interrupt flag (MI2CIF) is set. 14.12.1 I2C MASTER TRANSMISSION
When the interrupt is serviced, the source for the Transmission of a data byte, a 7-bit address, or the sec-
interrupt can be checked by reading the contents of the ond half of a 10-bit address, is accomplished by simply
I2CRCV to determine if the address was device writing a value to I2CTRN register. The user should
specific or a general call address. only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the Baud Rate Generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.

© 2008 Microchip Technology Inc. DS70139F-page 99

dsPIC30F2011/2012/3012/3013
14.12.2 I2C MASTER RECEPTION If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
Master mode reception is enabled by programming the
cleared, the SDA and SCL lines are de-asserted and a
Receive Enable bit, RCEN (I2CCON<3>). The I2C
value can now be written to I2CTRN. When the user
module must be Idle before the RCEN bit is set,
services the I2C master event Interrupt Service
otherwise the RCEN bit will be disregarded. The Baud
Routine, if the I2C bus is free (i.e., the P bit is set), the
Rate Generator begins counting and on each rollover,
user can resume communication by asserting a Start
the state of the SCL pin ACK and data are shifted into
condition.
the I2CRSR on the rising edge of each clock.
If a Start, Restart, Stop or Acknowledge condition was
14.12.3 BAUD RATE GENERATOR in progress when the bus collision occurred, the
In I2C Master mode, the reload value for the BRG is condition is aborted, the SDA and SCL lines are
located in the I2CBRG register. When the BRG is de-asserted, and the respective control bits in the
loaded with this value, the BRG counts down to ‘0’ and I2CCON register are cleared to ‘0’. When the user
stops until another reload has taken place. If clock services the bus collision Interrupt Service Routine,
arbitration is taking place, for instance, the BRG is and if the I2C bus is free, the user can resume
reloaded when the SCL pin is sampled high. communication by asserting a Start condition.

As per the I2C standard, FSCK may be 100 kHz or The master will continue to monitor the SDA and SCL
400 kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. be set.
A write to the I2CTRN will start the transmission of data
EQUATION 14-1: SERIAL CLOCK RATE at the first data bit regardless of where the transmitter
left off when bus collision occurred.
In a multi-master environment, the interrupt generation
I2CBRG = ( FFSCL
CY – FCY
1,111,111
) –1
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
14.12.4 CLOCK ARBITRATION register, or the bus is Idle and the S and P bits are
Clock arbitration occurs when the master de-asserts cleared.
the SCL pin (SCL allowed to float high) during any
receive, transmit, or Restart/Stop condition. When the 14.13 I2C Module Operation During CPU
SCL pin is allowed to float high, the Baud Rate Sleep and Idle Modes
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is 14.13.1 I2C OPERATION DURING CPU
sampled high, the Baud Rate Generator is reloaded SLEEP MODE
with the contents of I2CBRG and begins counting. This
When the device enters Sleep mode, all clock sources
ensures that the SCL high time will always be at least
to the module are shut down and stay at logic ‘0’. If
one BRG rollover count in the event that the clock is
Sleep occurs in the middle of a transmission and the
held low by an external device.
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
14.12.5 MULTI-MASTER COMMUNICATION,
if Sleep occurs in the middle of a reception, then the
BUS COLLISION, AND BUS reception is aborted.
ARBITRATION
Multi-master operation support is achieved by bus 14.13.2 I2C OPERATION DURING CPU IDLE
arbitration. When the master outputs address/data bits MODE
onto the SDA pin, arbitration takes place when the For the I2C, the I2CSIDL bit selects if the module will
master outputs a ‘1’ on SDA by letting SDA float high stop on Idle or continue on Idle. If I2CSIDL = 0, the
while another master asserts a ‘0’. When the SCL pin module will continue operation on assertion of the Idle
floats high, data should be stable. If the expected data mode. If I2CSIDL = 1, the module will stop on Idle.
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.

DS70139F-page 100 © 2008 Microchip Technology Inc.

 TABLE 14-2: I2C REGISTER MAP
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000

I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111
I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000
I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000
I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000
I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013
DS70139F-page 101
dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 102 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
15.0 UNIVERSAL ASYNCHRONOUS 15.1 UART Module Overview
RECEIVER TRANSMITTER The key features of the UART module are:
(UART) MODULE • Full-duplex, 8 or 9-bit data communication
Note: This data sheet summarizes features of • Even, odd or no parity options (for 8-bit data)
this group of dsPIC30F devices and is not • One or two Stop bits
intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit
source. For more information on the CPU, prescaler
peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a
general device functionality, refer to the 30 MHz instruction rate
“dsPIC30F Family Reference Manual”
• 4-word deep transmit data buffer
(DS70046).
• 4-word deep receive data buffer
This section describes the Universal Asynchronous • Parity, framing and buffer overrun error detection
Receiver/Transmitter Communications module. The
• Support for interrupt only on address detect
dsPIC30F2011/2012/3012 processors have one UART
(9th bit = 1)
module (UART1). The dsPIC30F3013 processor has
two UART modules (UART1 and UART2). • Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• Alternate receive and transmit pins for UART1

FIGURE 15-1: UART TRANSMITTER BLOCK DIAGRAM

Internal Data Bus

Control and Status bits

Write Write

UTX8 UxTXREG Low Byte Transmit Control

– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt

Load TSR
UxTXIF
UTXBRK

Data
Transmit Shift Register (UxTSR)
‘0’ (Start)
UxTX
‘1’ (Stop)

Parity 16x Baud Clock

Parity 16 Divider
Generator from Baud Rate
Generator

Control
Signals

Note: x = 1 or 2.

© 2008 Microchip Technology Inc. DS70139F-page 103

dsPIC30F2011/2012/3012/3013
FIGURE 15-2: UART RECEIVER BLOCK DIAGRAM

Internal Data Bus 16

Read Write Read Read Write

UxMODE UxSTA

URX8 UxRXREG Low Byte

Receive Buffer Control
– Generate Flags
– Generate Interrupt
– Shift Data Characters

LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control

FERR
PERR
Receive Shift Register Signals
UxRX 0 (UxRSR)

· Start bit Detect

· Parity Check
· Stop bit Detect 16 Divider
· Shift Clock Generation
· Wake Logic

16x Baud Clock from

Baud Rate Generator
UxRXIF

DS70139F-page 104 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
15.2 Enabling and Setting Up UART 15.3 Transmitting Data
15.2.1 ENABLING THE UART 15.3.1 TRANSMITTING IN 8-BIT DATA
The UART module is enabled by setting the UARTEN MODE
bit in the UxMODE register (where x = 1 or 2). Once The following steps must be performed to transmit 8-bit
enabled, the UxTX and UxRX pins are configured as an data:
output and an input respectively, overriding the TRIS
1. Set up the UART:
and LAT register bit settings for the corresponding I/O
First, the data length, parity and number of Stop
port pins. The UxTX pin is at logic ‘1’ when no
bits must be selected. Then, the transmit and
transmission is taking place.
receive interrupt enable and priority bits are
setup in the UxMODE and UxSTA registers.
15.2.2 DISABLING THE UART
Also, the appropriate baud rate value must be
The UART module is disabled by clearing the UARTEN written to the UxBRG register.
bit in the UxMODE register. This is the default state 2. Enable the UART by setting the UARTEN bit
after any Reset. If the UART is disabled, all I/O pins (UxMODE<15>).
operate as port pins under the control of the LAT and
3. Set the UTXEN bit (UxSTA<10>), thereby
TRIS bits of the corresponding port pins.
enabling a transmission.
Disabling the UART module resets the buffers to empty 4. Write the byte to be transmitted to the lower byte
states. Any data characters in the buffers are lost and of UxTXREG. The value will be transferred to the
the baud rate counter is reset. Transmit Shift register (UxTSR) immediately
All error and status flags associated with the UART and the serial bit stream will start shifting out
module are reset when the module is disabled. The during the next rising edge of the baud clock.
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and Alternatively, the data byte may be written while
UTXBF bits are cleared, whereas RIDLE and TRMT UTXEN = 0, following which, the user may set
are set. Other control bits, including ADDEN, UTXEN. This will cause the serial bit stream to
URXISEL<1:0>, UTXISEL, as well as the UxMODE begin immediately because the baud clock will
and UxBRG registers, are not affected. start from a cleared state.
Clearing the UARTEN bit while the UART is active will 5. A transmit interrupt will be generated,
abort all pending transmissions and receptions and depending on the value of the interrupt control
reset the module as defined above. Re-enabling the bit UTXISEL (UxSTA<15>).
UART will restart the UART in the same configuration.
15.3.2 TRANSMITTING IN 9-BIT DATA
15.2.3 ALTERNATE I/O MODE
The alternate I/O function is enabled by setting the The sequence of steps involved in the transmission
ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX of 9-bit data is similar to 8-bit transmission, except that
and UxARX pins (alternate transmit and alternate a 16-bit data word (of which the upper 7 bits are always
receive pins, respectively) are used by the UART clear) must be written to the UxTXREG register.
module instead of the UxTX and UxRX pins. If
ALTIO = 0, the UxTX and UxRX pins are used by the 15.3.3 TRANSMIT BUFFER (UXTXB)
UART module. The transmit buffer is 9 bits wide and 4 characters deep.
Including the Transmit Shift register (UxTSR), the user
15.2.4 SETTING UP DATA, PARITY AND effectively has a 5-deep FIFO (First-In, First- Out) buffer.
STOP BIT SELECTIONS The UTXBF bit (UxSTA<9>) indicates whether the
Control bits PDSEL<1:0> in the UxMODE register are transmit buffer is full.
used to select the data length and parity used in the If a user attempts to write to a full buffer, the new data
transmission. The data length may either be 8 bits with will not be accepted into the FIFO and no data shift will
even, odd or no parity, or 9 bits with no parity. occur within the buffer. This enables recovery from a
The STSEL bit determines whether one or two Stop bits buffer overrun condition.
will be used during data transmission. The FIFO is reset during any device Reset, but is not
The default (power-on) setting of the UART is 8 bits, no affected when the device enters or wakes up from a
parity and 1 Stop bit (typically represented as 8, N, 1). Power Saving mode.

© 2008 Microchip Technology Inc. DS70139F-page 105

dsPIC30F2011/2012/3012/3013
15.3.4 TRANSMIT INTERRUPT 15.4.2 RECEIVE BUFFER (UXRXB)
The transmit interrupt flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the
located in the corresponding interrupt flag register. Receive Shift register (UxRSR), the user effectively
The transmitter generates an edge to set the UxTXIF has a 5-word deep FIFO buffer.
bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive
on the UTXISEL control bit: buffer has data available. URXDA = 0 implies that the
a) If UTXISEL = 0, an interrupt is generated when buffer is empty. If a user attempts to read an empty
a word is transferred from the transmit buffer to buffer, the old values in the buffer will be read and no
the Transmit Shift register (UxTSR). This means data shift will occur within the FIFO.
that the transmit buffer has at least one empty The FIFO is reset during any device Reset. It is not
word. affected when the device enters or wakes up from a
b) If UTXISEL = 1, an interrupt is generated when Power Saving mode.
a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR) and the 15.4.3 RECEIVE INTERRUPT
transmit buffer is empty. The receive interrupt flag (U1RXIF or U2RXIF) can be
Switching between the two Interrupt modes during read from the corresponding interrupt flag register. The
operation is possible and sometimes offers more interrupt flag is set by an edge generated by the
flexibility. receiver. The condition for setting the receive interrupt
flag depends on the settings specified by
15.3.5 TRANSMIT BREAK the URXISEL<1:0> (UxSTA<7:6>) control bits.
Setting the UTXBRK bit (UxSTA<11>) will cause the a) If URXISEL<1:0> = 00 or 01, an interrupt is
UxTX line to be driven to logic ‘0’. The UTXBRK bit generated every time a data word is transferred
overrides all transmission activity. Therefore, the user from the Receive Shift register (UxRSR) to the
should generally wait for the transmitter to be Idle receive buffer. There may be one or more
before setting UTXBRK. characters in the receive buffer.
To send a Break character, the UTXBRK bit must be set b) If URXISEL<1:0> = 10, an interrupt is generated
by software and must remain set for a minimum of 13 when a word is transferred from the Receive Shift
baud clock cycles. The UTXBRK bit is then cleared by register (UxRSR) to the receive buffer, which as a
software to generate Stop bits. The user must wait for result of the transfer, contains 3 characters.
a duration of at least one or two baud clock cycles in c) If URXISEL<1:0> = 11, an interrupt is set when
order to ensure a valid Stop bit(s) before reloading the a word is transferred from the Receive Shift
UxTXB, or starting other transmitter activity. register (UxRSR) to the receive buffer, which as
Transmission of a Break character does not generate a a result of the transfer, contains 4 characters
transmit interrupt. (i.e., becomes full).
Switching between the Interrupt modes during
15.4 Receiving Data operation is possible, though generally not advisable
during normal operation.
15.4.1 RECEIVING IN 8-BIT OR 9-BIT
DATA MODE 15.5 Reception Error Handling
The following steps must be performed while receiving
8-bit or 9-bit data: 15.5.1 RECEIVE BUFFER OVERRUN
1. Set up the UART (see Section 15.3.1 “Trans- ERROR (OERR BIT)
mitting in 8-bit data mode”). The OERR bit (UxSTA<1>) is set if all of the following
2. Enable the UART (see Section 15.3.1 “Trans- conditions occur:
mitting in 8-bit data mode”). a) The receive buffer is full.
3. A receive interrupt will be generated when one b) The Receive Shift register is full, but unable to
or more data words have been received, depend- transfer the character to the receive buffer.
ing on the receive interrupt settings specified by c) The Stop bit of the character in the UxRSR is
the URXISEL bits (UxSTA<7:6>). detected, indicating that the UxRSR needs to
4. Read the OERR bit to determine if an overrun error transfer the character to the buffer.
has occurred. The OERR bit must be reset in soft-
Once OERR is set, no further data is shifted in UxRSR
ware.
(until the OERR bit is cleared in software or a Reset
5. Read the received data from UxRXREG. The act occurs). The data held in UxRSR and UxRXREG
of reading UxRXREG will move the next word to remains valid.
the top of the receive FIFO, and the PERR and
FERR values will be updated.

DS70139F-page 106 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
15.5.2 FRAMING ERROR (FERR) 15.6 Address Detect Mode
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the ADDEN bit (UxSTA<5>) enables this
instead of a Stop bit. If two Stop bits are selected, both special mode in which a 9th bit (URX8) value of ‘1’
Stop bits must be ‘1’, otherwise FERR will be set. The identifies the received word as an address, rather than
read-only FERR bit is buffered along with the received data. This mode is only applicable for 9-bit data
data. It is cleared on any Reset. communication. The URXISEL control bit does not
have any impact on interrupt generation in this mode
15.5.3 PARITY ERROR (PERR) since an interrupt (if enabled) will be generated every
The PERR bit (UxSTA<3>) is set if the parity of the time the received word has the 9th bit set.
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The 15.7 Loopback Mode
read-only PERR bit is buffered along with the received
data bytes. It is cleared on any Reset. Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
15.5.4 IDLE STATUS pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
When the receiver is active (i.e., between the initial
receive logic. However, the UxTX pin still functions as
detection of the Start bit and the completion of the Stop
in a normal operation.
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-
pletion of the Stop bit and detection of the next Start bit, To select this mode:
the RIDLE bit is ‘1’, indicating that the UART is Idle. a) Configure UART for desired mode of operation.
b) Set LPBACK = 1 to enable Loopback mode.
15.5.5 RECEIVE BREAK
c) Enable transmission as defined in Section 15.3
The receiver will count and expect a certain number of “Transmitting Data”.
bit times based on the values programmed in the PDSEL
(UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
15.8 Baud Rate Generator
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times The UART has a 16-bit Baud Rate Generator to allow
specified by PDSEL and STSEL. The URXDA bit is set, maximum flexibility in baud rate generation. The Baud
FERR is set, zeros are loaded into the receive FIFO, Rate Generator register (UxBRG) is readable and
interrupts are generated if appropriate and the RIDLE writable. The baud rate is computed as follows:
bit is set. BRG = 16-bit value held in UxBRG register
When the module receives a long break signal and the (0 through 65535)
receiver has detected the Start bit, the data bits and the FCY = Instruction Clock Rate (1/TCY)
invalid Stop bit (which sets the FERR), the receiver
The baud rate is given by Equation 15-1.
must wait for a valid Stop bit before looking for the next
Start bit. It cannot assume that the break condition on
the line is the next Start bit. EQUATION 15-1: BAUD RATE
Break is regarded as a character containing all ‘0’s with Baud Rate = FCY / (16*(BRG+1))
the FERR bit set. The Break character is loaded into
the buffer. No further reception can occur until a Stop bit
is received. Note that RIDLE goes high when the Stop Therefore, the maximum baud rate possible is:
bit has not yet been received. FCY /16 (if BRG = 0),
and the minimum baud rate possible is:
FCY / (16* 65536).
With a full 16-bit Baud Rate Generator at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.

© 2008 Microchip Technology Inc. DS70139F-page 107

dsPIC30F2011/2012/3012/3013
15.9 Auto-Baud Support 15.10.2 UART OPERATION DURING CPU
IDLE MODE
To allow the system to determine baud rates of
received characters, the input can be optionally linked For the UART, the USIDL bit selects if the module will
to a selected capture input (IC1 for UART1 and IC2 for stop operation when the device enters Idle mode or
UART2). To enable this mode, you must program the whether the module will continue on Idle. If USIDL = 0,
input capture module to detect the falling and rising the module will continue to operate during Idle mode. If
edges of the Start bit. USIDL = 1, the module will stop on Idle.

15.10 UART Operation During CPU

Sleep and Idle Modes
15.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is in
progress, then the transmission is aborted. The UxTX
pin is driven to logic ‘1’. Similarly, if entry into Sleep
mode occurs while a reception is in progress, then the
reception is aborted. The UxSTA, UxMODE, transmit
and receive registers and buffers, and the UxBRG
register are not affected by Sleep mode.
If the WAKE bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX pin
will generate a receive interrupt. The Receive Interrupt
Select mode bit (URXISEL) has no effect for this
function. If the receive interrupt is enabled, then this will
wake-up the device from Sleep. The UARTEN bit must
be set in order to generate a wake-up interrupt.

DS70139F-page 108 © 2008 Microchip Technology Inc.

 TABLE 15-1: UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

U1MODE 020C UARTEN — USIDL — — ALTIO — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

TABLE 15-2: UART2 REGISTER MAP FOR dsPIC30F3013(1)

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

U2MODE 0216 UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000

dsPIC30F2011/2012/3012/3013
U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U2TXREG 021A — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: UART2 is not available on dsPIC30F2011/2012/3012 devices.
2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70139F-page 109
dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 110 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
16.0 12-BIT ANALOG-TO-DIGITAL on the (VREF+/VREF-) pin. The ADC has a unique
feature of being able to operate while the device is in
CONVERTER (ADC) MODULE Sleep mode with RC oscillator selection.
Note: This data sheet summarizes features of The ADC module has six 16-bit registers:
this group of dsPIC30F devices and is not
• A/D Control Register 1 (ADCON1)
intended to be a complete reference
• A/D Control Register 2 (ADCON2)
source. For more information on the CPU,
• A/D Control Register 3 (ADCON3)
peripherals, register descriptions and gen-
• A/D Input Select Register (ADCHS)
eral device functionality, refer to the
• A/D Port Configuration Register (ADPCFG)
“dsPIC30F Family Reference Manual”
• A/D Input Scan Selection Register (ADCSSL)
(DS70046).
The ADCON1, ADCON2 and ADCON3 registers
The 12-bit Analog-to-Digital Converter allows control the operation of the ADC module. The ADCHS
conversion of an analog input signal to a 12-bit digital register selects the input channels to be converted. The
number. This module is based on a Successive ADPCFG register configures the port pins as analog
Approximation Register (SAR) architecture and inputs or as digital I/O. The ADCSSL register selects
provides a maximum sampling rate of 200 ksps. The inputs for scanning.
ADC module has up to 10 analog inputs which are
multiplexed into a sample and hold amplifier. The Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
output of the sample and hold is the input into the BUFM and ALTS bits, as well as the
converter which generates the result. The analog ADCON3 and ADCSSL registers, must
reference voltage is software selectable to either the not be written to while ADON = 1. This
device supply voltage (AVDD/AVSS) or the voltage level would lead to indeterminate results.

FIGURE 16-1: 12-BIT ADC FUNCTIONAL BLOCK DIAGRAM

AVDD/VREF+

AVSS/VREF-

0000 Comparator
AN0
DAC
0001
AN1

AN2 0010

0011 12-bit SAR Conversion Logic

AN3

AN4 0100

0101 16-word, 12-bit Data Format

AN5 Dual Port
Buffer

Bus Interface
0110
AN6

0111
AN7

1000 Sample Sample/Sequence

AN8 Control
1001
AN9

S/H CH0
Input Input MUX
Switches Control

© 2008 Microchip Technology Inc. DS70139F-page 111

dsPIC30F2011/2012/3012/3013
16.1 A/D Result Buffer 16.3 Selecting the Conversion
The module contains a 16-word dual port read-only
Sequence
buffer, called ADCBUF0...ADCBUFF, to buffer the A/D Several groups of control bits select the sequence in
results. The RAM is 12 bits wide but the data obtained which the A/D connects inputs to the sample/hold
is represented in one of four different 16-bit data channel, converts a channel, writes the buffer memory
formats. The contents of the sixteen A/D Conversion and generates interrupts.
Result Buffer registers, ADCBUF0 through ADCBUFF,
The sequence is controlled by the sampling clocks.
cannot be written by user software.
The SMPI bits select the number of
16.2 Conversion Operation acquisition/conversion sequences that would be per-
formed before an interrupt occurs. This can vary from 1
After the ADC module has been configured, the sample sample per interrupt to 16 samples per interrupt.
acquisition is started by setting the SAMP bit. Various
The BUFM bit will split the 16-word results buffer into
sources, such as a programmable bit, timer time-outs
two 8-word groups. Writing to the 8-word buffers will be
and external events, will terminate acquisition and start
alternated on each interrupt event.
a conversion. When the A/D conversion is complete,
the result is loaded into ADCBUF0...ADCBUFF, and Use of the BUFM bit will depend on how much time is
the DONE bit and the A/D interrupt flag, ADIF, are set available for the moving of the buffers after the
after the number of samples specified by the SMPI bit. interrupt.
The ADC module can be configured for different inter- If the processor can quickly unload a full buffer within
rupt rates as described in Section 16.3 “Selecting the the time it takes to acquire and convert one channel,
Conversion Sequence”. the BUFM bit can be ‘0’ and up to 16 conversions
The following steps should be followed for doing an (corresponding to the 16 input channels) may be done
A/D conversion: per interrupt. The processor will have one acquisition
and conversion time to move the sixteen conversions.
1. Configure the ADC module:
• Configure analog pins, voltage reference and If the processor cannot unload the buffer within the
digital I/O acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
• Select A/D input channels
then eight conversions will be loaded into 1/2 of the
• Select A/D conversion clock buffer, following which an interrupt occurs. The next
• Select A/D conversion trigger eight conversions will be loaded into the other 1/2 of the
• Turn on ADC module buffer. The processor will have the entire time between
2. Configure A/D interrupt (if required): interrupts to move the eight conversions.
• Clear ADIF bit The ALTS bit can be used to alternate the inputs
• Select A/D interrupt priority selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
3. Start sampling
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
4. Wait the required acquisition time selected for sampling. If the ALTS bit is ‘1’ and
5. Trigger acquisition end, start conversion SMPI<3:0> = 0000 on the first sample/convert
6. Wait for A/D conversion to complete, by either: sequence, the MUX A inputs are selected and on the
• Waiting for the A/D interrupt, or next acquire/convert sequence, the MUX B inputs are
• Waiting for the DONE bit to get set selected.
7. Read A/D result buffer; clear ADIF if required The CSCNA bit (ADCON2<10>) will allow the
multiplexer input to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is ‘1’, the
corresponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.

DS70139F-page 112 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
16.4 Programming the Start of The internal RC oscillator is selected by setting the
Conversion Trigger ADRC bit.
For correct ADC conversions, the ADC conversion
The conversion trigger will terminate acquisition and
clock (TAD) must be selected to ensure a minimum TAD
start the requested conversions.
time of 334 nsec (for VDD = 5V). Refer to Section 20.0
The SSRC<2:0> bits select the source of the “Electrical Characteristics” for minimum TAD under
conversion trigger. The SSRC bits provide for up to four other operating conditions.
alternate sources of conversion trigger.
Example 16-1 shows a sample calculation for the
When SSRC<2:0> = 000, the conversion trigger is ADCS<5:0> bits, assuming a device operating speed
under software control. Clearing the SAMP bit will of 30 MIPS.
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the EXAMPLE 16-1: ADC CONVERSION
conversion trigger is under A/D clock control. The CLOCK AND SAMPLING
SAMC bits select the number of A/D clocks between RATE CALCULATION
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple Minimum TAD = 334 nsec
channels. SAMC must always be at least one clock TCY = 33 .33 nsec (30 MIPS)
cycle. TAD
ADCS<5:0> = 2 –1
Other trigger sources can come from timer modules or TCY
external interrupts. 334 nsec
=2• –1
33.33 nsec
16.5 Aborting a Conversion = 19.04
Therefore,
Clearing the ADON bit during a conversion will abort Set ADCS<5:0> = 19
the current conversion and stop the sampling
sequencing until the next sampling trigger. The TCY
Actual TAD = (ADCS<5:0> + 1)
ADCBUF will not be updated with the partially 2
completed A/D conversion sample. That is, the 33.33 nsec
ADCBUF will continue to contain the value of the last = (19 + 1)
2
completed conversion (or the last value written to the
= 334 nsec
ADCBUF register).
If the clearing of the ADON bit coincides with an If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
auto-start, the clearing has a higher priority and a new
Since,
conversion will not start.
Sampling Time = Acquisition Time + Conversion Time
After the A/D conversion is aborted, a 2 TAD wait is = 1 TAD + 14 TAD
required before the next sampling may be started by = 15 x 334 nsec
setting the SAMP bit.
Therefore,
1
16.6 Selecting the ADC Conversion Sampling Rate =
(15 x 334 nsec)
Clock = ~200 kHz
The ADC conversion requires 14 TAD. The source of
the ADC conversion clock is software selected, using a
6-bit counter. There are 64 possible options for TAD.

EQUATION 16-1: ADC CONVERSION

CLOCK

TAD = TCY * (0.5*(ADCS<5:0> + 1))

© 2008 Microchip Technology Inc. DS70139F-page 113

dsPIC30F2011/2012/3012/3013
16.7 ADC Speeds
The dsPIC30F 12-bit ADC specifications permit a
maximum of 200 ksps sampling rate. Table 16-1
summarizes the conversion speeds for the dsPIC30F
12-bit ADC and the required operating conditions.
Figure 16-2 depicts the recommended circuit for the
conversion rates above 200 ksps. The dsPIC30F2011
is shown as an example.
TABLE 16-1: 12-BIT ADC EXTENDED CONVERSION RATES
dsPIC30F 12-bit ADC Conversion Rates

TAD Sampling
Speed Rs Max VDD Temperature Channels Configuration
Minimum Time Min
Up to 200 334 ns 1 TAD 2.5 kΩ 4.5V to 5.5V -40°C to +85°C
ksps(1)
VREF- VREF+

CHX
ANx
S/H ADC

Up to 100 668 ns 1 TAD 2.5 kΩ 3.0V to 5.5V -40°C to +125°C

ksps VREF- VREF+
or or
AVSS AVDD

ANx CHX
S/H ADC

ANx or VREF-

Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 16-2 for recommended
circuit.

FIGURE 16-2: ADC VOLTAGE REFERENCE SCHEMATIC

VDD
See Note 1:
R2
10 VDD VDD VDD

C2 C1 VDD C8 C7 C6
0.1 μF 0.01 μF 1 μF 0.1 μF 0.01 μF

R1
10
VSS
AVDD
VREF-

22
27
26

23

1 21
2 20
3 19
VDD
4 dsPIC30F2011 18
AVDD AVDD AVDD
VSS VDD
6 VSS
7 15 C5 C4 C3
VDD

1 μF 0.1 μF 0.01 μF
11

13
14
12
8
9

VDD

Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.

DS70139F-page 114 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
The configuration procedures below give the required The following figure shows the timing diagram of the
setup values for the conversion speeds above 100 ADC running at 200 ksps. The TAD selection in
ksps. conjunction with the guidelines described above allows
a conversion speed of 200 ksps. See Example 16-1 for
16.7.1 200 KSPS CONFIGURATION code example.
GUIDELINE
The following configuration items are required to 16.8 A/D Acquisition Requirements
achieve a 200 ksps conversion rate.
The analog input model of the 12-bit ADC is shown in
• Comply with conditions provided in Table 16-1. Figure 16-3. The total sampling time for the A/D is a
• Connect external VREF+ and VREF- pins following function of the internal amplifier settling time and the
the recommended circuit shown in Figure 16-2. holding capacitor charge time.
• Set SSRC<2.0> = 111 in the ADCON1 register to For the ADC to meet its specified accuracy, the charge
enable the auto convert option. holding capacitor (CHOLD) must be allowed to fully
• Enable automatic sampling by setting the ASAM charge to the voltage level on the analog input pin. The
control bit in the ADCON1 register. source impedance (RS), the interconnect
• Write the SMPI<3.0> control bits in the ADCON2 impedance (RIC) and the internal sampling switch
register for the desired number of conversions (RSS) impedance combine to directly affect the time
between interrupts. required to charge the capacitor CHOLD. The combined
impedance of the analog sources must therefore be
• Configure the ADC clock period to be:
small enough to fully charge the holding capacitor
1 within the chosen sample time. To minimize the effects
= 334 ns
(14 + 1) x 200,000 of pin leakage currents on the accuracy of the ADC, the
maximum recommended source impedance, RS,
is 2.5 kΩ. After the analog input channel is selected
by writing to the ADCS<5:0> control bits in the
(changed), this sampling function must be completed
ADCON3 register.
prior to starting the conversion. The internal holding
• Configure the sampling time to be 1 TAD by capacitor will be in a discharged state prior to each
writing: SAMC<4:0> = 00001. sample operation.

FIGURE 16-3: 12-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD RIC ≤ 250Ω Sampling RSS ≤ 3 kΩ

Switch
VT = 0.6V
Rs ANx RSS

CHOLD
VA CPIN I leakage = DAC capacitance
VT = 0.6V ± 500 nA = 18 pF

VSS

Legend: CPIN = input capacitance

VT = threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC = interconnect resistance
RSS = sampling switch resistance
CHOLD = sample/hold capacitance (from DAC)

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.

© 2008 Microchip Technology Inc. DS70139F-page 115

dsPIC30F2011/2012/3012/3013
16.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the ADC
The module has two internal power modes. module will then be turned off, although the ADON bit
When the ADON bit is ‘1’, the module is in Active mode; will remain set.
it is fully powered and functional.
16.10.2 A/D OPERATION DURING CPU IDLE
When ADON is ‘0’, the module is in Off mode. The
MODE
digital and analog portions of the circuit are disabled for
maximum current savings. The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will
In order to return to the Active mode from Off mode, the
continue operation on assertion of Idle mode. If
user must wait for the ADC circuitry to stabilize.
ADSIDL = 1, the module will stop on Idle.

16.10 A/D Operation During CPU Sleep

16.11 Effects of a Reset
and Idle Modes
A device Reset forces all registers to their Reset state.
16.10.1 A/D OPERATION DURING CPU This forces the ADC module to be turned off, and any
SLEEP MODE conversion and sampling sequence is aborted. The
values that are in the ADCBUF registers are not
When the device enters Sleep mode, all clock sources
modified. The A/D Result register will contain unknown
to the module are shut down and stay at logic ‘0’.
data after a Power-on Reset.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue 16.12 Output Formats
with a partially completed conversion on exit from
Sleep mode. The A/D result is 12 bits wide. The data buffer RAM is
Register contents are not affected by the device also 12 bits wide. The 12-bit data can be read in one of
entering or leaving Sleep mode. four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
The ADC module can operate during Sleep mode if the result on the data bus.
A/D clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits
one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed which
eliminates all digital switching noise from the
conversion. When the conversion is complete, the
CONV bit will be cleared and the result loaded into the
ADCBUF register.

FIGURE 16-4: A/D OUTPUT DATA FORMATS

RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0

Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0

Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

DS70139F-page 116 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
16.13 Configuring Analog Port Pins 16.14 Connection Considerations
The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD
operation of the A/D port pins. The port pins that are protection. This requires that the analog input be
desired as analog inputs must have their between VDD and VSS. If the input voltage exceeds this
corresponding TRIS bit set (input). If the TRIS bit is range by greater than 0.3V (either direction), one of the
cleared (output), the digital output level (VOH or VOL) diodes becomes forward biased and it may damage the
will be converted. device if the input current specification is exceeded.
The A/D operation is independent of the state of the An external RC filter is sometimes added for
CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. anti-aliasing of the input signal. The R component
When reading the PORT register, all pins configured as should be selected to ensure that the sampling time
analog input channels will read as cleared. requirements are satisfied. Any external components
connected (via high-impedance) to an analog input pin
Pins configured as digital inputs will not convert an (capacitor, zener diode, etc.) should have very little
analog input. Analog levels on any pin that is defined as leakage current at the pin.
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.

© 2008 Microchip Technology Inc. DS70139F-page 117

 TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012
DS70139F-page 118

dsPIC30F2011/2012/3012/3013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu

ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu
ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu
ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu
ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu
ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu
ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu
ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu
ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu
ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu
ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu
ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu
ADCBUFC 0298 — — — — ADC Data Buffer 12 0000 uuuu uuuu uuuu
ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu
ADCBUFE 029C — — — — ADC Data Buffer 14 0000 uuuu uuuu uuuu
ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu
ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — — ASAM SAMP DONE 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> — — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000
ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA — — — — — — — — CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013
© 2008 Microchip Technology Inc.

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu

ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu
ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu
ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu
ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu
ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu
ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu
ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu
ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu
ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu

dsPIC30F2011/2012/3012/3013
ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu
ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu
ADCBUFC 0298 — — — — ADC Data Buffer 12 0000 uuuu uuuu uuuu
ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu
ADCBUFE 029C — — — — ADC Data Buffer 14 0000 uuuu uuuu uuuu
ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu
ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — — ASAM SAMP DONE 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> — — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000
ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 — — — — — — PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA — — — — — — CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70139F-page 119
dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 120 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
17.0 SYSTEM INTEGRATION 17.1 Oscillator System Overview
Note: This data sheet summarizes features of The dsPIC30F oscillator system has the following
this group of dsPIC30F devices and is not modules and features:
intended to be a complete reference • Various external and internal oscillator options as
source. For more information on the CPU, clock sources
peripherals, register descriptions and • An on-chip PLL to boost internal operating
general device functionality, refer to the frequency
“dsPIC30F Family Reference Manual”
• A clock switching mechanism between various
(DS70046). For more information on the
clock sources
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s • Programmable clock postscaler for system power
Reference Manual” (DS70157). savings
• A Fail-Safe Clock Monitor (FSCM) that detects
There are several features intended to maximize clock failure and takes fail-safe measures
system reliability, minimize cost through elimination of • Clock Control register (OSCCON)
external components, provide Power Saving Operating
• Configuration bits for main oscillator selection
modes and offer code protection:
Configuration bits determine the clock source upon
• Oscillator Selection
Power-on Reset (POR) and Brown-out Reset (BOR).
• Reset Thereafter, the clock source can be changed between
- Power-on Reset (POR) permissible clock sources. The OSCCON register
- Power-up Timer (PWRT) controls the clock switching and reflects system clock
- Oscillator Start-up Timer (OST) related status bits.
- Programmable Brown-out Reset (BOR) Table 17-1 provides a summary of the dsPIC30F
• Watchdog Timer (WDT) Oscillator Operating modes. A simplified diagram of the
• Low-Voltage Detect oscillator system is shown in Figure 17-1.
• Power-Saving Modes (Sleep and Idle)
• Code Protection
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
dsPIC30F devices have a Watchdog Timer which is
permanently enabled via the Configuration bits or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a delay on
power-up only, designed to keep the part in Reset while
the power supply stabilizes. With these two timers
on-chip, most applications need no external Reset
circuitry.
Sleep mode is designed to offer a very low current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active but the CPU is shut-off. The RC oscillator
option saves system cost while the LP crystal option
saves power.

© 2008 Microchip Technology Inc. DS70139F-page 121

dsPIC30F2011/2012/3012/3013
TABLE 17-1: OSCILLATOR OPERATING MODES
Oscillator Mode Description

XTL 200 kHz-4 MHz crystal on OSC1:OSC2.

XT 4 MHz-10 MHz crystal on OSC1:OSC2.
XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled.
XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled.
XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1).
LP 32 kHz crystal on SOSCO:SOSCI(2).
HS 10 MHz-25 MHz crystal.
HS/2 w/PLL 4x 10 MHz -20 MHz crystal, divide by 2, 4x PLL enabled.
HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled.
HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled(1).
HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled.
HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled.
HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled(1).
EC External clock input (0-40 MHz).
ECIO External clock input (0-40 MHz), OSC2 pin is I/O.
EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled.
EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled.
EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1).
ERC External RC oscillator, OSC2 pin is FOSC/4 output(3).
ERCIO External RC oscillator, OSC2 pin is I/O(3).
FRC 7.37 MHz internal RC oscillator.
FRC w/PLL 4x 7.37 MHz Internal RC oscillator, 4x PLL enabled.
FRC w/PLL 8x 7.37 MHz Internal RC oscillator, 8x PLL enabled.
FRC w/PLL 16x 7.37 MHz Internal RC oscillator, 16x PLL enabled.
LPRC 512 kHz internal RC oscillator.
Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.
2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.
3: Requires external R and C. Frequency operation up to 4 MHz.

DS70139F-page 122 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

Oscillator Configuration bits

PWRSAV Instruction

Wake-up Request

FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<2:0>
Primary Osc
Internal FRC Osc
NOSC<2:0>

Primary
Internal Fast RC Oscillator OSWEN
Oscillator (FRC)
Stability Detector

Oscillator
POR Done Start-up
Timer Clock
Programmable
Switching
Secondary Osc Clock Divider System
and Control
Clock
Block
SOSCO
32 kHz LP Secondary 2
Oscillator
Oscillator
SOSCI Stability Detector
POST<1:0>

Internal Low LPRC

Power RC
Oscillator (LPRC)

CF
Fail-Safe Clock
FCKSM<1:0> Monitor (FSCM)
2 Oscillator Trap

To Timer1

© 2008 Microchip Technology Inc. DS70139F-page 123

dsPIC30F2011/2012/3012/3013
17.2 Oscillator Configurations 17.2.2 OSCILLATOR START-UP TIMER
(OST)
17.2.1 INITIAL CLOCK SOURCE
In order to ensure that a crystal oscillator (or ceramic
SELECTION resonator) has started and stabilized, an Oscillator
While coming out of Power-on Reset or Brown-out Start-up Timer is included. It is a simple 10-bit counter
Reset, the device selects its clock source based on: that counts 1024 TOSC cycles before releasing the
a) FOS<2:0> Configuration bits that select one of oscillator clock to the rest of the system. The time-out
four oscillator groups, period is designated as TOST.
b) and FPR<4:0> Configuration bits that select one The TOST time is involved every time the oscillator has
of 15 oscillator choices within the primary group. to restart (i.e., on POR, BOR and wake-up from Sleep).
The Oscillator Start-up Timer is applied to the LP
The selection is as shown in Table 17-2.
oscillator, XT, XTL and HS modes (upon wake-up from
Sleep, POR and BOR) for the primary oscillator.

TABLE 17-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator OSC2
Oscillator Mode FOS<2:0> FPR<4:0>
Source Function
ECIO w/PLL 4x PLL 1 1 1 0 1 1 0 1 I/O
ECIO w/PLL 8x PLL 1 1 1 0 1 1 1 0 I/O
ECIO w/PLL 16x PLL 1 1 1 0 1 1 1 1 I/O
FRC w/PLL 4X PLL 1 1 1 0 0 0 0 1 I/O
FRC w/PLL 8x PLL 1 1 1 0 1 0 1 0 I/O
FRC w/PLL 16x PLL 1 1 1 0 0 0 1 1 I/O
XT w/PLL 4x PLL 1 1 1 0 0 1 0 1 OSC2
XT w/PLL 8x PLL 1 1 1 0 0 1 1 0 OSC2
XT w/PLL 16x PLL 1 1 1 0 0 1 1 1 OSC2
HS2 w/PLL 4x PLL 1 1 1 1 0 0 0 1 OSC2
HS2 w/PLL 8x PLL 1 1 1 1 0 0 1 0 OSC2
HS2 w/ PLL 16x PLL 1 1 1 1 0 0 1 1 OSC2
HS3 w/PLL 4x PLL 1 1 1 1 0 1 0 1 OSC2
HS3 w/PLL 8x PLL 1 1 1 1 0 1 1 0 OSC2
HS3 w/PLL 16x PLL 1 1 1 1 0 1 1 1 OSC2
ECIO External 0 1 1 0 1 1 0 0 I/O
XT External 0 1 1 0 0 1 0 0 OSC2
HS External 0 1 1 0 0 0 1 0 OSC2
EC External 0 1 1 0 1 0 1 1 CLKO
ERC External 0 1 1 0 1 0 0 1 CLKO
ERCIO External 0 1 1 0 1 0 0 0 I/O
XTL External 0 1 1 0 0 0 0 0 OSC2
LP Secondary 0 0 0 X X X X X (Note 1, 2)
FRC Internal FRC 0 0 1 X X X X X (Note 1, 2)
LPRC Internal LPRC 0 1 0 X X X X X (Note 1, 2)
Note 1: The OSC2 pin is either usable as a general purpose I/O pin or is completely unusable, depending on the
Primary Oscillator mode selection (FPR<4:0>).
2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is
selected at all times.

DS70139F-page 124 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
17.2.3 LP OSCILLATOR CONTROL
Note: When a 16x PLL is used, the FRC fre-
Enabling the LP oscillator is controlled with two elements: quency must not be tuned to a frequency
1. The current oscillator group bits COSC<2:0>. greater than 7.5 MHz.
2. The LPOSCEN bit (OSCCON register).
TABLE 17-4: FRC TUNING
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if: TUN<3:0>
FRC Frequency
Bits
• COSC<2:0> = 000 (LP selected as main oscillator)
and 0111 + 10.5%
• LPOSCEN = 1 0110 + 9.0%
Keeping the LP oscillator on at all times allows for a fast 0101 + 7.5%
switch to the 32 kHz system clock for lower power oper- 0100 + 6.0%
ation. Returning to the faster main oscillator will still 0011 + 4.5%
require a start-up time 0010 + 3.0%
0001 + 1.5%
17.2.4 PHASE LOCKED LOOP (PLL)
0000 Center Frequency (oscillator is
The PLL multiplies the clock which is generated by the running at calibrated frequency)
primary oscillator or Fast RC oscillator. The PLL is
1111 - 1.5%
selectable to have either gains of x4, x8, and x16. Input
and output frequency ranges are summarized in 1110 - 3.0%
Table 17-3. 1101 - 4.5%
1100 - 6.0%
TABLE 17-3: PLL FREQUENCY RANGE 1011 - 7.5%
PLL 1010 - 9.0%
FIN FOUT
Multiplier 1001 - 10.5%
4 MHz-10 MHz x4 16 MHz-40 MHz 1000 - 12.0%
4 MHz-10 MHz x8 32 MHz-80 MHz
17.2.6 LOW-POWER RC OSCILLATOR
4 MHz-7.5 MHz x16 64 MHz-120 MHz (LPRC)
The PLL features a lock output which is asserted when The LPRC oscillator is a component of the Watchdog
the PLL enters a phase locked state. Should the loop Timer (WDT) and oscillates at a nominal frequency of
fall out of lock (e.g., due to noise), the lock signal will be 512 kHz. The LPRC oscillator is the clock source for
rescinded. The state of this signal is reflected in the the Power-up Timer (PWRT) circuit, WDT and clock
read-only LOCK bit in the OSCCON register. monitor circuits. It may also be used to provide a
low-frequency clock source option for applications
17.2.5 FAST RC OSCILLATOR (FRC) where power consumption is critical and timing accu-
The FRC oscillator is a fast (7.37 MHz ±2% nominal) racy is not required.
internal RC oscillator. This oscillator is intended to The LPRC oscillator is always enabled at a Power-on
provide reasonable device operating speeds without Reset because it is the clock source for the PWRT.
the use of an external crystal, ceramic resonator, or RC After the PWRT expires, the LPRC oscillator will remain
network. The FRC oscillator can be used with the PLL on if one of the following is true:
to obtain higher clock frequencies.
• The Fail-Safe Clock Monitor is enabled
The dsPIC30F operates from the FRC oscillator when-
• The WDT is enabled
ever the current oscillator selection control bits in the
OSCCON register (OSCCON<14:12>) are set to ‘001’. • The LPRC oscillator is selected as the system
clock via the COSC<2:0> control bits in the
The four bit field specified by TUN<3:0> (OSCTUN OSCCON register
<3:0>) allows the user to tune the internal fast RC
oscillator (nominal 7.37 MHz). The user can tune the If one of the above conditions is not true, the LPRC will
FRC oscillator within a range of +10.5% (840 kHz) shut-off after the PWRT expires.
and -12% (960 kHz) in steps of 1.50% around the Note 1: OSC2 pin function is determined by the
factory calibrated setting, see Table 17-4. Primary Oscillator mode selection
If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are (FPR<4:0>).
set to ‘00001’, ‘01010’ or ‘00011’, then a PLL 2: OSC1 pin cannot be used as an I/O pin
multiplier of 4, 8 or 16 (respectively) is applied. even if the secondary oscillator or an
internal clock source is selected at all
times.

© 2008 Microchip Technology Inc. DS70139F-page 125

dsPIC30F2011/2012/3012/3013
17.2.7 FAIL-SAFE CLOCK MONITOR The OSCCON register holds the Control and Status
bits related to clock switching.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator • COSC<2:0>: Read-only bits always reflect the
failure. The FSCM function is enabled by appropriately current oscillator group in effect.
programming the FCKSM Configuration bits (clock • NOSC<2:0>: Control bits which are written to
switch and monitor selection bits) in the FOSC Device indicate the new oscillator group of choice.
Configuration register. If the FSCM function is enabled, - On POR and BOR, COSC<2:0> and
the LPRC internal oscillator will run at all times (except NOSC<2:0> are both loaded with the Config-
during Sleep mode) and will not be subject to control by uration bit values FOS<2:0>.
the SWDTEN bit.
• LOCK: The LOCK bit indicates a PLL lock.
In the event of an oscillator failure, the FSCM will gen- • CF: Read-only bit indicating if a clock fail detect
erate a clock failure trap event and will switch the sys- has occurred.
tem clock over to the FRC oscillator. The user will then
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
have the option to either attempt to restart the oscillator
when a clock transition sequence is initiated.
or execute a controlled shutdown. The user may decide
Clearing the OSWEN control bit will abort a clock
to treat the trap as a warm Reset by simply loading the
transition in progress (used for hang-up
Reset address into the oscillator fail trap vector. In this
situations).
event, the CF (Clock Fail) bit (OSCCON<3>) is also set
whenever a clock failure is recognized. If Configuration bits FCKSM<1:0> = 1x, then the clock
switching and Fail-Safe Clock monitoring functions are
In the event of a clock failure, the WDT is unaffected
disabled. This is the default Configuration bit setting.
and continues to run on the LPRC clock.
If clock switching is disabled, then the FOS<2:0> and
If the oscillator has a very slow start-up time coming out
FPR<4:0> bits directly control the oscillator selection
of POR, BOR or Sleep, it is possible that the PWRT
and the COSC<2:0> bits do not control the clock selec-
timer will expire before the oscillator has started. In
tion. However, these bits will reflect the clock source
such cases, the FSCM will be activated and the FSCM
selection.
will initiate a clock failure trap, and the COSC<2:0> bits
are loaded with FRC oscillator selection. This will Note: The application should not attempt to
effectively shut-off the original oscillator that was trying switch to a clock of frequency lower than
to start. 100 kHz when the Fail-Safe Clock Monitor
The user may detect this situation and restart the is enabled. If such clock switching is
oscillator in the clock fail trap ISR. performed, the device may generate an
oscillator fail trap and switch to the Fast RC
Upon a clock failure detection, the FSCM module will
oscillator.
initiate a clock switch to the FRC oscillator as follows:
1. The COSC bits (OSCCON<14:12>) are loaded 17.2.8 PROTECTION AGAINST
with the FRC oscillator selection value. ACCIDENTAL WRITES TO OSCCON
2. CF bit is set (OSCCON<3>).
A write to the OSCCON register is intentionally made
3. OSWEN control bit (OSCCON<0>) is cleared. difficult because it controls clock switching and clock
For the purpose of clock switching, the clock sources scaling.
are sectioned into four groups: To write to the OSCCON low byte, the following code
1. Primary (with or without PLL) sequence must be executed without any other
2. Secondary instructions in between:
3. Internal FRC Byte Write “0x46” to OSCCON low
4. Internal LPRC Byte Write “0x57” to OSCCON low
The user can switch between these functional groups
Byte write is allowed for one instruction cycle. Write the
but cannot switch between options within a group. If the
desired value or use bit manipulation instruction.
primary group is selected, then the choice within the
group is always determined by the FPR<4:0> To write to the OSCCON high byte, the following
Configuration bits. instructions must be executed without any other
instructions in between:
Byte Write “0x78” to OSCCON high
Byte Write “0x9A” to OSCCON high

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

DS70139F-page 126 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
17.3 Reset Different registers are affected in different ways by
various Reset conditions. Most registers are not
The PIC18F1220/1320 differentiates between various affected by a WDT wake-up since this is viewed as the
kinds of Reset: resumption of normal operation. Status bits from the
a) Power-on Reset (POR) RCON register are set or cleared differently in different
b) MCLR Reset during normal operation Reset situations, as indicated in Table 17-5. These bits
are used in software to determine the nature of the
c) MCLR Reset during Sleep
Reset.
d) Watchdog Timer (WDT) Reset (during normal
operation) A block diagram of the On-Chip Reset Circuit is shown
in Figure 17-2.
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
g) Reset caused by trap lockup (TRAPR)
h) Reset caused by illegal opcode or by using an Internally generated Resets do not drive MCLR pin low.
uninitialized W register as an address pointer
(IOPUWR)

FIGURE 17-2: RESET SYSTEM BLOCK DIAGRAM

RESET
Instruction

Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module

VDD Rise POR

Detect S
VDD
Brown-out BOR
Reset
BOREN
R Q
SYSRST
Trap Conflict

Illegal Opcode/
Uninitialized W Register

17.3.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
A power-on event will generate an internal POR pulse
circuits are stable. Furthermore, a user selected
when a VDD rise is detected. The Reset pulse will occur
power-up time-out (TPWRT) is applied. The TPWRT
at the POR circuit threshold voltage (VPOR) which is
parameter is based on device Configuration bits and
nominally 1.85V. The device supply voltage
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
characteristics must meet specified starting voltage
delay is at device power-up, TPOR + TPWRT. When
and rise rate requirements. The POR pulse will reset a
these delays have expired, SYSRST will be negated on
POR timer and place the device in the Reset state. The
the next leading edge of the Q1 clock and the PC will
POR also selects the device clock source identified by
jump to the Reset vector.
the oscillator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 17-3 through Figure 17-5.

© 2008 Microchip Technology Inc. DS70139F-page 127

dsPIC30F2011/2012/3012/3013
FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TOST
OST TIME-OUT
TPWRT

PWRT TIME-OUT

INTERNAL Reset

FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TOST
OST TIME-OUT
TPWRT

PWRT TIME-OUT

INTERNAL Reset

FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TOST
OST TIME-OUT
TPWRT

PWRT TIME-OUT

INTERNAL Reset

DS70139F-page 128 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
17.3.1.1 POR with Long Crystal Start-up Time selected, the BOR will activate the Oscillator Start-up
(with FSCM Enabled) Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
The oscillator start-up circuitry is not linked to the POR
until the LOCK bit (OSCCON<5>) is ‘1’.
circuitry. Some crystal circuits (especially low
frequency crystals) will have a relatively long start-up Concurrently, the POR time-out (TPOR) and the PWRT
time. Therefore, one or more of the following conditions time-out (TPWRT) will be applied before the internal Reset
is possible after the POR timer and the PWRT have is released. If TPWRT = 0 and a crystal oscillator is being
expired: used, then a nominal delay of TFSCM = 100 μs is applied.
The total delay in this case is (TPOR + TFSCM).
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a The BOR Status bit (RCON<1>) will be set to indicate
crystal oscillator is used). that a BOR has occurred. The BOR circuit, if enabled,
will continue to operate while in Sleep or Idle modes
• The PLL has not achieved a LOCK (if PLL is
and will reset the device should VDD fall below the BOR
used).
threshold voltage.
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device FIGURE 17-6: EXTERNAL POWER-ON
will automatically switch to the FRC oscillator and the RESET CIRCUIT (FOR
user can switch to the desired crystal oscillator in the
SLOW VDD POWER-UP)
trap ISR.
VDD
17.3.1.2 Operating without FSCM and PWRT
If the FSCM is disabled and the Power-up Timer D R
(PWRT) is also disabled, then the device will exit rap- R1
MCLR
idly from Reset on power-up. If the clock source is
FRC, LPRC, ERC or EC, it will be active immediately. C dsPIC30F
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
perspective, the device will appear to be in Reset until
The diode D helps discharge the capacitor
a system clock is available. quickly when VDD powers down.
2: R should be suitably chosen so as to make
17.3.2 BOR: PROGRAMMABLE sure that the voltage drop across R does not
BROWN-OUT RESET violate the device’s electrical specifications.
The BOR (Brown-out Reset) module is based on an 3: R1 should be suitably chosen so as to limit
internal voltage reference circuit. The main purpose of any current flowing into MCLR from external
the BOR module is to generate a device Reset when a capacitor C, in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge
brown-out condition occurs. Brown-out conditions are
(ESD) or Electrical Overstress (EOS).
generally caused by glitches on the AC mains
(i.e., missing portions of the AC cycle waveform due to
bad power transmission lines, or voltage sags due to
Note: Dedicated supervisory devices, such as
excessive current draw when a large inductive load is
the MCP1XX and MCP8XX, may also be
turned on).
used as an external Power-on Reset
The BOR module allows selection of one of the circuit.
following voltage trip points (see Table 20-11):
• 2.6V-2.71V
• 4.1V-4.4V
• 4.58V-4.73V

Note: The BOR voltage trip points indicated here

are nominal values provided for design
guidance only. Refer to the Electrical
Specifications in the specific device data
sheet for BOR voltage limit specifications.
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source based on
the device Configuration bit values (FOS<2:0> and
FPR<4:0>). Furthermore, if an Oscillator mode is

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dsPIC30F2011/2012/3012/3013
Table 17-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.

TABLE 17-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1

Program
Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1
MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0
operation
Software Reset during 0x000000 0 0 0 1 0 0 0 0 0
normal operation
MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0
MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0
WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0
WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0
Interrupt Wake-up from PC + 2(1) 0 0 0 0 0 0 1 0 0
Sleep
Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0
Trap Reset 0x000000 1 0 0 0 0 0 0 0 0
Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

Table 17-6 shows a second example of the bit

conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.

TABLE 17-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2

Program
Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 u u u u u u u 0 1
MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u
operation
Software Reset during 0x000000 u u 0 1 0 0 0 u u
normal operation
MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u
MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u
WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u
WDT Wake-up PC + 2 u u u u 1 u 1 u u
Interrupt Wake-up from PC + 2(1) u u u u u u 1 u u
Sleep
Clock Failure Trap 0x000004 u u u u u u u u u
Trap Reset 0x000000 1 u u u u u u u u
Illegal Operation Reset 0x000000 u 1 u u u u u u u
Legend: u = unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

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 dsPIC30F2011/2012/3012/3013
17.4 Watchdog Timer (WDT) 17.6 Power-Saving Modes
17.4.1 WATCHDOG TIMER OPERATION There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV;
The primary function of the Watchdog Timer (WDT) is these are Sleep and Idle.
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer which The format of the PWRSAV instruction is as follows:
runs off an on-chip RC oscillator, requiring no external PWRSAV <parameter>, where ‘parameter’ defines
component. Therefore, the WDT timer will continue to Idle or Sleep mode.
operate even if the main processor clock (e.g., the
crystal oscillator) fails. 17.6.1 SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is
17.4.2 ENABLING AND DISABLING shut down. If an on-chip oscillator is being used, it is
THE WDT shut down.
The Watchdog Timer can be “Enabled” or “Disabled” The Fail-Safe Clock Monitor is not functional during
only through a Configuration bit (FWDTEN) in the Sleep since there is no clock to monitor. However,
Configuration register, FWDT. LPRC clock remains active if WDT is operational during
Setting FWDTEN = 1 enables the Watchdog Timer. The Sleep.
enabling is done when programming the device. By The brown-out protection circuit and the Low-Voltage
default, after chip erase, FWDTEN bit = 1. Any device Detect circuit, if enabled, will remain functional during
programmer capable of programming dsPIC30F Sleep.
devices allows programming of this and other
Configuration bits. The processor wakes up from Sleep if at least one of
the following conditions has occurred:
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset • any interrupt that is individually enabled and
(except during Sleep). To prevent a WDT time-out, the meets the required priority level
user must clear the Watchdog Timer using a CLRWDT • any Reset (POR, BOR and MCLR)
instruction. • WDT time-out
If a WDT times out during Sleep, the device will On waking up from Sleep mode, the processor will
wake-up. The WDTO bit in the RCON register will be restart the same clock that was active prior to entry into
cleared to indicate a wake-up resulting from a WDT Sleep mode. When clock switching is enabled, bits
time-out. COSC<2:0> will determine the oscillator source that
Setting FWDTEN = 0 allows user software to will be used on wake-up. If clock switch is disabled,
enable/disable the Watchdog Timer via the SWDTEN then there is only one system clock.
(RCON<5>) control bit. Note: If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<2:0>
17.5 Low Voltage Detect and FPR<4:0> Configuration bits.
The Low Voltage Detect (LVD) module is used to detect If the clock source is an oscillator, the clock to the
when the VDD of the device drops below a threshold device will be held off until OST times out (indicating a
value, VLVD, which is determined by the LVDL<3:0> stable oscillator). If PLL is used, the system clock is
bits (RCON<11:8>) and is thus user programmable. held off until LOCK = 1 (indicating that the PLL is
The internal voltage reference circuitry requires a nom- stable). In either case, TPOR, TLOCK and TPWRT delays
inal amount of time to stabilize, and the BGST bit are applied.
(RCON<13>) indicates when the voltage reference has If EC, FRC, LPRC or ERC oscillators are used, then a
stabilized. delay of TPOR (~ 10 μs) is applied. This is the smallest
In some devices, the LVD threshold voltage may be delay possible on wake-up from Sleep.
applied externally on the LVDIN pin. Moreover, if LP oscillator was active during Sleep and
The LVD module is enabled by setting the LVDEN bit LP is the oscillator used on wake-up, then the start-up
(RCON<12>). delay will be equal to TPOR. PWRT delay and OST
timer delay are not applied. In order to have the
smallest possible start-up delay when waking up from
Sleep, one of these faster wake-up options should be
selected before entering Sleep.

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dsPIC30F2011/2012/3012/3013
Any interrupt that is individually enabled (using the Any interrupt that is individually enabled (using IE bit)
corresponding IE bit) and meets the prevailing priority and meets the prevailing priority level will be able to
level will be able to wake-up the processor. The wake-up the processor. The processor will process the
processor will process the interrupt and branch to the interrupt and branch to the ISR. The Idle Status bit in
ISR. The Sleep Status bit in the RCON register is set the RCON register is set upon wake-up.
upon wake-up. Any Reset other than POR will set the Idle Status bit.
Note: In spite of various delays applied (TPOR, On a POR, the Idle bit is cleared.
TLOCK and TPWRT), the crystal oscillator If Watchdog Timer is enabled, then the processor will
(and PLL) may not be active at the end of wake-up from Idle mode upon WDT time-out. The Idle
the time-out (e.g., for low-frequency and WDTO Status bits are both set.
crystals). In such cases, if FSCM is
Unlike wake-up from Sleep, there are no time delays
enabled, then the device will detect this as a
involved in wake-up from Idle.
clock failure and process the clock failure
trap, the FRC oscillator will be enabled and
the user will have to re-enable the crystal 17.7 Device Configuration Registers
oscillator. If FSCM is not enabled, then the The Configuration bits in each device Configuration
device will simply suspend execution of register specify some of the device modes and are
code until the clock is stable and will remain programmed by a device programmer, or by using the
in Sleep until the oscillator clock has started. In-Circuit Serial Programming™ (ICSP™) feature of
All Resets will wake-up the processor from Sleep the device. Each device Configuration register is a
mode. Any Reset, other than POR, will set the Sleep 24-bit register, but only the lower 16 bits of each
Status bit. In a POR, the Sleep bit is cleared. register are used to hold configuration data. There are
If the Watchdog Timer is enabled, then the processor four device Configuration registers available to the
will wake-up from Sleep mode upon WDT time-out. The user:
Sleep and WDTO Status bits are both set. 1. FOSC (0xF80000): Oscillator Configuration
Register
17.6.2 IDLE MODE 2. FWDT (0xF80002): Watchdog Timer
In Idle mode, the clock to the CPU is shut down while Configuration Register
peripherals keep running. Unlike Sleep mode, the clock 3. FBORPOR (0xF80004): BOR and POR
source remains active. Configuration Register
Several peripherals have a control bit in each module 4. FGS (0xF8000A): General Code Segment
that allows them to operate during Idle. Configuration Register
LPRC Fail-Safe Clock remains active if clock failure 5. FICD (0xF8000C): FUSE Configuration
detect is enabled. Register
The processor wakes up from Idle if at least one of the The placement of the Configuration bits is
following conditions has occurred: automatically handled when you select the device in
your device programmer. The desired state of the
• any interrupt that is individually enabled (IE bit is Configuration bits may be specified in the source code
‘1’) and meets the required priority level (dependent on the language tool used), or through the
• any Reset (POR, BOR, MCLR) programming interface. After the device has been
• WDT time-out programmed, the application software may read the
Upon wake-up from Idle mode, the clock is re-applied Configuration bit values through the table read
to the CPU and instruction execution begins instructions. For additional information, please refer to
immediately, starting with the instruction following the the Programming Specifications of the device.
PWRSAV instruction. Note: If the code protection Configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages VDD ≥ 4.5V.

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 dsPIC30F2011/2012/3012/3013
17.8 Peripheral Module Disable (PMD) 17.9 In-Circuit Debugger
Registers When MPLAB® ICD2 is selected as a Debugger, the
The Peripheral Module Disable (PMD) registers In-Circuit Debugging functionality is enabled. This
provide a method to disable a peripheral module by function allows simple debugging functions when used
stopping all clock sources supplied to that module. with MPLAB IDE. When the device has this feature
When a peripheral is disabled via the appropriate PMD enabled, some of the resources are not available for
control bit, the peripheral is in a minimum power general use. These resources include the first 80 bytes
consumption state. The Control and Status registers of Data RAM and two I/O pins.
associated with the peripheral will also be disabled so One of four pairs of Debug I/O pins may be selected by
writes to those registers will have no effect and read the user using configuration options in MPLAB IDE.
values will be invalid. These pin pairs are named EMUD/EMUC,
A peripheral module will only be enabled if both the EMUD1/EMUC1, EMUD2/EMUC2 and
associated bit in the PMD register is cleared and the EMUD3/EMUC3.
peripheral is supported by the specific dsPIC DSC In each case, the selected EMUD pin is the
variant. If the peripheral is present in the device, it is Emulation/Debug Data line, and the EMUC pin is the
enabled in the PMD register by default. Emulation/Debug Clock line. These pins will interface
Note: If a PMD bit is set, the corresponding to the MPLAB ICD 2 module available from Microchip.
module is disabled after a delay of 1 The selected pair of Debug I/O pins is used by MPLAB
instruction cycle. Similarly, if a PMD bit is ICD 2 to send commands and receive responses, as
cleared, the corresponding module is well as to send and receive data. To use the In-Circuit
enabled after a delay of 1 instruction cycle Debugger function of the device, the design must
(assuming the module Control registers implement ICSP connections to MCLR, VDD, VSS,
are already configured to enable module PGC, PGD and the selected EMUDx/EMUCx pin pair.
operation). This gives rise to two possibilities:
1. If EMUD/EMUC is selected as the Debug I/O pin
pair, then only a 5-pin interface is required, as
Note: In the dsPIC30F2011, dsPIC30F3012 and
the EMUD and EMUC pin functions are multi-
dsPIC30F2012 devices, the U2MD bit is
plexed with the PGD and PGC pin functions in
readable and writable and will be read as
all dsPIC30F devices.
‘1’ when set.
2. If EMUD1/EMUC1, EMUD2/EMUC2 or
EMUD3/EMUC3 is selected as the Debug I/O
pin pair, then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.

© 2008 Microchip Technology Inc. DS70139F-page 133

 TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP
DS70139F-page 134

dsPIC30F2011/2012/3012/3013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)
OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN (Note 2)
OSCTUN 0744 — — — — — — — — — — — — TUN3 TUN2 TUN1 TUN0 (Note 2)
PMD1 0770 — — T3MD T2MD T1MD — — — I2CMD U2MD(3) U1MD — SPI1MD — — ADCMD 0000 0000 0000 0000
PMD2 0772 — — — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Reset state depends on type of Reset.
2: Reset state depends on Configuration bits.
3: Only available on dsPIC30F3013.

TABLE 17-8: DEVICE CONFIGURATION REGISTER MAP

File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FOSC F80000 — FCKSM<1:0> — — — FOS<2:0> — — — FPR<4:0>

FWDT F80002 — FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 — MCLREN — — — — Reserved(1) Reserved(1) Reserved(1) BOREN — BORV<1:0> — — FPWRT<1:0>
FGS F8000A — — — — — — — — — — — — — — Reserved(2) GCP GWRP
FICD F8000C — — — — — — — — — BKBUG COE — — — — ICS<1:0>
Legend: — = unimplemented bit, read as ‘0’
Note 1: These bits are always read as ‘1’.
2: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
3: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F2011/2012/3012/3013
18.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
Note: This data sheet summarizes features of • The W register (with or without an address
this group of dsPIC30F devices and is not modifier) or file register (specified by the value of
intended to be a complete reference ‘Ws’ or ‘f’)
source. For more information on the CPU,
• The bit in the W register or file register
peripherals, register descriptions and
(specified by a literal value or indirectly by the
general device functionality, refer to the
contents of register ‘Wb’)
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the The literal instructions that involve data movement may
device instruction set and programming, use some of the following operands:
refer to the “dsPIC30F Programmer’s • A literal value to be loaded into a W register or file
Reference Manual” (DS70030). register (specified by the value of ‘k’)
The dsPIC30F instruction set adds many • The W register or file register where the literal
enhancements to the previous PIC® MCU instruction value is to be loaded (specified by ‘Wb’ or ‘f’)
sets, while maintaining an easy migration from PIC However, literal instructions that involve arithmetic or
MCU instruction sets. logical operations use some of the following operands:
Most instructions are a single program memory word • The first source operand which is a register ‘Wb’
(24 bits). Only three instructions require two program without any address modifier
memory locations. • The second source operand which is a literal
Each single-word instruction is a 24-bit word divided value
into an 8-bit opcode which specifies the instruction • The destination of the result (only if not the same
type, and one or more operands which further specify as the first source operand) which is typically a
the operation of the instruction. register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped The MAC class of DSP instructions may use some of the
into five basic categories: following operands:
• Word or byte-oriented operations • The accumulator (A or B) to be used (required
• Bit-oriented operations operand)
• Literal operations • The W registers to be used as the two operands
• DSP operations
• The X and Y address space prefetch operations
• Control operations
• The X and Y address space prefetch destinations
Table 18-1 shows the general symbols used in
• The accumulator write-back destination
describing the instructions.
The other DSP instructions do not involve any
The dsPIC30F instruction set summary in Table 18-2
multiplication, and may include:
lists all the instructions, along with the status flags
affected by each instruction. • The accumulator to be used (required)
Most word or byte-oriented W register instructions • The source or destination operand (designated as
(including barrel shift instructions) have three Wso or Wdo, respectively) with or without an
operands: address modifier
• The amount of shift specified by a W register ‘Wn’
• The first source operand which is typically a
or a literal value
register ‘Wb’ without any address modifier
• The second source operand which is typically a The control instructions may use some of the following
register ‘Ws’ with or without an address modifier operands:
• The destination of the result which is typically a • A program memory address
register ‘Wd’ with or without an address modifier • The mode of the table read and table write
However, word or byte-oriented file register instructions instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’

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dsPIC30F2011/2012/3012/3013
All instructions are a single word, except for certain RETURN/RETFIE instructions, which are single-word
double-word instructions, which were made instructions but take two or three cycles. Certain
double-word instructions so that all the required instructions that involve skipping over the subsequent
information is available in these 48 bits. In the second instruction require either two or three cycles if the skip
word, the 8 MSbs are ‘0’s. If this second word is is performed, depending on whether the instruction
executed as an instruction (by itself), it will execute as being skipped is a single-word or two-word instruction.
a NOP. Moreover, double-word moves require two cycles. The
Most single-word instructions are executed in a single double-word instructions execute in two instruction
instruction cycle, unless a conditional test is true or the cycles.
program counter is changed as a result of the Note: For more details on the instruction set,
instruction. In these cases, the execution takes two refer to the Programmer’s Reference
instruction cycles with the additional instruction Manual.
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect
CALL/GOTO, all table reads and writes, and

TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description
#text Means literal defined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator write-back destination address register ∈ {W13, [W13]+=2}
bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address ∈ {0x0000...0x1FFF}
lit1 1-bit unsigned literal ∈ {0,1}
lit4 4-bit unsigned literal ∈ {0...15}
lit5 5-bit unsigned literal ∈ {0...31}
lit8 8-bit unsigned literal ∈ {0...255}
lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal ∈ {0...16384}
lit16 16-bit unsigned literal ∈ {0...65535}
lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be 0
None Field does not require an entry, may be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal ∈ {-512...511}
Slit16 16-bit signed literal ∈ {-32768...32767}
Slit6 6-bit signed literal ∈ {-16...16}

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 dsPIC30F2011/2012/3012/3013
TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wb Base W register ∈ {W0..W15}
Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn One of 16 working registers ∈ {W0..W15}
Wnd One of 16 destination working registers ∈ {W0..W15}
Wns One of 16 source working registers ∈ {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space prefetch address register for DSP instructions
∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7}
Wy Y data space prefetch address register for DSP instructions
∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

© 2008 Microchip Technology Inc. DS70139F-page 137

dsPIC30F2011/2012/3012/3013
TABLE 18-2: INSTRUCTION SET OVERVIEW
Base # of
Assembly # of Status Flags
Instr Assembly Syntax Description Cycle
Mnemonic Words Affected
# s

1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3 AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6 BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if greater than or equal 1 1 (2) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None
BRA GT,Expr Branch if greater than 1 1 (2) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None
BRA LE,Expr Branch if less than or equal 1 1 (2) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None
BRA LT,Expr Branch if less than 1 1 (2) None
BRA LTU,Expr Branch if unsigned less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None
BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None
BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
7 BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

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 dsPIC30F2011/2012/3012/3013
TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base # of
Assembly # of Status Flags
Instr Assembly Syntax Description Cycle
Mnemonic Words Affected
# s

9 BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None
(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call subroutine 2 2 None
CALL Wn Call indirect subroutine 1 2 None
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f=f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z
(Wb - Ws - C)
21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None
(2 or 3)
22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None
(2 or 3)
23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None
(2 or 3)
24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None
(2 or 3)
25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
26 DEC DEC f f = f -1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f = f -2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

© 2008 Microchip Technology Inc. DS70139F-page 139

dsPIC30F2011/2012/3012/3013
TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base # of
Assembly # of Status Flags
Instr Assembly Syntax Description Cycle
Mnemonic Words Affected
# s

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
31 DO DO #lit14,Expr Do code to PC+Expr, lit14+1 times 2 2 None
DO Wn,Expr Do code to PC+Expr, (Wn)+1 times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to address 2 2 None
GOTO Wn Go to indirect 1 2 None
39 INC INC f f=f+1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f=f+2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
43 LNK LNK #lit14 Link frame pointer 1 1 None
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB,
, SA,SB,SAB
AWB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 N,Z
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N,Z
MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None

DS70139F-page 140 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base # of
Assembly # of Status Flags
Instr Assembly Syntax Description Cycle
Mnemonic Words Affected
# s

48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB
MPY Square Wm to Accumulator 1 1 OA,OB,OAB,
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB
49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
, SA,SB,SAB
AWB
51 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * 1 1 None
unsigned(Ws)
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) * 1 1 None
signed(Ws)
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(Ws)
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(lit5)
MUL f W3:W2 = f * WREG 1 1 None
52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f=f+1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
53 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
54 POP POP f Pop f from top-of-stack (TOS) 1 1 None
POP Wdo Pop from top-of-stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from top-of-stack (TOS) to 1 2 None
W(nd):W(nd+1)
POP.S Pop Shadow Registers 1 1 All
55 PUSH PUSH f Push f to top-of-stack (TOS) 1 1 None
PUSH Wso Push Wso to top-of-stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns+1) to top-of-stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
57 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14+1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn)+1 times 1 1 None
59 RESET RESET Software device Reset 1 1 None
60 RETFIE RETFIE Return from interrupt 1 3 (2) None
61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None
62 RETURN RETURN Return from Subroutine 1 3 (2) None
63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

© 2008 Microchip Technology Inc. DS70139F-page 141

dsPIC30F2011/2012/3012/3013
TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base # of
Assembly # of Status Flags
Instr Assembly Syntax Description Cycle
Mnemonic Words Affected
# s

66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z
69 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
71 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f - WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z
73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z
74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z
75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG -f - (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z
76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
81 ULNK ULNK Unlink frame pointer 1 1 None
82 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

DS70139F-page 142 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
19.0 DEVELOPMENT SUPPORT 19.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers are supported with a full
range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit
microcontroller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB REAL ICE™ In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
- PICkit™ 2 Development Programmer • Integration of select third party tools, such as
• Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR
Boards and Evaluation Kits C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

© 2008 Microchip Technology Inc. DS70139F-page 143

dsPIC30F2011/2012/3012/3013
19.2 MPASM Assembler 19.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline
assembly code • Command line interface
• Conditional assembly for multi-purpose • Rich directive set
source files • Flexible macro language
• Directives that allow complete control over the • MPLAB IDE compatibility
assembly process
19.6 MPLAB SIM Software Simulator
19.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code
C Compilers development in a PC-hosted environment by
The MPLAB C18 and MPLAB C30 Code Development simulating the PIC MCUs and dsPIC® DSCs on an
Systems are complete ANSI C compilers for instruction level. On any given instruction, the data
Microchip’s PIC18 and PIC24 families of areas can be examined or modified and stimuli can be
microcontrollers and the dsPIC30 and dsPIC33 family applied from a comprehensive stimulus controller.
of digital signal controllers. These compilers provide Registers can be logged to files for further run-time
powerful integration capabilities, superior code analysis. The trace buffer and logic analyzer display
optimization and ease of use not found with other extend the power of the simulator to record and track
compilers. program execution, actions on I/O, most peripherals
and internal registers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE The MPLAB SIM Software Simulator fully supports
debugger. symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
19.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside
MPLIB Object Librarian of the hardware laboratory environment, making it an
The MPLINK Object Linker combines relocatable excellent, economical software development tool.
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

DS70139F-page 144 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
19.7 MPLAB ICE 2000 19.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PIC
complete microcontroller design tool set for PIC MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
2000 In-Circuit Emulator is advanced by the MPLAB the in-circuit debugging capability built into the Flash
Integrated Development Environment, which allows devices. This feature, along with Microchip’s In-Circuit
editing, building, downloading and source debugging Serial ProgrammingTM (ICSPTM) protocol, offers
from a single environment. cost-effective, in-circuit Flash debugging from the graph-
ical user interface of the MPLAB Integrated Develop-
The MPLAB ICE 2000 is a full-featured emulator ment Environment. This enables a designer to develop
system with enhanced trace, trigger and data and debug source code by setting breakpoints, single
monitoring features. Interchangeable processor stepping and watching variables, and CPU status and
modules allow the system to be easily reconfigured for peripheral registers. Running at full speed enables
emulation of different processors. The architecture of testing hardware and applications in real time. MPLAB
the MPLAB ICE 2000 In-Circuit Emulator allows ICD 2 also serves as a development programmer for
expansion to support new PIC microcontrollers. selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 19.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a
modular, detachable socket assembly to support
19.8 MPLAB REAL ICE In-Circuit
various package types. The ICSP™ cable assembly is
Emulator System included as a standard item. In Stand-Alone mode, the
MPLAB REAL ICE In-Circuit Emulator System is MPLAB PM3 Device Programmer can read, verify and
Microchip’s next generation high-speed emulator for program PIC devices without a PC connection. It can
Microchip Flash DSC and MCU devices. It debugs and also set code protection in this mode. The MPLAB PM3
programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable.
with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and
the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large
included with each kit. memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant,
Low-Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be
supported, and new features will be added, such as
software breakpoints and assembly code trace.
MPLAB REAL ICE offers significant advantages over
competitive emulators including low-cost, full-speed
emulation, real-time variable watches, trace analysis,
complex breakpoints, a ruggedized probe interface and
long (up to three meters) interconnection cables.

© 2008 Microchip Technology Inc. DS70139F-page 145

dsPIC30F2011/2012/3012/3013
19.11 PICSTART Plus Development 19.13 Demonstration, Development and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully
Integrated Development Environment software makes functional systems. Most boards include prototyping
using the programmer simple and efficient. The areas for adding custom circuitry and provide application
PICSTART Plus Development Programmer supports firmware and source code for examination and modifica-
most PIC devices in DIP packages up to 40 pins. tion.
Larger pin count devices, such as the PIC16C92X and The boards support a variety of features, including LEDs,
PIC17C76X, may be supported with an adapter socket. temperature sensors, switches, speakers, RS-232
The PICSTART Plus Development Programmer is CE interfaces, LCD displays, potentiometers and additional
compliant. EEPROM memory.
The demonstration and development boards can be
19.12 PICkit 2 Development Programmer
used in teaching environments, for prototyping custom
The PICkit™ 2 Development Programmer is a low-cost circuits and for learning about various microcontroller
programmer and selected Flash device debugger with applications.
an easy-to-use interface for programming many of In addition to the PICDEM™ and dsPICDEM™
Microchip’s baseline, mid-range and PIC18F families of demonstration/development board series of circuits,
Flash memory microcontrollers. The PICkit 2 Starter Kit Microchip has a line of evaluation kits and
includes a prototyping development board, twelve demonstration software for analog filter design,
sequential lessons, software and HI-TECH’s PICC™ KEELOQ® security ICs, CAN, IrDA®, PowerSmart
Lite C compiler, and is designed to help get up to speed battery management, SEEVAL® evaluation system,
quickly using PIC® microcontrollers. The kit provides Sigma-Delta ADC, flow rate sensing, plus many more.
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range Check the Microchip web page (www.microchip.com)
Flash memory family of microcontrollers. for the complete list of demonstration, development
and evaluation kits.

DS70139F-page 146 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
20.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1) ..................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS........................................................................................................ 0V to +13.25V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 2)................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 20-2 for PDMAX.

†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer to the Family Cross Reference Table.

20.1 DC Characteristics

TABLE 20-1: OPERATING MIPS VS. VOLTAGE

Max MIPS
VDD Range Temp Range
dsPIC30FXXX-30I dsPIC30FXXX-20E
4.5-5.5V -40°C to 85°C 30 —
4.5-5.5V -40°C to 125°C — 20
3.0-3.6V -40°C to 85°C 20 —
3.0-3.6V -40°C to 125°C — 15
2.5-3.0V -40°C to 85°C 10 —

© 2008 Microchip Technology Inc. DS70139F-page 147

dsPIC30F2011/2012/3012/3013
TABLE 20-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
dsPIC30F201x-30I
dsPIC30F301x-30I
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
dsPIC30F201x-20E
dsPIC30F301x-20E

Operating Junction Temperature Range TJ -40 — +150 °C

Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal chip power dissipation:
P INT = V DD × ( I DD – ∑ I OH) PD PINT + PI/O W
I/O Pin power dissipation:
P I/O = ∑ ( { V D D – V O H } × I OH ) + ∑ ( V OL × I OL )
Maximum Allowed Power Dissipation PDMAX (TJ - TA) / θJA W
TABLE 20-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 18-pin PDIP (P) θJA 44 — °C/W 1
Package Thermal Resistance, 18-pin SOIC (SO) θJA 57 — °C/W 1
Package Thermal Resistance, 28-pin SPDIP (SP) θJA 42 — °C/W 1
Package Thermal Resistance, 28-pin (SOIC) θJA 49 — °C/W 1
Package Thermal Resistance, 44-pin QFN θJA 28 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.
TABLE 20-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Operating Voltage(2)
DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature
DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature
DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V
DC16 VPOR VDD Start Voltage (to ensure — — VSS V
internal Power-on Reset signal)
DC17 SVDD VDD Rise Rate (to ensure 0.05 — — V/ms 0-5V in 0.1 sec
internal Power-on Reset signal) 0-3V in 60 ms
Note 1: “Typ” column data is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: This is the limit to which VDD can be lowered without losing RAM data.

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 dsPIC30F2011/2012/3012/3013
TABLE 20-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1) Max Units Conditions
No.
Operating Current (IDD)(2)
DC31a 1.6 3.0 mA 25°C
DC31b 1.6 3.0 mA 85°C 3.3V
DC31c 1.6 3.0 mA 125°C 0.128 MIPS
DC31e 3.6 6.0 mA 25°C LPRC (512 kHz)
DC31f 3.3 6.0 mA 85°C 5V
DC31g 3.2 6.0 mA 125°C
DC30a 3.0 5.0 mA 25°C
DC30b 3.0 5.0 mA 85°C 3.3V
DC30c 3.1 5.0 mA 125°C (1.8 MIPS)
DC30e 6.0 9.0 mA 25°C FRC (7.37 MHz)
DC30f 5.8 9.0 mA 85°C 5V
DC30g 5.7 9.0 mA 125°C
DC23a 9.0 15.0 mA 25°C
DC23b 10.0 15.0 mA 85°C 3.3V
DC23c 10.0 15.0 mA 125°C
4 MIPS
DC23e 16.0 24.0 mA 25°C
DC23f 16.0 24.0 mA 85°C 5V
DC23g 16.0 24.0 mA 125°C
DC24a 22.0 33.0 mA 25°C
DC24b 22.0 33.0 mA 85°C 3.3V
DC24c 22.0 33.0 mA 125°C
10 MIPS
DC24e 37.0 56.0 mA 25°C
DC24f 37.0 56.0 mA 85°C 5V
DC24g 37.0 56.0 mA 125°C
DC27a 41.0 60.0 mA 25°C
3.3V
DC27b 40.0 60.0 mA 85°C
DC27d 68.0 90.0 mA 25°C 20 MIPS
DC27e 67.0 90.0 mA 85°C 5V
DC27f 66.0 90.0 mA 125°C
DC29a 96.0 140.0 mA 25°C
5V 30 MIPS
DC29b 94.0 140.0 mA 85°C
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.

© 2008 Microchip Technology Inc. DS70139F-page 149

dsPIC30F2011/2012/3012/3013
TABLE 20-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1) Max Units Conditions
No.
Operating Current (IDD)(2)
DC51a 1.3 2.5 mA 25°C
DC51b 1.3 2.5 mA 85°C 3.3V
DC51c 1.2 2.5 mA 125°C 0.128 MIPS
DC51e 3.2 5.0 mA 25°C LPRC (512 kHz)
DC51f 2.9 5.0 mA 85°C 5V
DC51g 2.8 5.0 mA 125°C
DC50a 3.0 5.0 mA 25°C
DC50b 3.0 5.0 mA 85°C 3.3V
DC50c 3.0 5.0 mA 125°C (1.8 MIPS)
DC50e 6.0 9.0 mA 25°C FRC (7.37 MHz)
DC50f 5.8 9.0 mA 85°C 5V
DC50g 5.7 9.0 mA 125°C
DC43a 5.2 8.0 mA 25°C
DC43b 5.3 8.0 mA 85°C 3.3V
DC43c 5.4 8.0 mA 125°C
4 MIPS
DC43e 9.7 15.0 mA 25°C
DC43f 9.6 15.0 mA 85°C 5V
DC43g 9.5 15.0 mA 125°C
DC44a 11.0 17.0 mA 25°C
DC44b 11.0 17.0 mA 85°C 3.3V
DC44c 11.0 17.0 mA 125°C
10 MIPS
DC44e 19.0 29.0 mA 25°C
DC44f 19.0 29.0 mA 85°C 5V
DC44g 20.0 30.0 mA 125°C
DC47a 20.0 35.0 mA 25°C
3.3V
DC47b 21.0 35.0 mA 85°C
DC47d 35.0 50.0 mA 25°C 20 MIPS
DC47e 36.0 50.0 mA 85°C 5V
DC47f 36.0 50.0 mA 125°C
DC49a 51.0 70.0 mA 25°C
5V 30 MIPS
DC49b 51.0 70.0 mA 85°C
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

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 dsPIC30F2011/2012/3012/3013
TABLE 20-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1) Max Units Conditions
No.
Power-Down Current (IPD)(2)
DC60a 0.3 — μA 25°C
DC60b 1.3 30.0 μA 85°C 3.3V
DC60c 16.0 60.0 μA 125°C
Base Power-Down Current(3)
DC60e 0.5 — μA 25°C
DC60f 3.7 45.0 μA 85°C 5V
DC60g 25.0 90.0 μA 125°C
DC61a 6.0 9.0 μA 25°C
DC61b 6.0 9.0 μA 85°C 3.3V
DC61c 6.0 9.0 μA 125°C
Watchdog Timer Current: ΔIWDT(3)
DC61e 13.0 20.0 μA 25°C
DC61f 12.0 20.0 μA 85°C 5V
DC61g 12.0 20.0 μA 125°C
DC62a 4.0 10.0 μA 25°C
DC62b 5.0 10.0 μA 85°C 3.3V
DC62c 4.0 10.0 μA 125°C
Timer1 w/32 kHz Crystal: ΔITI32(3)
DC62e 4.0 15.0 μA 25°C
DC62f 6.0 15.0 μA 85°C 5V
DC62g 5.0 15.0 μA 125°C
DC63a 33.0 53.0 μA 25°C
DC63b 35.0 53.0 μA 85°C 3.3V
DC63c 19.0 53.0 μA 125°C
BOR On: ΔIBOR(3)
DC63e 38.0 62.0 μA 25°C
DC63f 41.0 62.0 μA 85°C 5V
DC63g 41.0 62.0 μA 125°C
DC66a 21.0 40.0 μA 25°C
DC66b 26.0 40.0 μA 85°C 3.3V
DC66c 27.0 40.0 μA 125°C
Low-Voltage Detect: ΔILVD(3)
DC66e 25.0 44.0 μA 25°C
DC66f 27.0 44.0 μA 85°C 5V
DC66g 29.0 44.0 μA 125°C
Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

© 2008 Microchip Technology Inc. DS70139F-page 151

dsPIC30F2011/2012/3012/3013
TABLE 20-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
VIL Input Low Voltage(2)
DI10 I/O pins:
with Schmitt Trigger buffer VSS — 0.2 VDD V
DI15 MCLR VSS — 0.2 VDD V
DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2 VDD V
DI17 OSC1 (in RC mode)(3) VSS — 0.3 VDD V
DI18 SDA, SCL VSS — 0.3 VDD V SM bus disabled
DI19 SDA, SCL VSS — 0.2 VDD V SM bus enabled
VIH (2)
Input High Voltage
DI20 I/O pins:
with Schmitt Trigger buffer 0.8 VDD — VDD V
DI25 MCLR 0.8 VDD — VDD V
DI26 OSC1 (in XT, HS and LP modes) 0.7 VDD — VDD V
DI27 OSC1 (in RC mode)(3) 0.9 VDD — VDD V
DI28 SDA, SCL 0.7 VDD — VDD V SM bus disabled
DI29 SDA, SCL 0.8 VDD — VDD V SM bus enabled
ICNPU CNXX Pull-up Current(2)
DI30 50 250 400 μA VDD = 5V, VPIN = VSS
IIL Input Leakage Current(2)(4)(5)
DI50 I/O ports — 0.01 ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high impedance
DI51 Analog input pins — 0.50 — μA VSS ≤ VPIN ≤ VDD,
Pin at high impedance
DI55 MCLR — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD
DI56 OSC1 — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS
and LP Osc mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
5: Negative current is defined as current sourced by the pin.

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 dsPIC30F2011/2012/3012/3013
TABLE 20-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
VOL Output Low Voltage(2)
DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V
— — 0.15 V IOL = 2.0 mA, VDD = 3V
DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V
(RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V
(2)
VOH Output High Voltage
DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V
VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V
DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V
(RC or EC Osc mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V
Capacitive Loading Specs
on Output Pins(2)
DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes
when external clock is used to
drive OSC1.
DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode
DO58 CB SCL, SDA — — 400 pF In I2C mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.

© 2008 Microchip Technology Inc. DS70139F-page 153

dsPIC30F2011/2012/3012/3013
FIGURE 20-1: LOW-VOLTAGE DETECT CHARACTERISTICS

VDD

LV10

LVDIF
(LVDIF set by hardware)

TABLE 20-10: ELECTRICAL CHARACTERISTICS: LVDL

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
LV10 VPLVD LVDL Voltage on VDD transition LVDL = 0000(2) — — — V
high-to-low
LVDL = 0001(2) — — — V
LVDL = 0010(2) — — — V
LVDL = 0011(2) — — — V
LVDL = 0100 2.50 — 2.65 V
LVDL = 0101 2.70 — 2.86 V
LVDL = 0110 2.80 — 2.97 V
LVDL = 0111 3.00 — 3.18 V
LVDL = 1000 3.30 — 3.50 V
LVDL = 1001 3.50 — 3.71 V
LVDL = 1010 3.60 — 3.82 V
LVDL = 1011 3.80 — 4.03 V
LVDL = 1100 4.00 — 4.24 V
LVDL = 1101 4.20 — 4.45 V
LVDL = 1110 4.50 — 4.77 V
LV15 VLVDIN External LVD input pin LVDL = 1111 — — — V
threshold voltage
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values not in usable operating range.

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 dsPIC30F2011/2012/3012/3013
FIGURE 20-2: BROWN-OUT RESET CHARACTERISTICS

VDD

(Device not in Brown-out Reset)

BO15
BO10
(Device in Brown-out Reset)

RESET (due to BOR)

Power-Up Time-out

TABLE 20-11: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
BO10 VBOR BOR Voltage(2) on BORV = 11(3) — — — V Not in operating
VDD transition high to range
low BORV = 10 2.6 — 2.71 V
BORV = 01 4.1 — 4.4 V
BORV = 00 4.58 — 4.73 V
BO15 VBHYS — 5 — mV
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: 11 values not in usable operating range.

© 2008 Microchip Technology Inc. DS70139F-page 155

dsPIC30F2011/2012/3012/3013
TABLE 20-12: DC CHARACTERISTICS: PROGRAM AND EEPROM
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Data EEPROM Memory(2)
D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to Read/Write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 2 — ms
D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications
are violated
D124 IDEW IDD During Programming — 10 30 mA Row Erase
Program Flash Memory(2)
D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VEB VDD for Bulk Erase 4.5 — 5.5 V
D133 VPEW VDD for Erase/Write 3.0 — 5.5 V
D134 TPEW Erase/Write Cycle Time 1 — 2 ms
D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications
are violated
D136 TEB ICSP™ Block Erase Time — 4 — ms
D137 IPEW IDD During Programming — 10 30 mA Row Erase
D138 IEB IDD During Programming — 10 30 mA Bulk Erase
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
2: These parameters are characterized but not tested in manufacturing.

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 dsPIC30F2011/2012/3012/3013
20.2 AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 20-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in Section 20.1 “DC
Characteristics”.

FIGURE 20-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 — for all pins except OSC2 Load Condition 2 — for OSC2

VDD/2

RL Pin CL

VSS
CL Legend:
Pin
RL = 464 Ω
VSS CL = 50 pF for all pins except OSC2
5 pF for OSC2 output

FIGURE 20-4: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO

OS40 OS41

© 2008 Microchip Technology Inc. DS70139F-page 157

dsPIC30F2011/2012/3012/3013
TABLE 20-14: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
OS10 FOSC External CLKN Frequency(2) DC — 40 MHz EC
(External clocks allowed only 4 — 10 MHz EC with 4x PLL
in EC mode) 4 — 10 MHz EC with 8x PLL
4 — 7.5 MHz EC with 16x PLL
Oscillator Frequency(2) DC — 4 MHz RC
0.4 — 4 MHz XTL
4 — 10 MHz XT
4 — 10 MHz XT with 4x PLL
4 — 10 MHz XT with 8x PLL
4 — 7.5 MHz XT with 16x PLL
10 — 25 MHz HS
10 — 20 MHz HS/2 with 4x PLL
10 — 20 MHz HS/2 with 8x PLL
10 — 15 MHz HS/2 with 16x PLL
12 — 25 MHz HS/3 with 4x PLL
12 — 25 MHz HS/3 with 8x PLL
12 — 22.5 MHz HS/3 with 16x PLL
31 — 33 kHz LP
— 7.37 — MHz FRC internal
— 7.37 — MHz FRC internal w/4x PLL
— 7.37 — MHz FRC internal w/8x PLL
— 7.37 — MHz FRC internal w/16x PLL
— 512 — kHz LPRC internal
OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10
for FOSC value
OS25 TCY Instruction Cycle Time(2)(3) 33 — DC ns See Table 20-17
(2)
OS30 TosL, External Clock in (OSC1) .45 x — — ns EC
TosH High or Low Time TOSC
OS31 TosR, External Clock(2) in (OSC1) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(2)(4) — — — ns See parameter DO31
(2)(4)
OS41 TckF CLKO Fall Time — — — ns See parameter DO32
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
4: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is
low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

DS70139F-page 158 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 20-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OS50 FPLLI PLL Input Frequency Range(2) 4 — 10 MHz EC with 4x PLL
4 — 10 MHz EC with 8x PLL
4 — 7.5(4) MHz EC with 16x PLL
4 — 10 MHz XT with 4x PLL
4 — 10 MHz XT with 8x PLL
4 — 7.5(4) MHz XT with 16x PLL
5(3) — 10 MHz HS/2 with 4x PLL
5(3) — 10 MHz HS/2 with 8x PLL
5(3) — 7.5(4) MHz HS/2 with 16x PLL
4 — 8.33(3) MHz HS/3 with 4x PLL
4 — 8.33(3) MHz HS/3 with 8x PLL
4 — 7.5(4) MHz HS/3 with 16x PLL
OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT, HS/2, HS/3
modes with PLL
OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Limited by oscillator frequency range.
4: Limited by device operating frequency range.
TABLE 20-16: PLL JITTER
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
Characteristic Min Typ(1) Max Units Conditions
No.
OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V
— 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V
— 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
Note 1: These parameters are characterized but not tested in manufacturing.

© 2008 Microchip Technology Inc. DS70139F-page 159

dsPIC30F2011/2012/3012/3013
TABLE 20-17: INTERNAL CLOCK TIMING EXAMPLES
Clock
FOSC MIPS(3) MIPS(3) MIPS(3) MIPS(3)
Oscillator TCY (μsec)(2)
(MHz)(1) w/o PLL w PLL x4 w PLL x8 w PLL x16
Mode
EC 0.200 20.0 0.05 — — —
4 1.0 1.0 4.0 8.0 16.0
10 0.4 2.5 10.0 20.0 —
25 0.16 6.25 — — —
XT 4 1.0 1.0 4.0 8.0 16.0
10 0.4 2.5 10.0 20.0 —
Note 1: Assumption: Oscillator Postscaler is divide by 1.
2: Instruction Execution Cycle Time: TCY = 1/MIPS.
3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction
cycle].

DS70139F-page 160 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 20-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
Characteristic Min Typ Max Units Conditions
No.
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
OS63 FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V
— — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V
Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to
compensate for temperature drift.

TABLE 20-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Characteristic Min Typ Max Units Conditions
No.

LPRC @ Freq. = 512 kHz(1)

OS65A -50 — +50 % VDD = 5.0V, ±10%
OS65B -60 — +60 % VDD = 3.3V, ±10%
OS65C -70 — +70 % VDD = 2.5V
Note 1: Change of LPRC frequency as VDD changes.

© 2008 Microchip Technology Inc. DS70139F-page 161

dsPIC30F2011/2012/3012/3013
FIGURE 20-5: CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin
(Input)

DI35
DI40

I/O Pin Old Value New Value

(Output)
DO31
DO32

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-20: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions
No.
DO31 TIOR Port output rise time — 7 20 ns
DO32 TIOF Port output fall time — 7 20 ns
DI35 TINP INTx pin high or low time (output) 20 — — ns
DI40 TRBP CNx high or low time (input) 2 TCY — — ns
Note 1: These parameters are asynchronous events not related to any internal clock edges
2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.
3: These parameters are characterized but not tested in manufacturing.
4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70139F-page 162 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS

VDD SY12

MCLR

Internal SY10
POR

SY11
PWRT
Time-out
SY30
OSC
Time-out

Internal
RESET

Watchdog
Timer
RESET
SY20
SY13
SY13

I/O Pins

SY35
FSCM
Delay Note: Refer to Figure 20-3 for load conditions.

TABLE 20-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C
SY11 TPWRT Power-up Timer Period 2 4 8 ms -40°C to +85°C, VDD =
10 16 32 5V
43 64 128 User programmable
SY12 TPOR Power On Reset Delay 3 10 30 μs -40°C to +85°C
SY13 TIOZ I/O high impedance from MCLR — 0.8 1.0 μs
Low or Watchdog Timer Reset
SY20 TWDT1 Watchdog Timer Time-out Period 1.1 2.0 6.6 ms VDD = 2.5V
TWDT2 (No Prescaler) 1.2 2.0 5.0 ms VDD = 3.3V, ±10%
TWDT3 1.3 2.0 4.0 ms VDD = 5V, ±10%
SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μs VDD ≤ VBOR (D034)
SY30 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
3: Refer to Figure 20-2 and Table 20-11 for BOR.

© 2008 Microchip Technology Inc. DS70139F-page 163

dsPIC30F2011/2012/3012/3013
FIGURE 20-7: BAND GAP START-UP TIME CHARACTERISTICS

VBGAP
0V

Enable Band Gap

(see Note)
Band Gap
SY40 Stable

Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.

TABLE 20-22: BAND GAP START-UP TIME REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SY40 TBGAP Band Gap Start-up Time — 40 65 µs Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON<13> bit
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70139F-page 164 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK
Tx10 Tx11

Tx15 Tx20
OS60
TMRX

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TA15
Synchronous, 10 — — ns
with prescaler
Asynchronous 10 — — ns
TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TA15
Synchronous, 10 — — ns
with prescaler
Asynchronous 10 — — ns
TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns
no prescaler
Synchronous, Greater of: — — — N = prescale
with prescaler 20 ns or value
(TCY + 40)/N (1, 8, 64, 256)
Asynchronous 20 — — ns
OS60 Ft1 SOSC1/T1CK oscillator input DC — 50 kHz
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY —
Edge to Timer Increment
Note: Timer1 is a Type A.

© 2008 Microchip Technology Inc. DS70139F-page 165

dsPIC30F2011/2012/3012/3013
TABLE 20-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TB15
Synchronous, 10 — — ns
with prescaler
TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TB15
Synchronous, 10 — — ns
with prescaler
TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY —
Edge to Timer Increment
Note: Timer2 and Timer4 are Type B.
TABLE 20-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 —
Edge to Timer Increment TCY
Note: Timer3 and Timer5 are Type C.

DS70139F-page 166 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICX

IC10 IC11
IC15

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-26: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Max Units Conditions
No.
IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.

© 2008 Microchip Technology Inc. DS70139F-page 167

dsPIC30F2011/2012/3012/3013
FIGURE 20-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx
(Output Compare
or PWM Mode) OC11 OC10

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

DS70139F-page 168 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-11: OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OCFA/OCFB

OC15

OCx

TABLE 20-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OC15 TFD Fault Input to PWM I/O — — 50 ns
Change
OC20 TFLT Fault Input Pulse Width 50 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

© 2008 Microchip Technology Inc. DS70139F-page 169

dsPIC30F2011/2012/3012/3013
FIGURE 20-12: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx
(CKP = 0)

SP11 SP10 SP21 SP20

SCKx
(CKP = 1)

SP35 SP20 SP21

SDOx MSb BIT 14 - - - - - -1 LSb

SP31 SP30

SDIx MSb IN BIT 14 - - - -1 LSb IN

SP40 SP41

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-29: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns —
SP11 TscH SCKX Output High Time(3) TCY/2 — — ns —
SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter
DO32
SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter
DO31
SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter
DO32
SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter
DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns —
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns —
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns —
TscL2diL to SCKX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

DS70139F-page 170 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-13: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)

SP11 SP10 SP21 SP20

SCKX
(CKP = 1)
SP35
SP20 SP21

SDOX MSb BIT 14 - - - - - -1 LSb

SP40 SP30,SP31

SDIX MSb IN BIT 14 - - - -1 LSb IN

SP41 Note: Refer to Figure 20-3 for load conditions.

TABLE 20-30: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP10 TscL SCKX output low time(3) TCY/2 — — ns —
SP11 TscH SCKX output high time(3) TCY/2 — — ns —
SP20 TscF SCKX output fall time(4) — — — ns See parameter
DO32
SP21 TscR SCKX output rise time(4) — — — ns See parameter
DO31
SP30 TdoF SDOX data output fall time(4) — — — ns See parameter
DO32
SP31 TdoR SDOX data output rise time(4) — — — ns See parameter
DO31
SP35 TscH2doV, SDOX data output valid after — — 30 ns —
TscL2doV SCKX edge
SP36 TdoV2sc, SDOX data output setup to 30 — — ns —
TdoV2scL first SCKX edge
SP40 TdiV2scH, Setup time of SDIX data input 20 — — ns —
TdiV2scL to SCKX edge
SP41 TscH2diL, Hold time of SDIX data input 20 — — ns —
TscL2diL to SCKX edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

© 2008 Microchip Technology Inc. DS70139F-page 171

dsPIC30F2011/2012/3012/3013
FIGURE 20-14: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP50 SP52
SCKX
(CKP = 0)

SP71 SP70 SP73 SP72

SCKX
(CKP = 1)

SP72 SP73
SP35

SDOX MSb BIT 14 - - - - - -1 LSb

SP30,SP31 SP51

SDIX MSb IN BIT 14 - - - -1 LSb IN

SP41
SP40
Note: Refer to Figure 20-3 for load conditions.

TABLE 20-31: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP70 TscL SCKX Input Low Time 30 — — ns —
SP71 TscH SCKX Input High Time 30 — — ns —
SP72 TscF SCKX Input Fall Time(3) — 10 25 ns —
SP73 TscR SCKX Input Rise Time(3) — 10 25 ns —
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See DO32
SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns —
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns —
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns —
TscL2diL to SCKX Edge
SP50 TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns —
TssL2scL
SP51 TssH2doZ SSX↑ to SDOX Output 10 — 50 ns —
high impedance(3)
SP52 TscH2ssH SSX after SCK Edge 1.5 TCY — — ns —
TscL2ssH +40
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Assumes 50 pF load on all SPI pins.

DS70139F-page 172 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-15: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSX

SP50 SP52
SCKX
(CKP = 0)

SP71 SP70 SP73 SP72

SCKX
(CKP = 1)
SP35
SP72 SP73
SP52

SDOX MSb BIT 14 - - - - - -1 LSb

SP30,SP31 SP51

SDIX
MSb IN BIT 14 - - - -1 LSb IN
SP41
SP40

Note: Refer to Figure 20-3 for load conditions.

© 2008 Microchip Technology Inc. DS70139F-page 173

dsPIC30F2011/2012/3012/3013
TABLE 20-32: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP70 TscL SCKX Input Low Time 30 — — ns —
SP71 TscH SCKX Input High Time 30 — — ns —
SP72 TscF SCKX Input Fall Time(3) — 10 25 ns —
(3)
SP73 TscR SCKX Input Rise Time — 10 25 ns —
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter
DO32
SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter
DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns —
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns —
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns —
TscL2diL to SCKX Edge
SP50 TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns —
TssL2scL
SP51 TssH2doZ SS↑ to SDOX Output 10 — 50 ns —
high impedance(4)
SP52 TscH2ssH SSX↑ after SCKX Edge 1.5 TCY + 40 — — ns —
TscL2ssH
SP60 TssL2doV SDOX Data Output Valid after — — 50 ns —
SCKX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

DS70139F-page 174 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-16: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCL
IM31 IM34
IM30 IM33

SDA

Start Stop
Condition Condition

Note: Refer to Figure 20-3 for load conditions.

FIGURE 20-17: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20 IM11 IM21

IM10
SCL
IM11 IM26
IM10 IM25 IM33
SDA
In
IM40 IM40 IM45

SDA
Out

Note: Refer to Figure 20-3 for load conditions.

© 2008 Microchip Technology Inc. DS70139F-page 175

dsPIC30F2011/2012/3012/3013
TABLE 20-33: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
I

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min(1) Max Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs
400 kHz mode TCY/2 (BRG + 1) — μs
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs
400 kHz mode TCY/2 (BRG + 1) — μs
(2)
1 MHz mode TCY/2 (BRG + 1) — μs
IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 100 ns
IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 300 ns
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(2) — — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode(2) — — ns
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for
Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start
condition
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the
Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is
generated
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs
Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2) TCY/2 (BRG + 1) — ns
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
From Clock 400 kHz mode — 1000 ns
1 MHz mode(2) — — ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be
400 kHz mode 1.3 — μs free before a new
transmission can start
1 MHz mode(2) — — μs
IM50 CB Bus Capacitive Loading — 400 pF
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)”
in the dsPIC30F Family Reference Manual (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

DS70139F-page 176 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCL
IS31 IS34
IS30 IS33

SDA

Start Stop
Condition Condition

FIGURE 20-19: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20 IS11 IS21

IS10
SCL
IS30 IS26
IS31 IS25 IS33
SDA
In
IS40 IS40 IS45

SDA
Out

TABLE 20-34: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Max Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — μs Device must operate at a
minimum of 10 MHz.
1 MHz mode(1) 0.5 — μs
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — μs Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — μs
IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

© 2008 Microchip Technology Inc. DS70139F-page 177

dsPIC30F2011/2012/3012/3013
TABLE 20-34: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Max Units Conditions
No.
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode(1) 0 0.3 μs
IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated
Setup Time 400 kHz mode 0.6 — μs Start condition
1 MHz mode(1) 0.25 — μs
IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period the first
Hold Time 400 kHz mode 0.6 — μs clock pulse is generated
1 MHz mode(1) 0.25 — μs
IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs
Setup Time 400 kHz mode 0.6 — μs
1 MHz mode(1) 0.6 — μs
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 — ns
1 MHz mode(1) 250 ns
IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns
From Clock 400 kHz mode 0 1000 ns
1 MHz mode(1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free
400 kHz mode 1.3 — μs before a new transmission
can start
1 MHz mode(1) 0.5 — μs
IS50 CB Bus Capacitive — 400 pF
Loading
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

DS70139F-page 178 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
FIGURE 20-20: CAN MODULE I/O TIMING CHARACTERISTICS

CXTX Pin Old Value New Value

(output)

CA10 CA11
CXRX Pin
(input)
CA20

TABLE 20-35: CAN MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
CA10 TioF Port Output Fall Time — 10 25 ns
CA11 TioR Port Output Rise Time — 10 25 ns
CA20 Tcwf Pulse Width to Trigger 500 — — ns
CAN Wake-up Filter
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

© 2008 Microchip Technology Inc. DS70139F-page 179

dsPIC30F2011/2012/3012/3013
TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD - 0.3 VDD + 0.3
or 2.7 or 5.5
AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.7 — AVDD V
AD06 VREFL Reference Voltage Low AVSS — AVDD - 2.7 V
AD07 VREF Absolute Reference AVSS - 0.3 — AVDD + 0.3 V
Voltage
AD08 IREF Current Drain — 200 300 μA A/D operating
.001 2 μA A/D off
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V See Note 1
AD11 VIN Absolute Input Voltage AVSS - 0.3 — AVDD + 0.3 V —
AD12 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
Source Impedance =
2.5 kΩ
AD13 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
Source Impedance =
2.5 kΩ
AD15 RSS Switch Resistance — 3.2K — Ω
AD16 CSAMPLE Sample Capacitor — 18 pF
AD17 RIN Recommended Impedance — — 2.5K Ω
of Analog Voltage Source
DC Accuracy(2)
AD20 Nr Resolution 12 data bits bits
AD21 INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD21A INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
AD22 DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD22A DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
AD23 GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD23A GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.

DS70139F-page 180 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
AD24 EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD24A EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
AD25 — Monotonicity(1) — — — — Guaranteed
Dynamic Performance
AD30 THD Total Harmonic Distortion — -71 — dB
AD31 SINAD Signal to Noise and — 68 — dB
Distortion
AD32 SFDR Spurious Free Dynamic — 83 — dB
Range
AD33 FNYQ Input Signal Bandwidth — — 100 kHz
AD34 ENOB Effective Number of Bits 10.95 11.1 — bits
Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.

© 2008 Microchip Technology Inc. DS70139F-page 181

dsPIC30F2011/2012/3012/3013
FIGURE 20-21: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS
(ASAM = 0, SSRC = 000)

AD50

ADCLK
Instruction
Execution Set SAMP Clear SAMP

SAMP

ch0_dischrg

ch0_samp

eoc

AD61
AD60

TSAMP AD55

DONE

ADIF

ADRES(0)

1 2 3 4 5 6 7 8 9

1 - Software sets ADCON. SAMP to start sampling.

2 - Sampling starts after discharge period.
TSAMP is described in Section 18. “12-bit A/D Converter” in the dsPIC30F Family Reference Manual (DS70046).
3 - Software clears ADCON. SAMP to Start conversion.
4 - Sampling ends, conversion sequence starts.
5 - Convert bit 11.
6 - Convert bit 10.
7 - Convert bit 1.
8 - Convert bit 0.
9 - One TAD for end of conversion.

DS70139F-page 182 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
TABLE 20-37: 12-BIT A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Clock Parameters
AD50 TAD A/D Clock Period 334 — — ns VDD = 3-5.5V (Note 1)
AD51 tRC A/D Internal RC Oscillator Period 1.2 1.5 1.8 μs
Conversion Rate
AD55 tCONV Conversion Time — 14 TAD ns
AD56 FCNV Throughput Rate — 200 — ksps VDD = VREF = 5V
AD57 TSAMP Sampling Time 1 TAD — — ns VDD = 3-5.5V source
resistance
RS = 0-2.5 kΩ
Timing Parameters
AD60 tPCS Conversion Start from Sample — 1 TAD — ns
Trigger
AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 ns
Sample (SAMP) Bit TAD
AD62 tCSS Conversion Completion to — 0.5 TAD — ns
Sample Start (ASAM = 1)
AD63 tDPU(2) Time to Stabilize Analog Stage — — 20 μs
from A/D Off to A/D On
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1).
During this time the ADC result is indeterminate.

© 2008 Microchip Technology Inc. DS70139F-page 183

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 184 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
21.0 PACKAGING INFORMATION

21.1 Package Marking Information

18-Lead PDIP Example

XXXXXXXXXXXXXXXXX dsPIC30F3012
XXXXXXXXXXXXXXXXX 30I/P e3
YYWWNNN 0610017

18-Lead SOIC Example

XXXXXXXXXXXX dsPIC30F2011
XXXXXXXXXXXX 30I/SO e3
XXXXXXXXXXXX
YYWWNNN 0610017

28-Lead SPDIP Example

XXXXXXXXXXXXXXXXX dsPIC30F2012
XXXXXXXXXXXXXXXXX 30I/SP e3
YYWWNNN 0610017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2008 Microchip Technology Inc. DS70139F-page 185

dsPIC30F2011/2012/3012/3013
21.2 Package Marking Information (Continued)

28-Lead SOIC (.300”) Example

XXXXXXXXXXXXXXXXXXXX dsPIC30F3013
XXXXXXXXXXXXXXXXXXXX 30I/SO e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 0610017

28-Lead QFN Example

XXXXXXX 30F2011
XXXXXXX 30I/MM e3

YYWWNNN 0610017

44-Lead QFN Example

XXXXXXXXXX dsPIC
XXXXXXXXXX 30F3013
XXXXXXXXXX 30I/ML e3
YYWWNNN 0610017

DS70139F-page 186 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013

             

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&& 255***'    '5 4


NOTE 1
E1

1 2 3
D

A A2

L c
A1
b1

b e eB

6&! 7,8.
'! 9'&! 7 7: ;
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&  1,
& &  = = 
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        * ,1

© 2008 Microchip Technology Inc. DS70139F-page 187

dsPIC30F2011/2012/3012/3013

   ! "  !"  #$ %&'   !"(

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E1

NOTE 1

1 2 3
e
b
α
h
h

c
φ
A A2

β
A1 L
L1

6&! 99. .

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3 &9& 9  = 
3 & & 9 .3
3 & I B = <B
9# 4!!   = --
9#>#& ) - = 
 # %& D B = B
 # %&1 && ' E B B=
 
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        * ,1

DS70139F-page 188 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013

) !*     !      !  

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&& 255***'    '5 4

N
NOTE 1
E1

1 2 3

A A2

L c

A1 b1
b e eB

6&! 7,8.
'! 9'&! 7 7: ;
7"')  %! 7 <
&  1,
& &  = = 
 ##4 4!!   - 
1!& &   = =
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:  9&  - -? 
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9 * 9#>#& )  < 
:   * + 1 = = -
 
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        * ,1

© 2008 Microchip Technology Inc. DS70139F-page 189

dsPIC30F2011/2012/3012/3013

)   ! "  !"  #$ %&'   !"(

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&& 255***'    '5 4

D
N

E
E1

NOTE 1

1 2 3
e
b

h
α
h

φ c
A A2

L
A1 L1 β

6&! 99. .

'! 9'&! 7 7: ;
7"')  %! 7 <
&  1,
:  8 &  = = ?
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:  >#& . -1,
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:  9&  1,
, '% @ & A  = 
3 &9& 9  = 
3 & & 9 .3
3 & I B = <B
9# 4!!  < = --
9#>#& ) - = 
 # %& D B = B
 # %&1 && ' E B = B
 
  !"#$%&" '  ()"&'"!&) &#*& &  & # 
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2 3 &4  (  - 3
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DS70139F-page 190 © 2008 Microchip Technology Inc.

D D2
EXPOSED
PAD
 dsPIC30F2011/2012/3012/3013

)   + ,  $   *- ..  /0/0&1   +,!

2 3 &4  (  - 3
  3 & ' !&" & 4# *!( !!&    4 %&  &#&
&& 255***'    '5 4

© 2008 Microchip Technology Inc. DS70139F-page 191

dsPIC30F2011/2012/3012/3013

44   + ,  $   *- .  0   +,

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D D2
EXPOSED
PAD

E2
b

2 2
1 1
N N K
NOTE 1 L

TOP VIEW BOTTOM VIEW

A3 A1

6&! 99. .

'! 9'&! 7 7: ;
7"')  %! 7 
&  ?1,
:  8 &  <  
&# %%    
, && 4!! - .3
:  >#& . <1,
.$ !##>#& . ?- ? ?<
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, &&>#& )  - -<
, &&9& 9 -  
, &&& .$ !## C  = =
 
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DS70139F-page 192 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013

44   + ,  $   *- .  0   +,

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&& 255***'    '5 4

© 2008 Microchip Technology Inc. DS70139F-page 193

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 194 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
APPENDIX A: REVISION HISTORY Revision F (May 2008)
This revision reflects these updates:
Revision D (August 2006)
• Added FUSE Configuration Register (FICD)
Previous versions of this data sheet contained details (see Section 17.7 “Device Configuration
Advance or Preliminary Information. They were Registers” and Table 17-8)
distributed with incomplete characterization data. • Added Note 2 to Device Configuration Registers
This revision reflects these updates: table (Table 17-8)
• Supported I2C Slave Addresses • Updated Bit 10 in the UART2 Register Map (see
(see Table 14-1) Table 15-2). This bit is unimplemented.
• ADC Conversion Clock selection to allow • Electrical Specifications:
200 kHz sampling rate (see Section 16.0 “12-bit - Resolved TBD values for parameters DO10,
Analog-to-Digital Converter (ADC) Module”) DO16, DO20, and DO26 (see Table 20-9)
• Operating Current (IDD) Specifications - 10-bit High-Speed ADC tPDU timing
(see Table 20-5) parameter (time to stabilize) has been
• Idle Current (IIDLE) Specifications updated from 20 µs typical to 20 µs maximum
(see Table 20-6) (see Table 20-37)
• Power-Down Current (IPD) Specifications - Parameter OS65 (Internal RC Accuracy) has
(see Table 20-7) been expanded to reflect multiple Min and
Max values for different temperatures (see
• I/O pin Input Specifications
Table 20-19)
(see Table 20-8)
- Parameter DC12 (RAM Data Retention
• BOR voltage limits
Voltage) has been updated to include a Min
(see Table 20-11)
value (see Table 20-4)
• Watchdog Timer time-out limits
- Parameter D134 (Erase/Write Cycle Time)
(see Table 20-21)
has been updated to include Min and Max
values and the Typ value has been removed
Revision E (December 2006) (see Table 20-12)
This revision includes updates to the packaging - Removed parameters OS62 (Internal FRC
diagrams. Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 20-18)
- Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 20-18)
- Updated Min and Max values and Conditions
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for
parameter SY20 (see Table 20-21)
• Additional minor corrections throughout the
document

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NOTES:

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 dsPIC30F2011/2012/3012/3013
INDEX I2C .............................................................................. 96
Input Capture Mode.................................................... 83
Numerics Oscillator System...................................................... 123
12-bit Analog-to-Digital Converter (A/D) Module .............. 111 Output Compare Mode ............................................... 87
Reset System ........................................................... 127
A Shared Port Structure................................................. 59
A/D .................................................................................... 111 SPI.............................................................................. 91
Aborting a Conversion .............................................. 113 SPI Master/Slave Connection..................................... 92
ADCHS Register ....................................................... 111 UART Receiver......................................................... 104
ADCON1 Register..................................................... 111 UART Transmitter..................................................... 103
ADCON2 Register..................................................... 111 BOR Characteristics ......................................................... 155
ADCON3 Register..................................................... 111 BOR. See Brown-out Reset.
ADCSSL Register ..................................................... 111 Brown-out Reset
ADPCFG Register..................................................... 111 Characteristics.......................................................... 155
Configuring Analog Port Pins.............................. 60, 117 Timing Requirements ............................................... 163
Connection Considerations....................................... 117 C
Conversion Operation ............................................... 112
C Compilers
Effects of a Reset...................................................... 116
MPLAB C18.............................................................. 144
Operation During CPU Idle Mode ............................. 116
Operation During CPU Sleep Mode.......................... 116 MPLAB C30.............................................................. 144
CAN Module
Output Formats ......................................................... 116
I/O Timing Characteristics ........................................ 179
Power-Down Modes.................................................. 116
Programming the Sample Trigger............................. 113 I/O Timing Requirements.......................................... 179
CLKOUT and I/O Timing
Register Map............................................................. 119
Characteristics.......................................................... 162
Result Buffer ............................................................. 112
Sampling Requirements............................................ 115 Requirements ........................................................... 162
Selecting the Conversion Sequence......................... 112 Code Examples
Data EEPROM Block Erase ....................................... 56
AC Characteristics ............................................................ 157
Data EEPROM Block Write ........................................ 58
Load Conditions ........................................................ 157
AC Temperature and Voltage Specifications .................... 157 Data EEPROM Read.................................................. 55
Data EEPROM Word Erase ....................................... 56
ADC
Data EEPROM Word Write ........................................ 57
Selecting the Conversion Clock ................................ 113
ADC Conversion Speeds .................................................. 114 Erasing a Row of Program Memory ........................... 51
Initiating a Programming Sequence ........................... 52
Address Generator Units .................................................... 43
Loading Write Latches................................................ 52
Alternate Vector Table ........................................................ 69
Analog-to-Digital Converter. See ADC. Code Protection ................................................................ 121
Control Registers ................................................................ 50
Assembler
NVMADR .................................................................... 50
MPASM Assembler................................................... 144
Automatic Clock Stretch...................................................... 98 NVMADRU ................................................................. 50
NVMCON.................................................................... 50
During 10-bit Addressing (STREN = 1)....................... 98
NVMKEY .................................................................... 50
During 7-bit Addressing (STREN = 1)......................... 98
Receive Mode ............................................................. 98 Core Architecture
Overview..................................................................... 19
Transmit Mode ............................................................ 98
CPU Architecture Overview ................................................ 19
B Customer Change Notification Service............................. 200
Bandgap Start-up Time Customer Notification Service .......................................... 200
Requirements............................................................ 164 Customer Support............................................................. 200
Timing Characteristics .............................................. 164 D
Barrel Shifter ....................................................................... 27
Data Accumulators and Adder/Subtractor .......................... 25
Bit-Reversed Addressing .................................................... 46
Data Space Write Saturation ...................................... 27
Example ...................................................................... 47
Implementation ........................................................... 46 Overflow and Saturation ............................................. 25
Round Logic ............................................................... 26
Modifier Values Table ................................................. 47
Write-Back .................................................................. 26
Sequence Table (16-Entry)......................................... 47
Block Diagrams Data Address Space........................................................... 35
Alignment.................................................................... 38
12-bit ADC Functional............................................... 111
Alignment (Figure) ...................................................... 38
16-bit Timer1 Module .................................................. 73
16-bit Timer2............................................................... 79 Effect of Invalid Memory Accesses (Table) ................ 38
MCU and DSP (MAC Class) Instructions Example .... 37
16-bit Timer3............................................................... 79
Memory Map......................................................... 35, 36
32-bit Timer2/3............................................................ 78
DSP Engine ................................................................ 24 Near Data Space ........................................................ 39
Software Stack ........................................................... 39
dsPIC30F2011 ............................................................ 12
Spaces........................................................................ 38
dsPIC30F2012 ............................................................ 13
dsPIC30F3013 ............................................................ 15 Width .......................................................................... 38
Data EEPROM Memory...................................................... 55
External Power-on Reset Circuit............................... 129
Erasing ....................................................................... 56

© 2008 Microchip Technology Inc. DS70139F-page 197

dsPIC30F2011/2012/3012/3013
Erasing, Block ............................................................. 56 I
Erasing, Word ............................................................. 56
I/O Pin Specifications
Protection Against Spurious Write .............................. 58
Input.......................................................................... 153
Reading....................................................................... 55 Output ....................................................................... 153
Write Verify ................................................................. 58
I/O Ports.............................................................................. 59
Writing ......................................................................... 57
Parallel (PIO) .............................................................. 59
Writing, Block .............................................................. 57 I2C 10-bit Slave Mode Operation........................................ 97
Writing, Word .............................................................. 57
Reception ................................................................... 98
DC Characteristics ............................................................ 147
Transmission .............................................................. 98
BOR .......................................................................... 155 I2C 7-bit Slave Mode Operation.......................................... 97
Brown-out Reset ....................................................... 155
Reception ................................................................... 97
I/O Pin Input Specifications ....................................... 153
Transmission .............................................................. 97
I/O Pin Output Specifications .................................... 153 I2C Master Mode Operation................................................ 99
Idle Current (IIDLE) .................................................... 150
Baud Rate Generator ............................................... 100
Low-Voltage Detect................................................... 154
Clock Arbitration ....................................................... 100
LVDL ......................................................................... 154 Multi-Master Communication, Bus Collision and
Operating Current (IDD)............................................. 149
Bus Arbitration .................................................. 100
Power-Down Current (IPD) ........................................ 151
Reception ................................................................. 100
Program and EEPROM............................................. 156 Transmission .............................................................. 99
Temperature and Voltage Specifications .................. 147
I2C Master Mode Support ................................................... 99
Development Support ....................................................... 143
I2C Module
Device Configuration Addresses................................................................... 97
Register Map............................................................. 134
Bus Data Timing Characteristics
Device Configuration Registers
Master Mode..................................................... 175
FBORPOR ................................................................ 132 Slave Mode....................................................... 177
FGS........................................................................... 132
Bus Data Timing Requirements
FOSC ........................................................................ 132
Master Mode..................................................... 176
FWDT........................................................................ 132
Slave Mode....................................................... 177
Device Overview ........................................................... 11, 19 Bus Start/Stop Bits Timing Characteristics
Disabling the UART........................................................... 105
Master Mode..................................................... 175
Divide Support..................................................................... 22
Slave Mode....................................................... 177
Instructions (Table) ..................................................... 22 General Call Address Support .................................... 99
DSP Engine......................................................................... 23
Interrupts .................................................................... 99
Multiplier...................................................................... 25
IPMI Support............................................................... 99
Dual Output Compare Match Mode .................................... 88 Operating Function Description .................................. 95
Continuous Pulse Mode .............................................. 88
Operation During CPU Sleep and Idle Modes .......... 100
Single Pulse Mode ...................................................... 88
Pin Configuration ........................................................ 95
E Programmer’s Model .................................................. 95
Register Map ............................................................ 101
Electrical Characteristics
Registers .................................................................... 95
AC ............................................................................. 157
Slope Control .............................................................. 99
DC ............................................................................. 147
Software Controlled Clock Stretching (STREN = 1) ... 98
Enabling and Setting Up UART
Various Modes............................................................ 95
Alternate I/O .............................................................. 105
Idle Current (IIDLE) ............................................................ 150
Setting Up Data, Parity and Stop Bit Selections ....... 105
In-Circuit Serial Programming (ICSP)......................... 49, 121
Enabling the UART ........................................................... 105
Input Capture (CAPX) Timing Characteristics .................. 167
Equations
Input Capture Module ......................................................... 83
ADC Conversion Clock ............................................. 113
Interrupts .................................................................... 84
Baud Rate ................................................................. 107
Register Map .............................................................. 85
Serial Clock Rate ...................................................... 100
Input Capture Operation During Sleep and Idle Modes...... 84
Errata .................................................................................. 10
CPU Idle Mode ........................................................... 84
Exception Sequence
CPU Sleep Mode ........................................................ 84
Trap Sources .............................................................. 67
Input Capture Timing Requirements................................. 167
External Clock Timing Characteristics
Input Change Notification Module....................................... 63
Type A, B and C Timer ............................................. 165
dsPIC30F2012/3013 Register Map (Bits 7-0)............. 63
External Clock Timing Requirements................................ 158
Instruction Addressing Modes ............................................ 43
Type A Timer ............................................................ 165
File Register Instructions ............................................ 43
Type B Timer ............................................................ 166
Fundamental Modes Supported ................................. 43
Type C Timer ............................................................ 166
MAC Instructions ........................................................ 44
External Interrupt Requests ................................................ 70
MCU Instructions ........................................................ 43
F Move and Accumulator Instructions............................ 44
Other Instructions ....................................................... 44
Fast Context Saving............................................................ 70
Instruction Set
Flash Program Memory....................................................... 49
Overview................................................................... 138
Summary .................................................................. 135

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 dsPIC30F2011/2012/3012/3013
Internal Clock Timing Examples ....................................... 160 P
Internet Address................................................................ 200
Packaging Information ...................................................... 185
Interrupt Controller
Marking............................................................. 185, 186
Register Map......................................................... 71, 72 Peripheral Module Disable (PMD) Registers .................... 133
Interrupt Priority .................................................................. 66
PICSTART Plus Development Programmer..................... 146
Traps........................................................................... 67
Pinout Descriptions............................................................. 16
Interrupt Sequence ............................................................. 69 PLL Clock Timing Specifications ...................................... 159
Interrupt Stack Frame ................................................. 69
POR. See Power-on Reset.
Interrupts ............................................................................. 65
Port Write/Read Example ................................................... 60
L PORTB
Register Map for dsPIC30F2011/3012 ....................... 61
Load Conditions ................................................................ 157
Register Map for dsPIC30F2012/3013 ....................... 61
Low Voltage Detect (LVD) ................................................ 131
PORTC
Low-Voltage Detect Characteristics .................................. 154
Register Map for dsPIC30F2011/2012/3012/3013 ..... 61
LVDL Characteristics ........................................................ 154
PORTD
M Register Map for dsPIC30F2011/3012 ....................... 61
Register Map for dsPIC30F2012/3013 ....................... 62
Memory Organization.......................................................... 29
Core Register Map...................................................... 39 PORTF
Register Map for dsPIC30F2012/3013 ....................... 62
Microchip Internet Web Site .............................................. 200
Power Saving Modes........................................................ 131
Modulo Addressing ............................................................. 44
Applicability ................................................................. 46 Idle............................................................................ 132
Sleep ........................................................................ 131
Incrementing Buffer Operation Example..................... 45
Sleep and Idle........................................................... 121
Start and End Address................................................ 45
W Address Register Selection .................................... 45 Power-Down Current (IPD)................................................ 151
Power-up Timer
MPLAB ASM30 Assembler, Linker, Librarian ................... 144
Timing Characteristics .............................................. 163
MPLAB ICD 2 In-Circuit Debugger ................................... 145
Timing Requirements ............................................... 163
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 145 Program Address Space..................................................... 29
Construction ............................................................... 31
MPLAB Integrated Development Environment Software .. 143
Data Access from Program Memory
MPLAB PM3 Device Programmer .................................... 145
MPLAB REAL ICE In-Circuit Emulator System................. 145 Using Program Space Visibility .......................... 33
Data Access From Program Memory
MPLINK Object Linker/MPLIB Object Librarian ................ 144
Using Table Instructions ..................................... 32
N Data Access from, Address Generation ..................... 31
NVM Data Space Window into Operation ........................... 34
Register Map............................................................... 53 Data Table Access (LS Word) .................................... 32
Data Table Access (MS Byte) .................................... 33
O Memory Map............................................................... 30
OC/PWM Module Timing Characteristics.......................... 169 Table Instructions
Operating Current (IDD)..................................................... 149 TBLRDH ............................................................. 32
Operating Frequency vs Voltage TBLRDL.............................................................. 32
dsPIC30FXXXX-20 (Extended)................................. 147 TBLWTH............................................................. 32
Oscillator TBLWTL ............................................................. 32
Configurations........................................................... 124 Program and EEPROM Characteristics............................ 156
Fail-Safe Clock Monitor .................................... 126 Program Counter ................................................................ 20
Fast RC (FRC) .................................................. 125 Programmable .................................................................. 121
Initial Clock Source Selection ........................... 124 Programmer’s Model .......................................................... 20
Low-Power RC (LPRC)..................................... 125 Diagram ...................................................................... 21
LP Oscillator Control ......................................... 125 Programming Operations.................................................... 51
Phase Locked Loop (PLL) ................................ 125 Algorithm for Program Flash....................................... 51
Start-up Timer (OST) ........................................ 124 Erasing a Row of Program Memory ........................... 51
Operating Modes (Table) .......................................... 122 Initiating the Programming Sequence ........................ 52
System Overview ...................................................... 121 Loading Write Latches................................................ 52
Oscillator Selection ........................................................... 121 Protection Against Accidental Writes to OSCCON ........... 126
Oscillator Start-up Timer
R
Timing Characteristics .............................................. 163
Timing Requirements................................................ 163 Reader Response............................................................. 201
Output Compare Interrupts ................................................. 89 Reset ........................................................................ 121, 127
Output Compare Module..................................................... 87 BOR, Programmable ................................................ 129
Register Map............................................................... 90 Brown-out Reset (BOR)............................................ 121
Timing Characteristics .............................................. 168 Oscillator Start-up Timer (OST)................................ 121
Timing Requirements................................................ 168 POR
Output Compare Operation During CPU Idle Mode............ 89 Operating without FSCM and PWRT................ 129
Output Compare Sleep Mode Operation ............................ 89 With Long Crystal Start-up Time ...................... 129
POR (Power-on Reset)............................................. 127

© 2008 Microchip Technology Inc. DS70139F-page 199

dsPIC30F2011/2012/3012/3013
Power-on Reset (POR) ............................................. 121 Interrupt ...................................................................... 74
Power-up Timer (PWRT) .......................................... 121 Operation During Sleep Mode .................................... 74
Reset Sequence.................................................................. 67 Prescaler .................................................................... 74
Reset Sources ............................................................ 67 Real-Time Clock ......................................................... 74
Reset Sources Interrupts ............................................................ 75
Brown-out Reset (BOR) .............................................. 67 Oscillator Operation............................................ 75
Illegal Instruction Trap................................................. 67 Register Map .............................................................. 76
Trap Lockout ............................................................... 67 Timer2 and Timer3 Selection Mode.................................... 88
Uninitialized W Register Trap ..................................... 67 Timer2/3 Module
Watchdog Time-out..................................................... 67 16-bit Timer Mode....................................................... 77
Reset Timing Characteristics ............................................ 163 32-bit Synchronous Counter Mode ............................. 77
Reset Timing Requirements.............................................. 163 32-bit Timer Mode....................................................... 77
Run-Time Self-Programming (RTSP) ................................. 49 ADC Event Trigger...................................................... 80
Gate Operation ........................................................... 80
S Interrupt ...................................................................... 80
Simple Capture Event Mode ............................................... 83 Operation During Sleep Mode .................................... 80
Buffer Operation.......................................................... 84 Register Map .............................................................. 81
Hall Sensor Mode ....................................................... 84 Timer Prescaler .......................................................... 80
Prescaler ..................................................................... 83 Timing Characteristics
Timer2 and Timer3 Selection Mode ............................ 84 A/D Conversion
Simple OC/PWM Mode Timing Requirements.................. 169 Low-speed (ASAM = 0, SSRC = 000) .............. 182
Simple Output Compare Match Mode................................. 88 Bandgap Start-up Time............................................. 164
Simple PWM Mode ............................................................. 88 CAN Module I/O........................................................ 179
Input Pin Fault Protection............................................ 88 CLKOUT and I/O ...................................................... 162
Period.......................................................................... 89 External Clock........................................................... 157
Software Simulator (MPLAB SIM)..................................... 144 I2C Bus Data
Software Stack Pointer, Frame Pointer............................... 20 Master Mode..................................................... 175
CALL Stack Frame...................................................... 39 Slave Mode....................................................... 177
SPI Module.......................................................................... 91 I2C Bus Start/Stop Bits
Framed SPI Support ................................................... 92 Master Mode..................................................... 175
Operating Function Description .................................. 91 Slave Mode....................................................... 177
Operation During CPU Idle Mode ............................... 93 Input Capture (CAPX)............................................... 167
Operation During CPU Sleep Mode ............................ 93 OC/PWM Module...................................................... 169
SDOx Disable ............................................................. 92 Oscillator Start-up Timer........................................... 163
Slave Select Synchronization ..................................... 93 Output Compare Module .......................................... 168
SPI1 Register Map ...................................................... 94 Power-up Timer ........................................................ 163
Timing Characteristics Reset ........................................................................ 163
Master Mode (CKE = 0) .................................... 170 SPI Module
Master Mode (CKE = 1) .................................... 171 Master Mode (CKE = 0).................................... 170
Slave Mode (CKE = 1) .............................. 172, 173 Master Mode (CKE = 1).................................... 171
Timing Requirements Slave Mode (CKE = 0)...................................... 172
Master Mode (CKE = 0) .................................... 170 Slave Mode (CKE = 1)...................................... 173
Master Mode (CKE = 1) .................................... 171 Type A, B and C Timer External Clock ..................... 165
Slave Mode (CKE = 0) ...................................... 172 Watchdog Timer ....................................................... 163
Slave Mode (CKE = 1) ...................................... 174 Timing Diagrams
Word and Byte Communication .................................. 92 PWM Output Timing ................................................... 89
Status Bits, Their Significance and the Initialization Time-out Sequence on Power-up
Condition for RCON Register, Case 1 ...................... 130 (MCLR Not Tied to VDD), Case 1 ..................... 128
Status Bits, Their Significance and the Initialization Time-out Sequence on Power-up
Condition for RCON Register, Case 2 ...................... 130 (MCLR Not Tied to VDD), Case 2 ..................... 128
Status Register.................................................................... 20 Time-out Sequence on Power-up
Symbols Used in Opcode Descriptions............................. 136 (MCLR Tied to VDD) ......................................... 128
System Integration Timing Diagrams and Specifications
Register Map............................................................. 134 DC Characteristics - Internal RC Accuracy............... 160
Timing Diagrams.See Timing Characteristics
T Timing Requirements
Table Instruction Operation Summary ................................ 49 A/D Conversion
Temperature and Voltage Specifications Low-speed ........................................................ 183
AC ............................................................................. 157 Bandgap Start-up Time............................................. 164
DC ............................................................................. 147 Brown-out Reset ....................................................... 163
Timer 2/3 Module ................................................................ 77 CAN Module I/O........................................................ 179
Timer1 Module .................................................................... 73 CLKOUT and I/O ...................................................... 162
16-bit Asynchronous Counter Mode ........................... 73 External Clock........................................................... 158
16-bit Synchronous Counter Mode ............................. 73 I2C Bus Data (Master Mode) .................................... 176
16-bit Timer Mode ....................................................... 73 I2C Bus Data (Slave Mode) ...................................... 177
Gate Operation ........................................................... 74

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 dsPIC30F2011/2012/3012/3013
Input Capture ............................................................ 167
Oscillator Start-up Timer ........................................... 163
Output Compare Module........................................... 168
Power-up Timer ........................................................ 163
Reset......................................................................... 163
Simple OC/PWM Mode............................................. 169
SPI Module
Master Mode (CKE = 0) .................................... 170
Master Mode (CKE = 1) .................................... 171
Slave Mode (CKE = 0) ...................................... 172
Slave Mode (CKE = 1) ...................................... 174
Type A Timer External Clock .................................... 165
Type B Timer External Clock .................................... 166
Type C Timer External Clock .................................... 166
Watchdog Timer........................................................ 163
Timing Specifications
PLL Clock.................................................................. 159
Trap Vectors ....................................................................... 69

U
UART Module
Address Detect Mode ............................................... 107
Auto-Baud Support ................................................... 108
Baud Rate Generator................................................ 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR)............................................... 107
Idle Status ................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview ................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break........................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt....................................................... 106
Receiving Data.......................................................... 106
Receiving in 8-bit or 9-bit Data Mode........................ 106
Reception Error Handling.......................................... 106
Transmit Break.......................................................... 106
Transmit Buffer (UxTXB)........................................... 105
Transmit Interrupt...................................................... 106
Transmitting Data...................................................... 105
Transmitting in 8-bit Data Mode................................ 105
Transmitting in 9-bit Data Mode................................ 105
UART1 Register Map................................................ 109
UART2 Register Map................................................ 109
UART Operation
Idle Mode .................................................................. 108
Sleep Mode............................................................... 108
Unit ID Locations............................................................... 121
Universal Asynchronous Receiver Transmitter (UART) Mod-
ule ............................................................................. 103

W
Wake-up from Sleep ......................................................... 121
Wake-up from Sleep and Idle ............................................. 70
Watchdog Timer
Timing Characteristics .............................................. 163
Timing Requirements................................................ 163
Watchdog Timer (WDT) ............................................ 121, 131
Enabling and Disabling ............................................. 131
Operation .................................................................. 131
WWW Address.................................................................. 200
WWW, On-Line Support ..................................................... 10

© 2008 Microchip Technology Inc. DS70139F-page 201

dsPIC30F2011/2012/3012/3013
NOTES:

DS70139F-page 202 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
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© 2008 Microchip Technology Inc. DS70139F-page 203

dsPIC30F2011/2012/3012/3013
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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Device: dsPIC30F2011/2012/3012/3 Literature Number: DS70139F

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DS70139F-page 204 © 2008 Microchip Technology Inc.

 dsPIC30F2011/2012/3012/3013
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

d s P I C 3 0 F 3 0 1 3 AT- 3 0 I / S P - E S
Custom ID (3 digits) or
Trademark Engineering Sample (ES)

Architecture

Package
P = DIP
Flash
SO = SOIC
SP = SPDIP
Memory Size in Bytes ML = QFN (8x8)
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K Temperature
5 = 49K to 96K I = Industrial -40°C to +85°C
6 = 97K to 192K E = Extended High Temp -40°C to +125°C
7 = 193K to 384K
8 = 385K to 768K
Speed
9 = 769K and Up
20 = 20 MIPS
30 = 30 MIPS
Device ID T = Tape and Reel

A,B,C… = Revision Level

Example:
dsPIC30F3013AT-30I/SP = 30 MIPS, Industrial temp., SPDIP package, Rev. A

© 2008 Microchip Technology Inc. DS70139F-page 205

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01/02/08

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