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CIT-3150-COMPUTER-SYSTEMS-ARCHITECTURE-1

The document outlines the examination details for the course CIT 3150: Computer Systems Architecture at Meru University of Science and Technology for the academic year 2016/2017. It includes instructions for answering questions, a variety of topics covered in the exam such as computer architecture, MIPS pipeline, CPU time, I/O module functions, and Moore's theorem. The exam consists of five questions, with specific sub-questions addressing key concepts in computer systems architecture.

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griffinwambua782
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71 views3 pages

CIT-3150-COMPUTER-SYSTEMS-ARCHITECTURE-1

The document outlines the examination details for the course CIT 3150: Computer Systems Architecture at Meru University of Science and Technology for the academic year 2016/2017. It includes instructions for answering questions, a variety of topics covered in the exam such as computer architecture, MIPS pipeline, CPU time, I/O module functions, and Moore's theorem. The exam consists of five questions, with specific sub-questions addressing key concepts in computer systems architecture.

Uploaded by

griffinwambua782
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY

P.O. Box 972-60200 – Meru-Kenya.


Tel: 020-2069349, 061-2309217. 064-30320 Cell phone: +254 712524293, +254 789151411
Fax: 064-30321
Website: www.must.ac.ke Email: [email protected]

University Examinations 2016/2017

FIRST YEAR, FIRST SEMESTER EXAMINATION FOR THE DEGREE OF BACHELOR


BUSINESS INFORMATION TECHNOLOGY, BACHELOR OF SCIENCE IN COMPUTER
SCIENCE, BACHELOR OF SCIENCE IN COMPUTER SCIENCE AND FORENSICS,
BACHELOR OF SCIENCE IN COMPUTER SCIENCE AND TECHNOLOGY AND BACHELOR
OF SCIENCE IN INFORMATION TECHONOLOGY

CIT 3150: COMPUTER SYSTEMS ARCHITECTURE

DATE: DECEMBER 2016 TIME: 2 HOURS

INSTRUCTIONS: Answer question one and any other two questions

QUESTION ONE (30 MARKS)

a) Differentiate between:
(i) Computer architecture and computer organization. (2 Marks)
(ii) RISC and CISC. (2 Marks)
(iii) DMA data transfer and interrupt driven data transfer. (2 Marks)
b) Draw the logic circuit for each of the Boolean expressions given below. (6 Marks)
(i) A.B + C

(ii)
P  Q . P  R 
c) Explain four structural components of a computer system. (6 Marks)
d) Explain the characteristics of the MIPS Instruction Set Architecture (ISA) that facilitate pipelined
execution. (6 Marks)

Meru University of Science & Technology is ISO 9001:2015 Certified


Foundation of Innovations Page 1
e) Define the terms “spatial locality” and “temporal locality”, and explain how caches are used to
exploit them for a performance benefit. Be specific in the different ways that caches exploit these
two phenomena. (6 Marks)

QUESTION TWO (20 MARKS)

a) The five stages of the simple MIPS pipeline are: instruction fetch, instruction decode and register
read, execute or calculate address, memory access and register write. Explain the purpose of each
of these stages. (10 Marks)
b) Determine the logic expression for the output Y from the truth table shown below. Simplify and
sketch the logic circuit for the simplified expression. (10 Marks)

QUESTION THREE (20 MARKS)

a) The CPU time of a program is defined as the product of the CPI (cycle per instruction) for the
processor on which it runs, the total number of instructions executed (I), and processor clock
period   . Describe the major factors which influence CPI, I and   . (8 Marks)
b) Explain the process of fetch-execute cycle of an instruction and the registers which are involved.
(6 Marks)
c) What is the relationship between instructions and micro-operations? (3 Marks)
d) Briefly explain what is meant by a hard wired implementation of a control unit. (3 Marks)

Meru University of Science & Technology is ISO 9001:2015 Certified


Foundation of Innovations Page 2
QUESTION FOUR (20 MARKS)

a) Explain five functions of the I/O module in computer system. (5 Marks)


b) Explain the process of DMA mode of data transfer. (6 Marks)
c) Describe the number of bits required in each entry of a TLB that has the following characteristics:
(i) Virtual addresses are 32 bit wide
(ii) Physical addresses are 31 bits wide.
(iii) The page size is 2K bytes.
(iv) The TLB contains 16 entries of the page table.
(v) The TLB is direct-mapped. (9 Marks)

QUESTION FIVE (20 MARKS)

a) According to Moore’s theorem the number of transistors in a circuit will double after every 18
months. Discuss the implication of this theorem to computer system architecture. (7 Marks)
b) Explain the hazards presented by instruction level parallelism and for each one indicate how it can
be resolved. (6 Marks)
c) Suppose physical addresses are 32 bits wide. Suppose there is a cache containing 256K words of
data (not including tag bits) and each cache block contains 4 words. For each of the following
cache configurations, a. direct mapped b. 2-way set associative c. 4-way set associative d. fully
associative. Specify how the 32-bit address would be partitioned. (7 Marks)

Meru University of Science & Technology is ISO 9001:2015 Certified


Foundation of Innovations Page 3

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