CIT-3150-COMPUTER-SYSTEMS-ARCHITECTURE-1
CIT-3150-COMPUTER-SYSTEMS-ARCHITECTURE-1
a) Differentiate between:
(i) Computer architecture and computer organization. (2 Marks)
(ii) RISC and CISC. (2 Marks)
(iii) DMA data transfer and interrupt driven data transfer. (2 Marks)
b) Draw the logic circuit for each of the Boolean expressions given below. (6 Marks)
(i) A.B + C
(ii)
P Q . P R
c) Explain four structural components of a computer system. (6 Marks)
d) Explain the characteristics of the MIPS Instruction Set Architecture (ISA) that facilitate pipelined
execution. (6 Marks)
a) The five stages of the simple MIPS pipeline are: instruction fetch, instruction decode and register
read, execute or calculate address, memory access and register write. Explain the purpose of each
of these stages. (10 Marks)
b) Determine the logic expression for the output Y from the truth table shown below. Simplify and
sketch the logic circuit for the simplified expression. (10 Marks)
a) The CPU time of a program is defined as the product of the CPI (cycle per instruction) for the
processor on which it runs, the total number of instructions executed (I), and processor clock
period . Describe the major factors which influence CPI, I and . (8 Marks)
b) Explain the process of fetch-execute cycle of an instruction and the registers which are involved.
(6 Marks)
c) What is the relationship between instructions and micro-operations? (3 Marks)
d) Briefly explain what is meant by a hard wired implementation of a control unit. (3 Marks)
a) According to Moore’s theorem the number of transistors in a circuit will double after every 18
months. Discuss the implication of this theorem to computer system architecture. (7 Marks)
b) Explain the hazards presented by instruction level parallelism and for each one indicate how it can
be resolved. (6 Marks)
c) Suppose physical addresses are 32 bits wide. Suppose there is a cache containing 256K words of
data (not including tag bits) and each cache block contains 4 words. For each of the following
cache configurations, a. direct mapped b. 2-way set associative c. 4-way set associative d. fully
associative. Specify how the 32-bit address would be partitioned. (7 Marks)