Lecture -7

Integrated Circuit Technology-1

Prepared By: Asif Mahfuz
Introduction
• In practice digital circuits are not constructed with individual gates.
• Rather digital circuits are constructed with integrated circuits.
• An integrated circuit (abbreviated as IC) is a small silicon semiconductor, crystal called a
chip, containing all the electronic components for the digital gates.
• The various gates are interconnected inside the chip to form the required circuit.
• This cheap is mounted in a ceramic or plastic container, and connections are welded to
external pins to form the IC.
• As an engineering when working with an IC we must
be aware of the following factors.
• The integration level
• The logic family or technology
• The logic level parameters.
• The performance parameters.
Integration Level
• The integration level of an IC or a semiconductor chip gives us an idea about the number
of gates that are present in the chip.
• Integration Level for Integrated Circuits.
• Small-Scale Integration (SSI) (<12 gates/chip).
• Medium-Scale Integration (MSI) (<100 gates/chip).
• Large-Scale Integration (LSI) (…1K gates/chip).
• Very Large-Scale Integration (VLSI) (…10K gates/chip).
• Ultra Large-Scale Integration (ULSI) (…100K gates/chip).
• Giga Scale Integration (GSI) (…1M gates/chip).
• Examples:
• Pentium III Coppermine( 32-bit, large cache): 21,000,000 gates
• Pentium 4 Willamette (32-bit, large cache): 42,000,000 gates
• Core 2 Duo Conroe (dual-core 64-bit, large caches): 291,000,000 gates
• ARM Cortex-A9 (32-bit, (optional) SIMD, caches):26,000,000 gates
• Atom (32-bit, large cache): 47,000,000
Digital Logic Family
• Digital integrated circuits are classified not only by their complexity or logical operation,
but also by the specific circuit technology to which they belong.
• The circuit technology is referred to as a digital logic family.
• The basic circuits in each technology is a NAND, NOR or an inverter gate.
• The logic families are:
• RTL → Resistor-Transistor Logic
• DTL → Diode- Transistor Logic
• I2L → Integrated injection Logic
• ECL → Emitter Collector Logic
• TTL → Transistor-Transistor Logic
• MOS → Metal Oxide Semiconductor
• CMOS → Complementary MOS
Logic Level Parameters
• Different Logic Families usually operate at different
voltage and current levels.
• Voltage Parameters
• High-Level Output Voltage, VOH(MIN): This is the
minimum output voltage available at the output under
stated loaded condition which corresponds to logic ‘1’.
• Low-Level Output Voltage, VOL(MAX): This is the
maximum output voltage available at the output
under stated loaded condition which corresponds to
logic ‘0’
• High-Level Input Voltage, VIH(MIN): This is the minimum
voltage required at an input to be recognized as a
logic ‘1’.
• Low-Level Input Voltage, VIL(MAX): This is the maximum
voltage at an input which will be recognized as a logic
‘0’.
Performance Parameters
• The performance parameters are also known as the special characteristics of a logic
family.
• The characteristics of IC digital logic families are usually compared by analyzing the
circuit of the basic gate in each family.
• The most important parameters that are evaluated and compared are
• Fan-Out
• Fan-In
• Power Dissipation
• Propagation Delay
• Speed-Power Product
• Noise Margin
Loading
• When the output of a gate is connected to the input
of one or more gates, a load is created on the driver
gate. There is a limit to the number of input that
the output a gate can drive. This is determined by
the fan-out.

TTL loading in LOW state

TTL loading in HIGH and LOW state

TTL loading in HIGH state
Performance Parameters: Fan-Out
• The fan-out of a gate specifies the number of standard loads that can be connected to the
output of the gate without degrading its normal operation.
• A standard load is usually defined as the amount of current needed by an input of another
gate in the same logic family. Sometimes the term loading is used instead of fan-out.
• This term is derived because the output of a gate can supply a limited amount of current,
above which it ceases to operate properly and is said to be overloaded.
• Each input consumes a certain amount of current from the gate output, so that each
additional connection adds to the load of the gate.
• Exceeding the specified maximum load may cause a malfunction because the circuit
cannot supply the power demanded from it.
• Also the propagation delay increases with fan-out.
• The fan-out is the maximum number of inputs that can be connected to the output of a
gate and is expressed by a number.
𝐈𝐎𝐇 𝐈𝐎𝐋
𝐃𝐂 𝐅𝐚𝐧𝐨𝐮𝐭 = 𝐦𝐢𝐧 ,
𝐈𝐈𝐇 𝐈𝐈𝐋
Performance Parameters: Fan-Out
• Calculating the Fan-out of a driving gate with the following parameters:
• IOH = 400μA and IIH = 40μA
• IIH = 16mA and IIL = 2mA
• Solution
400μA 16mA
FO = min , = 8units
40μA 2mA
Performance Parameters: Fan-In
• The fan in defined as the maximum number of inputs that a logic gate can accept.
• If number of input exceeds, the output will be undefined or incorrect.
• It is specified by manufacturer and is provided in the data sheet.
• Delay approximately has a quadratic relation with Fan-In.

Fan In = 2

Fan In = 3
Performance Parameters: Power Dissipation
• A gate draws in current both in HIGH and LOW states.
• Therefore, in both states a gate dissipates power.
• The power dissipation is a parameter expressed in
milliwatts (mW) and represents the amount of power
needed by the gate.
• The number that represents this parameter does not
include the power delivered from another gate; rather, it
represents the power delivered to the gate from the power
supply.
• An IC with four gates will require, from its power supply,
four times the power dissipated in each gate.
• The current associated with HIGH state is named I CCH .
• The current associated with LOW state is named I CCL.
Therefore,
• Power Dissipation in HIGH state, PDH = VCCICCH
• Power Dissipation in LOW state, PDL = VCCICCL
Performance Parameters: Power Dissipation
• When gate is pulsed, its output switches back and forth between HIGH and Low
• The amount of supply current also varies between ICCH and ICCL.
• The average power is dissipated when the duty cycle is 50%, the output is HIGH half the
time and LOW the other half.
• The average power dissipated in a cycle is,
𝐕𝐂𝐂 𝐈𝐂𝐂𝐇 + 𝐈𝐂𝐂𝐋
𝐏𝐃 =
𝟐
• So the power dissipated in a cycle with duty cycle of X%is,
𝐕𝐂𝐂 ( 𝐗 × 𝐈𝐂𝐂𝐇 + 𝟏𝟎𝟎 − 𝐗 𝐈𝐂𝐂𝐋 )
𝐏𝐃 =
𝟏𝟎𝟎
• Find the average power dissipated for a NAND gate with VCC = 5V, ICCH = 4mA and
ICCL = 2mA when the duty cycle is:
a) 40%
b) 75%
c) 20%
Performance Parameters: Propagation Delay
• When a signal passes through a logic circuit, it always
experiences a time delay.
• A change in the output level always occurs after a short
time, called the propagation delay.
• TPHL: Propagation delay for High to Low.
• TPLH: Propagation delay for Low to High.
𝟏
𝐭 𝐏𝐃 = (𝐭 𝐏𝐇𝐋 + 𝐭 𝐏𝐋𝐇 )
𝟐
• As an example, the delays for a standard TTL gate are
tPHL = 7 ns and tPLH = 11 ns. These quantities are given
in the TTL data book and are measured with a load
resistance of 400 ohms and a load capacitance of 15 pF.
The average propagation delay of the TTL gate is:
11 + 7
t PD = = 9 ns
2
Performance Parameters: Speed Power Product
• The speed power product provides the basis for the comparison of logic circuits when
both propagation delay time and power dissipation are important considerations in the
selection of the type of logic to be used in a certain application.
• The lower the speed-power the better.
• The unit of speed-power product is Pico joule(pJ).
• The speed power product can be calculated as:
𝐒𝐏𝐏 = 𝐏𝐨𝐰𝐞𝐫 𝐃𝐢𝐬𝐬𝐩𝐚𝐭𝐢𝐨𝐧 × 𝐏𝐫𝐨𝐩𝐚𝐠𝐚𝐭𝐢𝐨𝐧 𝐃𝐞𝐥𝐚𝐲
• The table below lists the parameters for three types of gates. Basing your decision on the
speed-power product, which one would you select for best performance?
Performance Parameters: Noise Margin
• All electrical circuits are susceptible to noise.
• Unwanted signals are referred to as noise.
• This unwanted induced voltage can disrupt the operation of a digital circuit.
• In order to not get adversely affected by noise the circuit should have some amount of
noise immunity.
• Noise Immunity is the ability to tolerate unwanted voltage fluctuation.
• There are two types of noise to be considered :
➢DC noise is caused by a drift in the voltage levels of a signal.
➢AC noise is a random pulse that may be created by other switching signals.
• Noise margin is the maximum noise voltage added to an input signal of a digital circuit that
does not cause an undesirable change in the circuit output.
• Noise margin is expressed in volts and represents the maximum noise signal that can be
tolerated by the gate.
Performance Parameters: Noise Margin
• There are two values of noise margin specified for a given logic circuit:
• the High-level noise margin (VNH ) and
• the Low-level noise margin (VNL).
• There parameters are defined by the following equations:
VNL = VIL − VOL
VNH = VOH − VIH
Performance Parameters: Noise Margin
• The figure below shows the different voltage level parameters for a +5V CMOS.
• The noise margin for +5V CMOS are:
VNH = 4.4V − 3.5V = 0.9V
VNL = 1.5V − 0.33V = 1.17

Logic Levels for +5V CMOS

Performance Parameters: Noise Margin
• The figure below shows the different voltage level parameters for a +3.3V CMOS.
• The noise margin for +3.3V CMOS are:
VNH = 2.4V − 2V = 0.4V
VNL = 0.8V − 0.4V = 0.4V

Logic Levels for +3.3 V CMOS

Performance Parameters: Noise Margin
• The figure below shows the different voltage level parameters for TTL.
• The noise margin for TTL are:
VNH = 2.4V − 2V = 0.4V
VNL = 0.8V − 0.4V = 0.4V

Logic Levels for TTL

Performance Parameters: Noise Margin
• Voltage specifications for three types of logic gates are given in the Table below. Select the
gate that you would use in a high-noise environment.

Solution:
• Gate A: NMH = 2.4V − 2V = 0.4V; NML = 0.8V − 0.4V = 0.4V
• Gate B: NMH = 3.5V − 2.5V = 1V; NML = 0.6V − 0.2V = 0.4V
• Gate C: NMH = 4.2V − 3.2V = 1V; NML = 0.8V − 0.2V = 0.6V
References
1. Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall – Pearson Education.