AMS/DSN/203

Wireline Serial-Link Transceivers

Summer 2023
Topic 5
Equalization
Sameh A. Ibrahim
Ain Shams University
ICL
(Courtesy of K. Yang – UCLA, S. Palermo – TAMU,
and E. Alon – UCB)
 Outline

⚫ Equalization Theory and Circuits

▪ Overview
▪ Classifications
⚫ Equalizer Implementations
▪ TX FIR
▪ RX FIR
▪ RX CTLE
▪ RX DFE

Equalization 2
 Basic Concept (1)
⚫ Channel has limited bandwidth.
⚫ A Simple model of channel: Single-pole lowpass filter

⚫ Bandwidth limitation causes intersymbol interference

(ISI)
⚫ Can we transmit signals that exceeds the channel
bandwidth?

Equalization 3
 Basic Concept (2)
⚫ Where is the energy loss?

⚫ Energy loss in R.
⚫ If we add VR back to output, we get the perfect signal.

⚫ This circuit can help us to compensate for the lowpass

filtering.
⚫ What is this circuit? Highpass filter

Equalization 4
 Channel Equalization
⚫ Equalization goal is to flatten the frequency response out
to the Nyquist Frequency and remove time-domain ISI.

Equalization 5
 Equalizer Topologies
⚫ TX vs. RX Equalization
Ease Adaptability
Adaptability - Swing Noise
⚫ Digital vs. Analog
Add/Sub V/I using GmC, RC or L

⚫ Linear vs. Non-Linear

Reflection
Ease
Timing
Loss Only
Crosstalk
Crosstalk

⚫ Continuous vs. Discrete-Time HPF, RC or L vs. FIR, IIR or DFE

Equalization 6
 TX FIR Filter
⚫ TX FIR filter pre-distorts transmitted pulse in order to
invert channel distortion at the cost of attenuated
transmit signal (de-emphasis).

2-Tap TX FIR Example

Equalization 7
 6 Gb/s TX FIR Equalization Example

⚫ Pros
▪ Simple to implement
▪ Can cancel ISI in pre-
cursor and beyond filter
span
⚫ Cons
▪ Attenuates low
frequency content due to
peak-power limitation
▪ Need a “back-channel”
to tune filter taps
Equalization 8
Time-Domain Representation

Equalization 9
 Frequency-Domain Representation

⚫ Equalizer has 14.4dB of frequency peaking

▪ Attenuates DC at -14.4dB and passes Nyquist
frequency at 0dB
Equalization 10
 TX FIR Coefficient Selection (1)
⚫ One approach to set the TX FIR coefficients is a
Minimum Mean-Square Error (MMSE) Algorithm

Equalization 11
 TX FIR Coefficient Selection (2)
⚫ Total system

⚫ Multiplying input symbols by TX Eq., wc=w*c

⚫ We desire the output vector, y, to be ISI free

Equalization 12
 Lone-Pulse Equalization Example
⚫ With lone-pulse
equalization, l=1 input
symbols, i.e. c=[1]

Equalization 13
 TX FIR Coefficient Selection (3)
⚫ We can calculate the error w.r.t. a desired output

⚫ Computing the error matrix norm2

⚫ Differentiating this w.r.t. tap matrix taps to find taps which yield
minimum error norm2

⚫ Solving for optimum TX Eq taps, W

⚫ This will yield a W matrix to produce a value of “1” at the output

cursor, i.e. an FIR filter with gain
▪ Need to normalize by the total abs(tap) sum for TX FIR realization

Equalization 14
 TX FIR Tap Resolution
⚫ Using the above MMSE algorithm for the Refined
Server Channel at 10Gb/s

⚫ Generally, TX DAC resolution is limited to between 4 to

6 bits.
⚫ Mapping these equalization coefficients with this
resolution may impact performance.

Equalization 15
 TX FIR Circuit Architectures
⚫ Direct FIR
▪ Parallel output drivers for output
taps
▪ Each parallel driver must be sized
to handle its potential maximum
current
▪ Lower power & complexity
▪ Higher output capacitance
⚫ Segmented DAC
▪ Minimum sized output transistors to
handle peak output current
▪ Lowest output capacitance
▪ Most power & complexity
▪ Need mapping table (RAM)
▪ Very flexible in equalization

Equalization 16
Direct FIR Example

[Rylyakov, CSICS 2005]

Equalization 17
Segmented DAC Example

[Casper, ISSCC 2006]

Equalization 18
 Pre-Emphasis in VM Drivers

• Reduce output (de-emphasis) • Shunt impedance in parallel • Power is minimum

by a path to ground in with channel when amplitude
combination with the main • Gkill can be removed reduces.
signal path. completely. • But termination is
• Amplitude changes without • Termination is not affected. corrupted.
impedance. • Power is reduced with swing.
• Power loss is high. Equalization 19
 Outline

⚫ Equalization Theory and Circuits

▪ Overview
▪ Classifications
⚫ Equalizer Implementations
▪ TX FIR
▪ RX FIR
▪ RX CTLE
▪ RX DFE

Equalization 20
 RX FIR Equalization

⚫ Delay analog input signal and multiply by equalization coefficients.

⚫ Pros
▪ With sufficient dynamic range, can amplify high frequency content
(rather than attenuate low frequencies).
▪ Can cancel ISI in pre-cursor and beyond filter span.
▪ Filter tap coefficients can be adaptively tuned without any back-channel.
⚫ Cons
▪ Amplifies noise/crosstalk.
▪ Implementation of analog delays
▪ Tap precision
Equalization 21
 Analog RX FIR Equalization Example
⚫ 5-tap equalizer with tap spacing of Tb/2

[Hernandez-Garduno, ISSCC 2007]

Equalization 22
 Digital RX FIR Equalization
⚫ Digitize the input signal with high-speed low/medium
resolution ADC and perform equalization in digital
domain
▪ Digital delays, multipliers, adders
▪ Limited to ADC resolution
⚫ Power can be high due to very fast ADC

Equalization 23
 Digital RX FIR Equalization Example

[Harwood, ISSCC 2007]

⚫ 12.5GS/s 4.5-bit Flash ADC in 65nm CMOS
⚫ 2-tap FFE & 5-tap DFE
⚫ XCVR power (inc. TX) = 330mW, Analog = 245mW,
Digital = 85mW
Equalization 24
 Continuous-Time Linear Equalizer (CTLE)
⚫ Passive R-C (or L) can implement
high-pass transfer function to
compensate for channel loss.
⚫ Cancel both precursor and long-
tail ISI.
⚫ Can be purely passive or
combined with an amplifier to
provide gain.

Passive CTLE Active CTLE

Equalization 25
 Passive CTLE
⚫ Passive structures offer excellent linearity, but no gain
at Nyquist frequency.

Equalization 26
 Active CTLE
⚫ Input amplifier with RC
degeneration can provide
frequency peaking with gain
at Nyquist frequency.
⚫ Potentially limited by gain-
bandwidth of amplifier.
⚫ Amplifier must be designed
for input linear range.
⚫ Often TX eq. provides some
low frequency attenuation.
⚫ Sensitive to PVT variations
and can be hard to tune.
⚫ Generally limited to 1st-order
compensation.
Equalization 27
 Active CTLE Example

⚫ Pros
▪ Provides gain and
equalization with low
power and area
overhead
▪ Can cancel both pre-
cursor and long-tail ISI
⚫ Cons
▪ Generally limited to 1st
order compensation
▪ Amplifies
noise/crosstalk
▪ PVT sensitivity
▪ Can be hard to tune

Equalization 28
 Active CTLE Tuning
⚫ Tune degeneration resistor
and capacitor to adjust zero
frequency and 1st pole
which sets peaking and DC
gain.
⚫ Increasing CS moves zero
and 1st pole to a lower
frequency w/o impacting
(ideal) peaking.
⚫ Increasing RS moves zero to
lower frequency and
increases peaking (lowers
DC gain)
▪ Minimal impact on 1st pole
Equalization 29
 Active CTLE Cascading

[Gondi, JSSC Sep. 2007]

⚫ Multiple stages are required for higher peaking with
reasonable DC gain.
⚫ Some gain stages can be used.
⚫ Reverse scaling provides bandwidth improvement in
applications where the input impedance need not be
very high.

Not Scaled Scaled

Equalization 30
 Dual-Path CTLE

⚫ Adding a high-pass filter

to an all-pass filter results
in peaking.
⚫ Phase matching between
the two paths is required,
especially for cascaded
stages.
⚫ Tuning is done by varying
the relative gains.
Equalization 31
 Outline

⚫ Equalization Theory and Circuits

▪ Overview
▪ Classifications
⚫ Equalizer Implementations
▪ TX FIR
▪ RX FIR
▪ RX CTLE
▪ RX DFE

Equalization 32
 Decision Feedback Equalizer (DFE)

1-Tap Example

⚫ DFE is a non-linear equalizer.

⚫ Slicer makes a symbol decision, i.e. quantizes input.
⚫ ISI is then directly subtracted from the incoming
signal via a feedback FIR filter.
Equalization 33
 RX DFE Pros & Cons
⚫ Pros
▪ Can boost high frequency content
without noise and crosstalk
amplification.
▪ Filter tap coefficients can be adaptively
tuned without any back-channel.
▪ Corrects both loss and reflections.
⚫ Cons
▪ Cannot cancel pre-cursor ISI.
▪ Chance for error propagation
• Low in practical links (BER=10-12)
▪ Critical feedback timing path
▪ Timing of ISI subtraction complicates
CDR phase detection.
▪ High power (especially, digital)

Equalization 34
 DFE Example
⚫ If only DFE equalization, DFE tap
coefficients should equal the
unequalized channel pulse
response values [a1 a2 … an].
⚫ With other equalization, DFE tap
coefficients should equal the pre-
DFE pulse response values.

Equalization 35
 Full-Rate DFE

☺ Direct implementation  Full-rate clock

☺ Lowest complexity

Equalization 36
 Half-Rate DFE

☺ Half-rate clock  Large area and power

☺ Relaxes FF design

Equalization 37
 Multiplexed-Half-Rate DFE

[Payne, JSSC Dec. 2005]

☺ Half-rate clock  Larger delay

☺ Saves one summing node

Equalization 38
 Half-Rate Loop-Unrolled DFE
☺ Half-rate clock
☺ Relaxes timing constraints
☺ Reduces loading at summing
nodes

 High complexity
 Four summing nodes

• Also called, lookahead,

speculative or partial
response DFE.
Equalization
[Bulzacchelli, JSSC Dec.2006] 39
 HR Loop-Unrolled Multiplexed DFE

[Ibrahim, ISSCC 2010]

☺ Loop unrolling  2-MUX delay

☺ Multiplexing
☺ Half-rate clock
☺ Other taps can be readily added

Equalization 40
 DFE Resistive-Load Summer

⚫ Summer performance is critical for DFE operation.

⚫ Summer must settle within a certain level of accuracy
(>95%) for ISI cancellation.
⚫ Trade-off between summer output swing and settling
time.
⚫ Can result in large bias currents for input and taps.

Equalization 41
 DFE Integrating Summer

[Park, ISSCC 2007]

⚫ Integrating current onto load capacitances eliminates RC

settling time.
⚫ Since ΔT/C > R, bias current can be reduced for a given
output swing.
▪ Typically a 3x bias current reduction
Equalization 42
 Charge-Steering Summer

⚫ 25 Gb/s DFE with low power consumption

⚫ Half-rate design so 12.5G clock is used.
⚫ Multiplexed design so 6.25G clock is used to implement
MUX.

Equalization 43
 Digital Implementation
⚫ Similar to RX FIR, RX DFE can be implemented digitally
after a high-speed ADC.

⚫ Pros
▪ Ability to do both FIR and IIR and even coding all
together (correct pre- & post-cursor)
▪ More programmable and flexible
▪ Better portability
⚫ Cons
▪ Requires accurate D/A or A/D
▪ Very difficult to build at high-speeds
▪ High resolution at multi-GS/s
▪ Signal processing at multi-GHz
Equalization 44
 ADC-Based Equalizer Example

[Chen, JSSC Apr. 2012]

⚫ HPF provides a low-power pre-filtering for post-cursor ISI.
⚫ FIR cancels the pre-cursor ISI at lower power than digital.
⚫ A VGA (up to 10dB) buffers the signal before the ADC and
provides an alternative for ADC FSR adjustment.
⚫ An ADC with non-uniform quantization levels is used to
reduce number of comparators.
⚫ A selection-based DFE is easy to implement in digital.
Equalization 45
 DFE with IIR Feedback

[Liu, ISSCS 2009]

⚫ Large 1st post-cursor H1 is canceled with normal FIR

feedback tap.
⚫ Smooth long tail ISI from 2nd post-cursor and beyond is
canceled with low-pass IIR feedback filter.
⚫ Note: channel needs to be smooth (not many
reflections) in order for this approach to work well.

Equalization 46
 Merged Summer & Partial Slicer

[Liu, ISSCS 2009]

⚫ Integrating summer with regeneration PMOS devices to

realize partial slicer operation.

Equalization 47
 Equalization Effectiveness

⚫ Some observations
▪ Big initial performance boost with 2-tap TX eq.
▪ With only TX eq., not much difference between 2 to 4-tap.
▪ RX equalization, particularly DFE, allows for further
performance improvement
• Caution – hard to build fast DFEs due to critical timing path
Equalization 48