ESC201: Lecture 18

Dr. Imon Mondal

ASSISTANT PROFESSOR,
ELECTRICAL ENGINEERING, IIT KANPUR

2024-25 SEM-I ESC201 INTRODUCTION TO ELECTRONICS

1
 Sequential Circuits

• Calculation divided into steps

• Each step is triggered by a clock

• At each step,
• output is based on the current values of
inputs and past values of inputs/outputs.

• Requires memory

Dr. Imon Mondal ESC201, 2024-25 Sem-I 2

 Synchronous Clocked Sequential Circuits

Input Combinational Output

Circuit
Flip-flops
Clock

Entire operation synchronized via clock

Employs signals that affect the stored value only at discrete instants of time.

Synchronization is achieved via the clock pulses.

Dr. Imon Mondal ESC201, 2024-25 Sem-I 3

 Analyzing sequential circuits
A memory
x A Output Logic
D

B
A B z
D
x x

Next state Logic clk

• Output z depends on the input x and on the state of the memory (A,B)
• The memory has 2 FFs and each FF can be in state 0 or 1.
• Thus there are four possible states: AB: 00,01,10,11
• To describe the behavior of a sequential circuit, we need to show
• How the system goes from one memory state to the next as the input changes
• How the output responds to input in each state
Dr. Imon Mondal ESC201, 2024-25 Sem-I 4
 Sequential Circuits

The binary information stored in the storage

elements at any given time defines the state
of the sequential circuit at that time

Output is a function of input as well as the present state (the stored value).

Next state is also a function of the present state and inputs.

Dr. Imon Mondal ESC201, 2024-25 Sem-I 5

Sequential Circuits
x
CC-1 z
x z
CC
x
CC-2

y Y
Memory
(FFs) y Y
Memory
(FFs)

CC-2 x
Next State logic

CC-1
Y y z
Memory
Output logic
clk
(FFs)
Example
Next state Logic Output Logic

A
x A
D

B
A B z
D
x x

clk

memory

CC-2 x
Next State logic

CC-1
Y y z
Memory
Output logic
clk
(FFs)
Analysis
Next state Logic Output Logic

A
x A
D

B
A B z
D
x x

clk
memory

The dependence of output z on input x depends on the state of the memory (A,B)

The memory has 2 FFs and each FF can be in state 0 or 1. Thus there are four possible
states: AB: 00,01,10,11.

To describe the behavior of a sequential circuit, we need to show

1. how the system goes from one memory state to the next as the input changes
2. How the output responds to input in each state
Analysis of Sequential Circuits
A memory Output Logic
x A
D

B
A B z
D
x x

Next state Logic

clk

State Transition Table

DA = A.x + B.x ; DB = A.x ; z = ( A + B ). x Present State Input Next State Output

A(t) B(t)
A B x(t)
x A(t+1)
A B(t+1)
B z(t)
z
A(t + 1) = A(t ).x + B(t ).x 0 0 0
0 0 0
0 0 1 0 1 0
B(t + 1) = A(t ).x
0 1 0 0 0 1
z = ( A + B). x 0 1 1 1 1 0
0 0 1
1 0 0
1 0 1 1 0 0

1 1 0 0 0 1
1 1 1 1 0 0
 State Transition Table
A memory Output Logic
x A Present State Input Next State Output
D
A(t) B(t)
A B x(t)
x A(t+1)
A B(t+1)
B z(t)
z
B 0 0 0 0 0 0
A
D
B z 0 0 1 0 1 0
x x
0 1 0 0 0 1
Next state Logic
clk
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
00 Memory state in which FF A& B have output values 00

If x = 0 then z = 0, When the clock edge comes the system

X(t)=0/z(t) would stay in 00 state.
?
00 If x = 1 then z = 0. When the clock edge comes the system
would go to 01 state.
x=1/z
0/0
?

00 01
1/0
Analysis of Sequential Circuits

A
x
memory
D
A
Output Logic A(t + 1) = A(t ).x + B(t ).x

B
B(t + 1) = A(t ).x
z
z = ( A + B). x
A B
D
x x

Next state Logic clk

State Transition Table

1/0
10 Present State Input Next State Output
0/0 0/1 A(t) B(t)
A B x(t)
x A(t+1)
A B(t+1)
B z(t)
z
1/0 0 0 0
0 0 0
00 01 11 0 0 1 0 1 0
1/0 1/0
0 1 0 0 0 1
0/1 0 1 1 1 1 0
0/1 0 0 1
1 0 0
1 0 1 1 0 0
State transition Graph
1 1 0 0 0 1
1 1 1 1 0 0
12
Design of Sequential Circuits
1/0
10
0/0 0/1
1/0

Specifications 00
1/0
01
1/0
11

0/1
0/1

State Diagram
State Transition Table

Present State Input Next State Output

A B x A B z
0 0 0 0 0 0
Choose FF 0 0 1
0 1 0

State Encoding 0
0
1
1
0
1
0 0 1
0
1 1
1 0 0 1
0 0
1 0 1
1 0 0
1 1 0
1 1 1 0 0 1
State Table 1 0 0

A
x A
D
Synthsize Combinational
B
Circuit A B z
D
x x

clk
System specification to State diagram

x Sequence detector Y

(0101101110111100......)

Detect 3 or more consecutive 1’s in the input stream

0/0
0/0

S0 S1
1/0
1/0
0/0 0/0

SS23 S2
1/1 1/1
Conversion of State transition graph to a circuit
Example-1

x
0/0 0/0
CC-2
Next State logic

S0 S1
1/0 y CC-1
z
Y Memory
Output logic
clk
(FFs)

1/1
3 blocks need to be designed

1. How many FFs do we need? N FFS can represent 2N states so Minimum is 1

2. Which FF do we choose? Say D FF

3. How are the states encoded? Say FF output Q=0 represents S0 and Q=1
represents S1 state
 0/0 CC-2
0/0 x
Next State logic

S0 S1 CC-1
1/0 z
D Q Output logic

clk
1/1

State Transition Table

Present State Input Next State D Output

Q(t) x Q(t+1) z
0 0 0 0 0 x D Q
z
0 1 1 1 0 clk

1 0 1 1 0
1 1 0 0 1

D = Q.x + Q.x ; z = Q. x
Example-2

CC-2 x
0/0 0/0 Next State logic

S0 S1
1/0 CC-1
Y y z
Memory
Output logic
clk
(FFs)
1/1

1. How many FFs do we need? 1

2. Which FF do we choose? Say JK FF

3. How are the states encoded? Say FF output Q=0 represents S0 and Q=1
represents S1 state
 CC-2
x
Next State logic
0/0 0/0
CC-1
z
S0 S1 J Q Output logic
1/0 clk
K Q

1/1
Q(t) Q(t+1) J K
0 0 0 X
State Transition Table
0 1 1 X
Present State Input Next State J K Output 1 0 X 1
Q(t) x Q(t+1) z
1 1 X 0
0 0 0 0 X 0
0 1 1 1 X 0

1 0 1 X 0 0 x J Q
1 1 0 1 z
X 1 clk
K

J = x ; K = x ; z = Q. x
Example-3

For 4 states a minimum of two FFs will be

1 required. Let us choose 2 D FFs A &B
0 1
x
S0 S3 NS logic
0
0
0 1
DA QA DB QB
S1 S2
1 clk clk

FF O/P Present State Input Next State

State A B A B x A B DA DB
0 0 0 0 1 0 1
S0 0 0
0 0 1 0 0 0 0

0 1 0 1 1 1 1
S1 0 1
0 1 1 1 0 1 0

1 0 0 1 1 1 1
S2 1 0
1 0 1 1 0 1 0

1 1 0 0 0 0 0
S3 1 1
1 1 1 1 1 1 1
Present State Input Next State
A B x A B DA DB DA
AB
0 0 0 0 1 0 1 x 00 01 11 10
0 0 1 0 0 0 0

0 1 0 1 1 1 1 0 0 1 0 1
0 1 1 1 0 1 0

1 0 0 1 1 1 1 1 0 1 1 1
1 0 1 1 0 1 0

1 1 0 0 0 0 0
1 1 1 1 1 1 1
DA = AB + xB + AB
= A  B + x.B

DB
AB
x 00 01 11 10 DB = x. A + x.B + x. A.B
1 1 0 1
0 = x.( A + B ) + x. A.B
1 0 0 1 0 = x. AB + x. AB = x  AB
 DA = A  B + x.B DB = x  AB

1
0 1

S0 S3 x
0
0
0 1

S1 S2
1

DA QA

clk DB QB

clk