Altium Designer 25 Tutorial

Copyright (C) Istvan Nagy, 2025 www.buenos.extra.hu Free to share!

1. Introduction
This tutorial is targeting complex high-speed digital circuit board designs with Altium Designer release 2024. There are different
grades of high-speed designs from the microcontroller boards up to the server computer motherboard and data center line card designs,
so the methodology here to be suitable for all, is based on the high-end and scalable down.
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Altium Designer 25 Tutorial _____________________1 4. Design Rules _______________________________ 5
1. Introduction _______________________________1 5. Constraint Manager ________________________ 6
2. Basic PCB Design ___________________________1 6. Interactive High-Sp Route ____________________ 8
2.1. Projects and Editor _________________ 1 7. Signal Integrity_____________________________ 9

2.2. SCH Library ________________________ 1 8. Typical Examples __________________________ 10

2.3. PCB Library ________________________ 2 8.1. PCIe Gen4 SERDES bus design ________ 10
2.4. Schematics ________________________ 2 8.2. DDR4 Memory-Down design ________ 10
2.5. PCB Design ________________________ 3
2.6. Design Reuse ______________________ 4
3. High-Speed Signal Objects ____________________4

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Altium also has several side panels for browsing and editing
objects. They appear depending on file type, and whether we
2. Basic PCB Design enabled them from the „Panels” button in the lower right corner.
We can dock them to the left or right side of the screen, they can
2.1. Projects and Editor be set to stacked, static, auto hide. When they hide a tab label is
In a project folder we have multiple files. One is the main shown. The projects panel shows the tree structure of our project,
project file .PRJPCB, then we have a layout file .PCBDOC, several we can open files from there. Keep these panels always visible:
schematic pages in separate .SCHDOC files, library files like Projects, PCB, Properties, List.
.SCHLIB and .PCBLIB, a folder for manufacturing When right clicking in the editor on empty space, a big menu
„ProjectOutputs”. All files open in the main window design opens with lots of settings and actions, dependent on what file we
explorer, but the menus are dependent on which file type was open. are editing, what mode we are in.
A top tab can be used to select which of the open files to edit. All Most companies have managed and released shared libraries,
drawings allow CTRL+scroll for zooming. but one-person companies can keep library files edited within
New project: file>new>project, give name, enable CM projects. We have to add existing company libraries to be
(whether we want to use constraint manager) then “create”. Create accessible by the project. Either Project>Add Existing, or on the
new files for the project on the projects panel, by right clicking the Components Panel> > Libraries Preferences> Installed>
PRJPCB and then >add new to project > schematic, or PCB or Install> select file type and browse.
library file...
2.2. SCH Library
To make our own schematic symbols, we have to create/open a
SCHLIB file on the projects panel by right clicking the PRJPCB
and then >add new to project >Schematic Lib. The schlib panel
opens, click Add, then enter name, select the new component it in
the schlib panel. In heterogenous split components the top level is
called component, the sub symbol is called a “part”. They appear
under the component name on the schlib panel. To add pins to the
single part component or to the first part of a heterogenous
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component: select component on schlib panel, then Tools > 2.4. Schematics
Symbol Wizard, set number of pins, then fill out the table or
import from Excel. We can prepare pin tables in Excel in a Every page is a separate SCHDOC file. Once we added
matching format like below, then select data (not header), then enough SCHDOC files, in each we click Properties Panel>
CTRL+C to copy, then in Altium upper/left cell CTRL+V to paste. Sheet Size drop down to set a larger page size.
For single-part-comp or first part we press Place> Symbol, for Multi-page schematics can be hierarchical with PORT
heterogenous sub-component-parts press Place> New Part. We (Place>Port) connections in the module and SHEET
SYMBOL in the top level schematic. The sub-module symbol is
can manually add more parts to a component by the button.
created by: design>create sheet symbol from sheet. We can
also design flat schematics with no top-level, then we have to use
Place> Off Sheet.
We can place components from the „Components” panel, but
first the SCHLIB file is selected on the top drop-down, then the
component, doubleclick and move to desired location on
schematic. Part rotation with SPACE key while moving it.
Doubleclick on a part and we can see/edit properties, but don’t edit
On the properties panel we have to enter parameters like part here, rather in the released library. For example, have a separate
number and value. We have to add company-specific properties, library item for a 1k resistor than a 10k resistor.
for example if we work at ACME-inc., then ACME_PN, A component can be do not populate DNP, to leave it out of
ACME_DNP, MFR_PN… We also need to add a footprint using the purchase BOM and pick&place file. Either to design for
add> footprint> browse. debugging (to swap a PU/PD on the prototype without trace
The signal length (Package Length PL or PinDelay A to B on cutting), add possible future features or product variants. We can
diagram) within large BGA packages have to be entered for do it in different ways depending on company; we could use a DNP
accurate length tuning later. When we are editing the schematic property in all components and NO means in place and Yes means
symbol, we have to do this separately for each sub-symbol (part). DNP, or overwrite the part number with “DNP”, then delete these
Prepare the PL data in excel (same unit as the tool, mils) for each rows from the BOM manually, or we can use variants. We could
subsymbol, sorted by pin number, select the length data only, have a base design (add text next near all planned DNPs as “DNP”
CTRL+C to copy. In Altium select all pins in the subsymbol the in red), and a production variant associated with the board part
drawing, but make sure the rectangle is not selected. Then open the number. In this variant we mark the DNPs. First we annotate
SCHLIBlist panel, in the PinDesignator column sort, then in the refdes, then we create variants in Project>Variants>Add Variant,
Pin/PckLength column click the first item, CTRL+V to paste. Close. Then in the projects panel select the variant to edit by double
Save. clicking. In the schematic on a component (sub-part-A if split part)
rightclick> Part Actions> Variants> In the column named after
our variant click the […] button, select “NotFitted”. All other edits
should be done on the default “NoVariations” variant double-
clicked in the Projects panel.
Once components are placed, we wire them with . We can
place power symbols with . For non-GND nets we have to
2.3. PCB Library place this first, then select it, then on the Properties panel select
Style=Circle, add a net name like P1V0_FPGAC, then we need to
To make our own footprint symbols, we have to create/open rotate it upside-down by moving and pressing TAB twice. We add
a PCBLIB file on the Projects Panel> PRJPCB> rightclick net labels with Place> Net Label. We can draw buses with
>add new to project >PCB lib. The pcblib panel opens. To “signal harnesses”. We can place parameter set directives with
add a new footprint: Tools> IPC Compliant Footprint Wizard , then Add>NetClass or Rule… In older versions of Altium we
(or just the basic Footprint Wizard), fill in the parameters. Once had to place diffpair symbols in the schematic (Place>
done, we can edit it, by moving/deleting pins, Place>Pad, Directives> Diffpair), but in AD24 we should define diffpairs in
editing pads (click, then Properties panel edit, padstack, X/Y- the PCB CM or PCB-panel. Either way diffpair nets must be
size), drawing on silkscreen. named with _P and _N suffixes. Nets and ports are local, Off-
For large BGAs with irregular pattern, we should import sheet-connectors and power symbols are global on all pages. If we
from Allegro or Excel. In allegro open the reference design, use off-sheet or port then we don’t need net labels.
export libraries, then open the footprint, reports> symbol pin
report, then copy (pin number and X/Y coordinates) it into
excel. We can also create this spreadsheet manually based on
the datasheet in Excel. Organize the excel file to have the same Once done, we annotate refdes (designator in Altium) to all
columns as the Altium PCBLIBlist panel table has. In Altium, components with Tools > Annotation> Force Annotate All.
footprint library, create a package with the same number of pins Then export a BOM with Reports> Bill Of Materials, and if we
using the wizard. Copy cells from Excel to Altium’s used variants or variant-based DNPs then we select the correct
PCBLIBlist XY coordinates columns. Make sure they were variant from the drop-down. Error checking with project>compile
sorted the same way on both ends of the copy. document. We also export a PDF schematic with File>
SmartPDF.

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 2.5. PCB Design Object Coloring: Nets can be displayed either in layer color,
or net color. On the PCB panel find and select the nets, then
Start: Project> Add New> PCB, save. The old versions had rightclick>Change Net Color. Enable Color Override for each net
a board wizard, that is now gone. Then we need to get a DXF file using the checkbox next to its name. Set solid coloring in Tools>
from our mechanical engineer, that contains the board outline, Preferences> PCB editor> Board Insight Color Overrides.
external connector outlines and mounting holes, and import it into The new Altium supports object filtering, like Allegro. Before
a mechanical layer. File> Import> DXF, then set up scale and layer moving or deleting objects, we can disable others on the
(mechanical-1). Set up View> Grids> Set Up Global Snap Grid Properties panel> Selection Filter, to avoid affecting them.
to be coarse/accurate, View> Board Planning Mode. Then Measure distance: Reports> Measure Distance
Design>Redefine Board Shape, then redraw it, then View> 2D Find items and zoom to them: Press “J”, then select component
Layout Mode, then set the grids again to 10mils for placement. Set or net, then type in the refdes or net name. To display info about an
the origin Edit>Origin>Set on the board near the lower left corner. object: left click, the Properties panel will display relevant data.
Once the board is set up: we have to import netlist from Component placement is, really just moving from the auto
schematic: design> import changes from [...prjpcb] validate, placed (when imported changes from SCH) area to the board
execute, close. This will place all parts next to the board. design. Before placement we make inner layers hidden, so we can
Stackup Layers: Design> Layer Stack Manager. Add select components instead of planes. Click on one comp, hold and
layers, define their thicknesses, signal/plane type order. Also move. If it doesn’t work then select the small area enveloping the
define via types like BB, microvia depths. Layers are not component then click/move. Rotate with SPACE, or move to
categorized as class/subclass like in Allegro. We use the bottom side with “L”. Move refdes as if it was a component. We
mechanical layers for all manufacturing comments and fab notes. can also select a few comps on the sch, if cross select mode is
To enable backdrilling, click the button, select backdrills, a enabled in tools, then in the layout move them. If the refdeses are
lower tab appears, click it, then add as many BD layer pairs as we too large, then we can select one, rightlcik> Find Similar
want to use with the [+Add] button, then editing the layers on the Objects> Refdes = same, OK, then on the Properties panel we
Properties panel. BD always starts from (Top or) Bottom, and ends change the text height. How close we can pack them is set in a
one layer away from our routing MNC layer. On the via types tab, constraint: CM> AllR> Placem> CompClearance.
we define normal via sizes, and layer pairs for microvias or BB. We can place footprints for floorplanning from the
Panels: Enable/disable panels from the lower/right Panels components panel. We can also place mounting holes and
button. During PCB design we use many panels, the most fiducials from it, although using schematic is preferred. MNT holes
important one is the PCB panel, with a drop-down list on the top to can also be placed as pads (Place> Pad then assign GND net).
select signal object type. In the PCB panel we can specify from a Design rules: When the PRJPCB is created we have to decide
drop-down list what should happen when we select an object: either whether we will be using the legacy design rules editor (DRE), or
no effect („Normal”), or highlight („Dim”), or highlight and the constraints manager (CM). DRE opens from Design>Rules.
disable editing of other objects („Mask”). It is cancelled by CM opens from Design > Constraint Manager, and stored in
pressing the „Clear” button in the bottom-right corner. The View constraints.xml file. We should set up at least some basic rules like
Configuration panel is needed to show/hide layers. The Properties clearance, width, solder mask, via style, plane connect/clr, diffpair
panel changes content depending on what we are doing. rules before any fanout or routing. See chapters on CM/DRE.
Interactive routing starts with the icon. Set the grids to
about 1mil for routing (View>Grids). Active layer is selected by
clicking the bottom tabs. Routing mode can be controlled from:
tools> Preferences> PCB> Interactive Routing in advance, or
from the properties panel during editing, for example push/shove.
We can just click on traces to slide/edit them; we don’t have to
select a specific mode first like in allegro.
Add Vias: press “+” click while routing. Ground stitching vias
can to be placed from Place>via, then assign the net name on the
Properties panel. The size is set in CM> Allr> Routing> Routing
Via Style (All, not net class) or DRE> Route> RoutViaSt.
Altium likes to create vias with soldermask opening, but modern
complex boards are made with all VIPPO (state in fab drawing
Connection Lines: View> Connections> Show/Hide… notes) and complete tenting (no opening) on both sides. Cheap
Layer colors and visibility can be changed: First enable the boards without VIPPO need complete tenting on top (especially
Panels>View Configuration panel at the lower/left panels button. under BGAs) and a small opening on bottom (for outgassing). So,
Then we can change colors and temporarily enable/disable specific we can select a via, rightclick> find similar > ok, then on the
layer visibility as needed, by single clicking on the eye icon . Properties Panel > Solder Mask Expansion = manual =
In Altium everything that is on a layer (pads, vias, traces) are tented. Or set a rule before use: CM> Allr> Mask> SolderMExp
visible or invisible in the same time. The active layer being edited create a new rule, Object Match = “IsVia”, then click checkbox for
is selected on the bottom/lower labs under the PCB: tenting. To use microvias, we have to create them in the Layer
Stack Manager, based on the layer-pairs form the vendor stackup.
Fanout: Set the constraints like width, clearance, SM
expansion and routing via style, as shown above. Then set up
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fanout behavior with CM> Allr> Routing> Fanout Control. Then Thieving cannot be applied in Altium, but we could use
select Route> Fanout> Component, click component. polygon pours with crosshatched pattern or rely on our PCB fab.
Draw Power Shapes: (polygon pour) on signal layers, for Preparing for manufacturing: Every layer should have text
power delivery or VRM circuit power nets. Doubleclick to add net. outside of the outline about layer name, layer number, whether it is
upside-down (mirrored), company info and design part numbers.
Voids can be drawn with rightclick on the button and select
On one mechanical layer meant for fab drawing, we place tables
. with Place> Drill Table and Place> Layer stack table, then we
Keepout shapes: place> keepout> fill, then on the Properties manually add text about technology statements, materials, surface
panel select object type to keep out (via, pad, trace…). For finish, coupons, impedance and loss tables. We also create an
example, via keepout on a routing layer. assembly drawing on another mechanical layer, for verifying the
We can specify areas where different rules would apply build, by using a dimensioned DXF from our ME. Once all done
locally. These areas are called „Rooms” and can be placed from the we fab-out: File> Fabrication Outputs> Gerber Files, and also
Design > Rooms > Place Rectangular Room menu. Then on NC Drill. We send a 3D model to our ME, to verify system fit:
the Properties panel they can be named and specify which layer to File> Export> Step3D. We generate additional documents: File>
be used on. Then they can be referenced in the design rules or CM Assembly> Pick & Place and Assembly drawing, and File>
(based on room name), so the rule will only apply within the area Smart PDF. Or all this in a more complicated way: Projects
covered by the Room. In the CM>Physical at the bottom of the Panel> PRJPCB> rightclick> Add New> Output Job file.
table AllRooms/name we can enter new width/via constraints. This We can export data reports from the PCB panel. Select the
is good for example for BGA breakout neck down, or smaller via desired object type (xSignals, Components), then select all classes
pads to implement “CLASS-3 with exception”. It doesn’t work for and all objects with CTRL+A, then rightclick>Report>Export.
plane clearance, so use class-based clearance rules.
Power plane layers: Altium supports negative planes, so they
need to be set in the stackup. On negative plane layers we place 2.6. Design Reuse
divider lines, enable the visibility of the layer on the ViewConf Design-reuse with a project is done using multi-channel
panel, then select the layer on the bottom tabs, then (Place >Line), hierarchical designs, with multiple instances of the same sch sheet
then doubleclick an area and select net. There is also a thick symbol. Each will create a "room" in the PCB, then we manually
outline layer to pull back from edge cuts. place&route one channel, then copy the work over to the other
Plane voids: All signal vias passing through planes will have channels: Design> Rooms> Copy Room Formats. Reusing
an antipad. Altium automatically removes all non-functional pads designs from other projects can also be done: File> New> Reuse
(NFPs) on plane layers, but leaves them on signal layers. That also Block, it will have both a schematic (single page) and a PCB file,
shrinks the antipads on the plane layers to AP= drill+2*CL we edit both and save, then on the Project panel "save to server".
clearance rule value, while keeping them larger AP= pad+2*CL on In our new project schematics Place> Reuse Block, the Design
signal layer power shapes. Most signals are fine with tight APs Reuse panel opens, we find out block, place button> rightclick>
around their via barrels, based only on etching clearance, but Place As Sheet Symbol.
SERDES signals need enlarged pads for via-impedance control and
backdrilling. BD requires a large BD-antipad AP= BD +
2*drillclearance. The drill clearance is usually 5…8mil on each 3. High-Speed Signal Objects
side, depending on our fab. The BD tool size is usually 6…12 mil The connection objects define the signals, or groups of signals.
larger in diameter than the via drill size, also depending on the fab. They can be browsed on the PCB panel. Categories:
So, we need to create two rules under CM> AllR> Plane> Plane Net: created using net labels in schema.
Cl, one for all signals with 5mil clearance, and one for the net or Bus: create using bus symbols in schema, it uses indexed
DP classes that belong to 8Gig+ SERDES difffpairs to force a large net names, like ABC1_[7..0]  ABC1_0. For serdes-
AP. Clearance= (AP-viadrill)/2. Signal layers also need a route links, it is better not to use buses, unless hierarchical.
keepout circle the same size as the BD antipad on planes. Diffpair (DP): Create them in the CM Physical tab with
rightclick > diffpair > Create Diffpairs From Nets, or
in the PCB panel’s “Differential Pair Rule Wizard” both
objects and rules get created. Or graphically in the sch.
Dual-voids are required Net Class (NetC): A group object. In PCB using
for high-speed diffpairs on Design> Classes window (add new). Used for all same
plane layers. Select GND type (non-DP) signals on a bus, for length rules. Also
layer on bottom tabs, then used on trace width (impedance) rules for single-ended.
Place> Arc(center) on the Diffpair Class (DPC): Similar to net class, create in the
pins then Place> Fill between. Either a small rectangle and 2 arcs, PCB Design>Classes editor. We need two rules for our
or a large rectangle to envelop them. If the clearance rule-driven DP class: a width and a diffpair rule (phase tol, gap,
void is large enough then we don’t need extra arcs. We copy these uncoupled). We need one for lane-to-lane matching.
on all planes. We can also copy this to the route keepouts, to help From-To: Same as the Allegro PinPair, but obsolete.
backdrilling and prevent signals passing between p/n vias. xSignal (XS): Same as the Allegro PinPair, preferred.
DRC check: Tools> Design Rule Check. The list of DRC This is to control propagation delay from a pin to another
violations should be worked down to zero by interactive layout pin. On a DDR4 fly-by address bus, on every address net
editing, except a few items that are reviewed and accepted/waived. we would have an xSignal from CPU-DRAM0, another

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 from CPU-DRAM1... They should be created with
Design> xSignals> Create xSignals, or with a wizard.
Xsignals also connect nets through res/cap.
xSignal Class (XSC): Similar to a matched group of
PinPairs in Allegro. We create one XSC for all the
xSignals of all DDR4 address nets between CPU-
DRAM1. Then create a length matching constraint/rule
for that XSC. Another XSC and a rule for CPU-DRAM2.
XNET: They can be created in the CM, XNETs are for
two nets passing a series passive part.
Classes are used to group signals before adding them to a rule.
We can have net classes, DP classes, xSignal classes. Classes are
created in the „Object Class Explorer” at Design>Classes, by 4. Design Rules
selecting a category, rightclick> Add Class, then add items to it. In Altium Designer in the traditional flow we normally specify
Diffpairs should be put into DP classes only, not net classes, to PCB design rules in the Design Rules editor (DRE), in the
avoid double definition of width when using the CM (not DRE). Design> Rules... menu item, instead of using a constraint
manager. For a PCB design, we have to set up various general
design rules, PCB fabricator-driven rules, as well as high-speed
design related trace length and impedance-driven width rules. In
every category there is a default rule, and several user created ones
that only apply to specific objects.
Trace length measurement still has bugs in AD25. It might fail
to measure xSignal lengths accurately, which case we have to
delete and reroute it. Either little trace segments overlap with
others, or a segment is not counted at all.
Xsignals and xSignal classes, as well as their associated design
rules could be created through the xSignal wizard: Design>
xSignals> Run Xsignals Wizard. The other way is through
Design> xSignals> Create xSignals (select source, load, nets,
then analyze, OK, redo for the next lane or chip), which better
shows exact parts. The XS names will end with “_PP1…N”, where
N is the Nth chip on the bus. A third way is in the
CM>Electrical>Nets tab, click on any nets, then the Topology
columns, then in the drop-down select “custom”. In the Design>
Classes> xSignal Classes we have to create XSCs so we can
apply rules to them later in the CM. Use the search with “*” to get
for example “MEM0_A*PP1” for address at DRAM1. We create
XS for point to point buses also, so we can match them in XSCs.

When the PRJPCB is created we have to decide whether we

will be using the legacy design rules in the design rules editor
(DRE), or the constraints manager (CM).
The DRE has a tree structure. Each item in the left menu is a
rule category. We can create several new rules for each category,
each rule will be applied to one class (or complex formula), by
rightclick> New Rule. Important categories:
Elecrical> clearance> clearance: mfr spacing.
Routing> width>width: trace width.
Routing> rout.via style: Set diameter, drill size, tenting.
Routing> Differential: diffp gap, phase-tol and
uncoupled.
Mask: solder mask and paste mask expansion param.
Create a rule for vias with scope=”IsVia”, and set tenting
on top and bottom. The default rule for all other pads
should be 2mil expansion and no tenting.
Plane: power plane/shape param, and via conn style.
High speed> Matched net lengths: Matching rules are
for setup/hold timing on source-synchronous and clock-
forwarding buses.
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 High speed> Length: max total trace length rules are for Matched length: With this rule we can control the trace lengths
synchronous or asynchronous bus SU/H timing or for relative to each other in a class of signals, diffpairs or xSignals. It
SERDES link loss budget (dB/inch). is used on source synchronous buses like DDR4 data bus, for
There is always a default rule, and specific rules for defined diffpair phase tolerance matching or for diffpair lane-to-lane
objects (nets, classes). The default rules are based on fabricator matching. We can find this at DRE> High Speed > Matched
minimum sizes (capability), the specific ones on calculations. Net Lengths. An important parameter of the rule is the types of
The typical DRE flow flow: 1. On PCB panel create objects objects which between the rule will be applied. For differential
like diffpairs, 2. In design>Classes create classes, 3. In Design phase tolerance rules, we enable only the „Check Nets Within
Rules create rules that apply to classes. Differential Pair” option, and leave the other two options disabled.
Every board needs basic rules like via direct plane connect and For lane-to-lane matching or for single-ended buses we enable the
plane clearance under DRE>Plane, component-to-comp clearance opposite. Note that the „Tolerance” value in the rule is the
under DRE> Placement, default trace width under DRE> maximum difference between the longest and shortest track.
Routing> Width and Via Style (size), and DRE> Electrical> Min/Max trace length: With this rule, we can specify a length
Clearance for copper trace gaps enforced by DRC and interactive range for a class of signals (Net/DP/XS). We can find the DRE>
push routing. Mask> SolderMask typically 2-3mils depending on High Speed > Length rule in the Design Rules Editor. It is useful
fab, and Routing> Fanout Control for via patterns. for synchronous, asynchronous and loss budget driven buses.
We can specify PCB design rules in the schematics level as
well. We add one PCB_Layout directive (which can contain
multiple rules) to a net. Instead of specifying the object to apply in
5. Constraint Manager
the rule, the object is specified graphically by attaching the rule Starting from 2024 Altium supports a spreadsheet-like
symbol to net or to multiple nets (copies of the same directive). We constraints manager window, like Cadence Allegro and Mentor
can place a rule directive from the Place> Directives> Expedition has. Open: Design > Constraint Manager. This is not
Parameter Set, then doubleclick on the symbol and doubleclick available in the cheapest license option. This is preferred instead of
on the rule in the list, then click on the „Edit rule Values” button. using the DRE if we have hundreds of xSignals or diffpairs, on
Trace width: Normally we put a group of nets based on large server or router board designs. When a project starts we have
characteristic impedance into a Net Class (for single-ended) or DP to decide whether it will be a legacy design rules-based design or a
class. Then we set up a DRE> Routing> Width rule for every class CM based design, we cannot have both. Although we can still
separately, and also a default width rule for all other or non- migrate an existing design from DRE to CM: Design > Migrate
impedance controlled traces (4mil). There are 3 values: for the Project to Constraint Manager Flow. Migration only works if
default rule set min=pref<<max, for others min=pref=max. We the system feature is enabled in: Tools> Preferences> System>
should use width rules instead of impedance rules, from our fab General> Advanced> Constraint Manager. Project Migration
vendor’s impedance/width/space calculations (from the negotiated Wizard = 1, then restart Altium.
approved stackup document). The contents of CM are saved into an XML file, but only when
Spacing in PCB design has two aspects: manufacturability and we close Altium. There is a bug in AD25, so we cannot enter values
controlling crosstalk levels. For the first aspect, we set up a DRE> to xSignal classes like tolerance or Target, but there is a solution:
Electrical> Clearance rule, which is normally the minimum Once we set up all xSignals and XSCs, save, close Altium, then
spacing that our PCB manufacturer recommends. The Differential open Altium again, go to CM and enter these values, save, close
Pair rules also contain a field called „Gap”, but this is a related to Altium (to ensure it doesn’t crash and lose all constraints, and re-
the differential impedance of the diffpair. For crosstalk control we open again). Now the constraints are usable in editing and DRC.
use a more flexible spacing rule: DRE> High-Speed> Parallel It has 3 tabs: Clearances, Physical (width, diffpairs), Electrical
Segment rule in the Design Rule Editor. This rule ignores short (lengths). Under electrical, there are 3 sub tabs: Nets, Diffpairs, and
parallel segments, and only checks spacing if the two traces run too xSignals. In any of these we can also create classes, by selecting
long in parallel. Basic spacing is enforced by a push/shove force in multiple signals, rightclick>classes>… or create new objects like
interactive routing. Sometimes we want to specify spacing (Parallel DP, XS, XSC… The Clearances tab allows us to add new rules, the
Segmenth rule) between differential pairs within a group, so we Phys/Elec tabs list objects that we can enter numbers for. The last
specify the rule’s scope like „InDifferentialPairClass('classname')” tab (AllRules) shows a tree of rule types, similar to the old DRE.
for the first object and „IsDifferentialPair” for the second object.
For diffpairs the DRE> Routing> Differential Pair Routing
rule has to be set up for every Differential-Pair Class, or to a list of
classes. The rule specifies the trace spacing (Gap) between the
positive and negative trace within a diffpair, and it is enforced in
interactive editing when we use the Interactive Differential Pair
routing option. Diffpair impedance is based on width+gap, we set We can use Constraint sets: Once we set up parameters for one
the gap in the diffpair rule and the width in the width rule. We will object, we can rightclick > Save As Constraint Set, then we can
also have to set up two „Matched Net Lengths” rules applied to a reapply it to other objects: rightclick> Select Constraint Set.
DP class, one to meet the phase tolerance requirements (within In the Clearances tab we can define a clearance between
DP=On, others=Off), and another one for lane-to-lane matching Net/DP classes in a matrix. We have to add existing classes to the
(within DP=Off, others=On). If we have two multi-lane PCIe links, matrix. When we click [+Add] then it creates both a column+row.
then each will be in a different DP class.

6
 The AllRules tab: This shows a tree of many rule types, similar
to the old DRE, mainly for basic rules. Check the DRE section for
detailed explanations! Here we can create new rules by rightclick>
Add Custom Rule, then enter ObjectMatch ([…]> Open Query
Builder for classes or object types) and numbers. In the
In the Physical tab we can see most signal objects types in a CM>AllRules > Mask> SolderMask category create a rule for
tree hierarchy browser view, like Class/DP/nets, and specify trace vias with scope=”IsVia”, and set tenting on top and bottom. The
width and via style/size to them. The PolygonConnect column default rule for all other pads should be 2mil expansion and no
should be set “DirectConnect” for “IsVia”. We can auto create all tenting. CM>AllRules > Routing> Routing Via Style sets the via
diffpairs here: rightclick > diffpair > Create Diffpair From Nets. pad and drill diameters. CM> AllRules > Routing> Fanout Contr
The editor will find them all from name suffixes _P/_N. sets pattern (auto, out, away, centered). The plane via connection
style (DirectConn), and plane layer clearance have to be set in
CM> AllRules> Plane> Power Plane Connect Style, and
clearance. The plane clearance should be set to achieve a desired
antipad size AP=BD+12mil= drill+2*CL. The CM> AllRules>
HighSpeed> Parallel Segment is good for crosstalk control
spacing that is only checked if it runs long (past limit). If we need
max length rules on xSignals, like on a synchronous multi-master
In the Electrical tab we can view/edit trace length related rules. PCI bus, se set up a rule under CM> AllRules> HighSpeed>
We enter values into an existing table, instead of creating rules. The Length. A multi-lane differential SERDES link requires lane-to-
Electrical tab has three different sub-tabs: Nets, DP and lane matching, with the CM> AllRules > HighSp> Matched
xSignals. Each shows object types in a hierarchy/tree browser. On Length. Backdrilling is defined by max stub length and oversize
the Nets sub-tab, we can create XNETs, and we can enter numbers (each side of hole) in CM> AllRules> HighSpeed> BackDrilling.
for max total length (for synchronous buses and loss-driven BD also requires definitions in the Layer Stack Manager.
SERDES links) and max via stub length constraints (for 8G+ Placement spacing: CM> AllRules > Placem> CompClearance.
SERDES links). On the Diffpairs sub-tab we can define diffpairs,
and we can enter numbers for diffpair width, gap, uncoupled length
and phase tolerance of the diffpairs.
The xSignals sub-tab at CM> Electr> xSignals tab doesn’t
allow object creation, so we have to do that in the Design>
xSignals> Create xSignals menu. When we first create XS/XSC
objects, the CM> Electr> xSignals tab seems to be read-only, so
we have to save, close Altium, reload Altium, and open CM, now
we can enter values. XSC-based rules in Altium were made for For diffpairs in the DRE we specify 4 rules, a width, a diffpair
trace length matching rules, so we have to enter tolerance in +/- rule, a matching rule for tolerance and a matching rule between
5mils or something, and click Target and open a drop-down menu lanes. In the CM we enter values for diffpairs on the CM> Electr>
to select which member of the XSC will serve as a target length for Diffp sub-tab, and on the CM> AllRules> HighSp> Matched
all other members. If we need max length rules on xSignals, like Length sub-tab also for lane matching (rightclick> add custom
on a synchronous multi-master PCI bus, then we have to use the rule, Object= InDifferentialPairClass(‘NAME’), then select
AllRules tab instead of the Electr> xSignals tab. The CM will “group- matched”). Altium25 seems to define width and gap rules
display the length measurements for each object as “Actual Value”, in two places, so to avoid using the wrong values in routing, we
or the matching rule deviation as “Margin”. The PCB panel also should set the same at both: CM> Physical and at CM> Electr>
displays these measurements. Diffp. Most values are entered to the rows of the DPCs. If we have
two multi-lane PCIe links, then each will be in a different DPC.
Maximum Length constraint values for SERDES buses come
from insertion loss budget calculations. The dB/inch loss data,
specific to a fabricator and material combination, comes from VNA
measurements on Delta-L test boards, then the max trace length is
calculated as L<budget/dBpi. The total budget comes from the
relevant standards like IEEE802.3xx, or SFF8418. For
synchronous, asynchronous, source-synch and clock forwarding
buses the rule values are either obtained from the chip vendor’s
datasheet or design guide document, or we calculate them using a
pre-layout timing analysis calculator spreadsheet, like this one:
https://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls

Typical high-speed objects and constraints:

Case Objects to Constraint numbers entered
create in CM

7
 Differential Pair point- •DP • CM> Physical (DPC) routing. We can manually route traces by right clicking the routing
to-point signal •DPC • CM> Electr> Diffp (DPC) mode button , select interactive routing, then clicking a pad, then
• CM> AllRules> HighSpeed>
Parallel Segment. (DPC) pulling the trace. For diffpairs we have to rightclick on the
• CM> AllRules> HighSpeed> button, then select Interactive Differential Pair Routing option .
BackDrilling (DPC, if >8Gbps) First we route all traces with plenty of spacing, then we tune them
Single-ended Sync/ •NetC • CM> Physical (NetC) later. Before routing starts, we should lock down large components
Async point-to-point • CM> AllRules> HighSpeed> by clicking on them, then Properties panel location clock the
bus with min/max len. Length (NetC) button. We can select objects in the schematic, then auto
• CM> AllRules> HighSpeed> highlighted in the PCB by tools> Cross Select Mode=on. We
Parallel Segment. (NetC) might want to hide most connection lines (ratsnests), to see clearly:
Single-en Source-sync •NetC • CM> Physical (NetC) View> Connections> Hide All, then select a few nets on the PCB
point-to-point bus •XS • CM> Electr>xSignals (XSC) panel, rightclick> Show.
with matched lengths •XSC • CM> AllRules> HighSpeed>
Parallel Segment. (NetC)

Multi-lane Point-to- •DP • CM> Physical (DPC)

point diff SERDES •DPC • CM> Electr> Diffp (DPC)
bus • CM> AllRules> HighSp>
Matched Length (DPC) Length tuning: We can delete then re-route trace segments,
• CM> AllRules> HighSpeed> auto-meander traces with the tuning button , or slide them
Parallel Segment. (DPC) (select, drag) to increase/decrease the signal length. The live tuning
• CM> AllRules> HighSpeed> gauge only pops up during actual tuning or SE-routing, not
BackDrilling (DPC, if >8Gbps)
diffpair-routing or sliding, so for those we have to rely on the PCB
Single-ended Sync/ •NetC • CM> Physical (NetC)
Async multi-drop bus
panel. While starting the tune, after pressing the tuning button, we
•XS • CM> AllRules> HighSpeed>
with min/max length. Length (XSC)
can press TAB to open the Properties panel, where we can select
•XSC
(one/chip) • CM> AllRules> HighSpeed> the meander pattern and parameters. Any editing mode can be
Parallel Segment. (NetC) exited/ended with the ESC key. Single-ended traces are tuned by
right clicking the tuning button , select Interactive Length
Tuning, while diffpairs (lane to lane match) are tuned using the
Single-ended Source- •NetC • CM> Physical (NetC)
sync multi drop bus
Interactive DiffPair Length Tuning option. During tuning, the
•XS • CM> Electr>xSignals (XSC)
with matched lengths Properties panel shows up with settings. Diffpairs need two tuning
•XSC • CM> AllRules> HighSpeed>
(one/chip) Parallel Segment. (NetC) actions, a single-ended one for phase tolerance match (with a 5mil
rule), and a differential one for lane-to-lane matching. The first
thing for phase tolerance is to twist at the pads manually, and only
after that we use meander tunes.
Diff multi drop bus •DP • CM> Physical (DPC)
(like DDR4 clock) •DPC • CM> Electr> Diffp (DPC)
•XS • CM> Electr>xSignals (XSC)
•XSC • CM> AllRules> HighSpeed>
(one/chip) Parallel Segment. (DPC)
Mixed SE/Diff multi- •NetC • CM> Physical (NetC for SE)
drop bus with matched (SE sign) • CM> Physical (DPC)
lengths, (DDR4 ACC) •DP • CM> Electr> Diffp (DPC)
•DPC • CM> Electr>xSignals (XSC)
•XS • CM> AllRules> HighSpeed>
•XSC Parallel Segment. (NetC+DPC)
(one/chip,
SE+diff)
Single-ended Source- •NetC • CM> Physical (NetC)
sync tree topology •XS • CM> Electr>xSignals (XSC)
•XSC • CM> AllRules> HighSpeed>
(one/chip) Parallel Segment. (NetC)

While we are manually tuning the traces, we can measure the

trace lengths. The Altium Designer’s on-screen Length Meter/
Gauge pops up during tuning,
6. Interactive High-Sp Route which shows the signal lengths
of the currently edited trace in
During interactive routing, the properties panel should be real time. The PCB panel also
visible, that allows us to alter routing parameters. TAB pauses shows all Net/DP/XS/XSC
8
lengths as a table, but we have to select the drop-down menu for Optimizer, then follow instructions. It swaps nets automatically.
object type first, and we have to complete the last trace edit for it Finally, we run Design> Update Schematic, then Validate,
to update. The CM also shows XS lengths. Execute, Close. If it fails with an error, then we find the “Remove
Pins From Nets” and “Add Pins to Nets” sections, take a
screenshot, paste into Paint, as our manual swap list, then manually
swap net labels or off-sheet connectors in the schematic, then save
SCH, go back to PCB and Design> Import Changes.
Backdrilling control is achieved by creating a CM> AllRules
> HighSpeed > Maximum Via Stub Length rule, define stub
length and net class, board side, backdrill oversize (each side of the
via barrel). The maximum value means any stub longer than that
will be backdrilled. The constraint is set slightly longer than what
we write in the fab notes. Up to 64Gbps we don’t backdrill from
bottom to L(N-2) routes, that results in a 2-layer deep stub
For long 8Gig+ SERDES signals, we use wavy routing and
(6…16mil), so we set the constraint slightly longer than that. We
odd-angle routing, to mitigate fiber weave effect. In Altium this is
have to avoid over drilling press-fit connector pins into their MBL
achieved by pressing TAB while routing, and selecting the 3rd
region, by using a room or custom query (‘IsPin’) and a longer stub
corner style on the Properties tab. SERDES links at 8Gbps+ should
value (MBL minus depth). The start/stop layers are defined by
use the curved corners (5th style) when possible. Switch between
adding a backdrill pair in the Design> Layer Stack Manager,
curved for short and angled for long segments. Curved corners also
upper right drop down menu select "backdrills", a new tab
enable snake fanout under offset-grid hex-BGAs.
appears. On the backdrills tab add several BD layer pairs (from
bottom or top to one layer away the routing MNC layer). We also
need to take care of large antipads on planes, and route keepouts
For low-cost and aerospace boards teardrops are used, that we on signal layers, around backdrilled vias, as described in the section
enable: Tools> Teardrops. about voids. We get a separate NC drill file for each depth.
Pin swapping might be required on many designs, if a parallel The Rules&Violations panel lists all the DRC violations. We
bus seems un-routable due to connection-line (ratsnest) crossings. can browse by category/rule/violation and click to highlight. We
With hard chips like CPUs the datasheet might tell us which pins can also see them on the PCB panel in red, or in the CM.
can be swapped with which (within groups), while with FPGAs we
can likely swap most signals (maybe except the diffpairs that must
be on diff capable pin pairs), if we also update the FPGA pinout
7. Signal Integrity
file. In Altium, once we are done with the escape routes and some To ensure good signal integrity, we utilize
long distance routes from both ends, then we can set up swapping. high-speed design techniques, as explained in
the book titled “Complex Digital Hardware
Design”. It also provides guidance about
architecture, debugging, constraints, timing-
based trace length calculations, trace
impedance control, crosstalk control, ground
 returns, stackup design, materials, backdrilling, via impedance
optimization, loss budgets and insertion loss control techniques.
Most SI simulations should be done in proper external tools,
for example pre-layout and decoupling in Keysight ADS, or post
layout in Hyperlynx, HFSS or Simbeor.
Power plane DC voltage drop can be simulated with the
Altium's built-in Power Analyzer by Keysight, that requires a
downloadable add-on install with a separate license. Run: Tools>
Visual Power Analyzer. It has an automated setup.
For differential SERDES links operating at 8Gbps/lane or
above we need to ensure that the impedance of the via structures
also comply to the impedance requirement. We do this by
Steps: Set the swap behavior to move net labels not pins: recreating the via structure in HFSS or Simbeor, optimize the
Project> Project Options> Options> Adding Rem Net Labels structure dimensions (via-to-via spacing, via diameter, and
= on, while Change Sch Pins = off. In the design, select the manual void shape/size), then adjusting them in simulation, then
component, then on the Properties panel> Swapping Options> replicating the structure in Altium layout to match the dimensions.
Enable Pin Swapping. Next, on the same component Rightclick
> Component Actions > Configure Pin/Part Swapping then
upper tab PinSwapping or DiffPair swapping, then find/select
multiple nets. Then on the selection list rightclick> Assign PS
Group> New. A number appears in the PinGroup column. OK to
close. Next is Tools> Pin/Part Swapping> Automatic Pin/Net 
9
 match them lane to lane using interactive DP length tuning. We can
8. Typical Examples monitor our progress on the PCB panel. Finally, we run the DRC,
These examples are based on the CM-flow, not the DRE-flow. and check the rules and violations panel to see what is left.
We also need to set up backdrilling. In the Layer Stack
8.1. PCIe Gen4 SERDES bus design Manager, we define all BD depths. Then we define the max stub
length on the DPCs at: CM> AllRules> HighSpeed>
The lane-to-lane matching groups, or diffpair class (DPC) setup BackDrilling. Any BD at the press-fit connector pins must be
depends on the architecture. If we have an AC-cap then it creates
limited, as to not cut into the minimum barrel length of the
a short segment between
connector.
the chip and the cap, and
a long segment between
the cap and the other chip. We should add a net name on both sides 8.2. DDR4 Memory-Down design
of the cap in the schematic. The „Memory-Down” is the design technique where we design
If we had a DC coupled Hyper Transport bus, then one DPC a complete DIMM memory on to the motherboard, so we don’t
would be enough. If our PCIe link is between two chips on the same need to use DIMM sockets, all the memory chips will be soldered
board, then we have AC-caps on both RX and TX signals on our down. The design rules come from CPU design guide documents.
board. So, we would need 2 DPCs, one class for the long segments We have to create objects for the address bus signals: A net
including both TX and RX signals, and the other class is for the class for trace width rules, xSignals for each CPU-to-DRAMn
short segments. If we are designing a PCIe link that passes through component pair on every address bus signal, one XSC (match 5mil)
a connector (a motherboard, add-in card or backplane system), then for each CPU-to-DRAMn component pair (containing address and
our constraints will only be created for the segments that exist on clock XS). Then we enter the width data for the net class in CM,
one board. This case we likely have an AC cap only on TX or on and match-length data for each XSC. If we had 25 signals and 4
RX signals on our board, and now we have 3 types of diffpairs DRAM chips, then we will have 4*25=100 xSignals and 4 XSCs.
(short to cap, long from cap, very long no-cap), so we need 3 DPCs. The clock needs diffpairs created, and a DP class for trace
width/impedance and diffpair parameters. We have to create
xSignals for the clocks too, while we are creating them for address
bus. These xSignals will go into the XSCs of the address bus.
The data bus: Since we have DQS diffpairs and DQ SE signals
We also need to calculate an insertion loss budget at the Gen4 in one matched group, we have to create xSignals for every signal,
16Gbps speed. We have a budget of 25dB@8GHz. If our PCIe link and XSCs (match 5mil) for every lane for matching, and use net
is on one board, then we have the whole 25dB available, but if it classes only for impedance, otherwise we would have two different
goes through a connector, then we only have a portion, budgeted width rules on DQS. We will need one net class for DQ width and
between 2 boards. Let’s assume we have 70% available for the one DP class for DQS width. We will need as many XSCs as the
motherboard, that means 25dB*0.7=17.5dB. We have to obtain a number of data byte lanes (containing DQ and DQS XS).
fabricator and material related dB/inch loss data from our SI team
or fab vendor, let’s say we got 2dB/inch@8GHz. With 17.5dB
budget and 2dB/inch we can have our max trace length
17.5dB/2=8.75”. On our motherboard we have 3 DPCs, the longest
one can have 8.75” max set in CM> AllRules> HighSpeed>
Length, while the other 2 DPCs have to share that 8.75”, so one
would have let’s say 3” max and the other 8.75-3=5.75” max.
The diffpairs need setting up. We create the diffpairs in the
CM> Physical, then the diffpair classes in Design> Classes.
Every separate refdes-to-refdes interface is a separate class. The
impedance-driven width is in CM>Physical (set on diffpair class).
The _P/_N phase tolerance matching is typically 5mils, that we set
in CM> Electrical> Diffpairs on the diffpair class. We also set up
a constraint for crosstalk control on all PCIe signals with CM>
AllRules> HighSpeed> Parallel Segment. For any reference
clocks, we only need diffpair rules, phase tolerance matching and
DP class trace width rules.
Embedded clock interfaces (like PCIe or HDMI) usually have
De-Skew circuits built-in, so they only need loose lane-to-lane
matching, maybe within 2 inches. Clock forwarding interfaces
(e.g., Hyper Transport 1.0 or XGMII) do tight matching between
diffpairs, maybe within 5 mils. We apply this in CM> AllRules>
HighSp> Matched Length, on each DPC separately.
During routing, we route all diffpairs using interactive DP
routing loosely. Then we match the phase tolerance within each
diffpair by twisting first then single ended tuning. After this we
10