PAE2248 System-on-Chip Design

UI-SoC Design Issues

L5: SoC Design Flow

Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept
 Lesson Plan
Sl. No. of
Lecture
No Hours
L1 Architecture of the SoC 1
L2 Design Issues of SoC 1

Hardware-Software Codesign - Codesign Flow &

L3 2
Codesign Tools

L4 Core Libraries, EDA tools, Web Pointers 1

L5 SoC Design Flow 1
L6 General Guidelines for Design Reuse 1
L7 On Chip Buses – Clock Distribution 1
L8 Physical Design and Deliverable Models 1
 Lecture 5
• SoC Design Flow
 Session Objectives
• To learn the SoC Design Flow
 Session Outcomes
• At the end of this lecture, the students will
be able to know about
– SoC Design Flow
Design Methodology: Logic Cores
• To maintain productivity levels when dealing with
ever-increasing design complexity, design-for-reuse is
an absolute necessity.
• In cores and SoC designs, design-for-reuse also helps
keep the design time within reasonable bounds.
• Design-for-reuse requires good functional
documentation, good coding practices, carefully
designed verification environments, thorough test
suites, and robust and versatile EDA tool scripts.
• Hard cores also require an effective porting
mechanism across various technology libraries.
• A core and its verification testbench targeted for a
single HDL language and a single simulator are
generally not portable across the technologies and
design environments.
Design Methodology: Logic Cores
• A reusable core implies availability of verifiably
different simulation models and test suites in several
major HDLs, such as Verilog and VHDL.
• Reusable cores must have stand-alone verification
testbenches that are complete and can be simulated
independently.
• Much of the difficulty surrounding the reuse of cores
is also due to inadequate description of the core, poor
or even nonexistent documentation.
• Particularly in the case of hard cores, a detailed
description is required of the design environment in
which the core was developed as well as a description
of the simulation models.
Design Methodology: Logic Cores
• Because a core provider cannot develop simulation
models for all imaginable uses, many times SoC
designers are required to develop their own
simulation models of the core.
• Without proper documentation, this is a daunting task
with a high probability of incomplete or erroneous
functionality.
 SoC Design Flow
• SoC designs require an unconventional design
methodology because pure top-down or bottom-up
design methodologies are not suitable for cores as
well as SoC.
• The primary reason is that during the design phase of
a core, all of its possible uses cannot be conceived.
• A pure top-down design methodology is suitable when
the environment in which the core will be used is
known a priori and that knowledge is used in
developing the functional specifications.
• The SoC design methodology is a combination of
bottom-up and top-down philosophies that look like
an interlaced model based on hardware software
codevelopment while simultaneously considering
physical design and performance.
 SoC Design Flow

Figure 1.11 Interlaced horizontal/vertical codevelopment

design methodology
 SoC Design Flow
• This design methodology is considerably different
than the traditional ASIC design philosophy in which
design tasks are done in sequential order.
• Such design flow is described in a horizontal/vertical
model as shown in figure 1.11.
• In this design flow, although the architectural design is based
on hardware software codevelopment, the VLSI design
requires simultaneous analysis and optimization of area,
performance, power, noise, test, technology constraints,
interconnect, wire loading, electromigration, and packaging
constraints.
• Because SoC may also contain embedded software,
the design methodology also requires that the both
hardware and software be developed concurrently to
ensure correct functionality.
 SoC Design Flow
• Hardware software codesign was briefly illustrated in
figure 1.9.
• The first part in this design process consists of
recursive development and verification of a set of
specifications until it is detailed enough to allow RTL
implementation.
• This phase also requires that any exceptions, corner
cases, limitations, and so on be documented and
shared with everyone directly involved in the project.
• The specifications should be independent of the
implementation method.
• There are two possible ways to develop specifications:
• Formal specifications
• Simulatable specifications
 SoC Design Flow
• Formal specifications can be used to compare the
implementation at various levels to determine the
correctness from one abstraction level to another,
such as using equivalence and property checking.
• A few formal specification languages such as VSPEC
have been developed to help in specifying functional
behavior, timing, power consumption, switching
characteristics, area constraints, and other
parameters.
• However, these languages are still in their infancy and
robust commercial tools for formal specifications are
not yet available.
 SoC Design Flow
• Nowadays, simulatable specifications are most widely
used.
• Simulatable specifications describe the functional
behavior of the design in an abstract form and do not
provide a direct link from high-level specs to the RT
level.
• Simulatable specifications are basically executable
software models written in C, C++, or SDL, while the
hardware is specified in Verilog or VHDL.
 Review Questions
1. What is SoC design flow?
2. What are the processes involved in
SoC design?
3. What is SoC design in VLSI?
4. What are the five big issues for SoC
design?
 Session Summary
• In this lecture, we have discussed about
– SoC Design Flow
 Text Books & References
1. Rochit Rajsuman, “System-on-a-chip: Design and
Test”, Advantest America R & D Centre, 2000.
2. Hubert Kaeslin, “Digital Integrated Circuit Design: From
VLSI Architectures to CMOS Fabrication”, Cambridge
University Press, 2008.
3. B. Al Hashimi, “System on chip-Next generation
electronics”, The IET, 2006.
4. P Mishra and N Dutt, “Processor Description Languages”,
Morgan Kaufmann, 2008.
5. Michael J. Flynn and Wayne Luk, “Computer System
Design: System-on-Chip”, Wiley, 2011.
Thank You