Ministry of higher education and

scientific research

Course: Computer Architectre 2

Dr. Tayeb Benzenati, Ph.D
University of Boumerdes, Faculty of Science,
Dep. of Computer Science,
last updated: September 28, 2024

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 Chapter 6:
Cache Memroy

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 What is a Cache Memory ?

• The processor speed is significantly higher

than that of main memory.
• It is imperative to find solutions that reduce the
access time (to data and instructions).
• Cache memory offers a reliable solution that
helps bridge the gap between the two
components (CPU and main memory).
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 Definition of the Cache Memory
• The cache is a memory placed between
the main memory and a processor or a
peripheral, often built using SRAM.
• It is used to store the data and
instructions that the CPU needs
immediately.

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 The operation principle
• During a read operation, the CPU sends the requested address
simultaneously to both the cache memory and the main memory
(MC).
1. First case: The address is found in the cache memory
The CPU retrieves the data and resumes execution.
2. Second case: The address is not found in the cache memory
The information is fetched from the main memory and
simultaneously delivered to both the CPU and the cache memory.
• If the CPU later needs the same information, it retrieves the
requested data directly from the cache memory, significantly
reducing access time.

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 The operation principle (2)
• The cache checks the availability of the requested information.
If it has the data, it transmits it to the requesting component—
this is called a cache hit.
• If the data is not available in the cache, this is referred to as a
cache miss. In this case:
• The required data is fetched from the main memory (MC).
• The data is then copied to the cache memory.
• Adjacent data is also copied to the cache, anticipating future access.
• The hit ratio is the probability of finding the requested data in
the cache memory.

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 The operation principle (3)
• When discussing memory access speed,
it is important to differentiate between
latency and bandwidth:
• Latency: The delay in completing an
operation, i.e., the time that elapses
between requesting the data and the
arrival of the first piece of data.
• Bandwidth: The maximum amount of
data that can be transferred within a
given period of time.

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 Levels of the cache memory
• Generally, the L1 cache is integrated into the same chip as the
microprocessor, often embedded directly within the CPU
architecture.
▪ Example: 64KB per core for Intel i7 processors, divided into two parts: one
for data and one for instructions.
• The L2 and L3 caches are usually located outside the
microprocessor:
• L2 cache is larger than the L1 cache (ranging from 256KB to 2MB).
• It is slower than the L1 cache but still about 10 times faster than
main memory.
• Increasingly, instructions and data are separated in both L2 and, in
some cases, L3 level caches.

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Levels of the cache memory

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 Spatial and temporal localities
• The principle of spatial locality suggests that accessing data
at address X is likely to be followed by access to data in a
nearby region.
• The principle of temporal locality means that once a memory
location is accessed, it is highly probable that it will be
accessed again soon after.

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 Access modes to cache memory
• The CPU can access information using its address in the case of
main memory (MC) or cache memory.
• A calculation must be performed to locate the position of the
information in the cache memory—this process is called mapping.
• The calculation varies depending on the method used to establish
the association between the main memory and the cache memory:
1. Fully associative cache (fr : cache purement associative)
2. Direct-mapped cache (fr : cache à accès direct)
3. Set-associative cache (fr : cache associative par bloc

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 Fully associative cache
• In this type, there is no direct relationship between the address
in main memory (MC) and the address in the cache memory.
• The information can be stored at any address in the cache
memory.
• The controller performs the address conversion using an
index table.
• The table is stored in associative memory, where each entry is
characterized by two fields:
• Field 1: Contains the word address in the main memory (MC).
• Field 2: Stores the word address in the cache memory.

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 Fully associative cache
@ MC @ Cache 0000 Information 3
000 Information 1
FFF0 000
F000 001 001 Information 2 F000 Information 2
.
. Information 1
. FFF0
Information 3
0000 009 009
… …

Index Table
 Advantages and limitations

Avantageous :
☺ These caches offer a very high hit
rate and excellent performance.
☺ Flexibility of use (information can
be stored in any location).

Weaknesses:
• High cost
• Implementation complexity
(requires associative memory).

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 Direct-mapped cache
• In this type, the main memory (MC) is divided into blocks
(pages) of the same size as the cache memory.
• One-to-One Mapping : Each location in the main memory is
mapped to one and only one location in the cache memory.
• The address in this case is divided into two parts:
• Block number (higher order bits)
• Word address within the block (low order bits).

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 Mapping process
• The block number is used to calculate the corresponding
cache line (via a modulo operation with the number of cache
lines).
Exemple : Assuming the cache’s size equals to 4 (4 lines) and
we are looking for the @ 5
5 mod 4 = 1 (which corresponds to the second block)
If the block exists : cache hit
Otherwise, it results in a cache miss,

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 Direct-mapped cache 0 000 Info.0.0 Bloc 0
Info.0.1
Bloc @ of word within Info.0.2
number the bloc
…
1 002 0 111 Info.0.k
Cache
Index Memory
1 000 Info.1.0
000 0 Info.0.0 1 001 Info.1.1
001 2 Info.2.1 1 002 Info.1.2
…
Bloc 1
002 2 Info.2.2
1 111 Info.1.k
… …
111 ? Info.X.k 2 000 Info.2.0
Comparaison
2 001 Info.2.1 Bloc 2
2 002 Info.2.2 .
presence bit … .
@ du mot Index of the bloc 17.
Dans le bloc 2 111 Info.2.k
 Advantages and weaknesses

Advantages:
• Greater flexibility Weaknesses:
• Simplicity • Requires more space (high cost)
• Efficient cache • Increased complexity
memory management

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 Set-associative cache
• This type is a compromise between the first and second types of cache.
• The cache memory is divided into blocks of the same size as those in the
main memory (MC).
• The difference is that the information from MC can be placed in any block
of the cache memory.
• The word must be stored at the corresponding location within the block of
MC (placement within the block).
• The controller has as many options for loading the word as there are blocks
in the cache memory (n blocks => n options).
Example: The word at address 0 of a block can be placed in the first position
of either block 0 or block 1 of the cache, etc.

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 Set-associative cache 0 000 Info.0.0
Info.0.1
Block 0

@ du mot Info.0.2
N° Bloc dans le bloc
…
1 001 Cache Memory
0 111 Info.0.k
Index
000 0 Info.0.0 1 000 Info.1.0
1 001 Info.1.1
001 1 Info.1.1
1 002 Info.1.2
111 … … Block 1
…
000 2 Info.2.0 1 111 Info.1.k

001 2 Info.2.1
2 000 Info.2.0
111 … … 2 001 Info.2.1 Block 2
Comparaison
2 002 Info.2.2 .
@ of the …
presence bit
word in the N° of bloc 2 111 Info.2.k 20
cahe
 Advantages and weaknesses

Advantages:
• Greater flexibility
• Simplicity
• Efficient cache memory
management Weaknesses:
• Requires more space (high cost)
• Increased complexity

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The end

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