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16 Ways To Fix Setup and Hold Time Violations

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45 views5 pages

16 Ways To Fix Setup and Hold Time Violations

Uploaded by

Heekwan Son
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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16 Ways To Fix Setup and Hold Time Violations

edn.com/ways-to-solve-the-setup-and-hold-time-violation-in-digital-logic/

December 8, 2021

What is a Setup and Hold Time Violation?


Typically, a production chip consists of several million flip-flops and billions of transistors.
All these flops must strictly adhere to a couple of timing requirements called setup and
hold time requirements. If any one of these flops fails to meet the setup and hold
requirement, then the flop enters a metastable condition that propagates through the
entire chip, making the chip useless.

In the chip manufacturing process, these timing criteria are not met on the first try. After
several interactive back-end flow runs, the timing requirement is successfully met, and
only then, the chip is taped out. In this article, we will discuss the methods that are used
in back-end flow to solve setup and hold time violations.

In basic data path logic, the data from the launch flop is sampled by capture flop in the
next clock edge. Hence, the setup time check occurs in the next active clock edge while
the hold time check occurs in the same clock edge.

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A detailed description of the setup and hold time requirement along with equations and
waveform can be found in the article titled “Setup and Hold Time Equations and
Formulas”.

Best ways to avoid and fix setup time violations


The fundamental idea behind solving setup violation is to make the data path logic
quicker. If that doesn’t work, then making the clock path logic slower will also help solve
the timing problem.

1. Improve the setup time constraint of the capture flip-flop


For any technology node, there will be several libraries that are provided by the
fabrication vendor. These libraries have different processes, voltages, and temperature
settings and hence they all have different timing requirements. So, the setup and hold
time requirements are different for different types of flops available in the library. When
there is a setup time violation on any path in design, the capture flop can be replaced with
a flop that has a small setup time window so that the path can accommodate large data
path delay.

2. Improve the drive strength of data path logic

The output capacitance of gate charges and discharges for the on and off operation of the
transistor. Charging operation can be quicker if a flop with increased drive strength is
used. This ultimately makes the data path logic quicker and hence eases the setup time
requirement on capture flop.

3. Reduce the clock-q to delay launch flop

Same as setup time number, the clock-q delay depends on the kind of flop and on the
library that is used. So, different flops will have a different clock-q delay. Since setup time
violation can be solved by decreasing the data path logic delay, using a flop with a smaller
clock-q delay for launch flip-flop will ease timing requirement.

4. Using a faster cell for launch flip-flop

Flip-flop comes with various threshold voltage (VT). Some flip-flops have less threshold
voltage while some have higher threshold voltage. These flops are categorized as LVT
(Low VT), SVT (Standard VT), and HVT (High VT). Using an LVT flop for launch flip-flop
will result in less time for turning on and turning off of transistors inside the flip-flop that
will ultimately result in faster data path logic. Other slow data path cells can also be
substituted with a faster counterpart to decrease the data path delay. Hence, substituting
an LVT cell instead of SVT or HVT can solve setup time violation.

5. Decreasing the logic delay

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Another way to reduce logic delay apart from replacing SVT and HVT cells with LVT is to
change the logic in register transfer level (RTL). This will most of the time result in
increased latency, resources, and power consumption but will ease timing requirement
and solves setup time violation.

6. Reducing long routing wire

In an ASIC, there will be different blocks scattered across the chip. For example, floor
planning is done in such a way that memories are nearer to the power source—near the
pad—and processors are placed in the center of the chip. In place and route phase, care
should be taken to avoid long wire connections between different flops from different
blocks. Long wire increases logic delay while a short direct connection will ease the
timing requirement.

7. Increasing the clock latency on capture flop


Any toggling of net from launch flop should be sampled by the capture flop in the next
active edge of the clock. It will ensure no data is lost. So, setup time check will occur in
the next active edge of the clock when the capture flop is sampling the change in the net.
Because of uneven buffers and inverters in the clock path, there will be a difference in
ideal clock position and actual clock position. This difference is referred to as skew. If
there is more skew on the clock path to capture flop, then the setup time check is delayed
until the clock reaches the capture flop. It will ease timing requirement and help solve
setup time violation on certain paths.

8. Increasing the clock period

All the approaches discussed till now are optimizations that will be done in the chip
developmental phase. When the chip is already taped out, these optimizations are
impossible to be done. Under such circumstances, as a last resort, the operating
frequency can be reduced by increasing the clock period. It will delay the setup time
check and will give sufficient time for data to settle to a stable value before the setup
check.

Best ways to avoid and fix hold time violations


The fundamental rule to solve hold time violation is to ensure slower data path logic than
clock path logic. In other words, data should change after the active edge of the clock
where the hold time check occurs.

1. Improving the hold time constraint of launch flip-flop

As discussed previously, different types of flip-flops are available based on different


library parameters. These flip-flops have different hold time requirement that needs to be
fulfilled. Using a flop with less hold time requirement as launch flop will ease timing
requirement and will help solve hold time violation when there is a large skew on launch
flop.

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2. Decrease the drive strength of data path logic
By decreasing the drive strength of cells found in the data path, we can slow the data
path signal to capture flop. It’s because the output gate capacitance will take a long time
to charge and discharge. It will help solve any hold violations.

3. Increase the clock-q delay of launch flip-flop


Similar to the previous fix, by choosing a flop that has more clock-q delay, delay can be
induced in data path logic. It will ease timing and help solve hold time violations.

4. Use a slower cell for launch flip-flop


As discussed previously, there will be different corners of library available for
implementation and they are typically grouped under LVT, SVT, and HVT. By substituting
LVT and SVT launch flop with an HVT one, we can introduce delay in signal connected to
capture flop. The higher threshold voltage will ensure delay to turn on and turn off
compared to a low threshold or typical threshold.

5. Increasing logic delay


Additional logic such as buffers can be added to data path logic to increase the delay on
data path logic. It will make the data path slower than the clock path and will help with
solving hold time violation.

6. Add long routing path


Re-routing data path to make the connection long between launch flop and capture flop
will increase wire delay, thus increasing delay in data path logic.

7. Reduce the clock latency on launch flip-flop

As discussed previously, skew plays a major role in the gap between the ideal clock edge
and actual clock edge. Increased skew on launch flop gives the data less time to settle to
a stable value before the active edge of the clock. Hence, keeping skew to a value as low
as possible is necessary to reduce the number of hold time violations.

8. Reduce operating voltage


After tape-out, if there is a setup time violation, it can be solved by reducing the operating
frequency. The same cannot be done for hold time violations, and hence at most,
precautions should be taken to avoid hold time violations. It’s done by running simulations
for worst-case scenarios using fast corner libraries and higher threshold voltage. Despite
all this, if a hold time violation is discovered after tape-out, it can sometimes be fixed by
reducing the supply voltage.

Following the steps outlined in this article will help solve setup and hold time violation and
will ensure no metastability propagation occurs inside the design.

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Deekshith Krishnegowda works as a digital IC design engineer at Marvell Technology Inc.
in Santa Clara, California.

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