Addressing Modes_all
Addressing Modes_all
The most common names for addressing modes (names may differ among architectures)
Addressing modes Example Instruction Meaning When used
Register Add R4,R3 R4 <- R4 + R3 When a value is in a register
Immediate Add R4, #3 R4 <- R4 + 3 For constants
Displacement Add R4, 100(R1) R4 <- R4 + M[100+R1] Accessing local variables
Register deffered Add R4,(R1) R4 <- R4 + M[R1] Accessing using a pointer or a computed address
Useful in array addressing:
Indexed Add R3, (R1 + R2) R3 <- R3 + M[R1+R2] R1 - base of array
R2 - index amount
Direct Add R1, (1001) R1 <- R1 + M[1001] Useful in accessing static data
Memory deferred Add R1, @(R3) R1 <- R1 + M[M[R3]] If R3 is the address of a pointer p, then mode yields *p
Useful for stepping through arrays in a loop.
Auto- R1 <- R1 +M[R2]
Add R1, (R2)+ R2 - start of array
increment R2 <- R2 + d
d - size of an element
Auto- R2 <-R2-d Same as autoincrement.
Add R1,-(R2)
decrement R1 <- R1 + M[R2] Both can also be used to implement a stack as push and pop
Scaled Add R1, 100(R2)[R3] R1<-R1+M[100+R2+R3*d] Used to index arrays. May be applied to any base addressing mode in some machines.
Notation:
<- - assignment
M - the name for memory:
M[R1] refers to contents of memory location whose address is given by the contents of R1
Immediate and displacement addressing modes dominate addressing mode usage. The major question for displacement-style addressing mode is that of the range of
displacement used. Choosing the displacement field size is important because it directly affects instruction length. According to measurements taken on the data access
on a GPR architecture using SPEC benchmarks displacement values are widely distributed.
Another important instruction set measurement is the range of values for immediates . Small immediate values are used most heavily. However, large immediates are
sometimes used, most likely in address calculations.
For small number of addressing modes or opcode/addressing mode combinations, the addressing mode can be encoded in opcode.
For a larger number of combinations, typically a separate address specifier is needed for each operand.
The architect has to balance several competing forces when encoding the instruction set: