AN50987

Getting Started with I 2C in PSoC ® 1

Author: Todd Dust and M. Ganesh Raja
Associated Project: Yes
Associated Part Family: CY8C21x23, 21x34, 21x45,
22x45,23x33, 24x23A, 24x33, 24x94, 27x43, 28xxx, 29x66
Software Version: PSoC ® Designer™5.4

AN50987 gives an overview of the I2C standard and explains how a PSoC® 1 device handles I2C communications.
After reading this application note, you should have an understanding of how I2C works, how to implement it in
PSoC 1, and how to choose the correct user module for a design. Example projects demonstrate how to configure
PSoC 1 as an I2C master/slave to communicate with other I2C devices on the bus.

Contents
Introduction ....................................................................... 2 Appendix A ...................................................................... 17
I2C Basics .......................................................................... 2 Hardware Registers.................................................... 17
The Physical Layer ....................................................... 2 Firmware Requirements ............................................. 17
The Protocol Layer ....................................................... 2 Arbitration ................................................................... 18
I2C in PSoC 1 .................................................................... 4 Appendix B ...................................................................... 20
Hardware ...................................................................... 5 EzI2Cs_ADC_LED_DAC Example Project ................. 20
I2C User Modules ......................................................... 6 I2CHW Slave Example Project ................................... 24
Firmware ........................................................................... 8 I2CHW Master Example Project ................................. 25
Slave Operation ............................................................ 8 Migrating Example Project ......................................... 26
Master Operation .......................................................... 9 Worldwide Sales and Design Support ............................. 28
Multimaster Slave Operation ...................................... 10
I2Cm ........................................................................... 11
Special I2C Considerations .............................................. 12
I2C Addressing ........................................................... 12
Pull-up Resistors ........................................................ 12
I2C and ISSP Programming Conflicts ......................... 12
Pin Glitches at Power-up ............................................ 13
Clock Speeds ............................................................. 13
Clock Stretching and Interrupt Latency ...................... 14
Hot Swapping ............................................................. 14
Glitch Filtering ............................................................ 14
I2C and Sleep ............................................................. 14
I2C and Dynamic Reconfiguration............................... 15
Dynamic Slave Addressing in I2CHW UM .................. 15
The SCL Line Gets Stuck LOW .................................. 15
Summary ......................................................................... 16

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Introduction Figure 2. Open Drain Drives LOW Pin Configuration

Vdd
Inter-integrated circuit (IIC or I2C) is a common chip-to-
chip serial communications standard developed by the
Philips semiconductor division (now NXP). I2C provides a SDA
I2C
simple way for ICs to communicate on the same printed Master 1 SCL

circuit board (PCB). I2C consists of a simple physical layer

that requires only two pins and minimal external
components. One advantage of I2C over a communication I2C I2C
standard such as SPI is that it has a built-in Slave 1 Master 2

communication protocol that allows easy, error-free I2C Slave 2

communication between devices.
Drive
The Cypress PSoC 1 device offers several choices for Line LOW

implementing I2C in a design. These choices come in the Receive

Data
form of user modules (UMs) that are found in the
PSoC Designer™ integrated development environment
(IDE). This application note first describes the basics of
I2C to help you understand how the PSoC 1 device Devices on the I2C bus have a master-slave relationship.
handles I2C. If you already have an understanding of I2C The master initiates all data transfers on the bus and
basics, skip to I2C in PSoC 1. If you are looking for help generates all clock signals. Each slave has a unique
troubleshooting your I2C design, skip to the Special I2C address; the master must first address a specific slave
Considerations section. and receive an acknowledgment before the data transfer
This application note assumes that you are familiar with can begin. Multiple masters and multiple slaves can exist
the PSoC 1 device and PSoC Designer IDE. together on the same bus. The I2C bus operates at a
variety of frequencies; typical frequencies are 100 kHz and
400 kHz. The I2C specification allows higher frequencies
I2C Basics of 1 MHz and 3.4 MHz.

The Physical Layer The I2C bus operates at different voltage levels depending
2 2 on the individual devices themselves. To determine if two
Figure 1 shows how I C devices connect to the I C bus. devices can successfully communicate, review their
The I2C bus consists of two physical lines: serial data respective datasheets to ensure that the logic levels are
(SDA) and serial clock (SCL). All devices on the bus must compatible.
connect to these two physical lines. The only external
hardware required are pull-up resistors to VDD (high rail) The I2C specification offers a solution for bridging between
on SDA and SCL. For more information, see the Pull-up buses of different voltage levels, in the event that the
Resistors section. voltage and logic levels of two devices are not compatible.

Figure 1. Typical I2C Bus The Protocol Layer

Vdd
Understanding the protocol layer of I2C is the next major
step in mastering this digital communication technique.
Each I2C transaction consists of the following elements:
I2C
SDA start (or repeated start), address, data, and stop.
Master 1 SCL
Start or Repeated Start
The master device controls the clock line and therefore
initiates all communication on the bus. To gain control of
I2C I2C I2C the bus and initiate a transaction, the master first sends a
Slave 1 Slave 2 Master 2
start condition; see Figure 3.
A start condition signals to every device on the bus that a
master has taken control and is ready to send an address.
SDA and SCL are bidirectional; the master can The bus is considered busy, so other masters must wait
communicate data to the slave and vice versa. SDA and for the bus to be freed by a stop condition to initiate a
SCL have an open-drain drive mode and drive LOW. A transfer.
device can drive the line to a logic LOW, or it can be high-
impedance. Therefore, no device can drive the lines Start = HIGH to LOW transition on SDA when SCL is
HIGH. This configuration prevents power-to-ground shorts HIGH
on the bus; see Figure 2. The pull-up resistors on SDA
and SCL produce a HIGH logic level.

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Figure 3. Start Condition Figure 5. 10-Bit Address

Start S 11110XX R/W A/N XXXXXXXX A/N

SDA 2 MSBs of Address Remaining 8 bits

SCL Data
After the master has sent the address and the slave has
A repeated start condition is physically identical to a start acknowledged it, data can be transferred eight bits at a
condition. It gives a signal that the master has maintained time. Both the master and the slave can transmit and
control of the bus and that the bus is not free. receive, so together they control the SDA line.

Ad d r e s s Data on the SDA line must be stable before the rising

edge of SCL. Data on SDA can change only when SCL is
The address is the first data byte sent by the master after
LOW; see Figure 6.
the start condition. Each slave device has a unique
address. Most I2C addresses are seven bits long. A Figure 6. SDA Data Change
read/write (R/W) bit completes the 8-bit byte and indicates
the direction of communication for the rest of the
SDA
transaction; see Figure 4. A read signifies that the master
Stable
wants to read data from the slave. A write indicates that Data
the master wants to write data to the slave. All address SCL
Data
and data bytes are sent in the order of most significant bit Change
(MSB).
For example, if the 7-bit address is 0x20, the full 8-bit byte If the master is performing a write operation, it writes out
for a read will be 0x40; the full 8-bit byte for a write will be eight bits of data on SDA and provides eight clock cycles
0x41. on SCL. After the master sends eight bits of data, the
Figure 4. 7-Bit Address slave must send an ACK or NAK on the ninth clock cycle;
see Figure 7.
ACK
SDA D7 D1 R/W  ACK = Slave has room for more data

 NAK = Slave cannot take any more data

SCL 1 7 8 9 The alternate condition is that the master wants to read
data from the slave. In this case, the master provides the
eight clock cycles but the slave transmits eight data bits on
SDA. After the eight data bits are transferred, the master
AC K / N AK must send the ACK or NAK.
After the master transmits the address, it waits for an
acknowledgment (ACK) from the slave. The ACK is an  ACK = Master wants to read more data
additional status bit at the end of each data byte; thus,
each I2C transaction is nine bits long.  NAK = Master is done reading
Note The slave does not have a way to inform the master
Each slave on the bus is responsible for reading the that it has no data to send.
incoming address and comparing it with its own internal
address. If the address matches, the slave must send out Figure 7. Eight Data Bits Followed by an ACK Bit
an ACK on the ninth clock cycle. If the address does not
match, the slave does not acknowledge (NAK). ACK
SDA D7 D1 D0
 ACK = 0 (LOW logic level)

 NAK = 1 (HIGH logic level) SCL 1 7 8 9

1 0 - B i t Ad d r e s s
The I2C specification also allows for 10-bit addressing; see Stop
Figure 5. To accomplish this, the master must send two After all bytes are sent, the master sends a stop condition.
address bytes to the slave. The first byte, which the slave A stop indicates that the current transaction is complete
must acknowledge, contains the sequence 11110 followed and the bus is free; see Figure 8.
by the two MSBs of the address followed by the R/W bit.
Stop = LOW to HIGH transition on SDA when SCL is
Next, the master sends the remaining eight bits of the
HIGH
address. Finally, the slave sends an ACK/NAK.

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Figure 8. Stop Condition stop driving the SDA line and must wait until the bus is
free before sending data again.
Stop As Figure 10 shows, the first master that leaves SDA
HIGH while another tries to drive it LOW loses arbitration
SDA and must wait.

Figure 10. Arbitration

SCL
SCL
Lost Arbitration
The master can send a repeated start condition instead of Device
1 0 Stops Driving
a stop. A repeated start condition is physically the same #1 SDA
SDA
as a start. The repeated start allows the master to
Device
maintain control of the bus when it wants to address a 1 0 0 1
#2 SDA
slave device to start a new transaction or change the
direction of data flow. SDA of
1 0 0 1
Bus
A repeated start is needed when a master wants to write
data to a specific slave and then turn around and read For more information on I2C and its protocol, see the I2C
data from that same slave. Using a repeated start allows Specification from Philips (NXP).
the master to maintain control of the bus. If the master
uses a stop, other masters on the bus can gain control. I2C in PSoC 1
P u t t i n g I t Al l T o g e t h e r In PSoC 1, a dedicated I2C hardware block handles I2C
Figure 9 shows a complete transaction for a master read transactions, removing much of the processing burden
of two bytes and a master write of two bytes. It also shows from the CPU and freeing the CPU for important real-time
a repeated start that first writes two bytes and then reads tasks. The basic structure of the block is similar for most
two bytes. PSoC 1 devices; see Table 1 for differences among the
part families.
Figure 9. Complete Transaction
Table 1. I2C Hardware Block Differences
Master Read 2
S Address R A Data A Data N P Device Master Slave HW Addr Two I C
Match Blocks
Master Write
S Address W A Data A Data N P 20x34 No Yes No No
20xx6A No Yes Yes No
Repeated Start Example:
Master Write Followed by Master Read 21x23 Yes Yes No No
S Address W A Data A Data A S
21x34 Yes Yes No No
22xxx/21x45 Yes Yes No No
Address R A Data A Data N P
23x33 Yes Yes No No
24x23A Yes Yes No No
S = Start Master to Slave
W = Write 24x94 Yes Yes No No
R = Read
Slave to Master 27x43 Yes Yes No No
A = ACK
N = NAK
28xxx Yes Yes Yes Yes
P = Stop
Address = 7-bit Slave Address 29x66 Yes Yes No No

Ar b i t r a t i o n
The I2C protocol allows multiple masters to communicate
on the same bus. Both masters may start communicating
at the same time. To prevent loss of data, each I2C master
2
must check the I C bus to ensure that the data on the bus
matches what it intended to put on the bus. If the data
does not match, the I2C master that loses arbitration must

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Hardware Table 2. Byte Complete Interrupt

As Figure 11 shows, the hardware block allows Ports 1.5, Mode Master Slave
1.0, 1.7, and 1.1 to connect to the I2C bus. Cypress
2
recommends avoiding Ports 1.1 and 1.0 for I C; these Transmitter After 8 bits of data After 8 bits of data
lines are used for programming. + ACK/NAK

Figure 11. I2C Hardware Block Receiver After 8 bits of data After 8 bits of data
+ ACK/NAK
SDA_OUT SDO SDA
SDA_IN SDI
GPIO Port1[5] For more information on the functionality of the I2C
SDE
or
Port1[0]
hardware block, see Appendix A and the I2C sections of
I2CBLK the PSoC Technical Reference Manual.
I2C Bus
Hardw are Blocks in CY8C28xxx
SCL_OUT SDO
Part family CY8C28xxx offers two separate I2C hardware
SCL
SCL_IN SDI
GPIO Port1[7]
or
blocks, allowing hardware connections to more than one
I2CEN SDE Port1[1] I2C bus at a time. In addition, each block provides
hardware address matching. The hardware interrupts the
The hardware block is a simple block that handles all of CPU only on an address match. However, it does not
the status and timing requirements of the I2C transaction. wake PSoC 1 out of a sleep state. After the address, the
This block generates the I2C clock when it is in master hardware interrupts the CPU according to the conditions in
mode. It also shifts I2C data in and out of PSoC 1 and Table 2.
reports the status of I2C transactions and errors. Each of the hardware blocks in part family CY8C28xxx
Interrupts and Transaction Queuing allows for additional I2C pin connections either on Ports
1.2 and 1.6 or on Ports 3.0 and 3.2.
The block is capable of receiving or transmitting only one
byte of data at a time. At each byte boundary, the block Having two I2C hardware blocks allows for many powerful
will generate an interrupt. The CPU must service the applications. Table 3 lists some of the unique applications
interrupt and provide more data to the block, or it must that can be achieved.
read the data that the block received. The CPU need not
service the block immediately, because the block holds Table 3. Two I2C Configurations with Common Use Cases
the SCL LOW until the CPU releases it; this process is
Configuration Common Uses
referred to as clock stretching. For more information, see
the Clock Stretching and Interrupt Latency section. 2
Two I C slaves
2
Multi-I C bus systems
2
The block is capable of queuing only one transaction at a I C shared memory device
time. Multiple starts cannot be queued in the block. 2 2
One I C slave, one I C
2
I C bus switch
Therefore, user code must ensure that the current I2C master or multimaster 2
I C hot-swap controller
transaction is complete before another transaction can be 2
I C buffer
initiated.
Debugging
The block automatically detects and reports arbitration 2
conditions in multimaster environments. In the case of an Two I C masters or Increase bandwidth
multimasters
arbitration event, the block reports to the CPU that it has
lost arbitration. User code checks to see if arbitration has
been lost. If so, then the code retries the transfer.
The I2C hardware block will generate an interrupt on three
conditions: a bus error, a stop, or a byte complete.
Bus errors occur when there is a misplaced start or stop
on the bus. When this occurs, all devices on the bus must
stop their current transfer and return to an idle state.
If enabled, the stop interrupt occurs every time there is a
stop condition on the bus.
The byte complete interrupt is triggered at different points
depending on the direction of data flow; see Table 2. This
table applies for both address and data transfers.

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I2C User Modules This UM is best suited for situations when PSoC needs to
2 stream data continuously to a master device and when
Cypress provides a set of preconfigured and precoded I C
you want to write minimal I2C code. For example, the UM
user modules (UMs), located in PSoC Designer in the UM
is popular in CapSense® applications. PSoC reads the
Catalog; see Figure 12.
state of CapSense buttons and the master device
Figure 12. I2C UMs in PSoC Designer communicates continuously with PSoC to see if a button
has been pressed. In this situation, expose the CapSense
variables to the EzI2Cs and the master can easily read the
state of the CapSense buttons.
EzI2Cs is patterned after an I2C-based memory such as
EEPROM. It uses subaddressing to write or read to
specific data locations within the exposed I2C data
structure. For example, consider an I2C data structure that
appears as follows:
struct MyI2C_Regs {
BYTE bStat;
BYTE bCmd;
int iVolts;
char cStr[6];
When these UMs are placed in a design, you will not see } MyI2C_Regs
them appear in the chip view within PSoC Designer,
because the UMs either use the dedicated hardware block The above data will be exposed to the master with the
or are a software master. They use digital blocks only with following memory map:
the 28xxx family; in that case, the chip view shows both
I2C hardware blocks visually so you know which block you 0x00 MyI2C_Regs.bStat
have used and how many remain; see Figure 13.
0x01 MyI2C_Regs.bCmd
Figure 13. Two I2C Blocks in 28xxx
0x02 MyI2C_Regs.iVolts(MSB)
0x03 MyI2C_Regs.iVolts(LSB)
0x04 MyI2C_Regs.cStr[0]
0x05 MyI2C_Regs.cStr[1]
0x06 MyI2C_Regs.cStr[2]

I2C UMs, which include EzI2Cs and I2CHW, provide a 0x07 MyI2C_Regs.cStr[3]
level of abstraction over the I2C hardware block. This 0x08 MyI2C_Regs.cStr[4]
section briefly describes each UM and explains when it will
be needed in a design. For more information, see the 0x09 MyI2C_Regs.cStr[5]
specific UM datasheet.
EzI2Cs If the master wants to write to iVolts, it first sends the slave
address, followed by a subaddress (0x02), which indicates
Ezl2Cs operates exclusively as a slave; there is no master the offset of iVolts in the structure. To calculate the offset,
version. If a design requires master operation, use I2CHW count the number of bytes before iVolts; in this example,
or I2Cm. the subaddress is „2.‟ To extend the example, a
EzI2Cs, as the name implies, is an easy-to-implement I2C subaddress of „0‟ will write to bStat, a subaddress of „1‟ will
slave interface. It is a firmware layer on top of the I2C write to bCmd, and a subaddress of „4‟ will write to the first
hardware block. It implements many of the firmware element of the cStr array. Figure 14 shows an example of
requirements mentioned in the hardware block description a master writing data to iVolts in an EzI2Cs UM with a
found in Appendix A. slave address of 0x04.

EzI2Cs is unique; it requires minimal user knowledge of Figure 14. EzI2Cs Example: Write to iVolts
how the I2C bus works. It allows you to set up a data
Slave Addr Subaddr Data to iVolts
structure in user code and expose that structure to the I2C S 0x04 WA 0x02 A 0x55 A 0xAA A P
master. All I2C transactions happen in the background
through interrupts. You need not worry about any of the
2
I C functionality after the UM is started. The application
If the master wants to read iVolts, it first needs to address
code just needs to update the data structure with data for
the PSoC slave and write the subaddress of „2.‟ It should
the master to read and then check and process data that
then address the slave again and read out two bytes.
the master writes.

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Each subsequent read will start at iVolts until a new 6 MHz, the actual speed of the slave will be 100 kHz. See
subaddress is written. Figure 15 shows an example of a the Clock Speeds section for more details.
master reading the data in iVolts.
I2C_Pins: This parameter selects the pins used for the I2C
Figure 15. EzI2Cs Example: Read from iVolts clock and data.

Slave Addr Subaddr After the UM parameters are configured, follow these
S 0x04 WA 0x02 A P steps to make the EzI2Cs work in firmware.

Slave Addr Data from iVolts 1. Create a data structure to expose to the master. For
S 0x04 R A 0x55 A 0xAA A P example:
structMyI2C_Regs {
Let‟s take a look at how EzI2Cs can be implemented in a BYTE bStat;
project. Figure 16 shows the parameters for the project. BYTE bCmd;
Figure 16. EzI2Cs UM Parameters int iVolts;
char cStr[6];
} MyI2C_Regs

2. Start the EzI2Cs by calling the EzI2Cs_Start function.

3. Enable interrupt by calling the EzI2Cs_EnableInt
function.
4. Expose the data structure to the master by using the
EzI2Cs_RamSetBuffer function.
EzI2Cs_SetRamBuffer(sizeof(MyI2C_Regs),
Slave_Addr: This parameter sets the address of the 2, (char*)&MyI2C_Regs);
EzI2Cs slave. If the ROM_Registers parameter is
disabled, the Slave_Addr is a 7-bit address in the range 0 The first parameter sets the size of the buffer. The
to 127. If the ROM_Registers parameter is enabled, the second parameter sets the write boundary and the
Slave_Addr is a 6-bit address in the range 0 to 63. third parameter initializes the pointer to the data
structure.
Address_Type: When the address type is set to static,
the address of the EzI2Cs slave is fixed to the value set in The EzI2Cs allows defining read/write permissions on
the Slave_Addr parameter. If the address type is set to the data structure through the SetRamBuffer function.
dynamic, the address can be changed in firmware using For example, in the code given in step 1, the
the EzI2Cs_SetAddr function. This is useful in applications application sets read/write permission to bStat and
in which more than one PSoC 1 EzI2Cs slave is in a bus bCmd variables and makes all other variables read-
and the address of the slaves can be set by configuring only by setting the write boundary to „2.‟ In this case, if
GPIO pins. the master tries to write to these read-only variables,
the slave will generate a NAK and ignore the data
ROM_Registers: By enabling the ROM_Registers written by the master.
parameter, it is possible to expose data stored in a ROM
array to an I2C master. When this parameter is enabled, 5. In the main loop, keep updating the data structure
the EzI2Cs is exposed to a master with two addresses. If with process data for the master to read and keep
the master wants to access the ROM memory space, it looking for fresh data from the master.
uses a 7-bit address with the seventh bit set. To access Data coherency is an important consideration when using
the RAM memory space, it uses a 7-bit address with the the EzI2Cs UM. In the example, iVolts is a two-byte
seventh bit cleared. For example, if the Slave_Addr is set variable. It is possible that the CPU started to update this
to 0x04, the master addresses the slave with an address variable but only had time to write to one byte before the
of 0x44 to access the ROM registers and an address of I2C master read both bytes. As a result, the master read
0x04 to access the RAM registers. This is why the incorrect data. For example, suppose that the variable
Slave_Addr should be a 6-bit address when the ROM iVolts has a value of 0x01FF. The CPU would have to
registers are enabled. update this with a new value of 0x0200. The CPU writes
I2C_Clock: This parameter sets the maximum speed at 0x02 to the MSB first and 0x00 to the least significant bit
which the slave can operate. Remember that the (LSB). If the I2C read occurs just after the CPU has written
maximum speed is based on a SYSCLK of 24 MHz. If the to the MSB, but before writing to the LSB, the master will
SYSCLK is set to 6 MHz or 12 MHz (SLIMO enabled) in read 0x2FF.
the Global Resources, the maximum clock speed will To combat this, it is best to use flags or semaphores
reduce by the same factor. For example, if the I2C_Clock between the master and slave to indicate when data is
parameter is set to 400 kHz and the SYSCLK is set to ready to be read or written. The EzI2Cs datasheet gives

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more details on other ways to ensure that the data is In the master operation, three parameters are available:
coherent. Read_Buffer_Type, I2C_Clock, and I2C_Pin.
Configuration of these parameters is the same as that
This application note includes a simple project that described for the slave operation below.
demonstrates how to use the EzI2Cs UM. For details on
how to use the project, see Appendix B. Multimaster and Slave Operation: Select this option if
you need the I2CHW as a master and slave in a
For a detailed description of how this UM works and how multimaster environment.
to use it, see the EzI2Cs datasheet.
Depending on the option you select, the UM parameter
EzI2Cs Summary and Important Notes window will populate.

EzI2Cs is an easy-to-implement slave-only UM. Slave_Addr: This is the 7-bit slave address. Unlike
EzI2Cs, I2CHW does not offer dynamic addressing or
EzI2Cs exposes a register structure to a master with separate address for ROM buffers. In multimaster and
clearly defined read/write permissions. slave operation, Slave_Addr is the address of the device
when it is addressed as a slave by another master on the
When ROM registers are enabled, the slave will have
bus.
two addresses, one for RAM space (seventh bit cleared)
and one for ROM space (seventh bit set). For this Read_Buffer_Type: When you select “RAM only,” the
reason, the slave address is limited to a 6-bit value when application will set up the read buffer only in RAM. When
ROM registers are enabled. you select ”RAM or flash,” the application exposes either a
RAM buffer or a flash buffer to the master.
When dealing with multiple byte values in EzI2Cs, take
care to ensure data coherency by using flags or Communication Service Type: When you select
semaphores between the master and slave. “Interrupt,” all I2C transactions are automatically handled
inside the interrupt. When you select “Polled,” I2C
I2CHW transactions are handled only when the foreground
application calls the I2CHW_Poll function. The hardware
This UM is a firmware layer on top of the I2C hardware
keeps the I2C clock stretched until the application calls
block and implements all the firmware tasks described in
I2CHW_Poll. Cypress recommends the “Interrupt” option.
Appendix A. You can use this flexible UM as a slave, a
master, or a multimaster slave. I2C_Clock: This parameter selects the speed of the slave.
2 As explained in the clock parameter of the EzI2Cs slave,
I CHW, unlike EzI2Cs, requires more code interaction.
the speed is based on a SYSCLK of 24 MHz.
Check status bits to see if an I2C transaction occurred,
reinitialize buffers when a transaction is complete, and I2C_Pin: This parameter selects the pins for the I2C.
clear status bits. Also, check the firmware for error Options are P1[0]-P1[1] and P1[5]-P1[7] for all devices
conditions on a transaction. except for CY8C28xxx. For CY8C28xxx, P1[2]-P1[6] and
P3[0]-P3[2] options are also available.
Here‟s how to implement I2CHW in a project. When you
double-click, the I2CHW topology selection window opens.
See Figure 17. Firmware
Figure 17. I2CHW Topology Window After the topology and parameters are configured, follow
these steps to get the I2CHW working in firmware.

Slave Operation
1. Declare a read buffer in RAM (or flash) for the master
to read from. For example:
BYTE ReadBuffer[16];

The buffer can also be a structure such as:

struct ReadBuffer {
BYTE bStatus;
int iVolts;
}ReadBuffer;

Slave Operation: Select this option if you need slave 2. Declare a write buffer in RAM for the master to write
operation. to. For example:
Single Master Operation: Select this option if you need a BYTE WriteBuffer[16];
simple operation in a single master environment.
The buffer can also be a structure such as:

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struct WriteBuffer { It is important to check for the RD_COMPLETE flag

BYTE bCmd; and reinitialize the buffer. Otherwise, on further reads
int iDACCounts; from the master, the last byte from the buffer will be
}WriteBuffer; transmitted repeatedly.

3. Enable global interrupts by calling the 8. Call the function I2CHW_bReadI2CStatus and check
M8C_EnableGInt macro. for the I2CHW_WR_COMPLETE flag. If this flag is
set, it means that the master has completed a write
M8C_EnableGInt ; transaction. Process the data, clear the flag, and
reinitialize the write buffer.
It is important to enable global interrupts, because all
of the I2C operations take place in the background // Check if a write operation is over
inside the I2C ISR. if (I2CHW_bReadI2CStatus() &
I2CHW_WR_COMPLETE)
4. Call the I2CHW_Start, I2CHW_EnableSlave, and {
I2CHW_EnableInt functions to start the slave. // Process data from Master
I2CHW_Start(); // Clear the flag
I2CHW_EnableSlave(); I2CHW_ClrWrStatus();
I2CHW_EnableInt();
// Re-initialize the buffer
5. Initialize the read buffer using I2CHW_InitRamRead. I2CHW_InitWrite(WriteBuffer,
I2CHW_InitRamRead(ReadBuffer, sizeof(WriteBuffer));
sizeof(ReadBuffer)); }

This function initializes a pointer to the read buffer It is important to reinitialize the write buffer; otherwise,
and sets the size of the buffer. Whenever the master the slave will not acknowledge any further data from
tries to read from the slave, data from the buffer is the master.
transmitted to the master automatically. If the master A simple project in this application note demonstrates how
tries to read more bytes than the size of the buffer, to use I2CHW as a slave that echoes the data written by
the last byte of the buffer is transmitted repeatedly. an I2C master. For details on the project, see Appendix B.
6. Initialize the write buffer using the I2CHW_InitWrite
function. Master Operation
I2CHW_InitWrite(WriteBuffer, 1. Declare a read buffer in RAM (or flash) where data
sizeof(WriteBuffer)); read from the slave will be stored. For example:
BYTE ReadBuffer[16];
This initializes a pointer to the write buffer and the The buffer can also be a structure similar to the one
buffer size. When the master writes data to the slave, discussed in the slave operation section above.
the data is automatically deposited in the buffer. If the
master tries to write a greater number of bytes than 2. Declare a write buffer in RAM for data that will be
the buffer size, the slave will not acknowledge the written to the I2C slave. For example:
extra bytes and those extra bytes will be discarded. BYTE WriteBuffer[16];
7. Call the function I2CHW_bReadI2CStatus and check
for the I2CHW_RD_COMPLETE flag. If this flag is 3. Enable global interrupts by calling the
set, it means that the master has completed a read M8C_EnableGInt macro.
transaction. Clear the status flag and reinitialize the M8C_EnableGInt;
read buffer.
// Check if a read operation is over It is important to enable global interrupts, because all
if (I2CHW_bReadI2CStatus() of the I2C operations take place in the background
I2CHW_RD_COMPLETE) inside the I2C ISR.
{
4. Call the I2CHW_Start, I2CHW_EnableMstr, and
// Prepare fresh data for Master
I2CHW_EnableInt functions to start the master.
// Clear the flag I2CHW_Start();
I2CHW_ClrRdStatus();
I2CHW_EnableMstr();
// Re-initialize the buffer I2CHW_EnableInt();
I2CHW_InitRamRead(ReadBuffer,
sizeof(ReadBuffer)); 5. To write to a slave, use the I2CHW_bWriteBytes
} function.

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I2CHW_bWriteBytes(0x50, WriteBuffer, 16, I2CHW_Start();

I2CHW_CompleteXfer); I2CHW_EnableMstr();
I2CHW_EnableSlave();
The first parameter is the slave address; use the 7-bit I2CHW_EnableInt();
slave address. The bWriteBytes function automatically
adds the read/write bit to the 7-bit address before 3. The slave mode operation is similar to the single
transmitting the address on the I2C bus. The second slave operation, but the function names are different.
parameter is the pointer to the buffer that has the data  Allocate read and write buffers; call these
for the slave. The third parameter is the number of functions to initialize: I2CHW_InitSlaveRamRead
bytes to be written to the slave. The fourth parameter and I2CHW_InitSlaveWrite.
is the transaction type and can have three different
values: I2CHW_CompleteXfer, I2CHW_NoStop, and  Call I2CHW_bReadSlaveStatus.
I2CHW_RepStart.  Check for I2CHW_RD_COMPLETE and
When you use I2CHW_CompleteXfer, one full I2C I2CHW_WR_COMPLETE flags. If these flags are
transaction is completed, which includes the start bit, set, reinitialize the buffers.
the address byte, the data bytes, and the stop bit. 4. The firmware for the master side of the operations
When you use I2CHW_NoStop, the stop is not has to deal with some special cases. In a multimaster
generated after writing the data. A transaction with a environment, when a master (let‟s call this Master 1)
NoStop can be followed by a transaction with the tries to initiate a transaction to a slave, there are three
I2CHW_RepStart. Usually, Cypress recommends different scenarios depending on the activities of other
I2CHW_CompleteXfer for most I2C transactions. master(s). (Assuming that there is another master in
The I2CHW_bWriteByte function initializes a pointer to the bus, let‟s call it Master 2.)
the buffer, sets a count value, and initiates the start bit a. The bus is free and Master 1 initiates and
in the I2C hardware. After this, all the operations take completes a read or write transaction.
place inside the ISR. The I2C hardware generates an
interrupt on every byte complete; the ISR takes care b. Master 2 had already initiated a transaction with
of incrementing the pointer to the buffer, transmitting another slave on the bus; because of this, the
the next byte to the slave. When all the bytes are bus is busy. Master 1 must wait until the bus
transferred, the ISR generates a stop. becomes free and then initiate the transaction.
6. Use the I2CHW_bReadI2CStatus function to check c. Master 1 initiates a read or write transaction at
that the write operation is complete, and then clear the same time Master 2 initiates a transaction. In
the flag. For example: this situation, arbitration occurs. If Master 1 wins
the arbitration, it completes the transaction. If
while(!(I2CHW_bReadI2CStatus() & Master 1 loses arbitration, it must retry the
I2CHW_WR_COMPLETE)); transaction after Master 2 completes its
I2CHW_ClrWrStatus(); transaction. Appendix A gives details about
arbitration.
The above code waits until the WR_COMPLETE flag I2CHW provides separate functions for the master for
is set. You can use an “if” condition instead of a handling the multimaster environment.
“while”; the processor can do other things when the
5. To write to a slave, call I2CHW_bWriteBytesNoStall.
I2C transaction takes place in the background.
To read from a slave, call I2CHW_fReadBytesNoStall.
7. Use the I2CHW_fReadBytes function to initiate a read These functions check if the bus is busy before
from the slave. Use the I2CHW_bReadI2CStatus initiating the transaction. If the bus is busy, these
function and check for the I2CHW_RD_COMPLETE functions return 0xFF. The firmware should check the
flag; then clear the read status. return value and retry the transaction if the return
value is 0xFF. For example, the following code loops
I2CHW_fReadBytes(0x50, ReadBuffer, 16,
until the I2CHW_bWriteBytesNoStall returns a value
I2CHW_CompleteXfer);
other than 0xFF.
while(!(I2CHW_bReadI2CStatus() &
I2CHW_RD_COMPLETE)); while(I2CHW_bWriteBytesNoStall(0x50,
I2CHW_ClrRdStatus(); WriteBuffer, 16, I2CHW_CompleteXfer) ==
0xFF);
Multimaster Slave Operation
You can use an “if” condition to check the return value
In the multimaster slave mode, the I2CHW can act as both instead of using a “while” loop, which is blocking. If the
master and slave in a multimaster environment. return value is 0xFF, you can retry the transaction
1. Call the I2CHW_Start function. after a fixed time interval.
2. Call I2CHW_EnableMstr and I2CHW_EnableSlave 6. When a read or write operation is started without a
functions to enable both master and slave modes and bus busy error, the firmware should next check if the
the I2CHW_EnableInt function to enable interrupt.

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operation is completed or if the master lost arbitration. overhead and does not support multimaster operation. It
Following is an example code that does this. requires 100 percent of CPU during I2C transactions. A
while((!(I2CHW_bReadMasterStatus() & second disadvantage is that it is limited to bus frequencies
I2CHW_WR_COMPLETE)) && of 100kHz.
(!(I2CHW_bReadBusStatus() & I2Cm is best for applications in which multiple masters are
I2CHW_LOST_ARB))); needed in a single chip or when the pins that connect to
if (I2CHW_bReadMasterStatus() & the I2C hardware are not available. Cypress recommends
I2CHW_WR_COMPLETE) using I2CHW for master operations if only one master is
{ needed and if P1.5, P1.7 or P1.0, P1.1 are available.
// Write is completed successfully.
// Clear flag Following are the steps to get this UM running in a project.
I2CHW_ClrMasterWrStatus();
} 1. Start the UM using the I2Cm_Start function.
if (I2CHW_bReadBusStatus() & 2. To write data from a RAM buffer (or a ROM buffer) to
I2CHW_LOST_ARB) a slave, use the I2Cm_bWriteBytes function. This
{ function accepts the slave address, pointer to the
// Master lost arbitration. Retry source data in RAM (or ROM), and the number of
later bytes to be transferred.
}
3. To read data from a slave, use the I2Cm_fReadBytes
The first line loops until either the write is completed function. This function accepts the address of the
or the LOST_ARB error flag is set. If the “while” loop slave, pointer to destination buffer where the read
terminates, the code checks to determine which data must be saved, and the number of bytes to be
condition caused the loop to terminate. If the read.
WR_COMPLETE flag is set, then clear the flag. If the This UM works by manipulating the drive mode
LOST_ARB flag is set, then retry the transaction later. (PRTxDMx) and data registers (PRTxDR) of the port on
This application note includes a simple project that which it is operating. For this reason, take care when
demonstrates how to use the I2CHW UM to read a manipulating data registers in user code; otherwise, I2C
standard EEPROM. For details, see Appendix B. traffic is affected adversely. The best way to avoid issues
is to use shadow registers when writing to the drive mode
For more information, see the I2CHW UM datasheet and 2
and data registers associated with the I Cm pins.
the I2C section of the Technical Reference Manual.
When I2Cm is placed in the project, PSoC Designer
2
I CHW Summary and Important Notes automatically creates shadow registers for the data
register and the two drive mode registers PRTxDM0 and
I2CHW can operate in single master, single slave, or PRTxDM1. Because the UM does not affect PRTxDM2, a
multimaster slave modes. shadow register is not created for this register.
In slave mode, when a master completes a read or write, These shadow registers are defined in psocconfig.asm
the buffers must be reinitialized for the next transaction and psocgpioint.h files. For example, if I2Cm is placed in
to take place. Port0, the following variables are defined in the
psocconfig.asm file.
In the master mode in a multimaster environment, the
firmware must check the return value of the ; write only register shadows
bWriteBytesNoStall and fReadBytesNoStall functions to _Port_0_Data_SHADE:
know if the bus is busy, and must retry the transaction. Port_0_Data_SHADE: BLK 1
_Port_0_DriveMode_0_SHADE:
In the master mode in a multimaster environment: When Port_0_DriveMode_0_SHADE: BLK 1
a read or write transaction is initiated, the firmware _Port_0_DriveMode_1_SHADE:
checks if the transaction has completed successfully or Port_0_DriveMode_1_SHADE: BLK 1
the master has lost arbitration to another master. If the
master lost arbitration, the transaction must be retried. The following definitions are placed in psocgpioint.h.
extern BYTE Port_0_Data_SHADE;
I2Cm extern BYTE Port_0_DriveMode_0_SHADE;
extern BYTE Port_0_DriveMode_1_SHADE;
I2Cm, another UM in PSoC 1, implements an I2C master
through software manipulation of GPIO port pins. This UM The application code uses these shadow registers to write
does not use the I2C hardware block. There is no I2C to the data and drive mode registers. For example, if the
software slave user module. application wants to set P0[0], use the following code:
The advantage of this UM over I2CHW is that it can be // Write to PRT0DR through shadow register
used on any pair of pins instead of just P1.5, P1.7 or P1.0, Port_0_Data_SHADE |= 0x01;
P1.1. One drawback is that it requires more CPU

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PRT0DR = Port_0_Data_SHADE; I2C Addressing

There are two common ways used to describe the I2C
To set P0[0] to strong mode using the PRT0DMx registers:
slave address. One uses the seven bits of address and
// Write to PRT0DM0 through shadow register not the read/write bit (for example, 0x42). This is how
Port_0_DriveMode_0_SHADE |= 0x01; Cypress‟s UMs treat the I2C slave address.
PRT0DM0 = Port_0_DriveMode_0_SHADE;
The other way is to include the read/write bit as part of the
// Write to PRT0DM1 through shadow register address (for example, 0x84/0x85).
Port_0_DriveMode_1_SHADE &= ~0x01; Make sure that you know which addressing method the
PRT0DM1 = Port_0_DriveMode_1_SHADE; devices you are working with use.
// Write to PRT0DM2 directly At this time, Cypress does not support 10-bit slave
PRT0DM2 &= ~0x01; addresses.

For more information on the need to use shadow registers, Pull-up Resistors
refer to the Shadow Registers Database. For more
Another common design consideration with I2C is the
information on this user module, see the I2Cm datasheet.
value of the pull-up resistors. The selected value of the
resistors depends on the communication frequency and
I2Cm Summary and Important Notes
the bus capacitance. A larger bus capacitance and pull-up
resistor size causes longer rise time on the clock and data
I2Cm is a software implementation of I2C master and
lines. The I2C specification provides a maximum rise time.
does not occupy the I2C hardware resource.
If the rise time on the bus exceeds the maximum, I2C
I2Cm uses all the CPU resources while reading or writing
communication does not occur properly. The I2C
to a slave.
specification offers the graph shown in Figure 18 to
If the application code has to write to the data or drive determine the value of the pull-up resistors. RS is a series
mode registers of the port in which I2Cm is placed, take resistor; the I2C specification defines the maximum RS.
care to use the shadow registers to avoid problems with
Pull-up resistors between 2.2 k and 4 k work for most
the I2C interface.
systems.

Figure 18. Pull-up Resistor Value

Special I2C Considerations
I2C offers an easy way for devices to communicate with
one another. As with any design, problems may occur
during the design process. This section seeks to answer
common questions and prevent problems that may occur
when designing with I2C. It includes the following topics:

 7-bit and 10-bit addressing

 Pull-up resistor consideration

 Sharing I2C and ISSP pins

 Glitches during power-up

 SYSCLK versus I2C clock speeds

 Clock stretching and interrupt latency I2C and ISSP Programming Conflicts
One common consideration when using I2C with PSoC is
 Hot swapping
the choice of which pins to use. When using the hardware
 Glitch filtering block, there are two pairs of fixed pins available for I2C:
P1.5, P1.7 and P1.0, P1.1. (In the 28xxx family, you can
 I2C and sleep also use P1.2 and P1.6 or P3.0 and P3.2.) You can also
use pins P1.0, P1.1 to program PSoC. Pull-up resistors on
 I2C and dynamic reconfiguration these lines can cause in-system programming failures.
 Dynamic addressing in I2CHW During programming, P1.0 uses the resistive pull-down
drive mode to force a logic level LOW on the line. The pull-
down resistor is approximately 5.6k. This internal pull-
down resistor and the external I2C pull-up resistor create a

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voltage divider. The voltage divider applies an

indeterminate or HIGH logic level on the line, which the  Set pin X to strong and write a „1‟ to it to connect to
the I2C bus.
programmer does not recognize as the desired LOW logic
level. This causes programming to fail. See the DC
Clock Speeds
programming specifications and GPIO logic levels in the
device specific datasheets to determine which voltage As stated earlier, the I2C hardware is responsible for
levels are appropriate. generating the clock on SCL when it is in master mode.
The available I2C clock frequencies in PSoC 1 are 50 kHz,
The best solution is to use P1.5, P1.7. Only use P1.0, 100 kHz, and 400 kHz. These frequencies are based on
P1.1 when it is necessary. Another option is to change the hardwired clock dividers of the system clock (SYSCLK).
drive mode in PSoC to pull up for P1.0, P1.1, instead of
using external pull-up resistors. The internal pull-up These clock dividers produce sampling clocks that
resistors are approximately 5.6 k. oversample the I2C lines 16 or 32 times. Table 4 lists the
internal sample rate.
Pin Glitches at Power-up Table 4. Internal Sampling Rates
As already stated, P1.0 and P1.1 are used for
programming, which means that these pins behave Clock SYSCLK Internal Sampling Samples
differently at power-up than other pins. Rate Pre-Scaler Clock Frequency Per Bit
(SYSCLK=24 MHz)
After the part is released from reset, P1.0 drives out a
strong HIGH. This will cause issues if one of the other I2C 50 kHz /16 1.5 MHz 32
devices on the bus is driving the line LOW. P1.1 drives out 100 kHz /4 1.5 MHz 16
a resistive LOW. As stated earlier, this will create a
voltage divider and an intermediate voltage on the bus, 400 kHz /16 6 MHz 16
which other devices may not recognize. After a set amount
of time, P1.0 transitions to a resistive LOW, causing an
intermediate voltage on that line. The internal sampling clocks assume that SYSCLK is at
24 MHz. If SYSCLK is slower than 24 MHz, the I2C clocks
Be aware of this behavior and how it will affect I2C devices are slower. For example, if SYSCLK is 12 MHz, then the
on the bus, if other I2C devices are powered and available speeds are 25 kHz, 50 kHz, and 200 kHz. If
connected to P1.0 and P1.1 when you start PSoC. SYSCLK is 6 MHz, the available I2C speeds are 12.5 kHz,
2 25 kHz, and 100 kHz. (See Table 5.)
To avoid this issue, use P1.5 and P1.7 for I C
communications. Or take steps to minimize the impact of Table 5. Actual Frequency versus IMO and UM Setting
the pin behavior on P1.0 and P1.1 during reset. This can
be as simple as keeping all other devices in reset until IMO (SYSCLK) Setting
PSoC has started up. Or implement a more complicated UM Setting
solution such as gating the output of PSoC with a 24 MHz 12 MHz 6 MHz
transistor or logic gates. See Figure 19.
400 kHz 400 kHz 200 kHz 100 kHz
Figure 19. Isolating PSoC 100 kHz 100 kHz 50 kHz 25 kHz
PSoC
50 kHz 50 kHz 25 kHz 12.5 kHz
D S Pin 1_0
I2C SDA
BSS145
G

D S Pin 1_1 Note SYSCLK is separate from CPU_Clock.

I2C SCL
BSS145 When operating in slave mode, the same rules apply for
G Pin X (to enable
I2C) the highest clock speed that the I2C block can read. The
100k oversample clock is used to monitor the I2C lines. Setting
the speed in slave mode indicates how often the clock and
data lines are oversampled by the hardware.
Notes
If the I2C clock frequency is 400 kHz and the hardware is
 It is important to place the N channel FETs used in configured for 100 kHz, the hardware will not receive data
this block so that the source of the FET is attached to properly. One common mistake is to set the I2C slave
the PSoC GPIO pin. clock frequency in PSoC Designer to 100 kHz and
SYSCLK to 6 MHz. The assumption that the slave will
 The FETs must be N channel and must have a VGSTH operate on the 100 kHz bus is incorrect. Because
rating of ≤ PSoC Vdd. For example, if the PSoC Vdd = SYSCLK is at 6 MHz, the slave can only operate on a 25-
3.3 V, choose an N channel FET with a rating of kHz bus. Therefore, to operate on a 100-kHz bus with a
VGSTH ≤ 3.3 V. SYSCLK of 6 MHz, choose 400 kHz as the I2C speed in
the user module properties.

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The frequency of SYSCLK depends on the supply voltage Figure 21. Byte Complete Interrupt Timing
for PSoC. If the supply voltage is above 3 V, then most
Max
devices have a 24-MHz SYSCLK. If the supply voltage is
4 Cycles
below 3 V, then many devices have a 6-MHz SYSCLK. Internal
Several devices have a 12-MHz SYSCLK option. Further, Sampling
the value of SYSCLK can be changed within PSoC Clock
Designer. When using I2C, do not change the frequency of SCL
SYSCLK or the CPU_CLK; this can cause glitches on the
I2C lines. For more information on clocks, see the clock Interrupt
section of the Technical Reference Manual.
Transmit: Ninth positive edge SCL
When using an external clock, be sure to use the correct Receive: Eighth positive edge SCL
I2C clock speed.
Using this information, you can determine if the clock will
Clock Stretching and Interrupt Latency be stretched and for how long. However, if there are other
Clock stretching is the process in which a slave device interrupts in the system, the time spent in those interrupts
holds the clock line LOW, thus stalling further must be considered.
communication on the bus by the master. The slave To minimize clock stretching in PSoC, the first step is to
device typically stretches the clock so it can process run the CPU at 24 MHz. Next, the I2C clock speed must be
information it is receiving from the master or prepare more 100 kHz or lower. Last, having minimal interrupts reduces
data to send to the master. This stretching can be done at clock stretching.
any point of the transaction. PSoC stretches the clock
after the byte complete interrupt. See Figure 20. Hot Swapping
2
The I C specification indicates that this is an optional Hot swapping is the process of attaching powered devices
feature; not all I2C devices need to support clock to an unpowered PSoC. I2C in PSoC is not designed to be
stretching. However, all Cypress PSoC 1 I2C slave UMs hot swappable. There are several factors to consider when
stretch the clock. If you use a master that does not support hot swapping PSoC. The first issue is back powering. If
clock stretching, the bus can lock up and fail to reset. PSoC is not powered but one of the external pins is at a
high voltage level, then there is a possibility of back
Figure 20. Clock Stretching Example powering the PSoC device. This is not a desirable
START 7-Bit Address R/W situation, because PSoC may execute in unexpected ways
ACK and the I2C lines may be adversely affected.

1 7 8 9 Glitch Filtering
The input of the SCL has a glitch filter, which Figure 22
Clock Stretching
shows.
The time the PSoC slave spends stretching the clock Figure 22. SCL Glitch Filter
depends on whether the master is reading or writing to the
slave and whether other interrupts occur in the system. It SCL Pin INPUT
also depends on the CPU speed.
0
PSoC 1 devices will stretch the clock a majority of the time 1

for I2C bus speeds of 100 kHz or greater. The ISR code in
SAMPLE
the EzI2Cs and I2CHW UMs contain 150 to 300 CPU
CLK
instruction cycles. With a 24-MHz CPU clock, the ISR
takes approximately 6 to 13 µs to execute. The SCL line is
The input is double-synchronized to the sample clock, and
released at the end of the ISR code.
then it is glitch-filtered. The raw input and the delayed
The ISR is triggered three or four internal sample clock input must match for a signal to pass through. Because
periods after the rising edge of SCL; see Figure 21. This is the sample clock is either 1.5 MHz or 6 MHz, glitches less
due to an internal glitch filter on SCL; see Figure 22. Refer than 666 ns and 166 ns are suppressed.
to Table 4 for the frequency of the sampling clock. For
100 kHz, the sample clock is 1.6 MHz, which means that I2C and Sleep
the ISR will fire ~2.5 µs after the rising edge of SCL. The When using I2C in designs that enter and exit sleep mode,
nominal period of a 100-kHz clock is 10 µs. If it takes 2.5 you need to take special design considerations into
µs for the ISR to be triggered and the ISR takes 6 to account.
13 µs, the clock will be stretched in most cases.
First, it is important that all I2C transactions are complete
before the I2C enters sleep mode. Otherwise, when the
part wakes up, the I2C block can erroneously interpret data

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as an address or vice-versa. After confirming that all I2C Figure 23. I2CHW UM Slave Address
traffic has stopped, follow these steps:

 Configure the I2C pins in a HIGHZ drive mode.

 Disable the I2C block. This is generally done by calling

the stop() API of the UM.

 Clear any pending I2C interrupts.

After these conditions are met, PSoC can be put to sleep.
When the part wakes from sleep, follow these steps to
ensure proper I2C operation after sleep:

 Ensure that no I2C activity is occurring on the bus. Follow these steps to replace the constant with a RAM
variable:
 Call the appropriate start API.
1. Create a RAM variable to hold the dynamic slave
 Configure I2C pins for open-drain drives LOW. address. In the I2CHW_1int.asm file, just below the
variable allocations, is a custom user code area.
 Enable interrupts. Under the custom declaration area, add this code:
If you follow these steps, you can avoid most errors when export _I2CSlaveAddress
using I2C in conjunction with sleep. export I2CSlaveAddress

I2C and Dynamic Reconfiguration Under the variable allocation area, add the following:
I2C UMs should never be loaded or unloaded through
dynamic reconfiguration. They should always be present. Area InterruptRAM(ram)
If they are loaded and unloaded, I2C errors will occur. _I2CSlaveAddress:
I2CSlaveAddress: BLK 1
The I2C UMs should be located either in the base
configuration or in a separate overlay that is always The variable with the „_‟ allows you to modify this in C
loaded. code.

Dynamic Slave Addressing in I2CHW UM 2. Modify the code that does the address comparison.
The EzI2Cs UM allows you to programmatically change mov A, reg[I2CHW_1_DR]
the I2C slave address on the fly. However, this functionality and F, 0xF9
is not available in the I2CHW UM; to achieve the same rrc A
functionality, do the following: xor A, [I2CSlaveAddress]

In the I2CHW UM, the address from the master is Because this code is inside a custom user code area,
processed inside the I2CHW_1int.asm file. The following changes to the UM library file are preserved during
code does the address matching. application generation. Note that if you rename the
UM, changes will be lost and must be made again.
mov A, reg[I2CHW_1_DR]
and F, 0xF9 3. Add a reference to the I2C slave address variable that
rrc A is defined in the I2CHW_1int.asm file by adding the
xor A, I2CHW_1_SLAVE_ADDR following code in main.c (or any other C file).
extern BYTE I2CSlaveAddress;
When the address is received from the master, it has a
7-bit address and the read/write bit. The „rrc A‟ drops the
read/write bit and compares the 7-bit address with the
The SCL Line Gets Stuck LOW
constant I2CHW_1_SLAVE_ADDR, which the device A common issue with I2C is the SCL getting stuck LOW.
editor creates according to the Slave_Addr set in the UM Follow these guidelines for debugging and fixing this issue
parameters for the I2CHW. This constant is located in the with PSoC 1 devices:
I2CHW_1.inc file.
1. Are you using EzI2Cs with PSoC Designer 5.0 SP5?
If yes, there is a known bug with this version of the
UM that causes the SCL to be stuck LOW. Update to
the latest version of PSoC Designer to fix this issue.
See the article I2C Clock Permanently Stuck to
Logical LOW.
2. Are you using PSoC Designer version prior to PD5.0?
If yes, then there are glitches on P1.5, P1.7 at startup.

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This issue has been resolved in the latest version of

PSoC Designer. For more information, see the article Summary
Glitch on the I2C Lines During Power-Up.
I2C is a simple two-wire chip-to-chip digital communication
3. Does the master device support clock stretching? protocol. The protocol is master oriented but allows
If no, then the communication between the slave and bidirectional communication on just two communication
master will become unsynchronized and undesirable lines.
behavior may occur, including the SCL being stuck
LOW. If the master does not support clock stretching, The Cypress PSoC offers several user modules for
there is no guarantee of PSoC functioning properly on the implementation of I2C in a design that includes
the bus. slave, master, and multimaster configurations. I2C
4. Does the CPU clock or SYSCLK change dynamically communication in PSoC is easy and reliable if you follow
during code execution? If yes, this can cause glitches the considerations that Cypress recommends.
on the SCL and SDA. To avoid this problem, do not
change clock speeds in code.
5. Are you enabling and disabling I2C interrupts in your About the Authors
code? If yes, make sure you are using the ResumeInt
API and not the EnableInt API, which clears the Name: Todd Dust
interrupt. If there is a pending I2C interrupt and you Title: Application Engineer
clear it, SCL will be stuck LOW forever.
Background: BSEE Seattle Pacific University
6. Can there be other I2C traffic on the bus when PSoC
starts up? If yes, then there is a known bug that has
been fixed in the latest version of PSoC Designer. If Name: M. Ganesh Raaja
you do not have the latest version and cannot update,
use the following workaround: In the chip editor, set Title: Application Engineer Principal
the drive mode of the I2C pins to analog High-Z. In the
Background: Ganesh earned his Diploma in
main code, enable the I2C UM. Then set the drive
Electronics and Communications
mode of the I2C pins to open-drain drive LOW.
Engineering at Motilal Nehru Govt.
7. Is sleep being used in the project? If yes, follow the Polytechnic in Pondicherry, India.
steps in the sleep section to avoid any issues. He has about 20 years of experience
The latest version of PSoC Designer has fixes and in analog circuit design and
workarounds for a majority of the issues discussed above. microcontrollers. He also writes the
Cypress always recommends using the latest version of blog PSoC Hacker on the Cypress
PSoC Designer. website.

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Appendix A
This appendix is for users who are curious about the I2C_SCR register. If the bit is a zero, then the slave has
2
detailed operation of the I C hardware block in PSoC. acknowledged; if the bit is a one, then the slave has not
acknowledged. Take appropriate action depending on this
Hardware Registers condition.
Several registers control the I2C hardware block and report Firmware is also responsible for setting the direction of
its status. communication. This is done by setting the transmit bit in
I2C_CFG Register: Controls the configuration of the I2C the SCR register. If a zero is written to the bit, the block is
hardware block. It controls the clock speed and the pins placed in receive mode. In this mode, the hardware
being used, and it indicates if the slave or master interrupts the CPU when it receives eight data bits. After
functionality is enabled. It also enables support for this interrupt, the firmware must determine if an ACK/NAK
interrupts on stop conditions and bus errors. needs to be sent.

I2C_SCR Register: Returns status flags from the I2C If a „1‟ is written to the transmit bit, the block is placed in
hardware block. It reports if a full byte (byte complete) is transmit mode. In this mode, the hardware interrupts after
sent or received. This register indicates if a bus error has the ACK/NAK is received from the slave device. The
occurred or if arbitration is lost. It also determines if the firmware again handles these cases.
last transaction was an address. When the SCR register is written, the master will start to
I2C_DR Register: This register holds the value of data generate clocks to either send or receive more data.
sent or received. It shifts data in only if the data is an S l a ve O p e r a t i o n
address, if the hardware block is configured as a slave
When the hardware detects a start condition in slave
and is addressed, or if the master has initiated a read.
mode, it shifts the next eight bits of data into the I2C_DR
I2C_MSCR Register: This register controls the master register. On receipt of the eighth bit, the hardware block
portion of the I2C transaction. It holds the bit that allows interrupts the CPU and causes the address bit in the
generating a start. The enable master bit in the I2C_CFG I2C_SCR register to go HIGH.
register must be set for this register to be available;
When the interrupt is posted, the hardware holds the clock
otherwise, this register is held in reset.
line LOW. It is then the firmware‟s responsibility to read
the incoming address and acknowledge whether the
Firmware Requirements address is its own. The firmware must set the ACK bit in
This section describes the operation of the hardware block the SCR register appropriately. The firmware should also
for different configurations. Note that wherever the text read the read/write bit of the address. If the bit is a „1,‟
mentions a requirement of firmware, all PSoC I2C user then the transmit bit in the SCR register is changed to a
modules run this code. „1.‟ After the CPU writes to the SCR register, the hardware
releases the clock line, which allows the transaction to
Start Generation continue.
If the start gen bit is set in the master status and control
register, the hardware block generates a start condition If the slave is configured as a transmitter, firmware must
and sends out the address in the data register. However, load valid data into the DR register before writing to the
the hardware recognizes if another device has taken SCR register and releasing the bus. After the bus is
control of the bus. If an external start condition is detected, released, the hardware shifts data out to the SDA line on
the hardware queues the current start until the bus is free. the clock edges provided by the master. The hardware
The start bit is not cleared until the hardware has waits until it receives an ACK/NAK from the master and
successfully sent out a start condition or the firmware has then interrupts the CPU. The firmware then must load new
cleared it. data or do nothing.

Only one start can be queued at a time. If the master If the slave is configured as a receiver, the hardware
attempts to send two starts while the bus is busy, the interrupts after the eighth bit of data is received. The
hardware sends only the last address. As stated earlier, firmware then decides if it can receive more data. It must
the user code must ensure that this situation does not then set the ACK bit appropriately.
occur.
Stop Condition
Master Operation When a transaction is completed in master mode, the
In master mode, after the start and address are sent, the hardware block generates a stop condition to indicate that
hardware waits until the ACK/NAK bit from the slave is the bus is free.
received. On receiving the ACK/NAK bit, the hardware In slave mode, the reception of a stop puts the hardware
interrupts the CPU. Firmware then determines if the slave block into an idle mode until it receives a new start
acknowledged or did not acknowledge the address. It condition.
does so by reading the last received bit (LRB) in the

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Interrupt Sources Arbitration

In the earlier examples, the hardware block interrupts on a The hardware block can also indicate if the master loses
byte-complete condition. The occurrence of this interrupt arbitration. This is necessary when operating in
depends on the direction of communication. multimaster mode. Arbitration occurs when two masters
start writing at the same time. The hardware monitors the
 Transmit: Byte Complete Interrupt = Ninth bit SDA line. If the master attempts to leave the bus HIGH but
another master pulls it LOW, the master signals that it has
 Receive: Byte Complete Interrupt = Eighth bit
lost arbitration. After the arbitration condition, the
The hardware block allows two additional interrupt hardware does not control the SDA line but continues to
sources. Setting the appropriate bit in the I2C_CFG clock the SCL line. On a subsequent byte-complete
register enables these interrupts. The hardware is capable interrupt, it is the firmware‟s responsibility to view the lost
of interrupting on a stop condition. This is useful when arbitration bit to see if arbitration was lost during the
operating in slave mode; the interrupt alerts the firmware previous transfer.
that the current transaction is complete. The next available
interrupt is on a bus error, which is a misplaced start or Basic I2C Flow
stop on the bus. If the hardware detects the interrupt, it Figure 24 and Figure 25 show the basic flow for I2C
stops its current activities and posts the interrupt; the transactions. This is the basic flow needed to implement
2
firmware then decides what to do with this situation. I C in PSoC 1 successfully. The provided UMs follow this
flow with added overhead.

Figure 24. Flow Diagram for a Successful Slave Transmitter/Receiver

Master transmits
another byte

CPU writes CPU issues ACK/ ACK = Slave OK to

(ACK) to An interrupt is SCL line is NAK command receive more.
I2C_SCR generated on byte held LOW. with a write to the Master may send
register. complete. I2C_CSR register. more or issue stop.

8-Bit Data STOP

ACK
ACK/
NAK
Write (RX)

A byte interrupt is SCL line is NAK = Slave says

generated. held LOW. 1 7 8 9 no more.

START 7-Bit Address R/W

CPU reads the
received byte from the CPU reads the
I2C_D register and received byte from
checks for “Own the I2C_D register.
1 7 8 Address” and R/W.
Read (TX)

CPU writes the CPU writes

byte to transmit (ACK | TRANSMIT) to An interrupt is generated
to the I2C_D I2C_CSR register. SCL line is
on a complete byte +
register. held LOW.
ACK/NAK.

8-Bit Data STOP

ACK NAK = Master
ACK/ says end of data.
NAK

9 1 7 8 9

ACK = Master
wants to read
another byte.

CPU writes a new byte to the

I2C_D register and then writes a
TRANSMIT command to
I2C_SCR to release SCL.

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Figure 25. Flow Diagram for a Successful Master Transmitter/Receiver

An interrupt is CPU issues ACK/

generated on byte NAK command to ACK = Master
complete. the I2C_SCR wants more.
register.

CPU issues a 8-Bit Data STOP

CPU issues command to the ACK/
GENERATE I2C_CSR. NAK
START
An interrupt is generated
command to
after the ACK is received. 1 7 8 9
I2C_MCR. NAK = Master
indicates end of

Read (RX)
data.
CPU reads the
START 7-Bit Address R/W received byte from
I2C_D register.
ACK
CPU checks Read/
Write Bit
1 7 8 9

CPU writes address Write (TX) CPU issues TRANSMIT

byte to the I2C_D command to the An interrupt is generated
register. CPU issues STOP
I2C_SCR register, on completion of the byte command
starting the transfer. + ACK/NAK.

CPU writes a byte to

transmit I2C_D NAK = Slave
8-Bit Data says no STOP
register.
ACK/ more.
NAK

1 7 8 9

ACK = Slave
says OK to
receive more.
Master can
send more or
Stop.
Master wants to
send more bytes.

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Appendix B
This appendix describes various example projects that written to the variable ADCValue. A master device can
demonstrate the use of the I2C UMs. read this variable.
In firmware, a local copy for LEDValue and DACValue are
EzI2Cs_ADC_LED_DAC Example Project created. The values of LEDVAlue and DACValue in the
This project demonstrates how to configure the EzI2Cs I2C register structure are continuously compared with the
UM. The project configures PSoC as an I2C slave and may local copies of these parameters. When the master writes
be considered as an implementation of an I2C-controlled a different DAC value or LED value, then the LED ports
analog peripheral device and port expander. (P0[0] to P0[3]) and DAC are updated with the new values.
This project creates the following data structure: The DAC output is available on P0[5].

struct I2CRegs Testing the Project

{ Figure 27 shows the setup for project testing. Use a
BYTE LEDValue;/* Updates LEDs */ CY3210 PSoC 1 evaluation board to wire the setup.
BYTE DACValue;/* Updates DAC */
BYTE ADCValue;/* Reads ADC value */ Figure 27. Schematic for EzI2Cs_ADC_LED_DAC_Project
}I2CRegs;

The structure is exposed to the I2C master through the

following API call:
EzI2Cs_1_SetRamBuffer(sizeof(I2CRegs), 2,
(BYTE *) &I2CRegs);

The first parameter sets the size of the structure. The

second parameter sets the number of parameters that
have read-write permission. Parameters beyond this
boundary are read-only. In this structure, LEDValue and
DACValue are read-write and ADCValue is read-only. The
final parameter is the pointer to the structure itself. P0[0] to P0[3] are connected to the LED1 to LED4 signals
on J5. P0[7] is connected to the variable resistor VR. A
Configure the EzI2Cs UM in the chip view as shown in digital multimeter is connected to P0[5] to monitor the DAC
Figure 26. output. The LCD is connected to the LCD connector J9.
Figure 26. EzI2Cs UM Configuration A CY3217 MiniProg1 or CY8CKIT-002 MiniProg3 can be
used to program the device using the ISSP header on the
CY3210 board. See Table 6.
A CY3240 USB-I2C Bridge PSoC Development Kit or
MiniProg3 may be used as I2C master. Figure 28 shows
the CY3210 board with the project in action. The CY3240
I2C-USB bridge is used here.
Table 6. Setup on the CY3210 Evaluation Board

PSoC 1 CY3210 Description

Pins Connections

P0[0] to LED1 to LED4 Connect P0[3:0] to the 4 LEDs

P0[3]
P0[7] VR Potentiometer input
Set the slave address to 0x04; set the address type to P0[5] - Connect multimeter
static; disable the ROM registers; set the clock speed to
400 kHz, fast mode; and use P1[0] and P1[1] as I2C pins. - ISSP header Connect MiniProg1 or MiniProg3
P1[0] and P1[1] are used in such a way that the ISSP port (J11) for programming
on the CY3210 PSoC 1 evaluation board can also be used - ISSP header Connect Cy3240/MiniProg3 for I2C
to connect the I2C master. (J11) communication to PC
In firmware, an ADC is used to read the voltage on P0.7.
You can simulate different voltages by connecting a
potentiometer to this pin. The value read by the ADC is

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Figure 28. Test Setup for EzI2Cs Example Project Figure 29. Bridge Control Panel

Command Window

Status/Response
Window

There are two methods for testing the project. You can
use Bridge Control Panel software or an external MCU.
Using Bridge Control Panel Software to Test Power Button Connect Button

The Cypress Bridge Control Panel software acts as a

4. To write to the LED and DAC parameters, type the
graphical front end to communicate with PSoC I2C slave
following command in the command window of the
devices. It is useful for testing, tuning, and debugging
Bridge Control Panel:
programs that have an I2C slave interface. You can install
the Bridge Control Panel with PSoC Designer and PSoC w 04 00 03 80 p
Programmer™.
„w‟ is the write command. „04‟ is the slave address.
After programming the device, connect the CY3240 or „00‟ is the subaddress where the values have to be
MiniProg3 to the ISSP connector. The CY3240 and the written. „03‟ is the value for LED. For a value of 03,
MiniProg3 have the pull-up resistors required for the SDA LED1 and LED2 will be turned on. „80‟ is the DAC
and SCL lines of the I2C. output. The output of the DAC is about 2.09 V for this
The following steps show how to use the Bridge Control value.
Panel to read the value of ADC and to control the LED and When you enter this command in the command
DAC outputs of the EzI2Cs_ADC_LED_DAC project. window and press Enter, the I2C master transmits the
1. Open Bridge Control Panel from the Windows start command to the EzI2Cs slave. Observe the state of
menu. It is located in the Cypress folder. LED and the output on P0[5] in the results window.
(See Figure 30.)
2. Select the MiniProg3 or the CY3240 from the device
list and click the Connect button. w 04+ 00+ 03+ 80+ p
3. Next, click the Power button to supply power to the
A „+‟ sign after each byte indicates that the EzI2Cs
CY3210 test setup. (See Figure 29.)
slave acknowledged the byte. A „−‟ sign indicates that
the byte was not acknowledged.
For example, try the following command:
w 04 00 03 80 55 p

The response would be:

w 04+ 00+ 03+ 80+ 55- p

Because we have set the third byte in the EzI2Cs

register structure as read-only, the slave will not
acknowledge (NAK) the write to this register.

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Figure 30. Write LED and DAC Values This write command sets the subaddress in the
EzI2Cs. Any further read operation will take place on
subaddress 0x0, which is the ADC value.
Next, type the following command and select the
Repeat button. Observe only the ADC value being
read.
r 04 x p

Figure 32. Read Only the ADC Register

5. To read the ADC result, type the following command

in the command window:
r 04 x x x p

„r‟ is the read command. „04‟ is the slave address. The

three „x’s indicate how many bytes to read from the
slave.
Now click the Repeat button in the Bridge Control
Panel and observe the result in the results window. Using an External MCU to Test
(See Figure 31.) You can also test the project with another microcontroller
acting as an I2C master. This section demonstrates the I2C
Figure 31. Read All of the I2C Registers interface with an Arduino Duemilanove board configured
as an I2C master and assumes that you are familiar with
the Arduino prototyping platform. For more information on
this board and the Arduino platform, visit www.arduino.cc.
Refer to Getting Started with Arduino for instructions on
connecting the Arduino board to the PC and uploading the
program.
The Arduino device is configured to have an I2C master
interface on the dedicated pins (AIN4, AIN5) and one
PWM output on pin 11.
The CY3210 is configured as an I2C slave having a 4-bit
digital display (four LEDs), one analog output (DAC), one
analog input (potentiometer connected to analog input
pin), and an LCD display.
1. Program the CY3210 board with the example project.
2. Open the included Arduino project file
“Arduino_I2C_Master_PSoC1_Slave.ino” using the
The last byte in the response is the ADC result. The Arduino software.
second and third bytes show the values of the LED
3. From Tools, select Board and then the Arduino
and DAC parameters respectively.
Duemilanove option.
6. If you want to read only the ADC value and not the 4. From Tools, select Serial Port and then the port on
LED and DAC values (see Figure 32), first execute which the board is connected.
the following command:
5. Download the program to the board using a USB A-B
w 04 02 p cable. Detach the USB cable after programming is
complete.
6. Make hardware connections according to Table 7.

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Table 7. Hardware Connections Figure 33. Arduino-to-PSoC Interface

Connections on Arduino Duemilanove

Pin Connection Description

Pin 11 (PWM) Connect an LED PWM output on Arduino

Connections on CY3210-PSoC Evaluation Board

Pin Connection Description

P00 LED1 on J5 Digital output Bit 0

P01 LED2 on J5 Digital output Bit 1
P02 LED3 on J5 Digital output Bit 2
P03 LED4 on J5 Digital output Bit 3
P05 Multimeter/Scope Analog output (DAC)
P07 VR on J5 Analog Input (ADC)

CY3210 to Arduino Connections

Arduino Pins PSoC 1 Pins Description

2
Analog in 4 P10 on J7 SDA for I C
(A4)
2
Analog in 5 P11 on J7 SCL for I C
(A5)
5V VCC on J5 Power PSoC 1 board
using Arduino 5 V
GND GND on J5 Ground

7. Connect a CY3217 MiniProg1 or CY8CKIT-002

MiniProg3 to the ISSP header on the CY3210 board.
After programming, remove the programmer from the
ISSP header.
8. Reattach the USB cable to the Arduino board. This
will power both the Arduino board and the CY3210
board. Figure 33 gives a snapshot of the setup.

PSoC reads the voltage on P07 (connected to

potentiometer) and stores the value in ADCValue. Arduino
reads this value using the I2C and controls the PWM
output on pin 11. Turning the potentiometer on the
CY3210 varies the brightness of the LED on the Arduino
board.
Arduino continuously sends a 4-bit pattern over the I2C
interface. PSoC reads this value and writes to Port0 pins,
which are connected to the four LEDs. Arduino also
continuously sends an 8-bit digital value, which is
converted to an analog voltage by the PSoC DAC. The
DAC code sent is an incremental value from 0 to 255.
Figure 34 shows the DAC output waveform on the PSoC
pin (P05) when viewed on an oscilloscope.
This example thus shows how an external MCU can
interface with a PSoC device using I2C.

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Figure 34. DAC Output Waveform on P05 Testing the Project

Figure 36 shows the setup for project testing.

Figure 36. Schematic for I2CHW_Slave Project

The only connections required to test the project are the

ISSP connections. The same ISSP connector is also used
to connect the I2C master. (See Table 8.)

I2CHW Slave Example Project Table 8. Connections for Project Testing

2
This project demonstrates how to configure I CHW as a PSoC 1 CY3210 Description
slave. Pins Connections
In this project, the data that is written to the I2CHW slave is - ISSP header Connect MiniProg1 or MiniProg3
echoed back to the master. This is done by configuring the (J11) for programming
read and write buffers as the same buffer. To do so, use
the following API: - ISSP header Connect Cy3240 or MiniProg3 for
2
(J11) I C communication to PC
/*When master writes data it will write to
rxtxBuffer*/ I2CHW_1_InitWrite(rxtxBuffer,
10); You can test the I2CHW slave project using the CY3210
/*When master reads data it will read from PSoC 1 evaluation board.
rxtxBuffer*/
Use a CY3217 MiniProg1 or CY8CKIT-002 PSoC
I2CHW_1_InitRamRead(rxtxBuffer, 10);
MiniProg3 to program the device, using the ISSP header
on the CY3210 board.
The main code checks to see if a master device has read
or written to the I2CHW slave. If it has, then the code will Use a CY3240 USB-I2C Bridge or MiniProg3 as the I2C
reset the buffers and clear the appropriate status flags. master.
Figure 35 shows the configuration of the I2CHW UM. The Figure 37 shows how to use the Bridge Control Panel to
slave address for the device is 0x04. write and read values from the I2CHW slave. Refer to the
EzI2Cs_ADC_LED_DAC example project for a brief
Figure 35. I2CHW UM Slave Configuration description of how to set up the Bridge Control Panel.
1. Type the following commands in the command
window of the Bridge Control Panel:
w 04 00 01 02 03 04 05 06 07 08 09 p

r 04 x x x x x x x x x x p

w 04 0a 0b 0c 0d 0e 0f 10 11 12 13

r 04 x x x x x x x x x x p

2. Select the “Send all strings” option and click the Send
button to execute all of the commands in sequence.
Observe in the results window that the same values
written using the write command are being read back
while executing the read command.

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Figure 37. Writing and Reading the I2CHW Slave When the slave generates an ACK, the master exits the
while loop.
Next, the master reads the data that it just wrote to the
EEPROM. This is done by first writing the two subaddress
bytes and then reading out 64 bytes of data from the
EEPROM. The master then compares the read data with
the written data. When all 64 bytes match, an LED is
turned on.
To test this project, connect P1.5 and P1.7 to the SDA and
SCL of an external I2C EEPROM. Make sure that you
have external pull-up resistors on those lines. Connect an
LED with a series resistor to P0_7. You can test the
project using a CY3210 PSoC evaluation board. (See
Table 9.)
Table 9. Connections for Project Testing

PSoC 1 CY3210 Description

Pins Connections
I2CHW Master Example Project P1[5] 2.2-kΩ pull-up Connect to SDA of 24C256 IC
2
This project demonstrates how to use the I CHW UM in to VDD
master mode. Specifically, it demonstrates how to use the P1[7] 2.2-kΩ pull-up Connect to SCL of 24C256 IC
I2CHW UM to read and write to an external I2C EEPROM. to VDD
P0[7] LED1 LED indicator
Figure 38 shows how to configure the I2CHW UM.
Figure 38. I2CHW Master Configuration Figure 39 shows the setup for project testing.

Figure 39. I2CHW_Master Test Schematic

In the main code, the I2CHW UM is initialized. After that, it

writes out 66 bytes to the EEPROM from the RAMBuffer
array. The first two bytes are the subaddress where the
data is written in the EEPROM. This project is tested with
a 32Kb EEPROM, which has a page size of 64 bytes.
When writing to smaller EEPROMs, limit the write to the
page size of the particular EEPROM.
When data is written to the EEPROM, the EEPROM
enters a write cycle. During this time, the slave does not
generate an ACK to any I2C transaction. Any further
operation can be done only when the EEPROM completes
the write cycle. To detect this, the master enters a “while”
loop in which it continuously sends a start and checks the
ACK status.
while(!(I2CHW_fSendStart(0x50,
I2CHW_READ)))
{
I2CHW_SendStop();
}

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Migrating Example Project Figure 40. Migrate Project

The projects can easily be migrated to other devices using
the built-in cloning feature of PSoC Designer. For
example, to migrate the EzI2Cs_ADC_LED_DAC project:
1. Open PSoC Designer and create a new project.
2. Select the Clone option in the Project Creation
parameter.
3. In the “Clone from Project” parameter, browse and
select the EzI2Cs_ADC_LED_DAC.cmx file in the
project folder of the EzI2Cs_ADC_LED_DAC project.
Then choose the device that you want to run this
project on by clicking the Device Catalog button.
4. After selecting the Device, click OK; PSoC Designer
will migrate the project to the new device. (Refer to
Figure 40.)

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Getting Started with I C in PSoC 1

Document History
Document Title: Getting Started with I2C in PSoC® 1 – AN50987
Document Number: 001-50987

Revision ECN Orig. of Submission Description of Change

Change Date

** 2641969 TDU 01/21/08 New Application Note

® 2
*A 3147658 TDU 01/19/2011 Updated Title to read “PSoC 1 I C Overview.”
Updated Abstract section.
Updated I2C and Sleep section.
Minor edits.
Specified PSoC 1 parts this Application Note is applicable too.
*B 3427861 TDU 11/11/2011 Updated to New Template
Modified Title
Added 3 example projects
Added Hardware Blocks in CY8C28xxx
Updated sections I2CHW, Clock Speeds, and Clock Stretching and Interrupt
Latency
Added sections Glitch Filtering, I2C and Dynamic Reconfiguration, The SCL Line
Gets Stuck , and Basic I2C Flow
*C 3672732 GRAA 07/11/2012 Improved the flow in EzI2Cs section
Added a section explaining the EzI2Cs parameters and steps to get it working in a
project
Added summary and important notes section for EzI2Cs
Added sections explaining in detail the hardware and firmware configuration for
2
the I CHW in slave, master, and multimaster modes.
Added summary and important notes section for I2CHW
2
Added section explaining how I Cm may be incorporated in a design.
2
Added more details about using the shadow registers when using I Cm
2
Added summary and important notes section for I Cm
2
Modified the I CHW example project to interface to 24C256 EEPROM and
updated Appendix D with the operation of the project.
*D 4078726 GRAA 07/26/2013 Minor modifications throughout document. Updated the example projects.
*E 4682397 GRAA 03/10/2015 Updated the example projects to PSoC Designer 5.4
Updated template
Sunset review
*F 5688054 AESATMP7 04/10/2017 Updated Cypress Logo and Copyright.

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Getting Started with I C in PSoC 1

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