B.

Tech III semester

DIGITAL SYSTEM DESIGN
Topic : Sequential Circuits
BY
Veena M Kurup
Assistant Professor

DEPARTMENT OF ECE
INSTITUTE OF AERONAUTICAL ENGINEERING
 Institute of Aeronautical Engineering
Sequential Circuits

MODULE –III: SEQUENTIAL LOGIC DESIGN

Building blocks like S-R, T FF, D FF, JK and Master-Slave JK FF, Edge
triggered FF, Characteristics and Excitation of SR, JK, T, D FF, Ripple and
Synchronous counters, Shift registers.
Finite state machines, Design of synchronous FSM, Algorithmic State
Machines charts. Designing synchronous circuits like Pulse train generator,
Pseudo Random Binary Sequence generator DON’T WRITE
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Sequential Circuits

 The outputs of the sequential circuits depend on both the combination of present inputs
and previous outputs.
 The sequential circuit contains the combinational circuit and its memory storage
elements.
 The sequential circuit can contain only the memory element.
Inputs X(t) Outputs Z(t)

Combinational
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Storage .
Element
S(t)
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Sequential Circuits

 The storage (memory) elements are devices capable of storing binary information.
 The binary information stored in these elements at any given time defines the state of
the sequential circuit at that time.
 The present contents of the memory element is referred as present state.
 The new content of the memory element which depend on the input and present state is
referred as next state.

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Combinational Circuit

 Combinational circuits are defined as the time independent circuits which do not
depends upon previous inputs to generate any output .In this output depends only upon
present input.

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Combinational Engineering
Circuit Vs Sequential Circuits

Combinational Circuit
 In this output depends only upon present input.
 There is no feedback between input and output.
 This is time independent.
 Elementary building blocks: Logic gates
 Combinational circuits don’t have capability to store any state.
 As combinational circuits don’t have clock, they don’t require triggering.DON’T WRITE
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 These circuits do not have any memory element. THIS AREA.
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 It is easy to use and handle. .

Examples – Encoder, Decoder, Multiplexer, Demultiplexer

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Combinational Circuit Vs Sequential Circuits
Sequential Circuits
 In this output depends upon present as well as past input.
 Speed is slow.
 There exists a feedback path between input and output.
 This is time dependent.
 Elementary building blocks: Flip-flops
 Mainly used for storing data.
 Sequential circuits have capability to store any state or to retain earlier state.
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 These circuits have memory element. THIS AREA.
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 It is not easy to use and handle. Examples – Flip-flops, Counters .
 Institute ofSequential
Aeronautical Engineering
Circuits

 Types of Sequential Circuits: There are two main types of sequential circuits:
Synchronous & Asynchronous Circuits
 Asynchronous Circuits
• The asynchronous sequential circuits don’t make use of the clock signals. So, the
changes in the input can easily make a change in the state of the circuit. Here, the
internal state gets altered whenever there is a change in the input.
• Unclocked flip flop or time delay is used as memory element.
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• Design of Asynchronous sequential circuits difficult OR PLACE ANY IMAGE IN
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• Since there is no clock signal delay, these are fast compared to the .
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Synchronous Sequential Circuits
 Institute ofSequential
Aeronautical Engineering
Circuits

 Synchronous Circuits
• The clock signal performs the synchronization of the state of memory elements in the
case of synchronous sequential circuits. The output gets synchronized with the clock’s
only positive edges or only the negative edges.
• The memory unit used for governance is clocked flip flop
• It is easy to design Synchronous sequential circuits
• The states of Synchronous sequential circuits are always predictable and thus reliable.
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• There are chances for the Asynchronous circuits to enter into a OR PLACE ANY IMAGE IN
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wrong state because of the time difference between the arrivals of .
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inputs. This is called "race condition"
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Clock

 Clock signal is an electronic logic signal (voltage or current) which oscillates between
a high and a low state at a constant frequency
 Clock signal is a periodic signal and its ON time and OFF time need not be the same.
We can represent the clock signal as a square wave, when both its ON time and OFF
time are same.

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Clock

 Types of Triggering
There are two types of triggering in sequential circuits: Level triggering & Edge
triggering
• Level triggering
There are two levels, namely logic High and logic Low in clock signal.
If the sequential circuit is operated with the clock signal when it is in Logic High,
then that type of triggering is known as Positive level triggering.
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in Logic Low, then that type of triggering is known as Negative level .
triggering.
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Clock

Edge triggering
• There are two types of transitions that occur in clock signal. That means, the
clock signal transitions either from Logic Low to Logic High or Logic High to Logic
Low.
• If the sequential circuit is operated with the clock signal that is transitioning from
Logic Low to Logic High, then that type of triggering is known as Positive edge
triggering.
• If the sequential circuit is operated with the clock signal that is transitioning from
Logic High to Logic Low, then that type of triggering is known as Negative edge
triggering. DON’T WRITE
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Latches Engineering

 Latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals. It is used to store either 1 or 0 at any
specified time.
 Latches can be implemented using various digital logic gates, such as AND, OR,
NOT, NAND, and NOR gates. Latches are useful for the design of the asynchronous
sequential circuit.
 It consists of two outputs, which are complement to each other.
 A gated latch is a latch that has a third input that must be active in order for the
inputs to take effect. This third input is sometimes called ENABLE because it
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enables the operation of the inputs. Latches are level-sensitive devices OR PLACE ANY IMAGE IN
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Flip flops

 Flip-flop is a digital memory circuit, and with the help of the flip-flop we can store one
bit of information.
 The fundamental blocks of various sequential circuits are flip-flops.
 Flip-Flop is sensitive to the clock signals and until there is a change in the clock signal, it
never changes the output.
 There are four kinds of flip-flops:
• Data or Delay (D) Flip-Flop
• JK Flip-Flop
• Toggle (T) Flip-Flop
• SR (Set-Reset) Flip-Flop DON’T WRITE
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Comparison of Latch and FFs

• Flip-Flop and Latches are bistable device, that is there are two stable
states, which are represented as 0 and 1.
• Gates like NOR, NOT, AND, NAND are building blocks of both flip flops and
latches.
• A flip-flop is synchronous ,it works based on the clock signal where as a
latch is asynchronous. It does not work based on the clock signal.
• A Latch is a level triggered device but a Flip-flop is an edge triggered device.
• Flip-flop is sensitive to the applied input and the clock signal where as
Latches are sensitive to the applied input signal- only when enabled.
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• It is quite easy to perform circuit analysis for Flip-flop but analyzing the
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circuit is quite complex for latches.
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SR-Flip Flop: Engineering

 In digital circuits many operations are to be carried out in a proper sequence at the
appropriate time.
 These operations are controlled by clock pulses
 The flip flop output is controlled i.e., neither be set nor reset without the preference of
the clock pulses. Such a flip flop is called as clocked SR-flip flop.

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SR-Flip Flop: Engineering

SR-Flip Flop Using NAND Gates:

 The logic circuit and symbol of clocked SR-Flip Flop using NAND gates is as shown in
figures

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Case (i): S=0, R=0, CP=1 Case (ii): S=0, R=1, CP=1

Case (iii): S=1, R=0, CP=1 Case (iv): S=1, R=1, CP=1
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 The truth table of clocked SR –Flip Flop using NAND gates is as shown in table

Q(t+1)=S+R′Q(t)

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SR-Flip Flop: Engineering

Clocked SR-Flip Flop Using NOR Gates:

 The logic circuit and truth table of clocked SR-Flip Flop using NOR gates is as shown
in figures

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JK-Flip Flop: Engineering

 The basic S-R flip-flop circuit has many advantages and uses in
sequential logic circuits but it suffers from two basic switching
problems.
1. The Indeterminate condition must always be avoided
2. If Set or Reset change state while the enable (EN) input is high
the correct latching action may not occur
 Then to overcome these two fundamental design problems with the DON’T WRITE
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SR flip-flop design, the JK flip Flop was developed. THIS AREA.
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JK-Flip Flop: Engineering

 This simple JK flip Flop is the most widely used of all the flip-flop
designs and is considered to be a universal flip-flop circuit.
 The two inputs labeled “J” and “K” are identical to “S” and “R” inputs
of SR- flip flop. These are chosen by its inventor Jack Kilby to
distinguish the flip-flop design from other types.
 The sequential operation of the JK flip flop is exactly the same as for
the previous SR flip-flop with the same “Set” and “Reset” inputs. DON’T WRITE
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The difference this time is that the “JK flip flop” has no invalid or THIS AREA.
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forbidden input states of the SR Latch even when S and R are both at .

logic “1”.
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 The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S
and R are equal to logic level “1”.

Logic Circuit Of JK Flip Flop

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Q(t+1)=JQ(t)′+K′Q(t) .
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 The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S
and R are equal to logic level “1”.

Logic Circuit Of JK Flip Flop

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There are two essential operating modes in JK Flip Flop: edge-triggered and level-
triggered.
•Edge-Triggered: In this mode, flip flop responds to a signal transition occurring at a
clock pulse. It is commonly used in synchronous systems, where the output changes
only when the clock signal changes from low to high or high to low. The edge-
triggered JK Flip Flop ensures stable output and prevents glitches caused by rapid
changes in input values.
•Level-Triggered: Unlike the edge-triggered mode, the level-triggered JK Flip
Flop responds to the input values continuously as long as the clock signal is held at a
specific level (high or low). This mode is mainly used in asynchronous systems
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 In J-K Flip flop, when J=K=1 the output will oscillates back and forth between 0 and 1 in
the duration tp of the clock pulse width. So at the end of the clock pulse the value of Q
is ambiguous.
 This situation is known as Race Around condition.
 It can be avoided if
tp < T

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 InstituteMaster Slave JK-Flip Engineering
of Aeronautical Flop:

 The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration.
 One flip-flop acts as the “Master” circuit, which triggers on the leading edge of the
clock pulse while the other acts as the “Slave” circuit, which triggers on the falling edge
of the clock pulse.
 The outputs from the “Slave” flip-flop are fed back to the inputs of
the “Master” with the outputs of the “Master” flip flop being DON’T WRITE
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 InstituteMaster Slave JK-Flip Engineering
of Aeronautical Flop:

 The input signals J and K are connected to the gated “master” SR flip flop which “locks”
the input condition while the clock (Clk) input is “HIGH” at logic level “1”.
 s the clock input of the “slave” flip flop is the inverse (complement) of the “master”
clock input, the “slave” SR flip flop does not toggle.

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 InstituteMaster Slave JK-Flip Engineering
of Aeronautical Flop:

Timing Diagram of a Master flip flop –

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 InstituteMaster Slave JK-Flip Engineering
of Aeronautical Flop:

 When the Clock pulse is high the output of master is high and remains high till the clock is
low because the state is stored.
 Now the output of master becomes low when the clock pulse becomes high again and
remains low until the clock becomes high again.
 Thus toggling takes place for a clock cycle.
 When the clock pulse is high, the master is operational but not the slave thus the output
of the slave remains low till the clock remains high.
 When the clock is low, the slave becomes operational and remains high until the clock
again becomes low.
 Toggling takes place during the whole process since the output is
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 This makes the Master-Slave J-K flip flop a Synchronous device as it THIS AREA.
only passes data with the timing of the clock signal. .
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 One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the
indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
 This state will force both outputs to be at logic “1”.
 To prevent this an inverter can be connected between the “SET” and the “RESET” inputs
to produce another type of flip flop circuit known as a Data Latch, Delay flip flop or D-
type Flip Flop

 The S and R inputs become complements of each other ensuring DON’T WRITE
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that the two inputs S and R are never equal (0 or 1) to each other at THIS AREA.
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the same time allowing us to control the toggle action of the flip-flop .

using one single D (Data) input.

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 D Flip-flops are used as a part of memory storage elements and data

processors as well. DON’T WRITE
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 The major applications of D flip-flop are to introduce delay in timing THIS AREA.
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circuit, as a buffer, sampling data at specific intervals. .
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 When D=1; clock=0; then s’=1, r’=1 and there is Clock Input Output
no change in output Q. D Q(t+1) Q’(t+1)
 When D=1; clock=1; then s’=0, r’=1 ,Q=1; Q’=0.
0 X Q(t) Q’(t)
Therefore output Q=D
1 0 0 1
 When D=0; clock=0; then s’=1, r’=1 and there is
no change in output Q. 1 1 1 0

 When D=1; clock=1; then s’=1, r’=0 Q=0; Q’=1. DON’T WRITE
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Therefore output Q=D THIS AREA.
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 The next state equation of D-flip flop is .

Qt+1= D
 T-Flip Flop: Engineering
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 T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same

input ‘T’ to both inputs of JK flip-flop.
 It operates with only positive clock transitions or negative clock transitions.

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 T flip-flop can be used for one of these two functions such as Hold, & Complement of
present state based on the input conditions, when positive transition of clock signal is
applied.
 The output of T flip-flop always T Q(t) Q(t+1)
toggles for every positive transition of 0 0 0
the clock signal, when input T 0 1 1
remains at logic High 1. Hence, T flip- 1 0 1 DON’T WRITE
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flop can be used in counters. THIS AREA.
1 1 0 .
Q(t+1) = T′Q(t) + TQ(t)′ .

⇒Q(t+1)=T ⊕ Q(t)
 Flip
Institute ofFlop Excitation Tables:
Aeronautical Engineering

 The excitation table has the minimum inputs, which will excite or trigger the flip flop to
go from its present state to the next state.
 It is derived from the truth table.
 Generally, the operation of each flip flop is explained with the help of the truth table.
 The truth table has all the input combinations, for which the flip flop reacts to produce
the next state output.

 The excitation table consists of two columns for present state(Qn) DON’T WRITE
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and next state(Qn+1) and one or two column for each inputs. The THIS AREA.
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input columns depend on the type of the flip flop. .
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Institute FlipAeronautical
Flop ExcitationEngineering
Table

Excitation Table of SR Flip Flop

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Truth Table of SR Flip Flop  The excitation table of SR flip flop can be constructed from.
the information available in the truth table.
 SR-Flip
Institute Flop ExcitationEngineering
of Aeronautical Table:

 For the state transition from Qn = 0 to Qn+1 = 0, the excitation inputs required are S = 0
and R = 0 or 1. Since R has two values(0 and 1), it is denoted as don’t care condition(x).
 To obtain the next state output Qn+1 = 1 from the present state input Qn = 0, the required
SR inputs are S = 1 and R = 0. Thus the excitation inputs required are S = 1 and R = 0.
 The state transition from present state Qn = 1 to the next state Qn+1 = 0 happens only
when the inputs are S = 0 and R = 1.

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 The state transition from Qn = 1 to Qn+1 = 1 happens at S = 0, R = 0 OR PLACE ANY IMAGE IN
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and S = 1, R = 0. It is filled in the fourth row of the excitation table .
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as Qn = 1, Qn+1 = 1 and S = x, R = 0.
 JK-Flip
Institute Flop ExcitationEngineering
of Aeronautical Table:

Excitation Table of JK Flip Flop

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Truth Table of JK Flip Flop .
 JK-Flip
Institute Flop ExcitationEngineering
of Aeronautical Table:

 For the present state and next state values Qn = 0 and Qn+1 = 0, the inputs are J = 0 and K
= 0 or 1. Since K input has two values, it is considered as don’t care condition(x).
 The state transition from Qn = 0 to Qn+1 = 0 takes place when J = 0, K = x.
 The state transition from present state Qn = 0 to the next state Qn+1 = 1 occur, when the
inputs are either J = 1, K = 0 or J = 1, K = 1. Thus for Qn = 0, Qn+1 = 1 the value of J = 1 and
K = x.
 For the transition of the state from 1 to 0, the inputs are J = 0, K = 1
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 For the state transition from Qn = 1 to Qn+1 = 1, the J input can be 0 .
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or 1 but the K input remains at 0 therefore the inputs are J = x and K
= 0.
 D-Flip
Institute Flop Excitation Engineering
of Aeronautical Table:

Excitation Table of D Flip-Flop:

 The excitation table of D flip flop can be constructed from the information available in
the truth table.
 The truth table of D flip flop is
as shown here

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 D-Flip
Institute Flop Excitation Engineering
of Aeronautical Table:

Excitation Table of D-Flip Flop

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 T-Flip
Institute Flop Excitation Engineering
of Aeronautical Table:

Excitation Table of T Flip-Flop:

 The excitation table of T flip flop can be constructed from the information available in
the truth table.
 The truth table of T flip flop is
as shown here

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 T-Flip
Institute Flop Excitation Engineering
of Aeronautical Table:

Excitation Table of T Flip Flop

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 T-Flip
Institute Flop Excitation Engineering
of Aeronautical Table:

 From the truth table, we can observe that, when T input is 0, there
is no change in the state.
 So for the state transition from the present state to the next state,
i.e., from Qn = 0 to Qn+1 = 0 and from Qn = 1 to Qn+1 = 1, the
excitation input require is T = 0.
 From the truth table, we can also observe, when T = 1, the state of
the flip flop toggles or complemented.
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0, the excitation input is T = 1. .
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 Institute of Aeronautical
SR-Latch: Engineering

 An SR latch (Set/Reset) is an asynchronous device. It works independently of control

signals and relies only on the state of the S and R inputs. It stores one bit of information.
 It has two inputs and two outputs which are complement to each other.
 It can be constructed from either two NOR gates or two NAND gates
NOR SR-Latch:

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Circuit Symbol For .
SR- Latch NOR SR- Latch
 Institute of Aeronautical
SR-Latch: Engineering

Case (i): S=1, R=0 Case (ii): S=0, R=1

Case (iii): S=0, R=0 Case (iv): S=1, R=1

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SR-Latch: Engineering

Truth Table of NOR SR- Latch

INPUT OUTPUT
INPUT OUTPUT
S R Q(t) Q(t+1) Q’(t+1) S R Q(t+1)
0 0 0 0 1 0 0 Q(t) (No Change)
0 0 1 1 0 0 1 0(Reset)

0 1 0 0 1 1 0 1(Set)

0 1 1 0 1 1 1 X (Indeterminate)

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1 0 1 1 0 THIS AREA.
1 1 0 0 0 .
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1 1 1 0 0
 Institute of Aeronautical
SR-Latch: Engineering

 NAND SR-LATCH

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Case (i): S=0, R=0 Case (ii): S=0, R=1

Case (iii): S=1, R=0 Case (iv): S=1, R=1

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Truth Table of NAND SR- Latch

INPUT OUTPUT
INPUT OUTPUT
S R Q(t) Q(t+1) Q’(t+1) S R Q(t+1)
0 0 0 1 1 0 0 X (Indeterminate)
0 1 1 (Set)
0 0 1 1 1
1 0 0 (Reset)
0 1 0 1 0
1 1 Q(t) (N0 Change)
0 1 1 1 0

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1 1 0 0 1 .
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1 1 1 1 0
 Institute of Aeronautical Engineering
Gated SR Latch
Side Heading

Latch is sensitive to input changes ONLY when C=1

A gated latch is a latch that has a third input that must be active in order for the SET
and RESET inputs to take effect. This third input is sometimes called ENABLE
because it enables the operation of the SET and RESET inputs.

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 Institute ofFlip Flop Conversion
Aeronautical Engineering

Procedure for converting one flip flop to another flip flop:

 Step 1: Write the Truth Table of the Desired Flip-Flop
 Step 2: Obtain the Excitation Table for the given Flip-Flop from its
Truth Table
 Step 3: Append the Excitation Table of the given Flip-Flop to the
Truth Table of the Desired Flip-Flop Appropriately to obtain
Conversion Table DON’T WRITE
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 Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop THIS AREA.
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 Step 5: Design the Necessary Circuit and make the Connections .

accordingly
 Problem 1: Engineering
Institute of Aeronautical

1. Convert SR Flip-Flop to JK
Step 1: Write the Truth Table of the Desired Flip-Flop

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 Problem 1: Engineering
Institute of Aeronautical

 Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table

 Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the
Desired Flip-Flop Appropriately to obtain Conversion Table

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 Problem 1: Engineering
Institute of Aeronautical

 Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop

 Step 5: Design the Necessary Circuit and make the Connections accordingly

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 Problem 2: Engineering
Institute of Aeronautical

2.Using the method of flip flop conversion carry out S-R to T conversion.
3.Convert the following flip flops into JK flip flop
i) SR flip-flop ii) T flip- flop.

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 Registers: Engineering
Institute of Aeronautical

 Flip-flop is a 1 bit memory cell which can be used for storing the digital data.
 To increase the storage capacity in terms of number of bits, we have to use a group of
flip-flop. Such a group of flip-flop is known as a Register.
 The n-bit register will consist of n number of flip-flop and it is capable of storing an n-
bit word.
 The binary data in a register can be moved within the register from one flip-flop to
another.
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 The registers that allow such data transfers are called as shift OR PLACE ANY IMAGE IN
THIS AREA.
registers. .
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 The bits stored in registers shifted when the clock pulse is applied
 Shift Registers: Engineering
Institute of Aeronautical

 A Shift Register can shift the bits either to the left or to the right. A Shift Register, which
shifts the bit to the left, is known as "Shift left register", and it shifts the bit to the right,
known as " Shift Right register".
 There are four mode of operations of a shift register.
1. Serial Input Serial Output
2. Serial Input Parallel Output
3. Parallel Input Serial Output
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4. Parallel Input Parallel Output OR PLACE ANY IMAGE IN
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5. Bi-directional Shift Register .
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6. Universal Shift Register
 Serial of
Institute In Serial out Shift Registers:
Aeronautical Engineering

 In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially.
 In SISO, a single bit is shifted at a time in either right or left direction under clock control.
 Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0.
 The D input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is
connected to the input of the next flip-flop i.e. D2 and so on.
 The block diagram of the "Serial IN Serial OUT" is

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 Serial of
Institute In Serial out Shift Registers:
Aeronautical Engineering

 When the clock signal application is disabled, the outputs Q3 Q2 Q1 Q0 = 0000. The LSB bit
of the number is passed to the data input Din, i.e., D3.
 We will apply the clock, and this time the value of D3 is 1. The first flip flop, i.e., FF-3, is
set, and the word is stored in the register at the first falling edge of the clock. Now, the
stored word is 1000.

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 Serial of
Institute In Serial out Shift Registers:
Aeronautical Engineering

 Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-
2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

 As soon as the third negative clock edge hits, FF-1 will be set and output will be modified
to Q3 Q2 Q1 Q0 = 1110.
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 Serial of
Institute In Serial out Shift Registers:
Aeronautical Engineering

 with the fourth negative clock edge arriving, the stored word in the register is
Q3 Q2 Q1 Q0 = 1111.

 Truth Table:

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 Serial of
Institute In Serial out Shift Registers:
Aeronautical Engineering

 Waveforms:

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 Serial In
Institute ofParallel Out ShiftEngineering
Aeronautical Registers:

 In the "Serial IN Parallel OUT" shift register, the data is passed

serially to the flip flop, and outputs are fetched in a parallel way.
 Data is loaded bit by bit. The outputs are disabled as long as the data
is loading.
 As soon as the data loading gets completed, all the flip-flops contain
their required data, the outputs are enabled so that all the loaded
data is made available over all the output lines at the same time.
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 4 clock cycles are required to load a four bit word. Hence the speed OR PLACE ANY IMAGE IN
THIS AREA.
of operation of SIPO mode is same as that of SISO mode. .
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 Serial In
Institute ofParallel Out ShiftEngineering
Aeronautical Registers:

 In SIPO, the input of the second flip flop is the output of the first flip flop, and so on.
 The same clock signal is applied to each flip flop since the flip flops synchronize each
other.
 The parallel outputs are used for communication.

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 Parallelof
Institute InAeronautical
Serial Out ShiftEngineering
Registers:

 In the "Parallel IN Serial OUT" register, the data is entered in a

parallel way, and the outcome comes serially. A four-bit "Parallel IN
Serial OUT" register is designed below.
 Output of previous Flip Flop is connected to the input of the next
one via a combinational circuit.
 The binary input word B0, B1, B2, B3 is applied though the same
combinational circuit.
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 There are two modes in which this circuit can work namely - shift OR PLACE ANY IMAGE IN
THIS AREA.
mode or load mode. .
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 Parallelof
Institute InAeronautical
Serial Out ShiftEngineering
Registers:

Block Diagram of PISO Register

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 Parallelof
Institute InAeronautical
Serial Out ShiftEngineering
Registers:

Load mode:
 When the shift or load bar line set to 0.
 The second, fourth, and sixth "AND" gates are active hence the bits
B0, B1, B2, and B3 are passed to the corresponding flip flops when.
 The binary inputs B0, B1, B2, and B3 will be paralelly loaded into the
respective flip-flops when the edge of the clock is low.
Shift mode:
 The second, fourth, and sixth gates are inactive when the load and
shift line set to 0. So, we are not able to load data in a parallel way.
 At this time, the first, third, and fifth gates will be activated, and the DON’T WRITE
shifting of the data will be left to the right bit. OR PLACE ANY IMAGE IN
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 Parallel Input Parallel
Institute Output (PIPO)
of Aeronautical Shift Registers:
Engineering

 In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the
data inputs D0, D1, D2, D3 respectively of the four flip-flops.
 As soon as a negative clock edge is applied, the input binary bits will
be loaded into the flip-flops simultaneously.
 The loaded bits will appear simultaneously to the output side. Only
clock pulse is essential to load all the bits.
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 Parallel Input Parallel
Institute Output (PIPO)
of Aeronautical Shift Registers:
Engineering

Block Diagram of Parallel In Parallel Out Register:

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 Bidirectional
Institute Shift Register:
of Aeronautical Engineering

 The binary number after shifting each bit of the number to the left
by one position will be equivalent to the number produced by
multiplying the original number by 2
 The binary number after shifting each bit of the number to the right
by one position will be equivalent to the number produced by
dividing the original number by 2.
 To perform the multiplication and division operation using the shift
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register, it is required that the data should be moved in both the OR PLACE ANY IMAGE IN
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direction, i.e., left or right in the register. Such registers are called .
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the "Bidirectional" shift register.
 Bidirectional
Institute Shift Register:
of Aeronautical Engineering

Block Diagram of Bidirectional Shift Register

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 DR is the "serial right shift data input", DL is the "left shift data .

input", and M is the "mode select input“.

 Bidirectional
Institute Shift Register:
of Aeronautical Engineering

Shift right operation(M=1)

 The first, third, fifth, and seventh AND gates will be enabled, but the second, fourth, sixth,
and eighth AND gates will be disabled.
 The data present on the data input DR is shifted bit by bit from the fourth flip flop to the
first flip flop when the clock pulse is applied.

Shift left operation(M=0)

 The second, fourth, sixth and eighth AND gates will be enabled, but
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 The data present on the data input DR is shifted bit by bit from the .
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first flip flop to the fourth flip flop when the clock pulse is applied.
 Universal
Institute Shift Register:
of Aeronautical Engineering

 A register where the data is shifted in one direction is known as

the "uni-directional" shift register.
 A register in which the data is shifted in both the direction is known
as "bi-directional" shift register.
 A "Universal" shift register is a special type of register that can load
the data in a parallel way and shift that data in both directions, i.e.,
right and left.
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 The design of a 4-bit universal shift register OR PLACE ANY IMAGE IN
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using multiplexers and flip-flops. .
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 Universal
Institute Shift Register:
of Aeronautical Engineering

Block Diagram: Truth Table:

S1 S0 Mode of Operation

0 0 No Change

0 1 Shift Right

1 0 Shift left

1 1 Parallel Loading

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 Shift Register:Engineering
Institute of Aeronautical

Applications of shift registers:

 Shift register is used as Parallel to serial converter, which converts
the parallel data into serial data. It is utilized at the transmitter
section after Analog to Digital Converter ADC block.
 Shift register is used as Serial to parallel converter, which converts
the serial data into parallel data. It is utilized at the receiver section
before Digital to Analog Converter DAC block.
 Shift register along with some additional gates generate the
sequence of zeros and ones. Hence, it is used as sequence generator.
 Shift registers are also used as counters. There are two types of
counters based on the type of output from right most D flip-flop is DON’T WRITE
OR PLACE ANY IMAGE IN
connected to the serial input. Those are Ring counter and Johnson THIS AREA.
Ring counter. .
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 Institute Sequence
of Aeronautical Engineering
generator

• The sequence generator generates a sequence of binary

bits (information).
• The length of the sequence is related to the number of
flip-flops that are required to produce a sequence
generator.
• First, count the number of zeros and ones in the given
sequence,let this number will be ‘N’.
• The no. of flip flops can be calculated as N = 2n-1
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 Institute Sequence
of Aeronautical Engineering
generator

• Write the bits in vertical order.

• Form groups of n bits starting from the top bit and convert
them to state numbers
• If entire train ofpulse can be examined without repeating a
state,the design can be done by n FFs.
• If there is a repetition of states take n+1 FFs.
• If repeated states still occur,take n+2 FFs

• Design a pulse train generator using shift register for the DON’T WRITE
following pulse train ......111010...... OR PLACE ANY IMAGE IN
THIS AREA.
• Design a pulse train generator using shift register for the
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following pulse train ......1110...... .
 Pseudo Random
Institute Binary Sequence
of Aeronautical generator
Engineering

• A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear
function of its previous state.
• The most commonly used linear function of single bits is exclusive-or(XOR).
• LFSR can generate a pseudo-random binary sequence using an n-bit shift register with
feedback through an exclusive or (XOR) function.
• The sequence of random numbers is a function of the current state and some previous
states.

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 Pseudo Random
Institute Binary Sequence
of Aeronautical generator
Engineering

• An LFSR has 3 configurable parameters

• number of bits in the register - n
• initial n-bit seed value - seed
• position of taps for XOR - taps

• The length of the cycle depends on the seed value and the tap configuration.

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 Counters: Engineering
Institute of Aeronautical

 A counter is a sequential circuit, which counts the number of pulses

produced by the clock input.
 The counter is one of the major applications of flip-flops.
 There are also several types of the counter.
 The value of the counter represents the number of clock pulses
arrived at the clock input.
 When the clock pulses are counted in an increasing way, it is
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 In the down counter, the count value is decremented by one on the .
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arrival of each clock pulses.
 Counters: Engineering
Institute of Aeronautical

 An n-bit binary counter can count up to n bits. The n-bit counter will have n number of flip
flops and has 2n distinct output states.
 For example, 2-bit counter has 2 flip lops and has 22 = 4 distinct states(00, 01, 10, 11).
Similarly, 3-bit counter will have 3 flip flops and has 23 = 8 distinct states(000, 001, 010,
011, 100, 101, 110, 111).

 A binary counter has a maximum count limit of 2n – 1.

 a 3-bit counter can have a maximum count of 23 – 1 = 7(in binary, it DON’T WRITE
OR PLACE ANY IMAGE IN
is equivalent to ‘111’). THIS AREA.
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 After reaching the maximum count of a counter, the counter will .

reset itself for the next clock pulse input and starts to count again.
 Counters: Engineering
Institute of Aeronautical

Types of counter:
 Counters are constructed with a series of flip-flops. Based on the input and the clock
pulses given to the flip-flops, there are several types of counters.
1. Asynchronous counter
2. Synchronous counter
3. Ring counter
4. Johnson counter
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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 It consists of a series of flip flops, in which the output of each flip flop is connected to the
clock input of the next higher-order flip flop.
 The clock pulse is given to the first flip-flop.
 The flip flops in the asynchronous counter are triggered individually, that is, they are not
synchronized.
 It is also called a Ripple counter.

 Asynchronous counters are further classified as: DON’T WRITE

OR PLACE ANY IMAGE IN
1. Asynchronous up counter, THIS AREA.
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2. Asynchronous down counter .

3. Asynchronous up/down counter.

 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

2-bit asynchronous up counter:

 For a 2-bit asynchronous counter, 2 flip-flops are used
 where the count is incremented for each clock pulse.
 A 2-bit counter will have 22 = 4 distinct states(00, 01, 10, 11).

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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 The clock pulse input is given to the first flip-flop only.

 The output(QA) of the first flip-flop is fed as the clock input for the
second flip-flop. DON’T WRITE
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 The HIGH or logic 1 is maintained at the T-input of both flip-flops. THIS AREA.
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 The clock pulse is digitally counted at the output QA and QB, where .

QA is the LSB and QB is the MSB.

 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 At every falling edge of the clock pulse, T FF1 will toggle its output state
 The output of the first flip-flop(FF1) is given as a clock pulse input for the second flip-
flop(FF2). At the every falling edge of QA output of FF1, the FF2 will get triggered and
produces a toggled output.

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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

3-bit asynchronous up counter

 The 3-bit asynchronous counter uses 3 T-flip-flops.
 This counter consists of 23 = 8 count states(000, 001, 010, 011, 100, 101, 110, 111). The
counter counts the incoming pulses starting from 0 to 7.

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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 the clock pulse is given as clock input for FF1.

 For the other flip-flops, the clock input is fed from the output of
previous flip-flops. DON’T WRITE
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 The clock pulse count is noted at the output of each flip- THIS AREA.
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flop(QCQBQA), where QA is the LSB and QC is the MSB. .
 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 At the falling edge of each clock pulse, the output of FF1 toggles.
 For each logic HIGH output(QA = 1) of FF1, at its falling edge, FF2 will toggle the
output(QB).
 Similarly, for each logic HIGH output(QB = 1) of FF2, FF3 will toggle the output(QC).

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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

3-bit asynchronous down counter

 The down counter will count the clock pulses from maximum value to zero. In other
words, for each clock pulse, the count value is decremented.
 The clock pulse input is given only to the first flip-flop. The clock input of the remaining
flip-flops is triggered by the Q output of the previous flip-flop.
 Since it is down counter, the 3-bit count value is measured from the (QC‘QB‘QA‘), where QC‘
is the MSB and QA‘ is the LSB.
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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

 If the output is taken at the normal Q output of each flip flop, then it
is an up counter. DON’T WRITE
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 If the output is taken at the complemented output (Q’) of each flip THIS AREA.
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flop, it is said to be the down counter. .
 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

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 Asynchronous
Institute counter / Ripple
of Aeronautical counter:
Engineering

Asynchronous Up/Down counter (or) Bidirectional counter

 For asynchronous up/down counter, control input is necessary for the control of the
operation as up or down counter.

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 When the control input is 1, gates 1 and 3 are enabled and gates 2 THIS AREA.
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and 4 are disabled. This makes a way for the Q output of flip-flops to .

drive the clock input of the next stage flip-flop.

 Synchronous
Institute of counter:
Aeronautical Engineering

Synchronous counter
 The synchronous counter is also an application of flip-flop
 If each flip flop in the counter is triggered at the same time through the clock pulse input,
it is said to be synchronous counter.
 To design a synchronous counter, Toggle flip-flop or T flip-flop is used. The clock pulse is
given to all the flip-flops in the counter.
 Synchronous counters are further classified as
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1. Synchronous up counter, OR PLACE ANY IMAGE IN
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2. Synchronous down counter .
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3. Synchronous up/down counter.
 Synchronous
Institute of counter:
Aeronautical Engineering

3-bit synchronous up counter

 Synchronous up Counter counts the number of clock pulses at its input from minimum to
maximum. A 3-bit counter consists of 3 flip-flops and has 23 = 8 states from 000 to 111.
 The TA input for the first T-flip-flop TFF1 is always maintained at logic HIGH. The output of
TFF1 is fed as an input for TFF2.
 The QA and QB output of TFF1 and TFF2 are ANDed together and its output is given to the
TFF3. The output states of the counter can be observed at QCQBQA.
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 Synchronous
Institute of counter:
Aeronautical Engineering

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 Synchronous
Institute of counter:
Aeronautical Engineering

4-bit Synchronous up counter

 A 4-bit synchronous up counter can be designed with 4 flip-flops.
 It has 16 output states, that this counter can count from 0000 to 1111.

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 The operation is similar to that of a 3-bit counter .
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 Synchronous
Institute of counter:
Aeronautical Engineering

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 Synchronous
Institute of counter:
Aeronautical Engineering

Synchronous Up/Down counter (or) Bidirectional counter

 The synchronous Counter can be made to operate as an up counter and as a down counter
with the help of control signals. Since it is capable of counting in either direction, It is also
called a bidirectional counter.

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 Synchronous
Institute of counter:
Aeronautical Engineering

 When control input = 1, it will disable the AND gates 2, 4 and enable gates 1, 3. At this
condition, the counter will count upwards.

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 Synchronous
Institute of counter:
Aeronautical Engineering

 When the control input is 0, it will enable the AND gates 2, 4 and disable gates 1, 3. Using
this condition, the counter will count downwards from 111(7) to 000(0).

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 Ring Counter: Engineering
Institute of Aeronautical

 A ring counter is a special type of application of the Serial IN

Serial OUT Shift register.
 The only difference between the shift register and the ring
counter is that the last flip flop output is taken as the output in
the shift register.
 In the ring counter, this output is passed to the first flip flop as an
input.
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No. of states in Ring counter = No. of flip-flop used OR PLACE ANY IMAGE IN
THIS AREA.
 The block diagram of the 4-bit ring counter is .
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 Ring Counter: Engineering
Institute of Aeronautical

 The same clock pulse is passed to the clock

input of all the flip flops as a synchronous
counter.
 The Overriding input(ORI) is used to design
this circuit where it is used
as clear and pre-set.
PR = 0, Q = 1
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 These two values(always fixed) are THIS AREA.
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independent with the input D and the .

Clock pulse (CLK).

 Ring Counter: Engineering
Institute of Aeronautical

 CLR and PR inputs are active low inputs

 The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0.
 The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed
to the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3.
 The pre-set input set to 0 for the first flip flop. So, the output of the first flip flop is one,
and the outputs of the remaining flip flops are 0.
 When the ORI input set to high, and the low clock pulse signal is
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passed as the negative clock edge triggered. OR PLACE ANY IMAGE IN
THIS AREA.
 A ring forms the pre-set 1 is shifted to the next flip-flop at each .
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clock pulse.
 So, 4-bit counter, 4 states are possible which are as follows
 Ring Counter: Engineering
Institute of Aeronautical

 Truth Table:

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 Institute Johnson Ring Counter:
of Aeronautical Engineering

 The Johnson counter is similar to the Ring counter.

 The only difference between the Johnson counter and the ring counter is that the
outcome of the last flip flop is passed to the first flip flop as an input.In Johnson counter,
the inverted outcome Q' of the last flip flop is passed as an input.
 It is also known as Twisted / Switch Tail Ring Counter
 In Johnson counter
No. of states in Johnson counter = No. of flip-flop used
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Number of used states=2n OR PLACE ANY IMAGE IN
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Number of unused states=2n - 2*n .
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 Institute Johnson Ring Counter:
of Aeronautical Engineering

CLR CP Q1 Q2 Q3 Q4
 Logic Circuit of Johnson Ring Counter:
X 0 0 0 0
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
1 0 1 1 1
1 0 0 1 1
1 0 0 0 1
1 0 0 0 0
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 Like Ring counter, four D flip flops are used in the 4-bit Johnson OR PLACE ANY IMAGE IN
THIS AREA.
counter, and the same clock pulse is passed to all the input of .
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the flip flops.
 Institute Johnson Ring Counter:
of Aeronautical Engineering

Advantages
 The Johnson counter counts twice the number of states the ring counter can count.
 The Johnson counter can also be designed by using D or JK flip flop.
 The data is count in a continuous loop in the Johnson ring counter.
 The circuit of the Johnson counter is self-decoding.

Disadvantages
 The Johnson counter is not able to count the states in a binary
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 In the Johnson counter, the unutilized states are greater than the THIS AREA.
states being utilized. .
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 InstituteAsynchronous Counters:
of Aeronautical Engineering

The asynchronous or ripple counter consists of series of flip-flops which are not synchronized
by the same clock pulse.
Design steps of synchronous counter
 Find the number of flip flops using 2n ≥ N, where N is the number of states and n is the
number of flip flops.
 Choose the type of flip flop.
 Draw the state table and state diagram.
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 Derive the flip flop reset input functions. OR PLACE ANY IMAGE IN
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(connect to clear pin using nand gate) .
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 Draw the logic circuit diagram.
 Problem 1: Engineering
Institute of Aeronautical

1) Design a BCD ripple counter using JK flip flops.

Solution:
 Step 1: Find the number of flip-flops
BCD is the 4-bit number and there are 9 valid states in a 4-bit BCD. Hence 4 flip-flops
should be used in the design.
The valid states are 0000, 0001, 0010, … 1001.
 Step 2: Choose the type of flip-flop.
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Let us design the BCD ripple / asynchronous counter with JK flip-flops. OR PLACE ANY IMAGE IN
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 Step 3: Draw the truth table for BCD ripple counter. .
 Problem 1: Engineering
Institute of Aeronautical

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 Problem 2: Engineering
Institute of Aeronautical

2) Design a Mod-6 asynchronous counter using JK flip flops.

Solution:
 Step 1: Find the number of flip-flops
Mod-6 counter represents that the counter will have 6 states. Thus, N =6.
The number of flip-flops used for counter design is determined using the formula, 2n ≥ N.
The number of flip-flops, n = 3.Hence the 6 counter states are 000, 001, 010, 011, 100, 101.
 Step 2: Choose the type of flip-flop.
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 Step 3: Draw the truth table for mod-6 asynchronous counter. .
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 Problem 2: Engineering
Institute of Aeronautical

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 Step 4: Use Kmap to find the reset logic function. OR PLACE ANY IMAGE IN
THIS AREA.
The above truth table for Mod-6 counter is implemented in .
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a Karnaugh map to get the reset logic function.
 Institute Synchronous Counters:
of Aeronautical Engineering

.
Design steps of synchronous counter
 Find the number of flip flops using 2n ≥ N, where N is the number of states and n is the
number of flip flops.
 Choose the type of flip flop.Write excitation table for that particular flip flop.
 Draw the state table for synchronous counter.
 Use K-map to derive the flip flop reset input functions.
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 Draw the logic circuit diagram. OR PLACE ANY IMAGE IN
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 Problem 1: Engineering
Institute of Aeronautical

1) Design a Mod 8 synchronous counter using JK flip flops.

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 Problem 1: Engineering
Institute of Aeronautical

 The excitation table for the 3-bit synchronous counter is determined from the excitation
table of JK flip flop.
 The excitation table is framed for 8 states of the counter. Since 3 flip-flops are used in the
design, the present state, next state and flip flop inputs for each flip flop are considered.

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 Problem 1: Engineering
Institute of Aeronautical

 Step 5: Derive the flip flop input functions.

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 Problem 1: Engineering
Institute of Aeronautical

 Step 6: Draw the logic diagram of the counter.

Draw the 3 JK flip-flops. The common clock input is given to all the flip-flops.
The inputs for each flip-flop are drawn as per the logic functions derived in the previous
step.
JA=KA=1, JB=KB=QA and JC=KC=QA.QB

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 Problem 2: Engineering
Institute of Aeronautical

2) Design a MOD-5 synchronous counter using flip flops and Implement it? Also draw the
timing diagram?
Solution:

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