RM0454

Reference manual
STM32G0x0 advanced Arm®-based 32-bit MCUs

Introduction
This reference manual complements the datasheets of the STM32G0x0 microcontrollers,
providing information required for application and in particular for software development. It
pertains to the superset of feature sets available on STM32G0x0 microcontrollers.
For feature set, ordering information, and mechanical and electrical characteristics of a
particular STM32G0x0 device, refer to its corresponding datasheet.
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ technical
reference manual.

Related documents
• “Cortex®-M0+ Technical Reference Manual”, available from: http://infocenter.arm.com
• PM0223 programming manual for Cortex®-M0+ core(a)
• STM32G0x0 datasheets(a)
• AN2606 application note on booting STM32 MCUs(a)

a. Available on STMicroelectronics website www.st.com

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Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 45
2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.4 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.1 FLASH Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.1 FLASH memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.2 FLASH empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.3 FLASH error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.4 FLASH read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.5 FLASH memory acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.6 FLASH program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.7 FLASH Main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.8 FLASH Main memory programming sequences . . . . . . . . . . . . . . . . . . 59
3.3.9 Read-while-write (RWW) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.1 FLASH option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.2 FLASH option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.5.1 FLASH read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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3.5.2 FLASH write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.7.1 FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 74
3.7.2 FLASH key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.7.3 FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 75
3.7.4 FLASH status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.7.5 FLASH control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.7.6 FLASH ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.7.7 FLASH ECC register 2 (FLASH_ECCR2) . . . . . . . . . . . . . . . . . . . . . . . 80
3.7.8 FLASH option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . 80
3.7.9 FLASH WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 82
3.7.10 FLASH WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 82
3.7.11 FLASH WRP2 area A address register (FLASH_WRP2AR) . . . . . . . . . 83
3.7.12 FLASH WRP2 area B address register (FLASH_WRP2BR) . . . . . . . . . 84
3.7.13 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.1.1 ADC reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.2 Battery backup of RTC domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.1.4 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.1 Power-on reset (POR) / power-down reset (PDR) . . . . . . . . . . . . . . . . . 90
4.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.3.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3.6 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.3.7 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.8 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3.9 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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4.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 110
4.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 111
4.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 111
4.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 112
4.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 112
4.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 113
4.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 113
4.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 114
4.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 114
4.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 115
4.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 115
4.4.18 Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 115
4.4.19 Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 116
4.4.20 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.1.3 RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.2.7 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 128
5.2.8 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.2.9 Clock security system for LSE clock (LSECSS) . . . . . . . . . . . . . . . . . 129
5.2.10 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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5.2.11 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.2.12 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.13 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.14 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2.15 Internal/external clock measurement with TIM14/TIM16/TIM17 . . . . . 131
5.2.16 Peripheral clock enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.4.2 Internal clock source calibration register (RCC_ICSCR) . . . . . . . . . . . 136
5.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 137
5.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 140
5.4.5 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 143
5.4.6 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 143
5.4.7 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 145
5.4.8 I/O port reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . 146
5.4.9 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 147
5.4.10 APB peripheral reset register 1 (RCC_APBRSTR1) . . . . . . . . . . . . . . 148
5.4.11 APB peripheral reset register 2 (RCC_APBRSTR2) . . . . . . . . . . . . . . 150
5.4.12 I/O port clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . 151
5.4.13 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 152
5.4.14 APB peripheral clock enable register 1 (RCC_APBENR1) . . . . . . . . . 153
5.4.15 APB peripheral clock enable register 2(RCC_APBENR2) . . . . . . . . . . 155
5.4.16 I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . 157
5.4.17 AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.4.18 APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.4.19 APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.4.20 Peripherals independent clock configuration register (RCC_CCIPR) . 163
5.4.21 Peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.4.22 RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 165
5.4.23 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.4.24 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 175
6.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 181
6.3.14 Using the GPIO pins in the RTC domain . . . . . . . . . . . . . . . . . . . . . . . 181
6.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.4.1 GPIO port mode register (GPIOx_MODER)
(x =A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . . . . . . . . . 187
6.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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7 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 189

7.1 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 189
7.1.2 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 192
7.1.3 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . . . . 194
7.1.4 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . . . . 194
7.1.5 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . . . . 195
7.1.6 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . . . . 195
7.1.7 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . . . . 196
7.1.8 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . . . . 196
7.1.9 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . . . . 196
7.1.10 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . . . . 197
7.1.11 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . . . . 197
7.1.12 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . . 198
7.1.13 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . . 198
7.1.14 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . . 199
7.1.15 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . . 199
7.1.16 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . . 199
7.1.17 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . . 200
7.1.18 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . . 200
7.1.19 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . . 200
7.1.20 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . . 201
7.1.21 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . . 201
7.1.22 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . . 201
7.1.23 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . . 202
7.1.24 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . . 202
7.1.25 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . . 202
7.1.26 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . . 203
7.1.27 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . . 203
7.1.28 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . . 204
7.1.29 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . . 204
7.1.30 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . . 204
7.1.31 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

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8.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.3.1 From TIM1, TIM3, TIM4, TIM15, TIM16, and TIM17,
to TIM1, TIM3, TIM4, and TIM15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8.3.2 From TIM1, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC . . . . . . . . . 210
8.3.3 From ADC to TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
8.3.4
From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM14,
TIM16, and TIM17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
8.3.5

From internal analog sources to ADC 211

8.3.6 From system errors to TIM1, TIM3, TIM4, TIM15, TIM16,
and TIM17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
8.3.7 From TIM16, TIM17, USART1, and USART4, to IRTIM . . . . . . . . . . . 212
8.3.8 From TIM14 to DMAMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

9 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 213

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
9.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
9.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.3.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.4.2 DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.4.3 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.4.4 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
9.4.5 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.4.6 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 220
9.4.7 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 223
9.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 225
9.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 226
9.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 229
9.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 230
9.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 230

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9.6.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

10 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 234

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
10.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
10.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
10.3.1 DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
10.3.2 DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
10.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
10.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
10.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
10.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
10.4.4 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
10.4.5 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
10.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
10.6.1 DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
10.6.2 DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
10.6.3 DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
10.6.4 DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
10.6.5 DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
10.6.6 DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
10.6.7 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 250

11.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
11.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
11.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

12 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 253

12.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
12.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

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12.2.1 EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . . 255

12.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.3.1 EXTI configurable event input wakeup . . . . . . . . . . . . . . . . . . . . . . . . 256
12.3.2 EXTI direct event input wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.3.3 EXTI mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
12.4 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
12.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12.5.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 259
12.5.2 EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . 260
12.5.3 EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . 260
12.5.4 EXTI rising edge pending register 1 (EXTI_RPR1) . . . . . . . . . . . . . . . 261
12.5.5 EXTI falling edge pending register 1 (EXTI_FPR1) . . . . . . . . . . . . . . . 261
12.5.6 EXTI external interrupt selection register (EXTI_EXTICRx) . . . . . . . . 262
12.5.7 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . . . . 263
12.5.8 EXTI CPU wakeup with event mask register (EXTI_EMR1) . . . . . . . . 264
12.5.9 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

13 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 267

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
13.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
13.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 270
13.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
13.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
13.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
14.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

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14.3.1 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

14.3.2 ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 277
14.3.3 Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
14.3.4 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 279
14.3.5 ADC clock (CKMODE, PRESC[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 281
14.3.6 ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3.7 Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.3.8 Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . . . . . . . . 284
14.3.9 Programmable sampling time (SMPx[2:0]) . . . . . . . . . . . . . . . . . . . . . 285
14.3.10 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.3.11 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 286
14.3.12 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.3.13 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
14.3.14 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 289
14.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 289
14.4.1 Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.4.2 Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 290
14.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 291
14.4.4 End of conversion sequence (EOS flag) . . . . . . . . . . . . . . . . . . . . . . . 291
14.4.5 Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
14.4.6 Low frequency trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.5 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.5.1 Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 294
14.5.2 ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.5.3 Managing a sequence of data converted without using the DMA . . . . 296
14.5.4 Managing converted data without using the DMA without overrun . . . 296
14.5.5 Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 296
14.6 Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
14.6.1 Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
14.6.2 Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
14.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH,
ADC_AWDxCR, ADC_AWDxTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.7.1 Description of analog watchdog 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.7.2 Description of analog watchdog 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . 301
14.7.3 ADC_AWDx_OUT output signal generation . . . . . . . . . . . . . . . . . . . . 301
14.7.4 Analog Watchdog threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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14.8 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

14.8.1 ADC operating modes supported when oversampling . . . . . . . . . . . . 306
14.8.2 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
14.8.3 Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
14.9 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 307
14.10 Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
14.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
14.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
14.12.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 312
14.12.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 314
14.12.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
14.12.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 318
14.12.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 322
14.12.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 323
14.12.7 ADC watchdog threshold register (ADC_AWD1TR) . . . . . . . . . . . . . . 324
14.12.8 ADC watchdog threshold register (ADC_AWD2TR) . . . . . . . . . . . . . . 325
14.12.9 ADC channel selection register [alternate] (ADC_CHSELR) . . . . . . . . 326
14.12.10 ADC channel selection register [alternate] (ADC_CHSELR) . . . . . . . . 327
14.12.11 ADC watchdog threshold register (ADC_AWD3TR) . . . . . . . . . . . . . . 329
14.12.12 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) . . . 330
14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . 330
14.12.15 ADC Calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . 331
14.12.16 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 331
14.13 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

15 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

15.1 TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
15.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
15.3 TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
15.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
15.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
15.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
15.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

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15.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

15.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
15.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
15.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
15.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
15.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
15.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
15.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 370
15.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
15.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
15.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 380
15.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
15.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
15.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
15.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
15.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
15.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
15.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
15.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
15.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
15.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
15.4 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
15.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 396
15.4.2 TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 397
15.4.3 TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 400
15.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 402
15.4.5 TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
15.4.6 TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 406
15.4.7 TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
15.4.8 TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
15.4.9 TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
15.4.10 TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

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15.4.11 TIM1 capture/compare enable register

(TIM1_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.4.12 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.13 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 418
15.4.16 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 418
15.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 419
15.4.18 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 419
15.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 420
15.4.20 TIM1 break and dead-time register
(TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
15.4.21 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 424
15.4.22 TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
15.4.23 TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
15.4.24 TIM1 capture/compare register 5 (TIM1_CCR5) . . . . . . . . . . . . . . . . . 427
15.4.25 TIM1 capture/compare register 6 (TIM1_CCR6) . . . . . . . . . . . . . . . . . 428
15.4.26 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . . 428
15.4.27 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . . 429
15.4.28 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . . 430
15.4.29 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

16 General-purpose timers (TIM3/TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . 434

16.1 TIM3/TIM4 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.2 TIM3/TIM4 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.3 TIM3/TIM4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
16.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
16.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

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16.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

16.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 462
16.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
16.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
16.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
16.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
16.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
16.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 469
16.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
16.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
16.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
16.4 TIM3/TIM4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.4.1 TIMx control register 1 (TIMx_CR1)(x = 3 to 4) . . . . . . . . . . . . . . . . . . 479
16.4.2 TIMx control register 2 (TIMx_CR2)(x = 3 to 4) . . . . . . . . . . . . . . . . . . 480
16.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 3 to 4) . . . . . . . . 482
16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 3 to 4) . . . . . . . 485
16.4.5 TIMx status register (TIMx_SR)(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . 486
16.4.6 TIMx event generation register (TIMx_EGR)(x = 3 to 4) . . . . . . . . . . . 488
16.4.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
16.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
16.4.9 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
16.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
16.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
16.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4) . . . . . . . . . . . . . . . . . 496
16.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4) . . . . . . . . . . . . . . . . . 497
16.4.14 TIMx prescaler (TIMx_PSC)(x = 3 to 4) . . . . . . . . . . . . . . . . . . . . . . . . 497
16.4.15 TIMx auto-reload register (TIMx_ARR)(x = 3 to 4) . . . . . . . . . . . . . . . 498
16.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 3 to 4) . . . . . . . . 498
16.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 3 to 4) . . . . . . . . 499
16.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3 to 4) . . . . . . . . 499
16.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 3 to 4) . . . . . . . . 500
16.4.20 TIMx DMA control register (TIMx_DCR)(x = 3 to 4) . . . . . . . . . . . . . . . 501
16.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 3 to 4) . . . . . . . 501

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16.4.22 TIM3 alternate function option register 1 (TIM3_AF1) . . . . . . . . . . . . . 502

16.4.23 TIM4 alternate function option register 1 (TIM4_AF1) . . . . . . . . . . . . . 502
16.4.24 TIM3 timer input selection register (TIM3_TISEL) . . . . . . . . . . . . . . . . 502
16.4.25 TIM4 timer input selection register (TIM4_TISEL) . . . . . . . . . . . . . . . . 503
16.4.26 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

17 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

17.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
17.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
17.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
17.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
17.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
17.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
17.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
17.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
17.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . . 515
17.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . . 517
17.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . . 517
17.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . 518
17.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . . 518
17.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . . 518
17.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 519
17.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . . 519
17.4.9 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

18 General-purpose timers (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

18.1 TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
18.2 TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
18.2.1 TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
18.3 TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
18.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
18.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
18.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
18.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
18.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

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18.3.6 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

18.3.7 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
18.3.8 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.3.9 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
18.3.10 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
18.3.11 Using timer output as trigger for other timers (TIM14) . . . . . . . . . . . . . 535
18.3.12 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.4 TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
18.4.1 TIM14 control register 1 (TIM14_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 536
18.4.2 TIM14 Interrupt enable register (TIM14_DIER) . . . . . . . . . . . . . . . . . . 537
18.4.3 TIM14 status register (TIM14_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
18.4.4 TIM14 event generation register (TIM14_EGR) . . . . . . . . . . . . . . . . . 538
18.4.5 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) 539
18.4.6 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) 540
18.4.7 TIM14 capture/compare enable register (TIM14_CCER) . . . . . . . . . . 542
18.4.8 TIM14 counter (TIM14_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
18.4.9 TIM14 prescaler (TIM14_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
18.4.10 TIM14 auto-reload register (TIM14_ARR) . . . . . . . . . . . . . . . . . . . . . . 544
18.4.11 TIM14 capture/compare register 1 (TIM14_CCR1) . . . . . . . . . . . . . . . 544
18.4.12 TIM14 timer input selection register (TIM14_TISEL) . . . . . . . . . . . . . . 545
18.4.13 TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

19 General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . 547

19.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
19.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
19.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
19.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . . 551
19.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
19.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
19.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
19.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
19.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
19.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
19.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
19.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
19.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

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19.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 567

19.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 568
19.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
19.4.14 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
19.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
19.4.16 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . 579
19.4.17 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
19.4.18 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . 581
19.4.19 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . 582
19.4.20 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 584
19.4.21 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
19.4.22 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
19.4.23 Using timer output as trigger for other timers (TIM16/TIM17) . . . . . . . 586
19.4.24 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
19.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
19.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 587
19.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 588
19.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 590
19.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 591
19.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
19.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 594
19.5.7 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
19.5.8 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
19.5.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 599
19.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
19.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
19.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 602
19.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 603
19.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 603
19.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 604
19.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 604
19.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 607
19.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 607
19.5.19 TIM15 alternate register 1 (TIM15_AF1) . . . . . . . . . . . . . . . . . . . . . . . 608
19.5.20 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . . 608

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19.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

19.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
19.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . . 612
19.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . . 613
19.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . . 614
19.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . 615
19.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . . 616
19.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
19.6.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
19.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . 620
19.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . 622
19.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 623
19.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . . 623
19.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . . 624
19.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . . 624
19.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 625
19.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . . 628
19.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . 628
19.6.17 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . . 629
19.6.18 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . . 629
19.6.19 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . . 630
19.6.20 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . . 630
19.6.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

20 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

21 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
21.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
21.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
21.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
21.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
21.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
21.3.4 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
21.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

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21.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

21.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
21.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . 639
21.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
21.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
21.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . 642
21.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

22 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 644

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
22.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
22.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
22.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
22.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
22.3.3 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
22.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 645
22.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
22.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
22.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
22.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 647
22.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . 648
22.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 649
22.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

23 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
23.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
23.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
23.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
23.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
23.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . . 653
23.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
23.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
23.3.6 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
23.3.7 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
23.3.8 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

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23.3.9 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

23.3.10 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
23.3.11 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
23.3.12 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
23.3.13 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
23.3.14 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
23.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
23.3.16 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
23.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
23.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
23.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
23.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
23.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
23.6.3 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 669
23.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . . 669
23.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 671
23.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 672
23.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
23.6.8 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 675
23.6.9 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 676
23.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 677
23.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 678
23.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 678
23.6.13 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 679
23.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 680
23.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 681
23.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 682
23.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 683
23.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
23.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . . 684
23.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . . 685
23.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

24 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . 689

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

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24.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

24.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
24.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
24.3.3 TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
24.3.4 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
24.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
24.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
24.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
24.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 695
24.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 696
24.6.3 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . . 697
24.6.4 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . . 698
24.6.5 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
24.6.6 TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . . 700
24.6.7 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . . 701
24.6.8 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . . 702
24.6.9 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

25 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 704

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
25.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
25.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
25.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
25.4.1 I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
25.4.2 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
25.4.3 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
25.4.4 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
25.4.5 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
25.4.6 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
25.4.7 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
25.4.8 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
25.4.9 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
25.4.10 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.4.11 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 738
25.4.12 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
25.4.13 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

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25.4.14 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 744

25.4.15 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
25.4.16 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . . 753
25.4.17 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
25.4.18 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
25.4.19 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
25.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
25.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
25.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
25.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
25.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
25.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 764
25.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 765
25.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
25.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . 767
25.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . 768
25.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . 770
25.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
25.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 772
25.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . 772
25.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

26 Universal synchonous receiver transmitter (USART) . . . . . . . . . . . . 775

26.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
26.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
26.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
26.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
26.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.5.2 USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
26.5.3 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
26.5.4 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
26.5.5 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
26.5.6 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
26.5.7 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
26.5.8 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 795

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26.5.9 USART Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

26.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . 799
26.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
26.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
26.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . . 803
26.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
26.5.15 USART single-wire Half-duplex communication . . . . . . . . . . . . . . . . . 809
26.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
26.5.17 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
26.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
26.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . . 817
26.5.20 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . . 819
26.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
26.6 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
26.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
26.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
26.8.1 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . . 827
26.8.2 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . . 831
26.8.3 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . 834
26.8.4 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . 838
26.8.5 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . 843
26.8.6 USART guard time and prescaler register (USART_GTPR) . . . . . . . . 843
26.8.7 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . 844
26.8.8 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . 845
26.8.9 USART interrupt and status register [alternate] (USART_ISR) . . . . . . 846
26.8.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . . 852
26.8.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . 857
26.8.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . 859
26.8.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . 859
26.8.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . . 860
26.8.15 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

27 Serial peripheral interface / integrated interchip sound (SPI/I2S) . . 863

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
27.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
27.3 I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

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27.4 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

27.5 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
27.5.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
27.5.2 Communications between one master and one slave . . . . . . . . . . . . . 866
27.5.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 868
27.5.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
27.5.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 870
27.5.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
27.5.7 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
27.5.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
27.5.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 874
27.5.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
27.5.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
27.5.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
27.5.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
27.5.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
27.6 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
27.7 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
27.7.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
27.7.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
27.7.3 Start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
27.7.4 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
27.7.5 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
27.7.6 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
27.7.7 I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
27.7.8 I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
27.7.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
27.8 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
27.9 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
27.9.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
27.9.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
27.9.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
27.9.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
27.9.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . . 915
27.9.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 915
27.9.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 915

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27.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . . 916

27.9.9 SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . . 918
27.9.10 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

28 Universal serial bus full-speed host/device interface (USB) . . . . . . . 920

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
28.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
28.3 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
28.4 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
28.4.1 Description of USB blocks used in both Device and Host modes . . . . 923
28.4.2 Description of host frame scheduler (HFS) specific to Host mode . . . 924
28.5 Programming considerations for Device and Host modes . . . . . . . . . . . 925
28.5.1 Generic USB Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
28.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
28.5.3 Double-buffered endpoints and usage in Device mode . . . . . . . . . . . . 932
28.5.4 Double buffered channels: usage in Host mode . . . . . . . . . . . . . . . . . 934
28.5.5 Isochronous transfers in Device mode . . . . . . . . . . . . . . . . . . . . . . . . 935
28.5.6 Isochronous transfers in Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 937
28.5.7 Suspend/resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
28.6 USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
28.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
28.6.2 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
28.6.3 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

29 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966

29.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
29.2 Reference Arm documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.3.1 SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.3.2 SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.3.3 Internal pull-up & pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . 968
29.4 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
29.5 SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
29.5.1 SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
29.5.2 SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
29.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 969

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29.5.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970

29.5.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
29.5.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
29.6 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
29.7 BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
29.7.1 BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
29.8 DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
29.8.1 DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
29.8.2 DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . . 973
29.9 MCU debug component (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
29.9.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 973
29.9.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 974
29.10 DBG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
29.10.1 DBG device ID code register (DBG_IDCODE) . . . . . . . . . . . . . . . . . . 974
29.10.2 DBG configuration register (DBG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 975
29.10.3 DBG APB freeze register 1 (DBG_APB_FZ1) . . . . . . . . . . . . . . . . . . . 975
29.10.4 DBG APB freeze register 2 (DBG_APB_FZ2) . . . . . . . . . . . . . . . . . . . 977
29.10.5 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978

30 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980

30.1 Flash memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
30.2 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980

31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982

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List of tables RM0454

List of tables

Table 1. Peripherals versus products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 2. STM32G0B0xx memory boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 3. STM32G070xx memory boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 4. STM32G030xx and STM32G050xx memory
boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5. STM32G0x0 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6. SRAM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 7. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 8. Flash memory organization for single-bank devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 9. Flash memory organization for 512 Kbytes dual-bank devices . . . . . . . . . . . . . . . . . . . . . 55
Table 10. Number of wait states according to Flash memory clock (HCLK) frequency . . . . . . . . . . . 56
Table 11. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 12. Organization of option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 13. Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 14. Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 71
Table 16. FLASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 17. FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 18. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 19. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 20. Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 21. Sleep mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 22. Low-power sleep mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 23. Stop 0 mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 24. Stop 1 mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 25. Standby mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 26. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 27. Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 28. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 29. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 30. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 31. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 32. Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 33. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 34. DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 35. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 221
Table 36. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 37. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 38. DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 39. DMAMUX: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 40. DMAMUX: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 41. DMAMUX: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . . 237
Table 42. DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 43. DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 44. DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 45. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 46. EXTI signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 47. EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 48. EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

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Table 49. EXTI line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 50. Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 51. EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 52. EXTI controller register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 53. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 54. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 55. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 56. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 57. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 58. Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 59. Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 60. tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 61. Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 62. Analog watchdog 1 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 63. Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 305
Table 64. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 65. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 66. Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Table 67. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Table 68. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Table 69. TIM1 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Table 70. Output control bits for complementary OCx and OCxN channels with break feature . . . . 416
Table 71. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Table 72. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Table 73. TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Table 74. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Table 75. TIM3/TIM4 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Table 76. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Table 77. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 78. TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Table 79. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 80. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Table 81. Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Table 82. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Table 83. Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Table 84. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Table 85. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Table 86. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Table 87. RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Table 88. RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Table 89. RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Table 90. PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Table 91. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Table 92. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Table 93. RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Table 94. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Table 95. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Table 96. TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Table 97. TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Table 98. TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

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Table 99. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Table 100. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Table 101. TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Table 102. STM32G0x0 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Table 103. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Table 104. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Table 105. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Table 106. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Table 107. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Table 108. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Table 109. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Table 110. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Table 111. Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Table 112. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Table 113. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Table 114. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Table 115. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 744
Table 116. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
Table 117. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Table 118. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Table 119. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Table 120. STM32G0x0 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Table 121. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Table 122. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Table 123. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 796
Table 124. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . . 797
Table 125. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Table 126. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Table 127. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Table 128. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Table 129. STM32G0x0 SPI and SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
Table 130. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Table 131. Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 902
Table 132. I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Table 133. SPI/I2S register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Table 134. STM32G0x0 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Table 135. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Table 136. Bulk double-buffering memory buffers usage (Device mode). . . . . . . . . . . . . . . . . . . . . . 933
Table 137. Bulk double-buffering memory buffers usage (Host mode) . . . . . . . . . . . . . . . . . . . . . . . 935
Table 138. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Table 139. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Table 140. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Table 141. Resume event detection for host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Table 142. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 143. Endpoint/channel type encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 144. Endpoint/channel kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 145. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 146. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Table 147. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Table 148. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

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Table 149. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

Table 150. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Table 151. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Table 152. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Table 153. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 971
Table 154. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Table 155. DEV_ID and REV_ID field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Table 156. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Table 157. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982

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List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 2. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3. Changing read protection (RDP) level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 4. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 5. POR, PDR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 6. Low-power modes state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 7. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 9. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 10. Frequency measurement with TIM14 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 11. Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 12. Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 13. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 14. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 15. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 16. Alternate function configuration- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 17. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 18. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 19. DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 20. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 241
Figure 21. Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 241
Figure 22. EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 23. Configurable event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 24. Direct event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 25. EXTI GPIO mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 26. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 27. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 28. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 29. Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 30. Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 31. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 32. ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 33. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 34. ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 35. Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 36. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 37. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 38. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 39. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 40. Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 294
Figure 41. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 42. Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 298
Figure 43. Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 44. Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 45. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 46. ADC_AWDx_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 47. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . . 302
Figure 48. ADC_AWDx_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 303

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Figure 49. Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 50. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 51. Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 52. Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 53. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 308
Figure 54. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 55. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 56. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 339
Figure 57. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 339
Figure 58. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 59. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 60. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 61. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 62. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 343
Figure 63. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 343
Figure 64. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 65. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 66. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 67. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 68. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 347
Figure 69. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 348
Figure 70. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Figure 71. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 349
Figure 72. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 73. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 350
Figure 74. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 351
Figure 75. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 352
Figure 76. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 77. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 78. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 79. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 80. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 81. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 82. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 83. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 358
Figure 84. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 85. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 359
Figure 86. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 87. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 360
Figure 88. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 89. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 90. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 91. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 92. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 368
Figure 93. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Figure 94. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 370
Figure 95. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 96. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 371
Figure 97. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 372
Figure 98. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 99. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 376
Figure 100. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 377

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Figure 101. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 102. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 103. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 104. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 105. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 106. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 107. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 108. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 386
Figure 109. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 110. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Figure 111. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 112. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 113. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 114. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Figure 115. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 116. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 437
Figure 117. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 437
Figure 118. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 119. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 120. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 121. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 122. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 440
Figure 123. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 441
Figure 124. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Figure 125. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Figure 126. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Figure 127. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Figure 128. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 445
Figure 130. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 446
Figure 132. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 447
Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 448
Figure 135. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 136. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 137. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Figure 138. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Figure 139. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 140. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 452
Figure 141. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 142. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 143. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 144. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Figure 145. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Figure 146. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 147. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 461
Figure 148. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 149. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 150. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Figure 151. Retriggerable one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

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Figure 152. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 467

Figure 153. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 468
Figure 154. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Figure 155. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Figure 156. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Figure 157. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 158. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 159. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . . 473
Figure 160. Gating TIMz with OC1REF of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Figure 161. Gating TIMz with Enable of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Figure 162. Triggering TIMz with update of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Figure 163. Triggering TIMz with Enable of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Figure 164. Triggering TIMy and TIMz with TIMy TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Figure 165. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 166. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 510
Figure 167. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 510
Figure 168. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Figure 169. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 170. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 171. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 172. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 173. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 174. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 175. General-purpose timer block diagram (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 176. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 524
Figure 177. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 524
Figure 178. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Figure 179. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 180. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 181. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 182. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 183. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Figure 184. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 529
Figure 185. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 529
Figure 186. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 187. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 188. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 189. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 190. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 191. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 192. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 552
Figure 193. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 552
Figure 194. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Figure 195. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Figure 196. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Figure 197. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Figure 198. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

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Figure 199. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 200. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 558
Figure 201. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 202. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 203. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 204. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 561
Figure 205. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 206. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Figure 207. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 562
Figure 208. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 209. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 210. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 211. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 212. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 213. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 569
Figure 214. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 570
Figure 215. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 216. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 217. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Figure 218. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Figure 219. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Figure 220. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 221. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 222. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Figure 223. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Figure 224. IRTIM internal hardware connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Figure 225. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Figure 226. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 227. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 228. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Figure 229. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 230. I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Figure 231. I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 232. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Figure 233. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Figure 234. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Figure 235. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Figure 236. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 237. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Figure 238. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 239. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 240. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 241. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . 724
Figure 242. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . 725
Figure 243. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 244. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 245. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 246. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 247. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

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Figure 248. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . 731
Figure 249. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 732
Figure 250. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 251. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . . 735
Figure 252. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 736
Figure 253. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 254. Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 255. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 746
Figure 256. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 746
Figure 257. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 748
Figure 258. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 259. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Figure 260. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Figure 261. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Figure 262. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 263. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Figure 264. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 265. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 266. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 267. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Figure 268. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Figure 269. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 270. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Figure 271. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 804
Figure 272. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 805
Figure 273. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 274. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 275. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Figure 276. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Figure 277. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Figure 278. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Figure 279. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Figure 280. IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Figure 281. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Figure 282. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Figure 283. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Figure 284. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Figure 285. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Figure 286. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . . 824
Figure 287. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Figure 288. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Figure 289. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Figure 290. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Figure 291. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
Figure 292. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
Figure 293. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
Figure 294. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

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Figure 295. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

Figure 296. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 873
Figure 297. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Figure 298. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Figure 299. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 300. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 301. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Figure 302. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 303. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Figure 304. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Figure 305. I2S Philips protocol waveforms (16/32-bit full accuracy). . . . . . . . . . . . . . . . . . . . . . . . . . 892
Figure 306. I2S Philips standard waveforms (24-bit frame) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Figure 307. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 308. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 309. I2S Philips standard (16-bit extended to 32-bit packet frame) . . . . . . . . . . . . . . . . . . . . . 893
Figure 310. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 893
Figure 311. MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 312. MSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 313. MSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Figure 314. LSB justified 16-bit or 32-bit full-accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Figure 315. LSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Figure 316. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 317. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 318. LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 319. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 897
Figure 320. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 321. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 898
Figure 322. Start sequence in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Figure 323. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Figure 324. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Figure 325. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
Figure 326. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 927
Figure 327. Block diagram of STM32G0x0 MCU and Cortex®-M0+-level debug support . . . . . . . . . 966

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1 Documentation conventions

1.1 General information

The STM32G0x0 devices have an Arm®(a) Cortex®-M0+ core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

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1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• SWD-DP (SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface
based on the Serial Wire Debug (SWD) protocol. Please refer to the Cortex®-M0+
technical reference manual.
• IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the SWD protocol or the bootloader while the device is mounted
on the user application board.
• Option bytes: product configuration bits stored in the Flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.
The following table shows per-product availability of peripherals that are not common to all
STM32G0x0 products.

Table 1. Peripherals versus products

Feature STM32G030 STM32G050 STM32G070 STM32G0B0

TIM4 No No No Yes
TIM6 and TIM7 No Yes Yes Yes
TIM15 No No Yes Yes
I2C3 No No No Yes
SPI3 No No No Yes
I2S2 No No No Yes
USART3, USART4 No No Yes Yes
USART5, USART6 No No No Yes
USART3 independent
N/A N/A No Yes
clock selection
I2C2 independent clock
No No No Yes
selection
USB No No No Yes
UCPDx_STROBE bits No No Yes Yes

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Table 1. Peripherals versus products (continued)

Feature STM32G030 STM32G050 STM32G070 STM32G0B0

DMA2 No No No Yes
MCO2 No No No Yes
GPIO port E No No No Yes
Switchable I/O
Yes Yes No Yes
clamping diode
PLLQCLK No No No Yes

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2 Memory and bus architecture

2.1 System architecture

The main system consists of:
• Two masters:
– Cortex®-M0+ core
– General-purpose DMA
• Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB with AHB-to-APB bridge that connects all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1.

Figure 1. System architecture

GPIO Ports Flash memory

A,B,C,D,E,F interface Flash memory

IOPORT
SRAM
Arm®
Cortex®-M0+ System bus Bus matrix
core AHB-to-APB
AHB bridge APB

DMA1/2
DMAMUX DMA bus
channels 1 to 12
SYSCFG,
ADC
TIM1, TIM2, TIM3, TIM4
TIM6, TIM7,
TIM14 to TIM17,
RCC CRC IWDG, WWDG,
RTC, PWR,
I2C1, I2C2, I2C3
EXTI USART1 to USART6,
SPI1/I2S1, SPI2/I2S2, SPI3
USB
DMA requests DBGMCU

System bus (S-bus)

This bus connects the system bus of the Cortex®-M0+ core (peripheral bus) to a bus matrix
that manages the arbitration between the core and the DMA.

DMA bus
This bus connects the AHB master interface of the DMA to the bus matrix that manages the
access of CPU and DMA to SRAM, Flash memory and AHB/APB peripherals.

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Bus matrix
The bus matrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of
masters (CPU, DMA) and slaves (Flash memory interface, SRAM and AHB-to-APB bridge).
AHB peripherals are connected on system bus through the bus matrix to allow DMA access.

AHB-to-APB bridge (APB)

The AHB-to-APB bridge provides full synchronous connections between the AHB and the
APB bus.
Refer to Section 2.2: Memory organization for the address mapping of the peripherals
connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory). Before using a peripheral its clock in the RCC_AHBENR, RCC_APBENRx or
RCC_IOPENR register must first be enabled.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2 Memory organization

2.2.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

Used space

Reserved space

0xFFFF FFFF 0 x 5 0 0 0 1FFF

IOPORT
0x5000 0000
block 7
Arm Cortex M0+
0xE000 0000 internal peripherals

0 x 4 0 0 2 63FF
AHB
block 6
0x4002 0000
0xC000 0000

0x4001 5BFF
block 5
APB
0xA000 0000
0x4001 0000

0x4000 A7FF
block 4
APB
0x8000 0000
0x4000 0000

block 3

0x6000 0000
0x1FFF 787F
Option bytes
0x1FFF 7800
Engineering bytes
block 2 0x1FFF 7500
0x1FFF 73FF
Peripherals OTP
0x4000 0000 0x1FFF 7000

System memory
block 1
0x1FFF 0000
RAM
0x2000 0000
(2 )

block 0 Code
Main Flash memory
0x0800 0000
0x0000 0000
(1 )
Addressable Main Flash memory /
space System memory /
RAM (3)
0x0000 0000

1. STM32G0B0xx: 0x0007 FFFF; STM32G070xx: 0x0001 FFFF; STM32G050xx, STM32G030xx: 0x0000 FFFF.
2. STM32G0B0xx: 0x0807 FFFF; STM32G070xx: 0x0801 FFFF; STM32G050xx, STM32G030xx: 0x0800 FFFF.
3. Depends on boot configuration
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered as reserved. For the detailed mapping of available memory and register areas,
refer to the following tables.

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Table 2. STM32G0B0xx memory boundary addresses

Type Boundary address Size Memory Area Register description

0x2002 4000 - 0x3FFF FFFF ~512 MB Reserved -

SRAM
0x2000 0000 - 0x2002 3FFF 144 KB SRAM Section 2.3 on page 49
0x1FFF 7880- 0x1FFF FFFF ~34 KB Reserved -
0x1FFF 7800 - 0x1FFF 787F 128 B Option bytes Section 3.4 on page 63
0x1FFF 7500 - 0x1FFF 77FF 768 B Engineering bytes -
0x1FFF 7400- 0x1FFF 74FF 256 B Reserved -
0x1FFF 7000 - 0x1FFF 73FF 1 KB OTP -

Code 0x1FFF 0000 - 0x1FFF 6FFF 28 KB System memory -

0x0808 0000 - 0x1FFF D7FF ~384 MB Reserved -
0x0800 0000 - 0x0807 FFFF 512 KB Main Flash memory Section 3.3.1 on page 53
0x0008 0000 - 0x07FF FFFF ~7.5 MB Reserved -
Main Flash memory, system
0x0000 0000 - 0x0007 FFFF 512 KB memory or SRAM depending -
on BOOT configuration

Table 3. STM32G070xx memory boundary addresses

Type Boundary address Size Memory Area Register description

0x2000 9000 - 0x3FFF FFFF ~512 MB Reserved -

SRAM
0x2000 0000 - 0x2000 8FFF 36 KB SRAM Section 2.3 on page 49
0x1FFF 7880- 0x1FFF FFFF ~34 KB Reserved -
0x1FFF 7800 - 0x1FFF 787F 128 B Option bytes Section 3.4 on page 63
0x1FFF 7500 - 0x1FFF 77FF 768 B Engineering bytes -
0x1FFF 7400- 0x1FFF 74FF 256 B Reserved -
0x1FFF 7000 - 0x1FFF 73FF 1 KB OTP -

Code 0x1FFF 0000 - 0x1FFF 6FFF 28 KB System memory -

0x0802 0000 - 0x1FFF D7FF ~384 MB Reserved -
0x0800 0000 - 0x0801 FFFF 128 KB Main Flash memory Section 3.3.1 on page 53
0x0002 0000 - 0x07FF FFFF ~8 MB Reserved -
Main Flash memory, system
0x0000 0000 - 0x0001 FFFF 128 KB memory or SRAM depending -
on BOOT configuration

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Table 4. STM32G030xx and STM32G050xx memory

boundary addresses
Type Boundary address Size Memory Area Register description

0x2000 2000 - 0x3FFF FFFF ~512 MB Reserved -

SRAM
0x2000 0000 - 0x2000 1FFF 8 KB SRAM Section 2.3 on page 49
0x1FFF 7880- 0x1FFF FFFF ~34 KB Reserved -
0x1FFF 7800 - 0x1FFF 787F 128 B Option bytes Section 3.4 on page 63
0x1FFF 7500 - 0x1FFF 77FF 768 B Engineering bytes -
0x1FFF 7400- 0x1FFF 74FF 256 B Reserved -
0x1FFF 7000 - 0x1FFF 73FF 1 KB OTP -
0x1FFF 2000 - 0x1FFF 6FFF ~20 KB Reserved -
Code
0x1FFF 0000 - 0x1FFF 1FFF 8 KB System memory -
0x0801 0000 - 0x1FFF D7FF ~384 MB Reserved -
0x0800 0000 - 0x0800 FFFF 64 KB Main Flash memory Section 3.3.1 on page 53
0x0001 0000 - 0x07FF FFFF ~8 MB Reserved -
Main Flash memory, system
0x0000 0000 - 0x0000 FFFF 64 KB memory or SRAM depending -
on BOOT configuration

The following table gives the boundary addresses of the peripherals.

Table 5. STM32G0x0 peripheral register boundary addresses

Bus Boundary address Size Peripheral Peripheral register map

Cortex®-M0+ internal
- 0xE000 0000 - 0xE00F FFFF 1MB -
peripherals
0x5000 1800 - 0x5FFF 17FF ~256 MB Reserved -
0x5000 1400 - 0x5000 17FF 1 KB GPIOF Section 6.4.12 on page 188
0x5000 1000 - 0x5000 13FF 1 KB GPIOE Section 6.4.12 on page 188
IOPORT 0x5000 0C00 - 0x5000 0FFF 1 KB GPIOD Section 6.4.12 on page 188
0x5000 0800 - 0x5000 0BFF 1 KB GPIOC Section 6.4.12 on page 188
0x5000 0400 - 0x5000 07FF 1 KB GPIOB Section 6.4.12 on page 188
0x5000 0000 - 0x5000 03FF 1 KB GPIOA Section 6.4.12 on page 188

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Table 5. STM32G0x0 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral Peripheral register map

0x4002 3400 - 0x4FFF FFFF ~256 MB Reserved -

0x4002 3000 - 0x4002 33FF 1 KB CRC Section 13.4.6 on page 273
0x4002 2400 - 0x4002 2FFF 3 KB Reserved -
0x4002 2000 - 0x4002 23FF 1 KB FLASH Section 3.7.13 on page 85
0x4002 1C00 - 0x4002 1FFF 3 KB Reserved -
0x4002 1800 - 0x4002 1BFF 1 KB EXTI Section 12.5.9 on page 265
AHB
0x4002 1400 - 0x4002 17FF 1 KB Reserved -
0x4002 1000 - 0x4002 13FF 1 KB RCC Section 5.4.24 on page 169
0x4002 0C00 - 0x4002 0FFF 1 KB Reserved -
0x4002 0800 - 0x4002 0BFF 2 KB DMAMUX Section 10.6.7 on page 248
0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 9.6.7 on page 231
0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 9.6.7 on page 231
0x4001 5C00 - 0x4001 FFFF 32 KB Reserved -
0x4001 5800 - 0x4001 5BFF 1 KB DBG Section 29.10.5 on page 978
0x4001 4C00 - 0x4001 57FF 3 KB Reserved -
0x4001 4800 - 0x4001 4BFF 1 KB TIM17 Section 19.6.21 on page 632
APB 0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 19.6.21 on page 632
0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 19.6.21 on page 632
0x4001 3C00 - 0x4001 3FFF 1 KB USART6 Section 26.8.15 on page 861
0x4001 3800 - 0x4001 3BFF 1 KB USART1 Section 26.8.15 on page 861
0x4001 3400 - 0x4001 37FF 1 KB Reserved -
0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1 Section 27.9.10 on page 919
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 15.4 on page 396
0x4001 2800 - 0x4001 2BFF 1 KB Reserved -
0x4001 2400 - 0x4001 27FF 1 KB ADC Section 14.13 on page 333
0x4001 0200 - 0x4001 23FF 8 KB Reserved -
(1)
0x4001 0080 - 0x4001 01FF SYSCFG(ITLINE) Section 7.1.31 on page 205
0x4001 0030 - 0x4001 007F 1 KB Reserved -
APB
0x4001 0000 - 0x4001 002F SYSCFG Section 7.1.31 on page 205
0x4000 B400- 0x4000 FFFF 19 KB Reserved -
0x4000 B000 - 0x4000 B3FF 1 KB TAMP (+ BKP registers) Section 24.6.9 on page 703
0x4000 8C00 - 0x4000 AFFF 9 KB Reserved -
0x4000 8800 - 0x4000 8BFF 1 KB I2C3 Section 25.7.12 on page 773
0x4000 7400 - 0x4000 87FF 5 KB Reserved -
0x4000 7000 - 0x4000 73FF 1 KB PWR Section 4.4.20 on page 117

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Table 5. STM32G0x0 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral Peripheral register map

0x4000 6000 - 0x4000 6FFF 4 KB Reserved -

0x4000 5C00 - 0x4000 5FFF 1 KB USB Section 28.6.3 on page 964
0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 25.7.12 on page 773
0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 25.7.12 on page 773
0x4000 5000 - 0x4000 53FF 1 KB USART5 Section 26.8.15 on page 861
0x4000 4C00 - 0x4000 4FFF 1 KB USART4 Section 26.8.15 on page 861
0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 26.8.15 on page 861
0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 26.8.15 on page 861
0x4000 4000 - 0x4000 43FF 1 KB Reserved -
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 Section 27.9.10 on page 919
0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 27.9.10 on page 919
0x4000 3400 - 0x4000 37FF 1 KB Reserved -
APB
0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 21.4.6 on page 643
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 22.5.4 on page 649
0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 23.6.21 on page 687
0x4000 2400 - 0x4000 27FF 1 KB Reserved -
0x4000 2000 - 0x4000 23FF 1 KB TIM14 Section 18.4.13 on page 545
0x4000 1800 - 0x4000 1FFF 2 KB Reserved -
0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 17.4.9 on page 520
0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 17.4.9 on page 520
0x4000 0C00 - 0x4000 0FFF 1 KB Reserved -
0x4000 0800 - 0x4000 0BFF 1 KB TIM4 Section 16.4.26 on page 505
0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 16.4.26 on page 505
0x4000 0000 - 0x4000 03FF 1 KB Reserved -
1. SYSCFG (ITLINE) registers use 0x4001 0000 as reference peripheral base address.

2.3 Embedded SRAM

The following table summarizes the SRAM resources on the devices, with parity check
enabled and disabled.
.

Table 6. SRAM size

SRAM with parity enabled SRAM with parity disabled
Device
(Kbyte) (Kbyte)

STM32G0B0xx 128 144

STM32G070xx 32 36

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Table 6. SRAM size (continued)

SRAM with parity enabled SRAM with parity disabled
Device
(Kbyte) (Kbyte)

STM32G050xx 16 18
STM32G030xx 8 8

The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at
maximum system clock frequency without wait state and thus by both CPU and DMA.
Parity check
The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Section 3.4: FLASH option bytes).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIM1/15/16/17, with the
SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2
(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).
Note: When enabling the SRAM parity check, it is advised to initialize by software the whole
SRAM at the beginning of the code, to avoid getting parity errors when reading non-
initialized locations.

2.4 Flash memory overview

The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of three parts:
– Option bytes for hardware and memory protection user configuration.
– System memory which contains the proprietary boot loader code.
– OTP (one-time programmable) area
Refer to Section 3: Embedded Flash memory (FLASH) for more details.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the Flash memory operations (Program/Erase)
controlled through the Flash registers.

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2.5 Boot configuration

In the STM32G0x0, three different boot modes can be selected through the BOOT0 pin and
boot configuration bits nBOOT1, BOOT_SEL and nBOOT0 in the User option byte, as
shown in the following table.

Table 7. Boot modes

Boot mode configuration
Selected boot area
nBOOT1 bit BOOT0 pin nBOOT_SEL bit nBOOT0 bit

x 0 0 x Main Flash memory

1 1 0 x System memory
0 1 0 x Embedded SRAM
x x 1 1 Main Flash memory
1 x 1 0 System memory
0 x 1 0 Embedded SRAM

The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is
up to the user to set boot mode configuration related to the required boot mode.
The boot mode configuration is also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is
accessible as follows:
• Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
• Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space 0x1FFF0000.
• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Empty check
Internal empty check flag (the EMPTY bit of the FLASH access control register
(FLASH_ACR)) is implemented to allow easy programming of virgin devices by the boot
loader. This flag is used when BOOT0 pin is defining Main Flash memory as the target boot
area. When the flag is set, the device is considered as empty and System memory (boot
loader) is selected instead of the Main Flash as a boot area to allow user to program the
Flash memory.
This flag is updated only during Option bytes loading: it is set when the content of the
address 0x0800 0000 is read as 0xFFFF FFFF, otherwise it is cleared. It means a power
reset or setting of OBL_LAUNCH bit in FLASH_CR register is needed to clear this flag after
programming of a virgin device to execute user code after System reset. The EMPTY bit
can also directly be written by software.

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Note: If the device is programmed for a first time but the Option bytes are not reloaded, the device
still selects System memory as a boot area after a System reset.

Physical remap
Once the boot mode is selected, the application software can modify the memory accessible
in the code area. This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1).

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory using one of the following serial
interfaces:
• USART1, USART2, I2C1 and I2C2 (applies to all devices)
• USART3, SPI1, and SPI2 (applies to STM32G070xx and to STM32G0B0xx)
• USB (DFU) (applies to STM32G0B0xx)
For further details, refer to the device data sheets and AN2606.

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3 Embedded Flash memory (FLASH)

3.1 FLASH Introduction

The Flash memory interface manages CPU (Cortex®-M0+) AHB to the Flash memory. It
implements erase and program Flash memory operations, read and write protection, and
security mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.

3.2 FLASH main features

• Up to 512 Kbytes of Flash memory (Main memory):
– up to 64 Kbytes for STM32G030xx / STM32G050xx
– up to 128 Kbytes for STM32G070xx
– up to 512 Kbytes for STM32G0B0xx
• Memory organization:
– 1 bank (products with up to 128 Kbytes of Flash memory)
– 2 banks (products with more than 128 Kbytes of Flash memory)
– Page size: 2 Kbytes
– Subpage size: 512 bytes
• 72-bit wide data read (64 bits plus 8 ECC bits)
• 72-bit wide data write (64 bits plus 8 ECC bits)
• Page erase (2 Kbytes), bank (single-bank) erase, and mass (all-bank) erase
Flash memory interface features:
• Flash memory read operations
• Flash memory program/erase operations
• Read protection activated by option (RDP)
• Two write protection areas per bank, selected by option (WRP)
• Flash memory empty check
• Prefetch buffer
• CPU instruction cache: two cache lines of 64 bits (16 bytes RAM)
• Error code correction (ECC): eight bits for 64 bits
• Option byte loader

3.3 FLASH functional description

3.3.1 FLASH memory organization

The Flash memory is organized as 72-bit-wide memory cells (64 bits plus 8 ECC bits) that
can be used for storing both code and data constants.

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The Flash memory is organized as follows:

• A Main memory block containing 128 pages of 2 Kbytes, each page with eight rows of
256 bytes.
• An Information block containing:
– System memory from which the CPU boots in System memory boot mode. The
area is reserved and contains the boot loader used to reprogram the Flash
memory through one of the following interfaces: USART1, USART2, I2C1, and
I2C2 (applies to all devices), USART3, SPI1, and SPI2 (applies to STM32G070xx
and to STM32G0B0xx), and through USB (DFU) and (applies to STM32G0B0xx).
On the manufacturing line, the devices are programmed and protected against
spurious write/erase operations. For further details, refer to the AN2606 available
from www.st.com.
– 1 Kbyte (128 double words) OTP (one-time programmable) for user data. The
OTP data cannot be erased and can be written only once. If only one bit is at 0,
the entire double word (64 bits) cannot be written anymore, even with the value
0x0000 0000 0000 0000.
The OTP area cannot be read when RDP level is 1 and boot source is not the
Main Flash memory area.
– Option bytes for user configuration.
The following tables show the mapping of the Flash memory into Information block and Main
memory area. The mapping for

Table 8. Flash memory organization for single-bank devices

Size 64 Kbyte 128 Kbyte
Area Addresses
(bytes) devices devices

0x1FFF 7800 - 0x1FFF 787F 128 Option bytes

0x1FFF 7500 - 0x1FFF 77FF 768 Engineering bytes
Information 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
System
0x1FFF 2000 - 0x1FFF 6FFF 20 K -
memory
0x1FFF 0000 - 0x1FFF 1FFF 8K System memory
0x0801 F800 - 0x0801 FFFF 2K Page 63
... ... - ...
0x0801 0000 - 0x0801 07FF 2K Page 32

Main 0x0800 F800 - 0x0800 FFFF 2K Page 31

memory ... ... ...
0x0800 1000 - 0x0800 17FF 2K Page 2
0x0800 0800 - 0x0800 0FFF 2K Page 1
0x0800 0000 - 0x0800 07FF 2K Page 0

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Table 9. Flash memory organization for 512 Kbytes dual-bank devices

Memory
Area Addresses Size (bytes)
type

Bank 2 0x1FFF F800 - 0x1FFF F80F 16

Option bytes
Bank 1 0x1FFF 7800 - 0x1FFF 780F 16
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
System memory
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
0x0807 F804 - 0x0807 FFFF 2K Page 383
... ... ...
Bank 2 0x0804 1000 - 0x0804 17FF 2K Page 258
0x0804 0800 - 0x0804 0FFF 2K Page 257

Main 0x0804 0000 - 0x0804 07FF 2K Page 256

memory 0x0803 F800 - 0x0803 FFFF 2K Page 127
... ... ...
Bank 1 0x0800 1000 - 0x0800 17FF 2K Page 2
0x0800 0800 - 0x0800 0FFF 2K Page 1
0x0800 0000 - 0x0800 07FF 2K Page 0

3.3.2 FLASH empty check

During the OBL phase, after loading all options, the Flash memory interface checks whether
the first location of the Main memory is programmed. The result of this check in conjunction
with the boot0 and boot1 information is used to determine where the system has to boot
from. It prevents the system to boot from Main Flash memory area when i.e. no user code
has been programmed.
The Main Flash memory empty check status can be read from the EMPTY bit in FLASH
access control register (FLASH_ACR). Software can modify the Main Flash memory empty
status by writing an appropriate value to the EMPTY bit.

3.3.3 FLASH error code correction (ECC)

Data in Flash memory words are 72-bits wide: eight bits are added per each double word
(64 bits). The ECC mechanism supports:
• One error detection and correction
• Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in FLASH
ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH ECC register
(FLASH_ECCR). In this case, a NMI is generated.

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When an ECC error is detected, the address of the failing double word is saved in
ADDR_ECC[16:0] bitfield of the FLASH_ECCR register. ADDR_ECC[2:0] are always
cleared. The bus-ID of the CPU accessing the address is saved in CPUID[2:0].
While ECCC or ECCD is set, FLASH_ECCR is not updated if a new ECC error occurs.
FLASH_ECCR is updated only when ECC flags are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected, but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. If
this is not the desired behavior, the user must reset the cache.

3.3.4 FLASH read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the FLASH access control register (FLASH_ACR) according to the
frequency of the Flash (HCLK) memory clock and the internal voltage range of the device
VCORE. Refer to Section 4.1.4: Dynamic voltage scaling management.

Table 10. Number of wait states according to Flash memory clock (HCLK) frequency

Wait states (WS) HCLK (MHz)

(LATENCY) VCORE Range 1 VCORE Range 2

0 WS (1 HCLK cycles) ≤ 24 ≤8
1 WS (2 HCLK cycles) ≤ 48 ≤ 16
2 WS (3 HCLK cycles) ≤ 64 -

After power reset, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait state (WS) is
configured in the FLASH_ACR register.
When wakeup from Standby, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait
state (WS) is configured in the FLASH_ACR register.
When changing the Flash memory clock frequency or Range, the following software
sequences must be applied in order to tune the number of wait states needed to access the
Flash memory:

Increasing the CPU frequency

1. Program the new number of wait states to the LATENCY bits of the FLASH access
control register (FLASH_ACR).
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading back the LATENCY bits of the FLASH access control register
(FLASH_ACR), and wait until the programmed new number is read.
3. Modify the system cock source by writing the SW bits of the RCC_CFGR register.
4. If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR
register.
5. Optionally, check that the new system clock source or/and the new core clock prescaler
value is/are taken into account by reading the clock source status (SWS bits) of the

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RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register.

Decreasing the CPU frequency

1. Modify the system clock source by writing the SW bits of the RCC_CFGR register.
2. If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR.
3. Check that the new system clock source or/and the new core clock prescaler value
is/are taken into account by reading the clock source status (SWS bits) of the
RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register, and wait until the programmed new system clock source or/and new Flash
memory clock prescaler value is/are read.
4. Program the new number of wait states to the LATENCY bits of the FLASH access
control register (FLASH_ACR).
5. Optionally, check that the new number of wait states is used to access the Flash
memory by reading back the LATENCY bits of the FLASH access control register
(FLASH_ACR).

3.3.5 FLASH memory acceleration

Instruction prefetch
Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bits current
instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU
cycles are needed to execute the previous read instruction line. Prefetch on the CPU S-bus
can be used to read the next sequential instruction line from the Flash memory while the
current instruction line is being requested by the CPU.
Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register
(FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash
memory.
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.

Cache memory
To limit the time lost due to jumps, it is possible to retain two cache lines of 64 bits (16 bytes)
in the instruction cache memory. This feature can be enabled by setting the instruction
cache enable (ICEN) bit of the FLASH access control register (FLASH_ACR). Each time a
miss occurs (requested data not present in the currently used instruction line, in the
prefetched instruction line or in the instruction cache memory), the line read is copied into
the instruction cache memory. If some data contained in the instruction cache memory are
requested by the CPU, they are provided without inserting any delay. Once all the
instruction cache memory lines are filled, the LRU (least recently used) policy is used to
determine the line to replace in the instruction memory cache. This feature is particularly
useful in case of code containing loops.
The Instruction cache memory is enabled after system reset.
No data cache is available on Cortex®-M0+.

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3.3.6 FLASH program and erase operations

The device-embedded Flash memory can be programmed using in-circuit programming or
in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using SWD protocol or the supported interfaces by the system boot loader,
to load the user application for the CPU, into the microcontroller. ICP offers quick and
efficient design iterations and eliminates unnecessary package handling or socketing of
devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, UART, I2C, SPI, etc.) to
download programming data into memory. IAP allows the user to re-program the Flash
memory while the application is running. Nevertheless, part of the application has to have
been previously programmed in the Flash memory using ICP.
The success of a data word programming operation and a page/bank erase operation is not
guaranteed if aborted due to device reset or power loss.
During a program/erase operation to the Flash memory, any attempt to read the Flash
memory stalls the bus. The read operation proceeds correctly once the program/erase
operation has completed.

Unlocking the Flash memory

After reset, write into the FLASH control register (FLASH_CR) is not allowed so as to
protect the Flash memory against possible unwanted operations due, for example, to
electric disturbances. The following sequence unlocks these registers:
1. Write KEY1 = 0x4567 0123 in the FLASH key register (FLASH_KEYR)
2. Write KEY2 = 0xCDEF 89AB in the FLASH key register (FLASH_KEYR).
Any wrong sequence locks the FLASH_CR registers until the next system reset. In the case
of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated.
The FLASH_CR registers can be locked again by software by setting the LOCK bit in one of
these registers.
Note: The FLASH_CR register cannot be written when the BSY1 bit of the FLASH status register
(FLASH_SR) is set. Any attempt to write to this register with the BSY1 bit set causes the
AHB bus to stall until the BSY1 bit is cleared.

3.3.7 FLASH Main memory erase sequences

The Flash memory erase operation can be performed at page level (page erase), or on the
whole memory (mass erase). Mass erase does not affect the Information block (system
Flash memory, OTP and option bytes).

Flash memory page erase

When a page is protected by WRP, it is not erased and the WRPERR bit is set.

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To erase a page (2 Kbytes), follow the procedure below:

1. Check that no Flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the PER bit and select the page to erase (PNB) in the FLASH control register
(FLASH_CR).
4. Set the STRT bit of the FLASH control register (FLASH_CR).
5. Wait until the BSY1 bit of the FLASH status register (FLASH_SR) is cleared.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.

Flash memory bank or mass erase

When WRP is enabled, the Flash memory mass erase is aborted, no erase starts, and the
WRPERR bit is set.
To perform a mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 (for Bank 1 or single-bank device) and/or MER2 (for Bank 2) bit of the
FLASH control register (FLASH_CR).
4. Set the STRT bit of the FLASH control register (FLASH_CR).
5. Wait until the BSY1 bit ofthe FLASH status register (FLASH_SR) is cleared.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.

3.3.8 FLASH Main memory programming sequences

The Flash memory is programmed 72 bits (64-bit data plus 8-bit ECC) at a time.
Programming a previously programmed address with a non-zero data is not allowed. Any
such attempt sets PROGERR flag of the FLASH status register (FLASH_SR).
It is only possible to program a double word (2 x 32-bit data).
• Any attempt to write byte (8 bits) or half-word (16 bits) sets SIZERR flag of the FLASH
status register (FLASH_SR).
• Any attempt to write a double word that is not aligned with a double word address sets
PGAERR flag of the FLASH status register (FLASH_SR).

Standard programming
The Flash memory programming sequence in standard mode is as follows:

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1. Check that no Main Flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR)..
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the PG bit of the FLASH control register (FLASH_CR).
4. Perform the data write operation at the desired memory address, inside Main memory
block or OTP area. Only double word (64 bits) can be programmed.
a) Write a first word in an address aligned with double word
b) Write the second word.
5. Wait until the BSY1 bit of the FLASH status register (FLASH_SR) is cleared.
6. Check that EOP flag of the FLASH status register (FLASH_SR) is set (programming
operation succeeded), and clear it by software.
7. Clear the PG bit of the FLASH control register (FLASH_CR) if there no more
programming request anymore.
Note: When the Flash memory interface has received a good sequence (a double word),
programming is automatically launched and BSY1 bit is set. The internal oscillator HSI16
(16 MHz) is enabled automatically when PG bit is set, and disabled automatically when PG
bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register.
ECC is calculated from the double word to program.

Fast programming
The main purpose of this mode is to reduce the page programming time. It is achieved by
eliminating the need for verifying the Flash memory locations before they are programmed,
thus saving the time of high voltage ramping and falling for each double word.
This mode allows programming a row (32 double words = 256 bytes).
During fast programming, the Flash memory clock (HCLK) frequency must be at least 8
MHz.
Only the Main memory can be programmed in Fast programming mode.
The Main Flash memory programming sequence in standard mode is described below:
1. Perform a mass or page erase. If not, PGSERR is set.
2. Check that no Main Flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR)..
3. Check and clear all error programming flag due to a previous programming.
4. Set the FSTPG bit in FLASH control register (FLASH_CR).
5. Write 32 double words to program a row (256 bytes).
6. Wait until the BSY1 bit of the FLASH status register (FLASH_SR) is cleared.
7. Check that EOP flag of the FLASH status register (FLASH_SR) is set (programming
operation succeeded), and clear it by software.
8. Clear the FSTPG bit of the FLASH status register (FLASH_SR) if there are no more
programming requests anymore.
Note: When attempting to write in Fast programming mode while a read operation is on going, the
programming is aborted without any system notification (no error flag is set).
When the Flash memory interface has received the first double word, programming is
automatically launched. The BSY1 bit is set when the high voltage is applied for the first

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double word, and it is cleared when the last double word has been programmed or in case
of error. The internal oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is
set, and disabled automatically when FSTPG bit is cleared, except if the HSI16 is previously
enabled with HSION in RCC_CR register.
The 32 double words must be written successively. The high voltage is kept on the Flash
memory for all the programming. Maximum time between two double words write requests
is the time programming (around 20 µs). If a second double word arrives after this time
programming, fast programming is interrupted and MISSERR is set.
High voltage must not exceed 8 ms for a full row between two erases. This is guaranteed by
the sequence of 32 double words successively written with a clock system greater or equal
to 8 MHz. An internal time-out counter counts 7 ms when Fast programming is set and stops
the programming when time-out is over. In this case the FASTERR bit is set.
If an error occurs, high voltage is stopped and next double word to programmed is not
programmed. Anyway, all previous double words have been properly programmed.

Programming errors
Several kind of errors can be detected. In case of error, the Flash memory operation
(programming or erasing) is aborted.
• PROGERR: Programming Error
In standard programming: PROGERR is set if the word to write is not previously erased
(except if the value to program is full zero).
• SIZERR: Size Programming Error
In standard programming or in fast programming: only double word can be
programmed, and only 32-bit data can be written. SIZERR is set if a byte or an
half-word is written.
• PGAERR: Alignment Programming error
PGAERR is set if one of the following conditions occurs:
– In standard programming: the first word to be programmed is not aligned with a
double word address, or the second word doesn’t belong to the same double word
address.
– In fast programming: the data to program doesn’t belong to the same row than the
previous programmed double words, or the address to program is not greater than
the previous one.
• PGSERR: Programming Sequence Error
PGSERR is set if one of the following conditions occurs:
– In the standard programming sequence or the fast programming sequence: a data
is written when PG and FSTPG are cleared.
– In the standard programming sequence or the fast programming sequence: MER1
and PER are not cleared when PG or FSTPG is set.
– In the fast programming sequence: the Mass erase is not performed before setting
the FSTPG bit.
– In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1 is
set.
– In the page erase sequence: PG, FSTPG and MER1 are not cleared when PER is
set.
– PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,
FASTERR or PGSERR is set due to a previous programming error.

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• WRPERR: Write Protection Error

WRPERR is set if one of the following conditions occurs:
– Attempt to program or erase in a write protected area (WRP).
– Attempt to perform a mass erase when one page or more is protected by WRP.
– The debug features are connected or the boot is executed from SRAM or from
system Flash memory when the read protection (RDP) is set to Level 1.
– Attempt to modify the option bytes when the read protection (RDP) is set to
Level 2.
• MISSERR: Fast Programming Data Miss Error
In fast programming: all the data must be written successively. MISSERR is set if the
previous data programmation is finished and the next data to program is not written yet.
• FASTERR: Fast Programming Error
In fast programming: FASTERR is set if one of the following conditions occurs:
– when FSTPG bit is set for more than 8 ms, which generates a time-out detection
– when the row fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR
If an error occurs during a program or erase operation, one of the following error flags of the
FLASH status register (FLASH_SR) is set:
• PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)
• WRPERR (protection error flag)
In this case, if the error interrupt enable bit ERRIE of the FLASH control register
(FLASH_CR) is set, an interrupt is generated and the operation error flag OPERR of the
FLASH status register (FLASH_SR) is set.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write request.

Programming and cache

If an erase operation in Flash memory also concerns data in the instruction cache, the user
has to ensure that these data are rewritten before they are accessed during code execution.
Note: The cache should be flushed only when it is disabled (ICEN = 0).

3.3.9 Read-while-write (RWW) function

Dual-bank devices support read-while-write function that allows reading from one bank
while erasing or programming within the other bank.
Note: Write-while-write operation, such as erasing within one bank while programming the other,
is not allowed.

Reading while page erasing

To erase a page in one bank while executing the code in the other bank, proceed as follows:

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1. Check that the busy flag of the bank to erase (BSY1 or BSY2) in the FLASH status
register (FLASH_SR) is low (no erase/programming in progress).
2. Set up the page erase, by setting the PER, PSB, and BKER bitfileds of the FLASH
control register (FLASH_CR).
3. Trigger the erase operation by setting the STRT bit of the FLASH control register
(FLASH_CR). This sets the corresponding busy flag BSY1 or BSY2.
The erase operation is completed when the corresponding busy flag (BSY1 or BSY2) is
back to low. The EOP interrupt can be used to indicate that event to the application
software.

Reading while bank erasing

To erase a bank while executing the code in the other bank, proceed as follows:
1. Check that the busy flag of the bank to erase (BSY1 or BSY2) in the FLASH status
register (FLASH_SR) is low (no erase/programming in progress).
2. Set the mass-erasure bit of the bank to erase (MER1 or MER2) in the FLASH control
register (FLASH_CR).
3. Trigger the erase operation by setting the STRT bit of the FLASH control register
(FLASH_CR). This sets the corresponding busy flag BSY1 or BSY2.
The erase operation is completed when the corresponding busy flag (BSY1 or BSY2) is
back to low. The EOP interrupt can be used to indicate that event to the application
software.

Reading while programming

To program a bank while executing the code in the other bank, proceed as follows:
1. Check that the busy flag of the bank to program (BSY1 or BSY2) in the FLASH status
register (FLASH_SR) is low (no erase/programming in progress).
2. Set the PG bit of the FLASH control register (FLASH_CR).
3. Write a word at a desired address within the bank to program. This sets the
corresponding busy flag (BSY1 or BSY2).
4. When the corresponding busy flag (BSY1 or BSY2) is back to low an there is more data
to write, go to the step 3
The word write operation is completed when the corresponding busy flag (BSY1 or BSY2) is
back to low. The EOP interrupt can be used to indicate that event to the application
software.

3.4 FLASH option bytes

3.4.1 FLASH option byte description

The option bytes are configured by the end user depending on the application requirements.
As a configuration example, the watchdog may be selected in hardware or software mode
(refer to Section 3.4.2: FLASH option byte programming).
A double word is split up in option bytes as indicated in Table 11.

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Table 11. Option byte format

63-56 55-48 47-40 39-32 31-24 23-16 15 -8 7-0

Complemented Complemented Complemented Complemented Option Option Option Option

option byte 3 option byte 2 option byte 1 option byte 0 byte 3 byte 2 byte 1 byte 0

The organization of these bytes in the information block is shown in Table 12 (superset for
single-bank and dual-bank devices). The option bytes can be read from the Flash memory
locations listed in Table 12 or from the Option byte registers:
• FLASH option register (FLASH_OPTR)
• FLASH WRP area A address register (FLASH_WRP1AR)
• FLASH WRP area B address register (FLASH_WRP1BR)
• FLASH WRP2 area A address register (FLASH_WRP2AR)
• FLASH WRP2 area B address register (FLASH_WRP2BR)

Table 12. Organization of option bytes

Address(1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
RAM_PARITY_CHECK

nSWAP_BANK

nRST_STDBY
IWDG_STOP
DUAL_BANK

IWDG_STBY
nBOOT_SEL

nRST_STOP
WWDG_SW

IWDG_SW
Reserved

Reserved

Reserved

Reserved
nBOOT0
nBOOT1

0x1FFF7800 RDP

0x1FFF7808
- Reserved
0x1FFF7840
0x1FFF7818 Reserved WRP1A_END Reserved WRP1A_STRT
0x1FFF7820 Reserved WRP1B_END Reserved WRP1B_STRT
0x1FFF7848 Reserved WRP2A_END Reserved WRP2A_STRT
0x1FFF7850 Reserved WRP2B_END Reserved WRP2B_STRT
1. The upper 32-bits of the double-word address contain the inverted data from the lower 32 bits.

User and read protection option bytes

Flash memory address: 0x1FFF 7800
Reset value: 0xDFFF E1AA (ST production value)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RAM_P
IWGD
n n nBOOT ARITY DUAL_ nSWAP WWDG IWDG IWDG
Res. Res. Res. Res. Res. Res. _STDB
BOOT0 BOOT1 _SEL _CHEC BANK _BANK _SW _STOP _SW
Y
K
r r r r r r r r r r

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_ nRST_
Res. Res. Res. Res. Res. Res. RDP[7:0]
STDBY STOP
r r r r r r r r r r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 25 nBOOT1: Boot configuration
Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit
configuration), this bit selects boot mode from the Main Flash memory, SRAM or the
System memory. Refer to Section 2.5: Boot configuration.
Bit 24 nBOOT_SEL: BOOT0 signal source selection
This option bit defines the source of the BOOT0 signal.
0: BOOT0 pin (legacy mode)
1: nBOOT0 option bit
Bit 23 Reserved, must be kept at reset value.
Bit 22 RAM_PARITY_CHECK: SRAM parity check control enable
0: Enable
1: Disable
Bit 21 DUAL_BANK: Dual-bank on 512 Kbytes Flash memory devices
0: 512 Kbytes single-bank Flash memory, contiguous addresses in Bank 1
1: 512 Kbytes dual-bank Flash memory, Refer to Table 9
Bit 20 nSWAP_BANK: Empty check boot configuration
This bit selects the bank that is the subject of empty check upon boot.
0: Bank 1
1: Bank 2
This bit pertains to dual-bank devices only. In single-bank devices, it is reserved.
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode

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Bit 13 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
Bits 12:8 Reserved, must be kept at reset value.
Bits 7:0 RDP[7:0]: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active

WRP1A address option bytes

Flash memory address: 0x1FFF 7818
Reset value: 0x0000 00FF (ST production value)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[6:0]
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_STRT[6:0]
r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1A_END[6:0]: WRP area A end offset (Bank 1)
WRP1A_END contains the offset of the last page of the WRP area A (in Bank 1 for dual-
bank devices).
Note: Values corresponding to addresses outside the Main memory are not allowed.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset (Bank 1)
WRP1A_STRT contains the offset of the first page of the WRP area A (in Bank 1 for dual-
bank devices).
Note: Values corresponding to addresses outside the Main memory are not allowed.

WRP1B address option bytes

Flash memory address: 0x1FFF 7820
Reset value: 0x0000 00FF (ST production value)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[6:0]
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_STRT[6:0]
r r r r r r r

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Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1B_END[6:0]: WRP area B end offset (Bank 1)
WRP1B_END contains the offset of the last page of the WRP area B (in Bank 1 for dual-
bank devices).
Note: Values corresponding to addresses outside the Main memory are not allowed.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset (Bank 1)
WRP1B_STRT contains the offset of the first page of the WRP area B (in Bank 1 for dual-
bank devices).
Note: Values corresponding to addresses outside the Main memory are not allowed.

WRP2A address option bytes

Flash memory address: 0x1FFF 7848
Reset value: 0x0000 00FF (ST production value)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[6:0]
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_STRT[6:0]
r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2A_END[6:0]: WRP area A end offset, Bank 2
WRP2A_END contains the offset of the last page of the WRP area A in Bank 2 of dual-bank
devices.
Note: Values corresponding to addresses outside the Main memory are not allowed.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2A_STRT[6:0]: WRP area A start offset, Bank 2
WRP2A_STRT contains the offset of the first page of the WRP area A in BAnk 2 of dual-
bank devices.
Note: Values corresponding to addresses outside the Main memory are not allowed.

WRP2B address option bytes

Flash memory address: 0x1FFF 7850
Reset value: 0x0000 00FF (ST production value)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[6:0]
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[6:0]
r r r r r r r

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Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2B_END[6:0]: WRP area B end offset, Bank 2
WRP2B_END contains the offset of the last page of the WRP area B in Bank 2 of dual-bank
devices.
Note: Values corresponding to addresses outside the Main memory are not allowed.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2B_STRT[6:0]: WRP area B start offset
WRP2B_STRT contains the offset of the first page of the WRP area B in Bank 2 of dual-
bank devices.
Note: Values corresponding to addresses outside the Main memory are not allowed.

3.4.2 FLASH option byte programming

After reset, the options related bits of the FLASH control register (FLASH_CR) are write-
protected. To run any operation on the option bytes page, the option lock bit OPTLOCK of
the FLASH control register (FLASH_CR) must be cleared. The following sequence is used
to unlock this register:
1. Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash
memory)
2. Write OPTKEY1=0x08192A3B of the FLASH option key register (FLASH_OPTKEYR)
3. Write OPTKEY2=0x4C5D6E7F of the FLASH option key register (FLASH_OPTKEYR)
Any wrong sequence locks up the Flash memory option registers until the next system
reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault
interrupt is generated.
The user options can be protected against unwanted erase/program operations by setting
the OPTLOCK bit by software.
Note: If LOCK is set by software, OPTLOCK is automatically set as well.

Modifying user options

The option bytes are programmed differently from a Main memory user address.
To modify the value of user options, follow the procedure below:
1. Clear OPTLOCK option lock bit with the clearing sequence described above
2. Write the desired values in the FLASH option registers.
3. Check that no Flash memory operation is ongoing, by checking the BSY1 bit of the
FLASH status register (FLASH_SR)..
4. Set the Options Start bit OPTSTRT of the FLASH control register (FLASH_CR).
5. Wait for the BSY1 bit to be cleared.
Note: Any modification of the value of one option is automatically performed by erasing user
option byte pages first, and then programming all the option bytes with the values contained
in the Flash memory option registers.
The complementary values are automatically computed and written into the complemented
option bytes upon setting the OPTSTRT bit.
Caution: Upon an option byte programming failure (for any reason, such as loss of power or a reset
during the option byte change sequence), the mismatch values of the option bytes are

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loaded after reset. Those mismatch values force a secure configuration that might
permanently lock the device. To prevent this, only program option bytes in a safe
environment – safe supply, no pending watchdog, and clean reset line.

Option byte loading

After the BSY1 bit is cleared, all new options are updated into the Flash memory, but not
applied to the system. A read from the option registers still returns the last loaded option
byte values, the new options has effect on the system only after they are loaded.
Option bytes loading is performed in two cases:
– when OBL_LAUNCH bit of the FLASH control register (FLASH_CR) is set
– after a power reset (exit from Standby mode)
Option byte loader performs a read of the options block and stores the data into internal
option registers. These internal registers configure the system and can be read by software.
Setting OBL_LAUNCH generates a reset so the option byte loading is performed under
system reset.
Each option bit has also its complement in the same double word. During option loading, a
verification of the option bit and its complement allows to check the loading has correctly
taken place.
During option byte loading, the options are read by double word. ECC on option words is not
taken into account during OBL, but only during direct SW read of option area.
If the word and its complement are matching, the option word/byte is copied into the option
register.
If the comparison between the word and its complement fails, a status bit OPTVERR is set.
Mismatch values are forced into the option registers:
– For USR OPT option, the value of mismatch is 1 for all option bits.
– For WRP option, the value of mismatch is the default value “No protection”.
– For RDP option, the value of mismatch is the default value “Level 1”.
Upon system reset, the option bytes are copied into the following option registers that can
be read and written by software:
• FLASH_OPTR
• FLASH_WRPyxR (x = A or B, y = 1 or 2)
These registers are also used to modify options. If these registers are not modified by user,
they reflect the options states of the system. See Modifying user options for more details.

3.5 FLASH memory protection

The Main Flash memory can be protected against external accesses with the read
protection (RDP). The pages can also be protected against unwanted write (WRP) due to
loss of program counter context. The write-protection WRP granularity is 2 Kbytes.

3.5.1 FLASH read protection (RDP)

The read protection is activated by setting the RDP option byte and then, by applying a
system reset to reload the new RDP option byte. The read protection protects the Main

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Flash memory, the option bytes, the backup registers (TAMP_BKPxR in TAMP) and the
SRAM.
Note: If the read protection is set while the debugger is still connected through SWD, apply power
reset instead of system reset.
There are three levels of read protection from no protection (Level 0) to maximum protection
or no debug (Level 2).
The Flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in Table 13.

Table 13. Flash memory read protection status

RDP byte value RDP complement byte value Read protection level

0xAA 0x55 Level 0

Any values except the combinations [0xAA, 0x55] and [0xCC, 0x33] Level 1 (default)
0xCC 0x33 Level 2

The System memory area is read-accessible whatever the protection level. It is never
accessible for program/erase operation.

Level 0: no protection
Read, program and erase operations within the Main Flash memory area are possible. The
option bytes and the backup registers are also accessible by all operations.

Level 1: Read protection

Level 1 read protection is set when the RDP byte and the RDP complemented byte contain
any value combinations other than [0xAA, 0x55] and [0xCC, 0x33]. Level 1 is the default
protection level when RDP option byte is erased.
• User mode: Code executing in user mode (boot from user Flash memory) can access
Main Flash memory, option bytes and backup registers with all operations.
• Debug, boot from SRAM, and boot from System memory modes: In debug mode
or when code boots from SRAM or System memory, the Main Flash memory and the
backup registers (TAMP_BKPxR in TAMP) are totally inaccessible. In these modes, a
read or write access to the Flash memory generates a bus error and a Hard Fault
interrupt.

Level 2: No debug
In this level, the protection Level 1 is guaranteed. In addition, the CPU debug port, the boot
from RAM (boot RAM mode) and the boot from System memory (boot loader mode) are no
more available. In user execution mode (boot FLASH mode), all operations are allowed on
the Main Flash memory.
Note: The CPU debug port is also disabled under reset.
Note: STMicroelectronics is not able to perform analysis on defective parts on which the Level 2
protection has been set.

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Changing the read protection level

The read protection level can change:
• from Level 0 to Level 1, upon changing the value of the RDP byte to any value except
0xCC
• from Level 0 or Level 1 to Level 2, upon changing the value of the RDP byte to 0xCC
• from Level 1 to Level 0, upon changing the value of the RDP byte to 0xAA
Once in Level 2, it is no more possible to modify the read protection level.
The change from Level 1 to Level 0 triggers full mass erase of the Main Flash memory. The
backup registers (TAMP_BKPxR) are also erased. The user options are set to their previous
values copied from FLASH_OPTR and FLASH_WRPyxR (x = A or B, y = 1 or 2). The OTP
area is not affected by mass erase and remains unchanged.
Note: Mass erase (full or partial) is only triggered by the RDP regression from Level 1 to Level 0.
RDP level increase (Level 0 to Level 1, 1 to 2, or 0 to 2) does not cause any mass erase.
To validate the protection level change, the option bytes must be reloaded by setting the
OBL_LAUNCH bit of the FLASH control register (FLASH_CR).

Figure 3. Changing read protection (RDP) level

Level 1
RDP ≠ 0xAA ≠ 0xCC

RDP = 0xAA
RDP = 0xCC RDP ≠ 0xCC ≠ 0xAA

Level 2 Level 0
RDP = 0xCC RDP = 0xAA
RDP = 0xCC

Read-protection level increase

Read-protection level decrease (with full or partial mass erase)

Erase/program option bytes without changing read-protection level (RDP kept unchanged)

MSv33468V3

Table 14. Access status versus protection level and execution modes
Debug/ BootFromRam/
Protection User execution (BootFromFlash)
Area BootFromLoader
level
Read Write Erase Read Write Erase

Main Flash 1 Yes Yes Yes No No No(3)

memory 2 Yes Yes Yes N/A(1) N/A(1) N/A(1)
System 1 Yes No No Yes No No
memory(2) 2 Yes No No N/A(1) N/A(1) N/A(1)

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Table 14. Access status versus protection level and execution modes (continued)
Debug/ BootFromRam/
Protection User execution (BootFromFlash)
Area BootFromLoader
level
Read Write Erase Read Write Erase
1 Yes Yes(3) Yes Yes Yes(3) Yes
Option bytes (1)
2 Yes No No N/A N/A(1) N/A(1)
Backup 1 Yes Yes N/A No No No(4)
registers 2 Yes Yes N/A N/A(1) N/A(1) N/A(1)
1 Yes Yes N/A No No N/A
OTP (1)
2 Yes Yes N/A N/A N/A(1) N/A(1)
1. When the protection Level 2 is active, the Debug port, the boot from RAM and the boot from System memory are disabled.
2. The System memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The Flash Main memory is erased when the RDP option byte is programmed with all level of protections disabled (0xAA).
4. The backup registers are erased when RDP changes from Level 1 to Level 0.

3.5.2 FLASH write protection (WRP)

The user area in Flash memory can be protected against unwanted write operations. Two
write-protected (WRP) areas can be defined, with page (2-Kbyte) granularity. Each area is
defined by a start page offset and an end page offset related to the physical Flash memory
base address. These offsets are defined in the WRP address registers FLASH WRP area A
address register (FLASH_WRP1AR) and FLASH WRP area B address register
(FLASH_WRP1BR), and, for dual-bank devices, also FLASH WRP2 area A address
register (FLASH_WRP2AR) and FLASH WRP2 area B address register
(FLASH_WRP2BR).
The WRP x area (x = A, B) of bank y (y = 1 or 2) is defined from the address
Flash memory Base address + [WRPyx_STRT x 0x0800] (included)
to the address
Flash memory Base address + [(WRPyx_END+1) x 0x0800] (excluded).
The minimum WRP area size is one WRP page (2 Kbytes):
WRPyx_END = WRPyx_STRT.
For example, to protect the Bank 1 of Flash memory by WRP from the address 0x0800 1000
(included) to the address 0x0800 3FFF (included):
If boot in Flash memory is selected, FLASH_WRP1AR register must be programmed
with:
– WRP1A_STRT = 0x02.
– WRP1A_END = 0x07.
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area B in
Flash memory).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.

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If an erase/program operation to a write-protected part of the Flash memory is attempted,

the write protection error flag (WRPERR) of the FLASH_SR register is set. This flag is also
set for any write access to:
– OTP area
– part of the Flash memory that can never be written like the ICP
Note: When the Flash memory read protection level is selected (RDP level = 1), it is not possible
to program or erase the memory if the CPU debug features are connected (single wire) or
boot code is being executed from SRAM or system Flash memory, even if WRP is not
activated. Any attempt generates a hard fault (BusFault).

Table 15: WRP protection

WRP registers values
WRP-protected area
(x = A or B, y= 1 or 2)

WRPyx_STRT = WRPyx_END Page WRPyx

WRPyx_STRT > WRPyx_END None (unprotected)
WRPyx_STRT < WRPyx_END Pages from WRPyx_STRT to WRPyx_END

Note: To validate the WRP options, the option bytes must be reloaded by setting the
OBL_LAUNCH bit in Flash memory control register.

3.6 FLASH interrupts

Table 16. FLASH interrupt requests
Event flag/interrupt Interrupt enable
Interrupt event Event flag
clearing method control bit

End of operation EOP(1) Write EOP=1 EOPIE

(2)
Operation error OPERR Write OPERR=1 ERRIE
Write protection error WRPERR Write WRPERR=1 N/A
Size error SIZERR Write SIZERR=1 N/A
Programming sequential error PROGERR Write PROGERR=1 N/A
Programming alignment error PGAERR Write PGAERR=1 N/A
Programming sequence error PGSERR Write PGSERR=1 N/A
Data miss during fast programming error MISSERR Write MISSERR=1 N/A
Fast programming error FASTERR Write FASTERR=1 N/A
ECC error correction ECCC Write ECCC=1 ECCCIE
ECC double error (NMI) ECCD Write ECCD=1 N/A
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.

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3.7 FLASH registers

3.7.1 FLASH access control register (FLASH_ACR)

Address offset: 0x000
Reset value: 0x0004 0600
s

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EMPTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. ICRST Res. ICEN PRFTEN Res. Res. Res. Res. Res. LATENCY[2:0]
rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 EMPTY: Main Flash memory area empty
This bit indicates whether the first location of the Main Flash memory area is erased or has a
programmed value.
0: Main Flash memory area programmed
1: Main Flash memory area empty
The bit can be set and reset by software.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 ICRST: CPU Instruction cache reset
0: CPU Instruction cache is not reset
1: CPU Instruction cache is reset
This bit can be written only when the instruction cache is disabled.
Bit 10 Reserved, must be kept at reset value.
Bit 9 ICEN: CPU Instruction cache enable
0: CPU Instruction cache is disabled
1: CPU Instruction cache is enabled
Bit 8 PRFTEN: CPU Prefetch enable
0: CPU Prefetch disabled
1: CPU Prefetch enabled
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Flash memory access latency
The value in this bitfield represents the ratio of the HCLK clock period to the Flash memory
access time.
000: Zero wait states
001: One wait state
010: Two wait states
Others: Reserved
A a new write into the bitfield becomes effective when it returns the same value upon read.

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3.7.2 FLASH key register (FLASH_KEYR)

Address offset: 0x008
Reset value: 0x0000 0000
s

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[31:0]: FLASH key

The following values must be written consecutively to unlock the FLASH control register
(FLASH_CR), thus enabling programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB

3.7.3 FLASH option key register (FLASH_OPTKEYR)

Address offset: 0x00C
Reset value: 0x0000 0000
s

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 OPTKEY[31:0]: Option byte key

The following values must be written consecutively to unlock the Flash memory option
registers, enabling option byte programming/erasing operations:
KEY1: 0x0819 2A3B
KEY2: 0x4C5D 6E7F

3.7.4 FLASH status register (FLASH_SR)

Address offset: 0x010
Reset value: 0x000X 0000
es

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFGBSY BSY2 BSY1
r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTV FAST MISS PGS SIZ PGA WRP PROG OP
Res. Res. Res. Res. Res. Res. EOP
ERR ERR ERR ERR ERR ERR ERR ERR ERR
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

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Bits 31:19 Reserved, must be kept at reset value.

Bit 18 CFGBSY: Programming or erase configuration busy.
This flag is set and reset by hardware. (set when first word is sent and reset when program
operation completes or is interrupted by an error.)
When set to 1 the programming and erase settings in requested by FLASH control register
(FLASH_CR) are used (busy), and cannot be changed (a programming or erase operation is
ongoing).
When reset to 0 programming and erase settings in in FLASH control register (FLASH_CR)
can be modified.
Bit 17 BSY2: Busy
This flag indicates that a Flash memory Bank 2 operation requested by FLASH control
register (FLASH_CR) is in progress. This bit is set at the beginning of the Flash memory
operation, and cleared when the operation finishes or when an error occurs.
Bit 16 BSY1: Busy
This flag indicates that a Flash memory (Bank 1 for dual-bank devices) operation requested
by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the
Flash memory operation, and cleared when the operation finishes or when an error occurs.
Bit 15 OPTVERR: Option and Engineering bits loading validity error
Set by hardware when the options and engineering bits read may not be the one configured
by the user or production. If options and engineering bits haven’t been properly loaded,
OPTVERR is set again after each system reset. Option bytes that fail loading are forced to a
safe value, see Section 3.4.2: FLASH option byte programming.
Cleared by writing 1.
Bits 14:10 Reserved, must be kept at reset value.
Bit 9 FASTERR: Fast programming error
Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted
due to an error (alignment, size, write protection or data miss). The corresponding status bit
(PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time.
Cleared by writing 1.
Bit 8 MISSERR: Fast programming data miss error
In Fast programming mode, 32 double words (256 bytes) must be sent to Flash memory
successively, and the new data must be sent to the logic control before the current data is
fully programmed. MISSERR is set by hardware when the new data is not present in time.
Cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while
PG or FSTPG have not been set previously. Set also by hardware when PROGERR,
SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous
programming error.
Cleared by writing 1.
Bit 6 SIZERR: Size error
Set by hardware when the size of the access is a byte or half-word during a program or a fast
program sequence. Only double word programming is allowed (consequently: word access).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same double word
(64-bit) Flash memory in case of standard programming, or if there is a change of page
during fast programming.
Cleared by writing 1.

76/989 RM0454 Rev 5

RM0454 Embedded Flash memory (FLASH)

Bit 4 WRPERR: Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected
part (by WRP or RDP Level 1) of the Flash memory.
Cleared by writing 1.
Bit 3 PROGERR: Programming error
Set by hardware when a double-word address to be programmed contains a value different
from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Set by hardware when a Flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE=1).
Cleared by writing ‘1’.
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operation (programming / erase) has
been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE=1).
Cleared by writing 1.

3.7.5 FLASH control register (FLASH_CR)

Address offset: 0x014
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
This register cannot be modified when CFGBSY in FLASH status register (FLASH_SR) is
set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPT OBL_ OPT
LOCK Res. Res. Res. ERRIE EOPIE Res. Res. Res. Res. Res. FSTPG STRT
LOCK LAUNCH STRT
rs rs rc_w1 rw rw rw rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER2 Res. BKER PNB[9:0] MER1 PER PG
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 LOCK: FLASH_CR Lock

This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware
after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Bit 30 OPTLOCK: Options Lock
This bit is set only. When set, all bits concerning user option in FLASH_CR register and so
option page are locked. This bit is cleared by hardware after detecting the unlock sequence.
The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 29:28 Reserved, must be kept at reset value.

RM0454 Rev 5 77/989

85
Embedded Flash memory (FLASH) RM0454

Bit 27 OBL_LAUNCH: Option byte load launch

When set, this bit triggers the load of option bytes into option registers. It is automatically
cleared upon the completion of the load. The high state of the bit indicates pending option
byte load.
The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
Bit 26 Reserved, must be kept at reset value.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR
register.
0: Disable
1: Enable
Bit 24 EOPIE: End-of-operation interrupt enable
This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
0: Disable
1: Enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: Fast programming enable
0: Disable
1: Enable
Bit 17 OPTSTRT: Start of modification of option bytes
This bit triggers an options operation when set.
This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
Bit 16 STRT: Start erase operation
This bit triggers an erase operation when set.
This bit is possible to set only by software and to clear only by hardware. The hardware
clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
Bit 15 MER2: Mass erase, Bank 2
When set, this bit triggers the mass erase of Bank 2 (all user pages).
Bits 14 Reserved, must be kept at reset value.
Bit 13 BKER: Bank selection for erase operation
This bit selects the target of erase operation (Bank 1 or Bank 2).
0: Bank 1
1: Bank 2
The bit has no effect on the single-bank devices.
Bits 12:3 PNB[9:0]: Page number selection
These bits select the page to erase:
0x00: page 0
0x01: page 1
...
0x17F: page 383
Note: Values corresponding to addresses outside the Main memory are not allowed.

78/989 RM0454 Rev 5

RM0454 Embedded Flash memory (FLASH)

Bit 2 MER1: Mass erase (Bank 1)

When set, this bit triggers the mass erase, that is, all user pages (of Bank 1 for dual-bank
devices).
Bit 1 PER: Page erase enable
0: Disable
1: Enable
Bit 0 PG: Flash memory programming enable
0: Disable
1: Enable

3.7.6 FLASH ECC register (FLASH_ECCR)

Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
This register applies to single-bank products and to Bank 1 of dual-bank products.

Bit 31 ECCD: ECC detection

Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
Cleared by writing 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: System Flash memory ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system Flash memory.
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:0 ADDR_ECC[13:0]: ECC fail double-word address offset
In case of ECC error or ECC correction detected, this bitfield contains double-word offset
(multiple of 64 bits) to Main Flash memory.

RM0454 Rev 5 79/989

85
Embedded Flash memory (FLASH) RM0454

3.7.7 FLASH ECC register 2 (FLASH_ECCR2)

Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
This register applies to Bank 2 of dual-bank products.

Bit 31 ECCD: ECC detection

Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
Cleared by writing 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: System Flash memory ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system Flash memory.
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:0 ADDR_ECC[13:0]: ECC fail double-word address offset
In case of ECC error or ECC correction detected, this bitfield contains double-word offset
(multiple of 64 bits) to Main Flash memory.

3.7.8 FLASH option register (FLASH_OPTR)

Address offset: 0x020
Reset value: 0b1101 1XXX 1X1X XXXX 1XX0 0001 XXXX XXXX (The option bits are
loaded with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RAM
_ IWGD
n n nBOOT DUAL_ SWAP WWDG IWDG IWDG
Res. Res. Res. Res. Res. Res. PARITY _
BOOT0 BOOT1 _SEL BANK _BANK _SW _STOP _SW
_ STDBY
CHECK
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_ nRST_
Res. Res. Res. Res. Res. Res. RDP[7:0]
STDBY STOP
rw rw rw rw rw rw rw rw rw rw

80/989 RM0454 Rev 5

RM0454 Embedded Flash memory (FLASH)

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 nBOOT0: nBOOT0 option bit
0: nBOOT0=0
1: nBOOT0=1
Bit 25 nBOOT1: Boot configuration
Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit
configuration), this bit selects boot mode from the Main Flash memory, SRAM or the
System memory. Refer to Section 2.5: Boot configuration
Bit 24 nBOOT_SEL
0: BOOT0 signal is defined by BOOT0 pin value (legacy mode)
1: BOOT0 signal is defined by nBOOT0 option bit
Bit 23 Reserved, must be kept at reset value.
Bit 22 RAM_PARITY_CHECK: SRAM parity check control
0: SRAM parity check enable
1: SRAM parity check disable
Bit 21 DUAL_BANK: Dual-bank on 512 Kbytes or 256 Kbytes Flash memory devices
0: 256 Kbytes/512 Kbytes single-bank Flash memory, contiguous addresses in Bank 1
1: 256 Kbytes/512 Kbytes dual-bank Flash memory, Refer to Table 9
Bit 20 nSWAP_BANK: Empty check boot configuration
This bit selects the bank that is the subject of empty check upon boot.
0: Bank 1
1: Bank 2

Bit 19 WWDG_SW: Window watchdog selection

0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generated when entering the Standby mode
Bit 13 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode

RM0454 Rev 5 81/989

85
Embedded Flash memory (FLASH) RM0454

Bits 12:8 Reserved, must be kept at reset value.

Bits 7:0 RDP[7:0]: Read protection level
Note: 0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active

3.7.9 FLASH WRP area A address register (FLASH_WRP1AR)

Address offset: 0x02C
Reset value: 0x00XX 00XX (The option bits are loaded with values from Flash memory at
power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_STRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1A_END[6:0]: WRP area A end offset (Bank 1)
This bitfield contains the offset of the last page of the WRP area A (in Bank 1 for dual-bank
devices).(1)
Bits 15:6 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset (Bank 1)
This bitfield contains the offset of the first page of the WRP area A (in Bank 1 for dual-bank
devices).(1)
1. The number of effective bits depends on the size of Flash memory in the device.

3.7.10 FLASH WRP area B address register (FLASH_WRP1BR)

Address offset: 0x030
Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[6:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_STRT[6:0]
rw rw rw rw rw rw rw rw

82/989 RM0454 Rev 5

RM0454 Embedded Flash memory (FLASH)

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1B_END[6:0]: WRP area B end offset (Bank 1)
This bitfield contains the offset of the last page of the WRP area B (in Bank 1 for dual-bank
devices).(1)
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset (Bank 1)
This bitfield contains the offset of the first page of the WRP area B (in Bank 1 for dual-bank
devices).(1)
1. The number of effective bits depends on the size of Flash memory in the device.

3.7.11 FLASH WRP2 area A address register (FLASH_WRP2AR)

Address offset: 0x04C
Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_STRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2A_END[6:0]: WRP area A end offset, Bank 2
This bitfield contains the offset of the last page of the WRP area A in Bank 2.(1)
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2A_STRT[6:0]: WRP area A start offset, Bank 2
This bitfield contains the offset of the first page of the WRP area A in Bank 2.(1)
1. The number of effective bits depends on the size of Flash memory in the device.

RM0454 Rev 5 83/989

85
Embedded Flash memory (FLASH) RM0454

3.7.12 FLASH WRP2 area B address register (FLASH_WRP2BR)

Address offset: 0x050
Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2B_END[6:0]: WRP area B end offset, Bank 2
This bitfield contains the offset of the last page of the WRP area B in Bank 2.(1)
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2B_STRT[6:0]: WRP area B start offset, Bank 2
This bitfield contains the offset of the first page of the WRP area B in Bank 2.(1)
1. The number of effective bits depends on the size of Flash memory in the device.

84/989 RM0454 Rev 5

 0x050
0x030
0x020
0x018
0x014
0x010
0x008
0x004
0x000

0x07F
0x02B

0x04C
0x02C
0x00C
Offset

0x034 -
0x024 -
3.7.13
RM0454

KEYR

FLASH_
FLASH_
FLASH_
FLASH_

Reserved
Reserved
Reserved

WRP2BR
WRP2AR
WRP1BR
WRP1AR
Register

FLASH_SR

FLASH_CR
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
FLASH_OPT
FLASH_ACR

FLASH_KEYR

FLASH_OPTR
FLASH_ECCR

0
1
0
0
Res. Res. Res. Res. Res. Res. Res. ECCD LOCK Res. Res. Res. 31

0
1
0
0
Res. Res. Res. Res. Res. Res. Res. ECCC OPTLOCK Res. Res. Res. 30

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. OBL_LAUNCH Res. Res. Res. 27

0
0

X
Res. Res. Res. Res. Res. Res. .nBOOT0 Res. Res. Res. Res. Res. 26

0
0
0

X
Res. Res. Res. Res. Res. Res. nBOOT1 Res. ERRIE Res. Res. Res. 25
FLASH register map

0
0
0
0

X
Res. Res. Res. Res. Res. Res. nBOOT_SEL ECCCIE EOPIE Res. Res. Res. 24

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
0
0

X
X
X
X
X
Res. Res. RAM_PARITY_CHECK Res. Res. Res. 0 Res. Res. 22
0

X
X
X
X
X
Res. Res. DUAL_BANK Res. Res. Res. Res. Res. 21

0
0
0

X
X
X
X
Res. Res. Res. SYSF_ECC Res. Res. Res. Res. 20
0
0

X
X
X
X
X
Res. Res. WWDG_SW Res. Res. Res. Res. Res. 19

0
0
0
0

X
X
X
X
X
Res. Res. IWDG_STBY Res. FSTPG CFGBSY Res. Res. 18

0
0
0
0

X
X
X
X
X

RM0454 Rev 5
Res. Res. IWDG_STOP Res. OPTSTRT BSY2 Res. Res. 17

WRP2B_END[6:0]
WRP2A_END[6:0]
WRP1B_END[6:0]
WRP1A_END[6:0]
0
0
0
0
X

X
X
X
X
X
Res. Res. IWDG_SW Res. STRT BSY1 Res. EMPTY 16

0
0
0

X
X

Res. Res. Res. Res. Res. Res. Res. Res. MER2 OPTVERR Res. Res. 15
KEYR[31:0]

0
0

X
Res. Res. Res. Res. Res. Res. nRST_STDBY Res. Res. Res. Res. Res. 14
OPTKEY[31:0]
0

0
0
0

X
Res. Res. Res. Res. Res. Res. nRST_STOP BKER Res. Res. Res. 13
0
0

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
0

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. ICRST 11
Table 17. FLASH register map and reset values

0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
0
0
1

0
0
0

Res. Res. Res. Res. Res. Res. Res. FASTERR Res. ICEN 9

Refer to Section 2.2 on page 44 for the register boundary addresses.

0
0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. MISERR Res. PRFTEN 8
0
0
0

0
0

X
Res. Res. Res. Res. Res. Res. PGSERR Res. Res. 7
PNB[9:0]
0

0
0
0

X
X
X
X
X
Res. Res. SIZERR Res. Res. 6
0
0

0
0
0

X
X
X
X
X
Res. Res. PGAERR Res. Res. 5
ADDR_ECC[13:0]
0
0

0
0
0

X
X
X
X
X
Res. Res. WRPERR Res. Res. 4
0
0

0
0
0

X
X
X
X
X
Res. Res. PROGERR Res. Res. 3
RDP[7:0]
0
0
0
0

X
X
X
X
X
Res. Res. MER1 Res. Res. 2
0
0
0
0

0
0

X
X
X
X
Res. Res. X PER OPERR Res. 1
[2:0]

WRP2B_STRT[6:0]
WRP2A_STRT[6:0]
WRP1B_STRT[6:0]
WRP1A_STRT[6:0]
0
0
0
0

0
0

X
X
X
X
X
Res. Res. PG EOP Res. 0
LATENCY
Embedded Flash memory (FLASH)

85/989
85
Power control (PWR) RM0454

4 Power control (PWR)

4.1 Power supplies

The STM32G0x0 devices require a 2.0 V to 3.6 V operating supply voltage (VDD). Several
different power supplies are provided to specific peripherals:
• VDD = 2.0 V to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
• VDDA = 2.0 V to 3.6 V
VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to
VDD voltage as it is provided externally through VDD/VDDA pin.
• VDDIO1 = VDD
VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage
as it is provided externally through VDD/VDDA pin.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply (through a power switch) for RTC, TAMP, low-speed external
32.768 kHz oscillator and backup registers when VDD is not present. VBAT is provided
externally through VBAT pin. When this pin is not available on the package, it is
internally bonded to VDD/VDDA.
• VREF+ is the input reference voltage for the ADC. It must be between 2 V and VDDA. It
can be grounded when the ADC is not active.
VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is
internally connected with VDD.
• VCORE
An embedded linear voltage regulator is used to supply the VCORE internal digital
power. VCORE is the power supply for digital peripherals, SRAM and Flash memory.
The Flash memory is also supplied by VDD.

86/989 RM0454 Rev 5

RM0454 Power control (PWR)

Figure 4. Power supply overview

VDDA domain
VREF+
VREF+
VDDA A/D converter
VSSA

VDDIO1 domain
VDDIO1
I/O ring

VDD domain

Reset block
Temp. sensor VCORE domain
PLL, HSI
Core
VSS Standby circuitry
VSS/VSSA (Wakeup, IWDG) SRAM
VDD VCORE Digital
VDD/VDDA Voltage
regulator peripherals

Low-voltage Flash memory

detector

RTC domain
BKP registers
VBAT
LSE crystal 32.768 kHz osc
RCC BDCR register
RTC and TAMP

MSv47920V1

4.1.1 ADC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) signal.

4.1.2 Battery backup of RTC domain

To retain the content of the backup registers and supply the RTC and TAMP functions when
VDD is turned off, the VBAT pin can be connected to an optional backup voltage supplied by
a battery or by another source.
The VBAT pin powers the RTC and TAMP units, the LSE oscillator and the PC13 to PC15
I/Os, allowing the RTC and TAMP to operate even when the main power supply is turned off.
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset
block.

Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR

has been detected, the power switch between VBAT and VDD
remains connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot

RM0454 Rev 5 87/989

118
Power control (PWR) RM0454

support this current injection, it is recommended to connect

an external low-drop diode between this power supply and
the VBAT pin.

If no external battery is used in the user application, it is recommended to connect VBAT pin
externally to VDD/VDDA pin with a 100 nF external ceramic decoupling capacitor.
When the RTC domain is supplied by VDD (power switch connected to VDD), all the related
pin functions are available:
When the RTC domain is supplied by VBAT (power switch connected to VBAT because VDD
is not present), only the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to
Section 23.3: RTC functional description)
• RTC_OUT1 function on PC13
• RTC_TS function on PC13 or PA4
• TAMP_IN1 function on PC13 or PA4 and TAMP_IN2 function on PA0
Note: Due to the fact that the power switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(e.g. to drive a LED).

RTC domain access

After a system reset, the RTC domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the RTC domain, proceed
as follows:
1. Enable the power interface clock by setting the PWREN bits of the APB peripheral
clock enable register 1 (RCC_APBENR1).
2. Set the DBP bit of the Power control register 1 (PWR_CR1) to enable access to the
RTC domain.
3. Select the RTC clock source in the RTC domain control register (RCC_BDCR).
4. Enable the RTC clock by setting the RTCEN bit in the RTC domain control register
(RCC_BDCR).

VBAT battery charging

When VDD is present, it is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kΩ resistor or through a 1.55 kΩ resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.

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4.1.3 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the RTC domain. The main regulator output voltage (VCORE) can be
programmed by software to two different power ranges (Range 1 and Range 2) in order to
optimize the consumption depending on the system maximum operating frequency (refer to
Section 5.2.7: Clock source frequency versus voltage scaling and to Section 3.3.4: FLASH
read access latency.
The voltage regulators are always enabled after a reset. Depending on the user application
modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power
regulator (LPR).
• In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the VCORE domain (core, memories and digital peripherals).
• In Low-power run and Low-power sleep modes, the main regulator is off and the low-
power regulator (LPR) supplies low-power to the VCORE domain, preserving the
contents of the registers and SRAM.
• In Stop 1 mode, the main regulator is off and the low-power regulator (LPR) supplies
low-power to the VCORE domain, preserving the contents of the registers and SRAM.
• In Standby mode, both regulators are powered off. The contents of the registers and
SRAM is lost except for the Standby circuitry and the RTC domain.

4.1.4 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the application performance and power consumption needs.
Dynamic voltage scaling to increase VCORE is known as overvolting. It allows to improve the
device performance.
Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
Two voltage ranges are available:
• Range 1: High-performance range
The main regulator provides a typical output voltage at 1.2 V. The system clock
frequency can be up to 64 MHz. The Flash access time for read access is minimum,
write and erase operations are possible.
• Range 2: Low-power range
The main regulator provides a typical output voltage at 1.0 V. The system clock
frequency can be up to 16 MHz.The Flash memory access time for a read access is
increased as compared to Range 1; write and erase operations are not possible.
The voltage scaling is selected through the VOS bit in the PWR_CR1 register.
The sequence to go from Range 1 to Range 2 is:
1. Reduce the system frequency to a value lower than 16 MHz
2. Adjust number of wait states according new frequency target in Range 2 (LATENCY
bits in the FLASH_ACR).
3. Program the VOS[1:0] bits to 10 in the Power control register 1 (PWR_CR1).

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The sequence to go from Range 2 to Range 1 is:

1. Program the VOS[1:0] bits to 01 in the Power control register 1 (PWR_CR1).
2. Wait until the VOSF flag is cleared in the Power status register 2 (PWR_SR2).
3. Adjust number of wait states according new frequency target in Range 1 (LATENCY
bits in the FLASH access control register (FLASH_ACR).
4. Increase the system frequency.

4.2 Power supply supervisor

4.2.1 Power-on reset (POR) / power-down reset (PDR)

The device features an integrated power-on reset (POR) / power-down reset (PDR). The
POR/PDR is active in all power modes.
During power-on, the POR keeps the device under reset until the VDD supply voltage
reaches the specified POR threshold (VPOR). At this point, the device reset is released and
the system can start. During power-down, when VDD drops below the PDR threshold
(VPDR), the device is put under reset again.

Figure 5. POR, PDR thresholds

VDD

VPOR
VPDR

t
tRSTTEMPO

Reset

POR threshold
PDR threshold

MSv47933V1

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4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The device features seven low-power modes:
• Sleep mode: CPU clock off, all peripherals including Cortex®-M0+ core peripherals
such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an
event occurs. Refer to Section 4.3.4: Sleep mode.
• Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
regulator is in low-power mode to minimize the regulator's operating current. Refer to
Section 4.3.2: Low-power run mode (LP run).
• Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®-
M0+ is off. Refer to Section 4.3.5: Low-power sleep mode (LP sleep).
• Stop 0 and Stop 1 modes: SRAM and all registers content are retained. All clocks in the
VCORE domain are stopped, the PLL, the HSI16 and the HSE are disabled. The LSI
and the LSE can be kept running.
The RTC and TAMP can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop
mode to detect their wakeup condition.
In Stop 0 mode, the main regulator remains ON, which allows the fastest wakeup time
but with higher consumption. The active peripherals and wakeup sources are the same
as in Stop 1 mode.
The system clock, when exiting Stop 0 or Stop 1 mode, is the HSISYS clock. If the
device is configured to wake up in Low-power run mode, the HSIDIV bits in RCC_CR
register must be configured prior to entering Stop mode to provide a frequency not
greater than 2 MHz.
Refer to Section 4.3.6: Stop 0 mode for details on Stop 0 mode.
• Standby mode: VCORE domain, the main regulator and the low-power regulator are
powered off.
All clocks in the VCORE domain are stopped and the PLL, the HSI16, and the HSE
oscillators are disabled. The LSI and the LSE oscillators can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is the HSI16 oscillator clock.
Refer to Section 4.3.8: Standby mode.
In addition, the power consumption in Run mode can be reduced by one of the following
means:
• Slowing down the system clocks
• Gating the clocks to the APB and AHB peripherals when they are unused.

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Figure 6. Low-power modes state diagram

Low-power sleep mode

Stop 0 mode Low-power run mode

Standby mode

Stop 1 mode Run mode

Sleep mode

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Table 18. Low-power mode summary

Voltage
Wakeup Wakeup regulators
Mode name Entry Effect on clocks
source(1) system clock
MR LPR

Sleep WFI or Return Same as before CPU clock OFF

Any interrupt
(Sleep-now or from ISR entering Sleep no effect on other clocks ON
Sleep-on-exit) WFE Wakeup event mode or analog clock sources

Low-power Same as Low-

Set LPR bit Clear LPR bit None
run power run clock
Set LPR bit +
WFI or Return Any interrupt Same as before OFF
CPU clock OFF
Low-power from ISR entering Low-
sleep no effect on other clocks
power sleep
Set LPR bit + or analog clock sources ON
Wakeup event mode
WFE
LPMS=”000” +
SLEEPDEEP bit Any EXTI line
Stop 0 ON
+ WFI or Return (configured in the
from ISR or WFE EXTI registers)
LPMS=”001” + Specific
SLEEPDEEP bit peripherals
Stop 1 + WFI or Return events All clocks OFF except
HSISYS
LSI and LSE
from ISR or WFE
LPMS=”011” + WKUP pin edge, OFF
Clear RRS bit + RTC event, TAMP
Standby SLEEPDEEP bit event, external OFF
+ WFI or Return reset on NRST
from ISR or WFE pin, IWDG reset

1. Refer to Table 19: Functionalities depending on the working mode.

Table 19. Functionalities depending on the working mode(1)

Stop 0/1 Standby
Low-power sleep
Low-power run

Wakeup capability

Wakeup capability

Function Run Sleep VBAT

- -

CPU Y - Y - - - - - -
Flash memory Y Y O(2) O(2) O(2) - - - -
(3) Y(3)
SRAM Y Y Y Y - - - -
Backup Registers Y Y Y Y Y - Y - Y
DMA1/2 O O O O - - - - -

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Table 19. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Standby

Low-power sleep
Low-power run

Wakeup capability

Wakeup capability
Function Run Sleep VBAT
- -

(4)
HSI16 O O O O - - - -

HSE O O O O - - - - -

LSI O O O O O - O - -

LSE O O O O O - O - O

PLL O O - - - - - - -

CSS O O O(5) O(5) - - - - -

CSS on LSE O O O O O O O O -
RTC / Auto wakeup O O O O O O O O O
TAMP1/2/3 O O O O O O O O O
(6)
USART1/2 O O O O O O(6) - - -
USART3/4/5/6 O O O O - - - - -
I2C1 O O O O O(7) O(7) - - -
I2C2/3 O O O O - - - - -
SPI1/2/3 O O O O - - - - -
ADC O O O O - - - - -
Temperature sensor O O O O - - - - -
TIMx O O O O - - - - -

IWDG O O O O O O O O -

WWDG O O O O - - - - -

SysTick timer O O O O - - - - -
CRC O O O O - - - - -
USB O O - - - - - - -
up to
(8) 5
GPIOs O O O O O O -
pins
(9)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash memory can be configured in power-down mode. By default, it is not in power-down mode.

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3. The SRAM clock can be gated ON or OFF.

4. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is
woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put OFF
when the peripheral does not need it anymore.
5. If CSS is used on HSE clock in Low power run or Low power sleep modes, configure HSIDIV such as not to
drive SYSCLK clock above the maximum frequency for either mode, in case of external clock failure
detection.
6. USART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address
match.
8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
9. I/Os with wakeup from Standby mode capability (WKUPx).

Debug mode
By default, the debug connection is lost if the user application puts the MCU in Stop 0,
Stop1, or Standby mode while the debug features are used. This is due to the fact that the
Cortex®-M0+ core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 29.9.1: Debug support for low-power modes.

4.3.1 Run mode

Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering Sleep mode.
For more details, refer to Section 5.4.3: Clock configuration register (RCC_CFGR).

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBENR and RCC_APBENRx
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBSMENR and RCC_APBSMENRx registers.

4.3.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2 MHz.
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

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I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter Low-power run mode, proceed as follows:
1. Optional: Jump into the SRAM and power-down the Flash memory by setting the
FPD_LPRUN bit in the Power control register 1 (PWR_CR1).
2. Decrease the system clock frequency below 2 MHz.
3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.
Refer to Table 20: Low-power run on how to enter Low-power run mode.

Exiting Low-power run mode

To exit Low-power run mode, proceed as follows:
1. Force the regulator in main mode by clearing the LPR bit in the Power control register 1
(PWR_CR1).
2. Wait until REGLPF bit is cleared in the Power status register 2 (PWR_SR2).
3. Increase the system clock frequency.
Refer to Table 20: Low-power run on how to exit Low-power run mode.

Table 20. Low-power run

Low-power run mode Description

Decrease the system clock frequency below 2 MHz

Mode entry
LPR = 1
LPR = 0
Mode exit Wait until REGLPF = 0
Increase the system clock frequency
Wakeup latency Regulator wakeup time from low-power mode

4.3.3 Low-power modes

Entering low-power modes
The MCU enters low-power modes by executing the WFI (wait for interrupt), or WFE (wait
for event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M0+ system control
register is set on return from ISR.
Entering low-power mode through WFI or WFE is executed only if no interrupt is pending or
no event is pending.

Exiting low-power modes

The MCU exits Sleep and Stop low-power modes in a way depending on how the low-power

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mode was entered:

• If the WFI instruction or Return from ISR was used to enter low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter low-power mode, the MCU exits low-power
mode as soon as an event occurs. The wakeup event can be generated either by:
– NVIC IRQ interrupt.
When SEVONPEND = 0 in the Cortex®-M0+ system control register: by enabling
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
When SEVONPEND = 1 in the Cortex®-M0+ system control register: by enabling
an interrupt in the peripheral control register and optionally in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and when enabled
the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
register) have to be cleared.
All NVIC interrupts wake the MCU up, even the disabled ones.
– Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
The MCU exits Standby low-power mode upon an external reset (NRST pin), an IWDG
reset, a rising or falling edge on one of enabled WKUPx pins, or upon an RTC event. See
Figure 228: RTC block diagram.
After waking up from Standby mode, program execution restarts in the same way as after a
reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

4.3.4 Sleep mode

I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The MCU enters Sleep mode according to section Entering low-power modes, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is clear.
Refer to Table 21: Sleep mode summary for details on how to enter Sleep mode.

Exiting Sleep mode

The MCU exits Sleep mode according to Exiting low-power modes.
Refer to Table 21: Sleep mode summary for more details on how to exit Sleep mode.

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Table 21. Sleep mode summary

Characteristic Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ system control register.
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M0+ system control register.
If WFI or return from ISR was used for entry
Interrupt: refer to Table 45: Vector table
If WFE was used for entry and SEVONPEND = 0:
Mode exit Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 45: Vector table or
Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
Wakeup latency None

4.3.5 Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

The MCU enters Low-power sleep mode from Low-power run mode according to Entering
low-power modes, when the SLEEPDEEP bit in the Cortex®-M0+ System Control register is
clear.
Refer to Table 22: Low-power sleep mode summary for details on how to enter Low-power
sleep mode.

Exiting Low-power sleep mode

The MCU exits Low-power sleep mode according to Exiting low-power modes. When exiting
Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run
mode.
Refer to Table 22: Low-power sleep mode summary for details on how to exit Low-power
sleep mode.

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Table 22. Low-power sleep mode summary

Characteristic Description

Low-power sleep mode is entered from the Low-power run mode.

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register.
Mode entry Low-power sleep mode is entered from the Low-power run mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register.
If WFI or Return from ISR was used for entry
Interrupt: refer to Table 45: Vector table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
Mode exit
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 45: Vector table
Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
After exiting Low-power sleep mode, the MCU is in Low-power run mode.
Wakeup latency None

4.3.6 Stop 0 mode

The Stop 0 mode is based on the Cortex®-M0+ deepsleep mode combined with the
peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop
0 mode, all clocks in the VCORE domain are stopped; the PLL, the HSI16 and the HSE
oscillators are disabled. Some peripherals with the wakeup capability (I2C1, USART1,
USART2) can switch on the HSI16 to receive a frame, and switch off the HSI16 after
receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated
only to the peripheral requesting it.
SRAM and register contents are preserved.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 0 mode

The MCU enters Stop 0 mode according to section Entering low-power modes, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
Refer to Table 23: Stop 0 mode summary for details on how to enter Stop 0 mode.
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.

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In Stop 0 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except upon a reset. See
Section 21.3: IWDG functional description.
• real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control
register (RCC_BDCR).
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: USART1,
USART2, and I2C1.
The ADC and the temperature sensor can consume power during the Stop 0 mode, unless
they are disabled before entering this mode.

Exiting Stop 0 mode

The MCU exits Stop 0 mode according to section Entering low-power modes.
Refer to Table 23: Stop 0 mode summary for details on how to exit Stop 0 mode.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSISYS oscillator
is selected as system clock. If the device is configured to wake up in Low-power run mode,
the HSIDIV bits in RCC_CR register must be configured prior to entering Stop 0 mode to
provide a frequency not greater than 2 MHz.
When exiting Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2 depending
on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the Power
control register 1 (PWR_CR1).

Table 23. Stop 0 mode summary

Characteristic Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “000” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
Mode entry
– No interrupt is pending
– LPMS = “000” in PWR_CR1
Note: To enter Stop 0 mode, all EXTI Line pending bits (in EXTI rising
edge pending register 1 (EXTI_RPR1) and EXTI falling edge
pending register 1 (EXTI_FPR1)), and the peripheral flags
generating wakeup interrupts must be cleared. Otherwise, the Stop
0 mode entry procedure is ignored and program execution
continues.

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Table 23. Stop 0 mode summary (continued)

Characteristic Description

If WFI or Return from ISR was used for entry

Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 45: Vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 12.3.2: EXTI
Mode exit
direct event input wakeup.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 45: Vector table.
Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
Longest wakeup time between HSI16 wakeup time and Flash wakeup time
Wakeup latency
from Stop 0 mode.

4.3.7 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only
the low-power regulator is on. Stop 1 mode can be entered from Run mode and from Low-
power run mode.
Refer to Table 24: Stop 1 mode summary for details on how to enter and exit Stop 1 mode.

Table 24. Stop 1 mode summary

Characteristic Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “001” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
Mode entry
– No interrupt is pending
– LPMS = “001” in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in EXTI rising
edge pending register 1 (EXTI_RPR1) and EXTI falling edge
pending register 1 (EXTI_FPR1)), and the peripheral flags
generating wakeup interrupts must be cleared. Otherwise, the Stop
1 mode entry procedure is ignored and program execution
continues.

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Table 24. Stop 1 mode summary

Characteristic Description

If WFI or Return from ISR was used for entry

Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 45: Vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 12.3.2: EXTI
Mode exit
direct event input wakeup.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 45: Vector table.
Wakeup event: refer to Section 12.3.2: EXTI direct event input wakeup
Longest wakeup time between HSI16 wakeup time and regulator wakeup
Wakeup latency
time from Low-power mode + Flash wakeup time from Stop 1 mode.

4.3.8 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex®-M0+ deepsleep mode, with the voltage regulators disabled (except when the
SRAM content is preserved). The PLL, the HSI16 and the HSE oscillators are also switched
off.
The content of the registers is lost except for the registers in the RTC domain and Standby
circuitry (see Figure 4). The SRAM content is lost.

I/O states in Standby mode

In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x=A, B, C, D, F), or with a pull-down (refer to PWR_PDCRx registers (x=A, B, C,
D, F)), or can be kept in analog mode.
The RTC outputs on PC13 and PA4 are functional in Standby mode. PC14 and PC15 used
for LSE are also functional. Five wakeup pins (WKUPx, x=1,2,4,5,6) and the two tampers
are available.

Entering Standby mode

The MCU enters Standby mode according to Entering low-power modes, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
Refer to Table 25: Standby mode summary for details on how to enter Standby mode.

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In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 21.3: IWDG functional description.
• Real-time clock (RTC) and tamper (TAMP): this is configured by the RTCEN bit in the
RTC domain control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR)

Exiting Standby mode

The MCU exits Standby mode according to section Entering low-power modes. The SBF
status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in
Standby mode. All registers are reset after wakeup from Standby except for Power control
register 3 (PWR_CR3).
Refer to Table 25: Standby mode summary for more details on how to exit Standby mode.

Table 25. Standby mode summary

Characteristic Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “011” in Power control register 1 (PWR_CR1)
– WUFx bits are cleared in Power status register 1 (PWR_SR1)

On return from ISR while:

Mode entry – SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “011” in Power control register 1 (PWR_CR1)
– WUFx bits are cleared in Power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared
WKUPx pin edge, RTC event, TAMP event, external reset on NRST pin,
Mode exit
IWDG reset
Wakeup latency Reset phase

4.3.9 Auto-wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop (0, 1) or Standby modes at regular intervals. For this purpose, two of

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the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0]
bits in the RTC domain control register (RCC_BDCR):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
• Low-power internal RC Oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wake up from Stop mode with an RTC alarm or an RTC wakeup event, it is necessary to:
• Configure the EXTI Line 19 to be sensitive to rising edge.
• Configure the RTC to generate the wakeup event.
To wake up from Standby mode, there is no need to configure the EXTI line 19.

4.4 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

4.4.1 Power control register 1 (PWR_CR1)

Address offset: 0x00
Reset value: 0x0000 0208. This register is reset after wakeup from Standby mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPD_ FPD_ FPD_
Res. LPR Res. Res. Res. VOS[1:0] DBP Res. Res. LPMS[2:0]
LPSLP LPRUN STOP
rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR: Low-power run
When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS: Voltage scaling range selection
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
Bit 8 DBP: Disable RTC domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and backup registers disabled
1: Access to RTC and backup registers enabled
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 FPD_LPSLP: Flash memory powered down during Low-power sleep mode
This bit determines whether the Flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power sleep mode.
0: Flash memory idle
1: Flash memory powered down
Bit 4 FPD_LPRUN: Flash memory powered down during Low-power run mode
This bit determines whether the Flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power run mode. The Flash memory can be put in power-
down mode only when the user code is executed from SRAM.
0: Flash memory idle
1: Flash memory powered down
Bit 3 FPD_STOP: Flash memory powered down during Stop mode
This bit determines whether the Flash memory is put in power-down mode or remains in idle
mode when the device enters Stop mode.
0: Flash memory idle
1: Flash memory powered down
Bits 2:0 LPMS[2:0]: Low-power mode selection
These bits select the low-power mode entered when CPU enters deepsleep mode.
000: Stop 0 mode
001: Stop 1 mode
010: Reserved
011: Standby mode
Note: 1xx: Reserved

4.4.2 Power control register 2 (PWR_CR2)

This register is available on STM32G0B0xx only. It is reserved otherwise.
Address offset: 0x04
Reset value: 0x0000 0000. This register is reset when exiting Standby mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. USV Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 USV: USB supply enable
0: Disable
1: Enable
The bit must be set for the USB peripheral to operate.
Bits 9:0 Reserved, must be kept at reset value.

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4.4.3 Power control register 3 (PWR_CR3)

Address offset: 0x08
Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWUP EWUP EWUP EWUP EWUP EWUP
EIWUL Res. Res. Res. Res. APC Res. Res. Res. Res.
6 5 4 3 2 1
rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL: Enable internal wakeup line
0: Disable
1: Enable
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 APC: Apply pull-up and pull-down configuration
This bit determines whether the I/O pull-up and pull-down configurations defined in the
PWR_PUCRx and PWR_PDCRx registers are applied.
0: Not applied
1: Applied
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 EWUP6: Enable WKUP6 wakeup pin
When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs. The active edge is configured through
WP6 bit in the PWR_CR4 register.
Bit 4 EWUP5: Enable WKUP5 wakeup pin
When this bit is set, the WKUP5 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs.The active edge is configured via the
WP5 bit in the PWR_CR4 register.
Bit 3 EWUP4: Enable WKUP4 wakeup pin
When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs. The active edge is configured via the
WP4 bit in the PWR_CR4 register.

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Bit 2 EWUP3: Enable WKUP3 wakeup pin

When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs. The active edge is configured via the
WP3 bit of the PWR_CR4 register.
Bit 1 EWUP2: Enable WKUP2 wakeup pin
When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs. The active edge is configured via the
WP2 bit of the PWR_CR4 register.
Bit 0 EWUP1: Enable WKUP1 wakeup pin
When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup from
Standby mode when a rising or a falling edge occurs. The active edge is configured via the
WP1 bit of the PWR_CR4 register.

4.4.4 Power control register 4 (PWR_CR4)

Address offset: 0x0C
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. VBRS VBE Res. Res. WP6 WP5 WP4 WP3 WP2 WP1

rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 VBRS: VBAT battery charging resistor selection
0: 5 kΩ
1: 1.5 kΩ
Bit 8 VBE: VBAT battery charging enable
0: Disable
1: Enable
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 WP6: WKUP6 wakeup pin polarity
WKUP6 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge
Bit 4 WP5: WKUP5 wakeup pin polarity
WKUP5 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge

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Bit 3 WP4: WKUP4 wakeup pin polarity

WKUP4 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge
Bit 1 WP3: WKUP3 wakeup pin polarity
WKUP3 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge
Bit 1 WP2: WKUP2 wakeup pin polarity
WKUP2 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge
Bit 0 WP1: WKUP1 wakeup pin polarity
WKUP1 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge

4.4.5 Power status register 1 (PWR_SR1)

Address offset: 0x10
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WUFI Res. Res. Res. Res. Res. Res. SBF Res. Res. WUF6 WUF5 WUF4 WUF3 WUF2 WUF1

r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI: Wakeup flag internal
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
Bits 14:9 Reserved, must be kept at reset value.
Bit 8 SBF: Standby flag
This bit is set by hardware when the device enters Standby mode and is cleared by setting
the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter Standby mode
1: The device entered Standby mode
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 WUF6: Wakeup flag 6

This bit is set when a wakeup event is detected on WKUP6 wakeup pin. It is cleared by
writing 1 in the CWUF6 bit of the PWR_SCR register.
Bit 4 WUF5: Wakeup flag 5
This bit is set when a wakeup event is detected on WKUP5 wakeup pin. It is cleared by
writing 1 in the CWUF5 bit of the PWR_SCR register.
Bit 3 WUF4: Wakeup flag 4
This bit is set when a wakeup event is detected on WKUP4 wakeup pin. It is cleared by
writing 1 in the CWUF4 bit of the PWR_SCR register.
Bit 2 WUF3: Wakeup flag 3
This bit is set when a wakeup event is detected on WKUP3 wakeup pin. It is cleared by
writing 1 in the CWUF3 bit of the PWR_SCR register.
Bit 1 WUF2: Wakeup flag 2
This bit is set when a wakeup event is detected on WKUP2 wakeup pin. It is cleared by
writing 1 in the CWUF2 bit of the PWR_SCR register.
Bit 0 WUF1: Wakeup flag 1
This bit is set when a wakeup event is detected on WKUP1 wakeup pin. It is cleared by
writing 1 in the CWUF1 bit of the PWR_SCR register.

4.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14
Reset value: 0x0000 0000. This register is partially reset when exiting Standby mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGLP REGLP FLASH
Res. Res. Res. Res. Res. VOSF Res. Res. Res. Res. Res. Res. Res.
F S _RDY
r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level
Bit 9 REGLPF: Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A
polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in main mode (MR)
1: The regulator is in low-power mode (LPR)

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Bit 8 REGLPS: Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on
reset or Standby. If the Standby mode is entered while REGLPS bit is still cleared, the
wakeup from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bit 7 FLASH_RDY: Flash ready flag
This bit is set by hardware to indicate when the Flash memory is ready to be accessed after
wakeup from power-down. To place the Flash memory in power-down, set either
FPD_LPRUN, FPD_LPSLP or FPD_STP bits.
0: Flash memory in power-down
1: Flash memory ready to be accessed
Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is
set, prior to jumping to Flash memory.
Bits 6:0 Reserved, must be kept at reset value.

4.4.7 Power status clear register (PWR_SCR)

Address offset: 0x18
Reset value: 0x0000 0000.
Access: three additional APB cycles are needed to write this register, compared to a
standard APB write.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWUF CWUF CWUF CWUF CWUF CWUF
Res. Res. Res. Res. Res. Res. Res. CSBF Res. Res.
6 5 4 3 2 1
w w w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF: Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 CWUF6: Clear wakeup flag 6
Setting this bit clears the WUF6 flag in the PWR_SR1 register.
Bit 4 CWUF5: Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.
Bit 3 CWUF4: Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.

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Bit 2 CWUF3: Clear wakeup flag 3

Setting this bit clears the WUF3 flag in the PWR_SR1 register.
Bit 1 CWUF2: Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.
Bit 0 CWUF1: Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.

4.4.8 Power Port A pull-up control register (PWR_PUCRA)

Address offset: 0x20
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port A pull-up bit y (y = 0 to 15)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PA[y] I/O.

4.4.9 Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port A pull-down bit y (y = 0 to 15)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PA[y] I/O.

4.4.10 Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port B pull-up bit y (y = 0 to 15)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PB[y] I/O.

4.4.11 Power Port B pull-down control register (PWR_PDCRB)

Address offset: 0x2C
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port B pull-down bit y (y = 0 to 15)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PB[y] I/O.

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4.4.12 Power Port C pull-up control register (PWR_PUCRC)

Address offset: 0x30
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port C pull-up bit y (y = 0 to 15)(1)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PC[y] I/O.
1. In STM32G030xx as well as STM32G050xx devices, the bits PD0 to PD5 and PD8 to PD12 are
reserved.

4.4.13 Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port C pull-down bit y (y = 0 to 15)(1)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PC[y] I/O.
1. In STM32G030xx as well as STM32G050xx devices, the bits PD0 to PD5 and PD8 to PD12 are
reserved.

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4.4.14 Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port D pull-up bit y (y = 0 to 15)(1)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PD[y] I/O.
1. In STM32G070xx devices, the bits PU15 to PU10 and PU7 are reserved. In STM32G030xx as well
as in STM32G050xx devices, PU15 to PU4 are reserved.

4.4.15 Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port D pull-down bit y (y = 0 to 15)(1)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PD[y] I/O.
1. In STM32G070xx devices, the bits PD15 to PD10 and PD7 are reserved. In STM32G030xx as well
as in STM32G050xx devices, PD15 to PD4 are reserved.

114/989 RM0454 Rev 5

RM0454 Power control (PWR)

4.4.16 Power Port E pull-up control register (PWR_PUCRE)

Address offset: 0x40
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port E pull-up bit y (y = 0 to 15)(1)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PE[y] I/O.
1. Only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.17 Power Port E pull-down control register (PWR_PDCRE)

Address offset: 0x44
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port E pull-down bit y (y = 0 to 15)(1)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PE[y] I/O.
1. Only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.18 Power Port F pull-up control register (PWR_PUCRF)

Address offset: 0x48

RM0454 Rev 5 115/989

118
Power control (PWR) RM0454

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PUy: Port F pull-up bit y (y = 0 to 13)(1)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PF[y] I/O.
1. Bits PU13 to PU3 only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.19 Power Port F pull-down control register (PWR_PDCRF)

Address offset: 0x4C.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1).
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PDy: Port F pull-down bit y (y = 0 to 13)(1)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device
on the PF[y] I/O.
1. Bits PU13 to PU3 only applies to STM32G0B0xx devices. Reserved for the other devices.

116/989 RM0454 Rev 5

 0x034
0x030
0x028
0x024
0x020
0x018
0x014
0x010
0x008
0x004
0x000

0x02C
0x00C
Offset
4.4.20
RM0454

PWR_SR2
PWR_SR1
PWR_CR4
PWR_CR3
PWR_CR2
PWR_CR1

PWR_SCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_PDCRB
PWR_PUCRB
PWR_PDCRA
PWR_PUCRA

PWR_PDCRC
PWR_PUCRC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
PWR register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0
0
0
1

PD15 PU15 PD15 PU15 PD15 PU15 Res. Res. WUFI Res. EIWUL Res. Res. 15

0
0
0
0
0
0
0

PD14 PU14 PD14 PU14 PD14 PU14 Res. Res. Res. Res. Res. Res. LPR 14

0
0
0
0
0
0
PD13 PU13 PD13 PU13 PD13 PU13 Res. Res. Res. Res. Res. Res. Res. 13

0
0
0
0
0
0
PD12 PU12 PD12 PU12 PD12 PU12 Res. Res. Res. Res. Res. Res. Res. 12

0
0
0
0
0
0
PD11 PU11 PD11 PU11 PD11 PU11 Res. Res. Res. Res. Res. Res. Res.
Table 26. PWR register map and reset values

11

0
0
0
0
0
0
0
0
0
0

PD10 PU10 PD10 PU10 PD10 PU10 Res. VOSF Res. Res. APC USV 10
[1:0]
VOS

0
0
0
0
0
0
0
0
1

PD9 PU9 PD9 PU9 PD9 PU9 Res. REGLPF Res. VBRS Res. Res. 9

0
0
0
0
0
0
0
0
0
0
0

PD8 PU8 PD8 PU8 PD8 PU8 CSBF REGLPS SBF VBE Res. Res. DBP 8

0
0
0
0
0
0
PD7 PU7 PD7 PU7 PD7 PU7 Res. 0 FLASH_RDY Res. Res. Res. Res. Res. 7

0
0
0
0
0
0
PD6 PU6 PD6 PU6 PD6 PU6 Res. Res. Res. Res. Res. Res. Res. 6

0
0
0
0
0
0
0
0
0
0
0

PD5 PU5 PD5 PU5 PD5 PU5 CWUF6 Res. WUF6 WP6 EWUP6 Res. FPD_LPSLP 5

0
0
0
0
0
0
0
0
0
0
0

PD4 PU4 PD4 PU4 PD4 PU4 CWUF5 Res. WUF5 WP5 EWUP5 Res. FPD_LPRUN 4

0
0
0
0
0
0
0
0
0
0
1

PD3 PU3 PD3 PU3 PD3 PU3 CWUF4 Res. WUF4 WP4 EWUP4 Res. FPD_STOP 3

0
0
0
0
0
0
0

PD2 PU2 PD2 PU2 PD2 PU2 Res. Res. Res. Res. Res. Res. 2

0
0
0
0
0
0
0
0
0
0
0

PD1 PU1 PD1 PU1 PD1 PU1 CWUF2 Res. WUF2 WP2 EWUP2 Res. 1
[2:0]
LPMS

0
0
0
0
0
0
0
0
0
0
0

PD0 PU0 PD0 PU0 PD0 PU0 CWUF1 Res. WUF1 WP1 EWUP1 Res. 0
Power control (PWR)

117/989
118
 0x048
0x044
0x040
0x038

0x04C
0x03C
Offset

118/989
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_PDCRF
PWR_PUCRF
PWR_PDCRE
PWR_PUCRE
PWR_PDCRD
PWR_PUCRD
Power control (PWR)

Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. 16
0
0
0
0

Res. Res. PD15 PU15 PD15 PU15 15

0
0
0
0

0 Res. Res. PD14 PU14 PD14 PU14 14

0
0
0
0
0

PD13 PU13 PD13 PU13 PD13 PU13 13

0
0
0
0
0
0

PD12 PU12 PD12 PU12 PD12 PU12 12

0
0
0
0
0
0

PD11 PU11 PD11 PU11 PD11 PU11 11

0
0
0
0
0
0

PD10 PU10 PD10 PU10 PD10 PU10 10

0
0
0
0
0
0

PD9 PU9 PD9 PU9 PD9 PU9 9

Refer to Section 2.2 on page 44 for the register boundary addresses.
Table 26. PWR register map and reset values (continued)

0
0
0
0
0
0

PD8 PU8 PD8 PU8 PD8 PU8 8

0
0
0
0
0
0

PD7 PU7 PD7 PU7 PD7 PU7 7

0
0
0
0
0
0

PD6 PU6 PD6 PU6 PD6 PU6 6

0
0
0
0
0
0

PD5 PU5 PD5 PU5 PD5 PU5 5

0
0
0
0
0
0

PD4 PU4 PD4 PU4 PD4 PU4 4

0
0
0
0
0
0

PD3 PU3 PD3 PU3 PD3 PU3 3

0
0
0
0
0
0

PD2 PU2 PD2 PU2 PD2 PU2 2

0
0
0
0
0
0

PD1 PU1 PD1 PU1 PD1 PU1 1

0
0
0
0
0
0

PD0 PU0 PD0 PU0 PD0 PU0 0

RM0454
RM0454 Reset and clock control (RCC)

5 Reset and clock control (RCC)

5.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.

5.1.1 Power reset

A power reset is generated when one of the following events occurs:
• power-on reset (POR)
• exit from Standby mode
Power reset set all registers to their reset values except the registers of the RTC domain.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value.
Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby mode control) is not
impacted.

5.1.2 System reset

System reset sets all registers to their reset values except the reset flags in the clock
control/status register (RCC_CSR) and the registers in the RTC domain.
System reset is generated when one of the following events occurs:
• low level on the NRST pin (external reset)
• window watchdog event (WWDG reset)
• independent watchdog event (IWDG reset)
• software reset (SW reset) (see Software reset)
• low-power mode security reset (see Low-power mode security reset)
• option byte loader reset (see Option byte loader reset)
• power-on reset
The reset source can be identified by checking the reset flags in the RCC_CSR register
(see Section 5.4.23: Control/status register (RCC_CSR)).

NRST pin (external reset):

Valid reset signal on the pin is propagated to the internal logic, and each internal reset
source is led to a pulse generator the output of which drives this pin. The pulse generator
guarantees a minimum reset pulse duration of 20 µs for each internal reset source to be
output on the NRST pin.

RM0454 Rev 5 119/989

172
Reset and clock control (RCC) RM0454

Figure 7. Simplified diagram of the reset circuit

VDD

RPU
System reset

External
reset Filter
NRST WWDG reset
IWDG reset
Pulse Software reset
generator
(min 20 μs) Low-power manager reset
Option byte loader reset
POR

MSv40966V2

Caution: Upon power reset, the NRST pin is configured as Reset input/output and driven low by the
system until it is reconfigured to the expected mode when the option bytes are loaded, in the
fourth clock cycle after the end of trstempo.

Software reset
The SYSRESETREQ bit in Cortex®-M0+ Application interrupt and reset control register
must be set to force a software reset on the device (refer to the programming manual
PM0223).

120/989 RM0454 Rev 5

RM0454 Reset and clock control (RCC)

Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, two low-power
mode security resets are available. If enabled in option bytes, the resets are generated in
the following conditions:
• Entering Standby mode
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
• Entering Stop mode
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the user option bytes, refer to Section 3.4.1: FLASH option byte
description.

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.

5.1.3 RTC domain reset

The RTC domain has two specific resets.
A RTC domain reset is generated when one of the following events occurs:
• Software reset, triggered by setting the BDRST bit in the RTC domain control register
(RCC_BDCR).
• VDD or VBAT power on, if both supplies have previously been powered off.
A RTC domain reset only affects the LSE oscillator, the RTC, the backup registers and the
RCC RTC domain control register.

5.2 Clocks
The device provides the following clock sources producing primary clocks:
• HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about
16 MHz)
• HSE OSC - a high-speed oscillator with external crystal/ceramic resonator or external
clock source, producing HSE clock (4 to 48 MHz)
• LSI RC - a low-speed fully-integrated RC oscillator producing LSI clock (about 32 kHz)
• LSE OSC - a low-speed oscillator with external crystal/ceramic resonator or external
clock source, producing LSE clock (accurate 32.768 kHz or external clock up to
1 MHz)
• I2S_CKIN - pin for direct clock input for I2S1 peripheral
Each oscillator can be switched on or off independently when it is not used, to optimize
power consumption. Check sub-sections of this section for more functional details. For
electrical characteristics of the internal and external clock sources, refer to the device
datasheet.

RM0454 Rev 5 121/989

172
Reset and clock control (RCC) RM0454

The device produces secondary clocks by dividing or/and multiplying the primary clocks:
• HSISYS - a clock derived from HSI16 through division by a factor programmable from 1
to 128
• PLLPCLK, PLLQCLK and PLLRCLK - clocks output from the PLL block
• SYSCLK - a clock obtained through selecting one of LSE, LSI, HSE, PLLRCLK, and
HSISYS clocks
• HCLK - a clock derived from SYSCLK through division by a factor programmable from
1 to 512
• HCLK8 - a clock derived from HCLK through division by eight
• PCLK - a clock derived from HCLK through division by a factor programmable from 1 to
16
• TIMPCLK - a clock derived from PCLK, running at PCLK frequency if the APB
prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
More secondary clocks are generated by fixed division of HSE, HSI16 and HCLK clocks.
The HSISYS is used as system clock source after startup from reset, with the division by 1
(producing HSI16 frequency).
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains,
respectively. Their maximum allowed frequency is 64 MHz.
The peripherals are clocked with the clocks from the bus they are attached to (HCLK for
AHB, PCLK for APB) except:
• TIMx, with these clock sources to select from:
– TIMPCLK (selectable for all timers) running at PCLK frequency if the APB
prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
• ADC, with these clock sources to select from:
– SYSCLK (system clock)
– HSI16
– PLLPCLK
• USARTx, with these clock sources to select from:
– SYSCLK (system clock)
– HSI16
– LSE
– PCLK (APB clock)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• I2Cx, with these clock sources to select from:
– SYSCLK (system clock)
– HSI16
– PCLK (APB clock)
The wakeup from Stop mode is supported only when the clock is HSI16.
• I2Sx, with these clock sources to select from:
– SYSCLK (system clock)
– HSI16
– PLLPCLK
– I2S_CKIN pin

122/989 RM0454 Rev 5

RM0454 Reset and clock control (RCC)

• RTC, with these clock sources to select from:

– LSE
– LSI
– HSE clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• IWDG, always clocked with LSI clock.
• USB, with these clocks to select from:
– HSE
– PLLQCLK
• SysTick (Cortex® core system timer), with these clock sources to select from:
– HCLK (AHB clock)
– HCLK clock divided by 8
The selection is done through SysTick control and status register.
HCLK is used as Cortex®-M0+ free-running clock (FCLK). For more details, refer to the
programming manual PM0223.

RM0454 Rev 5 123/989

172
Reset and clock control (RCC) RM0454

Figure 8. Clock tree

LSI RC LSI to IWDG

32 kHz

LSCO LSI LSI

LSE LSE to RTC
HSE /32
OSC32_OUT LSE OSC LSE
32.768 kHz
HSE
OSC32_IN Clock to USB(2)
detector
PLLQCLK

LSE to PWR
LSI
to AHB bus, core, memory and DMA
MCO2(2) SYSCLK
/ 1...1024
HSE AHB HCLK FCLK Cortex free-running clock
MCO HSI16 PRESC
(2)
/ 1...1024 / 1,2,..512
PLLPCLK(2) to Cortex system timer
HCLK8
PLLQCLK(2) /8
LSE
PLLRCLK
LSI APB PCLK to APB peripherals
PRESC
HSE SYSCLK / 1,2,4,8,16
OSC_OUT HSE OSC PLLRCLK
4-48 MHz
HSE PCLK to USART2(1)
HSISYS LSE to USART1
OSC_IN Clock HSI16
detector SYSCLK to USART3(2)
HSISYS
/1…128
PCLK
HSI RC HSI16 to I2C1
HSI16
16 MHz SYSCLK to I2C2(2)

PLL
HSE x1, x2
fPLLIN to TIM1/3/6/7/14/16/17
VCO x /M HSI16 TIMPCLK to TIM15(1)

fVCO /N to TIM4(2)

/ R fPLLR PLLRCLK

PLLQCLK(2) SYSCLK
/ Q fPLLQ HSI16 to ADC
/P
fPLLP PLLPCLK PLLPCLK

SYSCLK
PLLPCLK
to I2S1
HSI16
I2S_CKIN I2S_CKIN to I2S2(2)

BOLD: clock origin

1. Only applies to STM32G070xx and to STM32G0B0xx.

2. Only applies to STM32G0B0xx.

124/989 RM0454 Rev 5

RM0454 Reset and clock control (RCC)

5.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 9. HSE/ LSE clock sources

Clock source Hardware configuration

OSC_IN OSC_OUT
External clock
GPIO
(OSC_EN as AF)
External
source

OSC_IN OSC_OUT
Crystal/Ceramic
resonators

CL1 CL2
Load
capacitors

RM0454 Rev 5 125/989

172
Reset and clock control (RCC) RM0454

External crystal/ceramic resonator (HSE crystal)

The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 9. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60 % duty
cycle depending on the frequency (refer to the datasheet) must drive the OSC_IN pin, on
devices where OSC_IN and OSC_OUT pins are available (see Figure 9). The OSC_OUT
pin can be used as a GPIO.
The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate
function, to provide an enable signal to external clock synthesizer. It allows stopping the
external clock source when the device enters low power modes.
Note: For details on pin availability, refer to the pinout section in the corresponding device
datasheet.
To minimize the consumption, it is recommended to use the square signal.

5.2.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator.
However, even after calibration, it is less accurate than an oscillator using a frequency
reference such as quartz crystal or ceramic resonator.
The HSISYS clock derived from HSI16 can be selected as system clock after wakeup from
Stop modes (Stop 0 or Stop 1). Refer to Section 5.3: Low-power modes. It can also be used
as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to
Section 5.2.8: Clock security system (CSS).

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal
clock source calibration register (RCC_ICSCR).
Voltage or temperature variations in the application may affect the HSI16 frequency of the
RC oscillator. It can be trimmed using the HSITRIM[6:0] bits in the Internal clock source
calibration register (RCC_ICSCR).

126/989 RM0454 Rev 5

RM0454 Reset and clock control (RCC)

For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.15:
Internal/external clock measurement with TIM14/TIM16/TIM17.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 5.2.8: Clock security system (CSS) on page 129.

5.2.3 PLL
The internal PLL multiplies the frequency of HSI16- or HSE-based clock fetched on its input,
to produce three independent clock outputs. The allowed input frequency range is from 2.66
to 16 MHz. The dedicated divider PLLM with division factor programmable from one to eight
allows setting a frequency within the valid PLL input range. Refer to Figure 8: Clock tree and
PLL configuration register (RCC_PLLCFGR).
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
enable register (RCC_CIER).
The enable bit of each PLL output clock (PLLPEN, PLLQEN, and PLLREN) can be modified
at any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as
system clock.

5.2.4 LSE clock

The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of
providing a low-power but highly accurate clock source to the real-time clock peripheral
(RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low-power-
consumption on the other side. The LSE drive can be decreased to the lower drive
capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the
drive capability can not be increased if LSEON=1.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt enable register (RCC_CIER).

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External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the AHB peripheral
clock enable in Sleep/Stop mode register (RCC_AHBSMENR). The external clock signal
(square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the
OSC32_OUT pin can be used as GPIO. See Figure 9.

5.2.5 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For
more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).

5.2.6 System clock (SYSCLK) selection

One of the following clocks can be selected as system clock (SYSCLK):
• LSI
• LSE
• HSISYS
• HSE
• PLLRCLK
The system clock maximum frequency is 64 MHz. Upon system reset, the HSISYS clock
derived from HSI16 oscillator is selected as system clock. When a clock source is used
directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the Internal
clock source calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and
which clock is currently used as a system clock.

5.2.7 Clock source frequency versus voltage scaling

The following table gives the different clock source frequencies depending on the product
voltage range.

Table 27. Clock source frequency

Maximum clock frequency (MHz)
Clock
Range 1 Range 2

HSI16 16 16
HSE 48 16
PLLPCLK 122(1) 40(2)

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Table 27. Clock source frequency (continued)

Maximum clock frequency (MHz)
Clock
Range 1 Range 2

PLLQCLK 128(1) 32(2)

PLLRCLK 64(1) 16(2)
1. Maximum VCO frequency is 344 MHz.
2. Maximum VCO frequency is 128 MHz.

5.2.8 Clock security system (CSS)

Clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock:
• the HSE oscillator is automatically disabled
• a clock failure event is sent to the break input of TIM1, TIM15, TIM16 and TIM17 timers
• CSSI (clock security system interrupt) is generated
The CSSI is linked to the Cortex®-M0+ NMI (non-maskable interrupt) exception vector. It
makes the software aware of a HSE clock failure to allow it to perform rescue operations.
Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically
generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It
is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the Clock
interrupt clear register (RCC_CICR).
If HSE is selected directly or indirectly (PLLRCLK selected for SYSCLK and HSE selected
as PLL input) as system clock, and a failure of HSE clock is detected, the system clock
switches automatically to HSISYS and the HSE oscillator is disabled. If the HSE clock
(divided or not) is the clock entry of the PLL and PLLRCLK is used as system clock when
the failure occurs, the PLL is disabled, too.

5.2.9 Clock security system for LSE clock (LSECSS)

A clock security system on LSE can be activated by setting the LSECSSON bit in RTC
domain control register (RCC_BDCR). This bit can be cleared only by a hardware reset or
RTC software reset, or after LSE clock failure detection. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY
flags set by hardware), and after selecting the RTC clock by RTCSEL.
The LSECSS works in all modes except VBAT. It keeps working also under system reset
(excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no
longer supplied to the RTC but its registers are not impacted.
Note: If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is
automatically generated. The NMI is executed infinitely unless the LSECSS interrupt
pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by
setting the LSECSSC bit in the Clock interrupt clear register (RCC_CICR).
If LSE is used as system clock, and a failure of LSE clock is detected, the system clock
switches automatically to LSI. In low-power modes, an LSE clock failure generates a
wakeup. The interrupt flag must then be cleared within the RCC registers.

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The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by
clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL),
or take any appropriate action to secure the application.
The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.

5.2.10 ADC clock

The ADC clock is derived from the system clock, or from the PLLPCLK output. It can reach
122 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bitfields in the ADC1_CCR.
If the programmed factor is 1, the AHB prescaler must be set to 1.

5.2.11 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR). This
selection cannot be modified without resetting the RTC domain. The system must always be
configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency
for a proper operation of the RTC.
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the VDD supply is powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock:
– The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the VCORE domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.

5.2.12 Timer clock

The timer clock TIMPCLK is derived from PCLK (used for APB) as follows:
1. If the APB prescaler is set to 1, TIMPCLK frequency is equal to PCLK frequency.
2. Otherwise, the TIMPCLK frequency is set to twice the PCLK frequency.

5.2.13 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

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5.2.14 Clock-out capability

MCO and MCO2
The MCO and MCO2 pins output, independently of each other, the clock selected from:
• LSI
• LSE
• SYSCLK
• HSI16
• HSE
• PLLPCLK
• PLLQCLK
• PLLRCLK
• RTCCLK
• RTC WAKEUP
The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and
MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR). Their outputs are
further divided by a factor set through the MCOPRE[2:0] and MCO2PRE[2:0] bitfields of the
Clock configuration register (RCC_CFGR).
Note: The MCO2 output and the associated MCO2SEL[3:0] and MCO2PRE[2:0] bitfields are only
available on the STM32G0B0xx devices. On the other devices, the divider ratio is limited to
128 and the clock sources do not include PLLPCLK, PLLQCLK, RTCCLK, and RTC
WAKEUP.

LSCO
The LSCO pin allows outputting on of low-speed clocks:
• LSI
• LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit of the
RTC domain control register (RCC_BDCR). The configuration registers of the
corresponding GPIO port must be programmed in alternate function mode.
This function remains available in Stop 0, Stop 1 and Standby modes.

5.2.15 Internal/external clock measurement with TIM14/TIM16/TIM17

It is possible to indirectly measure the frequency of all on-board clock sources with the
TIM14, TIM16 and TIM17 channel 1 input capture, as represented in Figure 10, Figure 11
and Figure 12.

TIM14
By setting the TI1SEL[3:0] field of the TIM14_TISEL register, the clock selected for the input
capture channel1 of TIM14 can be one of:
• GPIO (refer to the alternate function mapping in the device datasheets)
• RTC clock (RTCCLK)
• HSE clock divided by 32
• MCO (MCU clock output)

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The last option is controlled by the MCOSEL[3:0] field of the clock configuration register
(RCC_CFGR). All clock sources can be selected for the MCO pin.

Figure 10. Frequency measurement with TIM14 in capture mode

TIM 14

TI1SEL[3:0]

GPIO
RTCCLK
TI1
HSE / 32

MCO
MSv42174V1

TIM16
By setting the TI1SEL[3:0] field of the TIM16_TISEL register, the clock selected for the input
capture channel1 of TIM16 can be one of:
• GPIO (refer to the alternate function mapping in the device datasheets).
• LSI clock
• LSE clock
• RTC wakeup interrupt signal
The last option requires to enable the RTC interrupt.

Figure 11. Frequency measurement with TIM16 in capture mode

TIM 16

TI1SEL[3:0]

GPIO
LSI
TI1
LSE
RTC wakeup interrupt

MSv42175V1

TIM17
By setting the TI1SEL[3:0] field of the TIM17_TISEL register, the clock selected for the input
capture channel1 of TIM17 can be one of:
• GPIO Refer to the alternate function mapping in the device datasheets.
• HSE divided by 32
• MCO (MCU clock output)
The last option is controlled by the MCOSEL[3:0] field of the clock configuration register
(RCC_CFGR). All clock sources can be selected for the MCO pin.

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Figure 12. Frequency measurement with TIM17 in capture mode

TIM 17

TI1SEL[3:0]

GPIO
HSE / 32 TI1

MCO
MSv42176V1

Calibration of the HSI16 oscillator

For TIM14, TIM15 and TIM17, the primary purpose of connecting the LSE to the channel 1
input capture is to precisely measure HSISYS (derived from HSI16) selected as system
clock. Counting HSISYS clock pulses between consecutive edges of the LSE clock (the
time reference) allows measuring the HSISYS (and HSI16) clock period. Such
measurement can determine the HSI16 oscillator frequency with nearly the same accuracy
as the accuracy of the 32.768 kHz quartz crystal used with the LSE oscillator (typically a few
tens of ppm). The HSI16 oscillator can then be trimmed to compensate for deviations from
target frequency, due to manufacturing, process, temperature and/or voltage variation.
The HSI16 oscillator has dedicated user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (for example, the
HSISYS/LSE ratio): the measurement accuracy is therefore closely related to the ratio
between the two clock sources. Increasing the ratio allows improving the measurement
accuracy.
Generated by the HSE oscillator, the HSE clock (divided by 32) used as time reference is
the second best method for reaching a good HSI16 frequency measurement accuracy. It is
recommended in absence of the LSE clock.
In order to further improve the precision of the HSI16 oscillator calibration, it is advised to
employ one or a combination of the following measures to increase the frequency
measurement accuracy:
• set the HSISYS divider to 1 for HSISYS frequency to be equal to HSI16 frequency
• average the results of multiple consecutive measurements
• use the input capture prescaler of the timer (one capture every up to eight periods)
• use LSE clock for the RTC and the RTC wakeup interrupt signal as time reference
The last point significantly increases the reference period for HSI16 clock pulse counting,
which improves the accuracy of a single measurement. For operation, the RTC wakeup
interrupt must be enabled.

Calibration of the LSI oscillator

The calibration of the LSI oscillator uses the same principle as that for calibrating the HSI16
oscillator. TIM16 channel1 input capture must be used for LSI clock, and HSE selected as
system clock source. The number of HSE clock pulses between consecutive edges of the
LSI signal, counted by TIM16, is then representative of the LSI clock period.

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5.2.16 Peripheral clock enable registers

Each peripheral clock can be enabled by the corresponding enable bit of the
RCC_AHBENR or RCC_APBENRx registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are
not supported.
Caution: The enable bit has a synchronization mechanism to create a glitch-free clock for the
peripheral. After the enable bit is set, there is a 2-clock-cycle delay before the clock be
active, which the software must take into account.

5.3 Low-power modes

• AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks
(Flash memory and SRAM interfaces) can be stopped by software during sleep mode.
The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all
the clocks of the peripherals connected to them are disabled.
• Stop modes (Stop 0 and Stop 1) stop all the clocks in the VCORE domain and disable
the PLL as well as the HSI16 and HSE oscillators.
The USART1, USART2, USART3, I2C1, and I2C2 peripherals can enable the HSI16
oscillator even when the MCU is in Stop mode (if HSI16 is selected as clock source for
one of those peripherals).
The USART1,USART2, and USART3 peripherals can also operate with the clock from
the LSE oscillator when the system is in Stop mode, if LSE is selected as clock source
for that peripheral and the LSE oscillator is enabled (LSEON set). In that case, the LSE
oscillator remains active when the device enters Stop mode (these peripherals do not
have the capability to turn on the LSE oscillator).
• Standby mode stops all clocks in the VCORE domain and disable the PLL, as well as the
HSI16 and HSE oscillators.
The CPU deepsleep mode can be overridden for debugging, by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When leaving the Stop 0 or Stop 1 modes, HSISYS becomes automatically the system
clock.
When leaving the Standby mode, HSISYS (with frequency equal to HSI16) becomes
automatically the system clock. At wakeup from Standby mode, the user trim is lost.
If a Flash memory programming operation is ongoing, Stop and Standby entry is delayed
until the Flash memory interface access is finished. If an access to the APB domain is
ongoing, the Stop and Standby entry is delayed until the APB access is finished.

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5.4 RCC registers

Unless otherwise specified, the RCC registers support word, half-word, and byte access,
without any wait state.

5.4.1 Clock control register (RCC_CR)

Address offset: 0x00
Power-on reset value: 0x0000 0500
Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous
value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL CSS HSE HSE HSE
Res. Res. Res. Res. Res. Res. PLLON Res. Res. Res. Res.
RDY ON BYP RDY ON
r rw rs rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI HSI
Res. Res. HSIDIV[2:0] HSION Res. Res. Res. Res. Res. Res. Res. Res.
RDY KERON
rw rw rw r rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable the PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if the
PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector
is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE
clock failure is detected. This bit is set only and is cleared by reset.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock

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Bit 17 HSERDY: HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable.
0: HSE oscillator not ready
1: HSE oscillator ready
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit
cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:11 HSIDIV[2:0]: HSI16 clock division factor
This bitfield controlled by software sets division factor of the HSI16 clock divider to produce
HSISYS clock:
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
Bit 10 HSIRDY: HSI16 clock ready flag
Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is
enabled by software by setting HSION.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.
Bit 9 HSIKERON: HSI16 always enable for peripheral kernels.
Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only
feed USART1, USART2, and I2C1 peripherals configured with HSI16 as kernel clock.
Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed
because of the HSI16 startup time. This bit has no effect on HSION value.
0: No effect on HSI16 oscillator.
1: HSI16 oscillator is forced ON even in Stop mode.
Bit 8 HSION: HSI16 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop or Standby mode.
Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as
system clock (also when leaving Stop or Standby modes, or in case of failure of the HSE
oscillator used for system clock).
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
Bits 7:0 Reserved, must be kept at reset value.

5.4.2 Internal clock source calibration register (RCC_ICSCR)

Address offset: 0x04

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Reset value: 0x0000 40XX, where X is factory-programmed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. HSITRIM[6:0] HSICAL[7:0]
rw rw rw rw rw rw rw r r r r r r r r

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:8 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI16 clock.
The default value is 64.
Bits 7:0 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value. Refer to DS for the trimming steps granularity. The frequency progression presents
discontinuities when HSICAL crosses multiples of 64.

5.4.3 Clock configuration register (RCC_CFGR)

One or two wait states are inserted if this register is accessed during clock source switch,
and between zero and 15 wait states are inserted if during an update of APB or AHB
prescaler values.
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MCOPRE[3:0] MCOSEL[3:0] (1) (1)

MCO2PRE[3:0] MCO2SEL[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PPRE[2:0] HPRE[3:0] Res. Res. SWS[2:0] SW[2:0]
rw rw rw rw rw rw rw r r r rw rw rw

1. Only significant on devices integrating the corresponding output, otherwise reserved. Refer to Section 1.4: Availability of
peripherals.

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Bits 31:28 MCOPRE[3:0]: Microcontroller clock output prescaler

This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Other: reserved
It is highly recommended to set this field before the MCO output is enabled.
Note: Values above 0111 are only significant for STM32G0B0xx. Reserved for the other
devices.
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output clock selector
This bitfield is controlled by software. It sets the clock selector for MCO output as follows:
0000: no clock, MCO output disabled
0001: SYSCLK
0010: Reserved
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: PLLPCLK
1001: PLLQCLK
1010: RTCCLK
1011: RTC WAKEUP
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Values above 0111 are only significant for STM32G0B0xx. Reserved for the other
devices.
Bits 23:20 MCO2PRE[3:0]: Microcontroller clock output 2 prescaler(1)
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Other: reserved
It is highly recommended to set this field before the MCO2 output is enabled.

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Bits 19:16 MCO2SEL[3:0]: Microcontroller clock output 2 clock selector(1)

This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:
0000: no clock, MCO2 output disabled
0001: SYSCLK
0010: Reserved
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: PLLPCLK
1001: PLLQCLK
1010: RTCCLK
1011: RTC WAKEUP
Note: This clock output may have some truncated cycles at startup or during MCO2 clock
source switching.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 PPRE[2:0]: APB prescaler
This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of
HCLK clock as follows:
0xx: 1
100: 2
101: 4
110: 8
111: 16
Bits 11:8 HPRE[3:0]: AHB prescaler
This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of
SYSCLK clock as follows:
0xxx: 1
1000: 2
1001: 4
1010: 8
1011: 16
1100: 64
1101: 128
1110: 256
1111: 512
Caution: Depending on the device voltage range, the software has to set correctly these bits to
ensure that the system frequency does not exceed the maximum allowed frequency
(for more details, refer to Section 4.1.4: Dynamic voltage scaling management). After
a write operation to these bits and before decreasing the voltage range, this register
must be read to be sure that the new value has been taken into account.
Bits 7:6 Reserved, must be kept at reset value.

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Bits 5:3 SWS[2:0]: System clock switch status

This bitfield is controlled by hardware to indicate the clock source used as system clock:
000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved
Bits 2:0 SW[2:0]: System clock switch
This bitfield is controlled by software and hardware. The bitfield selects the clock for
SYSCLK as follows:
000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved
The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop or
Standby mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is
detected.

5.4.4 PLL configuration register (RCC_PLLCFGR)

Address offset: 0x0C
Reset value: 0x0000 1000
This register configures the PLL clock outputs according to the formulas:
• fVCO = fPLLIN × (N / M)
• fPLLP = fVCO / P
• fPLLQ = fVCO / Q
• fPLLR = fVCO / R
where fPLLIN is the PLL input clock frequency, fVCO is the PLL VCO frequency, and P, Q and
R are fVCO division factors and fPLLP, fPLLQ and fPLLR the clock frequencies of the PLLPCLK,
PLLQCLK and PLLRCLK PLL clock outputs, respectively.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL PLL PLL
PLLR[2:0]
REN PLLQ[2:0](1) QEN
Res. Res. PLLP[4:0]
PEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLN[7:0] Res. PLLM[2:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw

1. Only significant on devices integrating PLLQCLK, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

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Bits 31:29 PLLR[2:0]: PLL VCO division factor R for PLLRCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor R as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
The PLLRCLK clock can be selected as system clock.
Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
Bit 28 PLLREN: PLLRCLK clock output enable
This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL:
0: Disable
1: Enable
This bit cannot be written when PLLRCLK output of the PLL is selected for system clock.
Disabling the PLLRCLK clock output, when not used, allows saving power.
Bits 27:25 PLLQ[2:0]: PLL VCO division factor Q for PLLQCLK clock output(1)
This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 128 MHz on this clock.
Bit 24 PLLQEN: PLLQCLK clock output enable(1)
This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLQCLK clock output, when not used, allows saving power.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:17 PLLP[4:0]: PLL VCO division factor P for PLLPCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor P as follows:
00000: Reserved
00001: 2
...
11111: 32
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 122 MHz on this clock.

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Bit 16 PLLPEN: PLLPCLK clock output enable

This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLPCLK clock output, when not used, allows saving power.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: PLL frequency multiplication factor N
This bit is controlled by software to set the division factor of the fVCO feedback divider (that
determines the PLL multiplication ratio) as follows:
0000000: Invalid
0000001: Reserved
...
0000111: Reserved
0001000: 8
0001001: 9
...
1010101: 85
1010110: 86
1010111: Reserved
...
1111111: Reserved

The bitfield can be written only when the PLL is disabled.

Caution: The software must set these bits so that the VCO output frequency is between 64
and 344 MHz.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM: Division factor M of the PLL input clock divider
This bit is controlled by software to divide the PLL input clock before the actual phase-locked
loop, as follows:
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the PLL input frequency after the /M divider
is between 2.66 and 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC: PLL input clock source
This bit is controlled by software to select PLL clock source, as follows:
00: No clock
01: Reserved
10: HSI16
11: HSE
The bitfield can be written only when the PLL is disabled.
When the PLL is not used, selecting 00 allows saving power.

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5.4.5 Clock interrupt enable register (RCC_CIER)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL HSE HSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RDYIE RDYIE RDYIE RDYIE RDYIE
rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock:
0: Disable
1: Enable
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization:
0: Disable
1: Enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization:
0: Disable
1: Enable
Bit 2 Reserved, must be kept at reset value.
Bit 1 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization:
0: Disable
1: Enable
Bit 0 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization:
0: Disable
1: Enable

5.4.6 Clock interrupt flag register (RCC_CIFR)

Address offset: 0x1C
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSE PLL HSE HSI LSE LSI
Res. Res. Res. Res. Res. Res. CSSF Res. Res. Res.
CSSF RDYF RDYF RDYF RDYF RDYF
r r r r r r r

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSF: LSE clock security system interrupt flag
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software by setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Bit 8 CSSF: HSE clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response
to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set
but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not
set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator

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Bit 2 Reserved, must be kept at reset value.

Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

5.4.7 Clock interrupt clear register (RCC_CICR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSE PLL HSE HSI LSE LSI
Res. Res. Res. Res. Res. Res. CSSC Res. Res. Res.
CSSC RDYC RDYC RDYC RDYC RDYC
w w w w w w w

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the HSECSSF flag.
0: No effect
1: Clear CSSF flag
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag

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Bit 2 Reserved, must be kept at reset value.

Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag

5.4.8 I/O port reset register (RCC_IOPRSTR)

Address: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST(1) RST RST RST RST

rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFRST: I/O port F reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port F
Bit 4 GPIOERST: I/O port E reset(1)
This bit is set and cleared by software.
0: no effect
1: Reset I/O port E
Bit 3 GPIODRST: I/O port D reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port D

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Bit 2 GPIOCRST: I/O port C reset

This bit is set and cleared by software.
0: no effect
1: Reset I/O port C
Bit 1 GPIOBRST: I/O port B reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port B
Bit 0 GPIOARST: I/O port A reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port A

5.4.9 AHB peripheral reset register (RCC_AHBRSTR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC FLASH DMA2 DMA1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST(1) RST

rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST: Flash memory interface reset
Set and cleared by software.
0: No effect
1: Reset Flash memory interface
This bit can only be set when the Flash memory is in power down mode.

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Bits 7:2 Reserved, must be kept at reset value.

Bit 0 DMA2RST: DMA2 and DMAMUX reset(1)
Set and cleared by software.
0: No effect
1: Reset DMA2 and DMAMUX
Bit 0 DMA1RST: DMA1 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA1 and DMAMUX

5.4.10 APB peripheral reset register 1 (RCC_APBRSTR1)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWR DBG I2C3 I2C2 I2C1 USART4 USART3 USART2
Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST(1) RST RST RST(1) RST(1) RST
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3 SPI2 USB USART6 USART5 TIM7 TIM6 TIM4 TIM3
Res. Res. Res. Res. Res. Res. Res.
RST(1) RST RST(1) RST(1) RST(1) RST(1) RST(1) RST(1) RST
rw rw rw rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset PWR
Bit 27 DBGRST: Debug support reset
Set and cleared by software.
0: No effect
1: Reset DBG
Bit 26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3RST: I2C3 reset(1)
Set and cleared by software.
0: No effect
1: Reset I2C3

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Bit 22 I2C2RST: I2C2 reset

Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 Reserved, must be kept at reset value.
Bit 19 USART4RST: USART4 reset(1)
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset(1)
Set and cleared by software.
0: No effect
1: Reset USART3
Note:
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bits 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset(1)
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bit 13 USBRST: USB reset(1)
Set and cleared by software.
0: No effect
1: Reset USB
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 USART6RST: USART3 reset(1)
Set and cleared by software.
0: No effect
1: Reset USART6
Bit 8 USART5RST: USART3 reset(1)
Set and cleared by software.
0: No effect
1: Reset USART5
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 TIM7RST: TIM7 timer reset(1)

Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset(1)
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3 Reserved, must be kept at reset value.
Bit 2 TIM4RST: TIM3 timer reset(1)
Set and cleared by software.
0: No effect
1: Reset TIM4
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 Reserved, must be kept at reset value.

5.4.11 APB peripheral reset register 2 (RCC_APBRSTR2)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADC TIM17 TIM16 TIM15

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST(1)
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYS
TIM14 USART1 SPI1 TIM1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFG
RST RST RST RST
RST
rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADCRST: ADC reset
Set and cleared by software.
0: No effect
1: Reset ADC
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM17 timer

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Bit 17 TIM16RST: TIM16 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST: TIM15 timer reset(1)
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14 timer
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG

5.4.12 I/O port clock enable register (RCC_IOPENR)

Address: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN(1) EN EN EN EN
rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

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Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFEN: I/O port F clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOEEN: I/O port E clock enable(1)
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 3 GPIODEN: I/O port D clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 2 GPIOCEN: I/O port C clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBEN: I/O port B clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOAEN: I/O port A clock enable
This bit is set and cleared by software.
0: Disable
1: Enable

5.4.13 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x38
Reset value: 0x00000 0100

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC FLASH DMA2 DMA1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN(1) EN
rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:13 Reserved, must be kept at reset value.

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Bit 12 CRCEN: CRC clock enable

Set and cleared by software.
0: Disable
1: Enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHEN: Flash memory interface clock enable
Set and cleared by software.
0: Disable
1: Enable
This bit can only be cleared when the Flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2EN: DMA2 and DMAMUX clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
Bit 0 DMA1EN: DMA1 and DMAMUX clock enable
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.

5.4.14 APB peripheral clock enable register 1 (RCC_APBENR1)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWR DBG I2C3 I2C2 I2C1 USART4 USART3 USART2

Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN(1) EN EN EN(1) EN(1) EN
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC USART USART
SPI3 SPI2 USB WWDG TIM7 TIM6 TIM4 TIM3
Res. APB 6 5 Res. Res. Res. Res.
EN(1) EN EN(1) EN EN(1) EN(1) EN(1) EN
EN EN(1) EN(1)
rw rw rw rw rw rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Disable
1: Enable

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Bit 27 DBGEN: Debug support clock enable

Set and cleared by software.
0: Disable
1: Enable
Bit 26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: I2C3 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 20 Reserved, must be kept at reset value.
Bit 19 USART4EN: USART4 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3EN: USART3 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBEN: USB clock enable(1)
Set and cleared by software.
0: Disable
1: Enable

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Bit 12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: WWDG clock enable
Set by software to enable the window watchdog clock. Cleared by hardware system
reset
0: Disable
1: Enable
This bit can also be set by hardware if the WWDG_SW option bit is 0.
Bit 10 RTCAPBEN: RTC APB clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 9 USART6EN: USART6 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 USART5EN: USART5 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6EN: TIM6 timer clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 2 TIM4EN: TIM4 timer clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 0 Reserved, must be kept at reset value.

5.4.15 APB peripheral clock enable register 2(RCC_APBENR2)

Address offset: 0x40
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADC TIM17 TIM16 TIM15

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN(1)
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYS
TIM14 USART1 SPI1 TIM1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFG
EN EN EN EN
EN
rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADCEN: ADC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15EN: TIM15 timer clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: Disable
1: Enable

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Bit 11 TIM1EN: TIM1 timer clock enable

Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG clock enable
Set and cleared by software.
0: Disable
1: Enable

5.4.16 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)

Address: 0x44
Reset value: 0x0000 003F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOE
GPIOF SMEN GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN (1) SMEN SMEN SMEN SMEN

rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of peripherals.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFSMEN: I/O port F clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOESMEN: I/O port E clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 3 GPIODSMEN: I/O port D clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable

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Bit 2 GPIOCSMEN: I/O port C clock enable during Sleep mode

Set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBSMEN: I/O port B clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOASMEN: I/O port A clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable

5.4.17 AHB peripheral clock enable in Sleep/Stop mode register

(RCC_AHBSMENR)
Address offset: 0x48
Reset value: 0x0005 1303

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA2
CRC SRAM FLASH SMEN DMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN SMEN SMEN (1) SMEN

rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of peripherals.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 Reserved, must be kept at reset value.
Bits 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAMSMEN: SRAM clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable

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Bit 8 FLASHSMEN: Flash memory interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
This bit can be activated only when the Flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2SMEN: DMA2 and DMAMUX clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
Bit 0 DMA1SMEN: DMA1 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.

5.4.18 APB peripheral clock enable in Sleep/Stop mode register 1

(RCC_APBSMENR1)
Address offset: 0x4C
Reset value: 0b0001 1000 1110 1110 1110 1111 0011 0110

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C3 USART4 USART3
PWR DBG SMEN I2C2 I2C1 SMEN SMEN USART2
Res. Res. Res. Res. Res. Res. Res. Res.
SMEN SMEN (1) SMEN SMEN (1) (1) SMEN

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB
SPI3 RTC USART6 USART5 TIM7 TIM6 TIM4
SPI2 SME Res. WWDG TIM3
SMEN APB SMEN SMEN Res. Res. SMEN SMEN Res. SMEN Res.
(1) SMEN N SMEN (1) (1) (1) (1) (1) SMEN
(1) SMEN

rw rw rw rw rw rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of peripherals.

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWRSMEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable

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Bit 27 DBGSMEN: Debug support clock enable during Sleep mode

Set and cleared by software.
0: Disable
1: Enable
Bit 26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3SMEN: I2C3 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 20 Reserved, must be kept at reset value.
Bit 19 USART4SMEN: USART4 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3SMEN: USART3 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBSMEN: USB clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable

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Bit 12 Reserved, must be kept at reset value.

Bit 11 WWDGSMEN: WWDG clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 9 USART6SMEN: USART6 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 USART5SMEN: USART5 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6SMEN: TIM6 timer clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 3 Reserved, must be kept at reset value.
Bit 2 TIM4SMEN: TIM4 timer clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 1 TIM3SMEN: TIM3 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 Reserved, must be kept at reset value.

5.4.19 APB peripheral clock enable in Sleep/Stop mode register 2

(RCC_APBSMENR2)
Address offset: 0x50
Reset value: 0x0017 D801

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADC TIM17 TIM16 TIM15S

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN SMEN SMEN MEN(1)

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYS
TIM14 USART1 SPI1 TIM1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFG
SMEN SMEN SMEN SMEN
SMEN
rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of peripherals.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADCSMEN: ADC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 TIM16SMEN: TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15SMEN: TIM15 timer clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 TIM14SMEN: TIM14 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable

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Bit 11 TIM1SMEN: TIM1 timer clock enable during Sleep mode

Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable

5.4.20 Peripherals independent clock configuration register (RCC_CCIPR)

Address: 0x54
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM15 TIM1
ADCSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res.
SEL(1) SEL

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3SEL USART2SEL USART1SEL
I2C2I2S1SEL[1:0] I2C1SEL[1:0] Res. Res. Res. Res.
[1:0](1) [1:0](1) [1:0]
rw rw rw rw rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral supporting independent clock selection (or supporting
the corresponding function), otherwise reserved. Refer to Section 1.4: Availability of peripherals and Section 26.4: USART
implementation.

Bits 31:30 ADCSEL[1:0]: ADCs clock source selection

This bitfield is controlled by software to select the clock source for ADC:
00: System clock
01: PLLPCLK
10: HSI16
11: Reserved
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 TIM15SEL: TIM15 clock source selection(1)
This bit is set and cleared by software. It selects TIM15 clock source as follows:
0: TIMPCLK
1: PLLQCLK
Bit 23 Reserved, must be kept at reset value.
Bit 22 TIM1SEL: TIM1 clock source selection
This bit is set and cleared by software. It selects TIM1 clock source as follows:
0: TIMPCLK
1: PLLQCLK(1)
Bits 21:20 Reserved, must be kept at reset value.
Bits 19:18 Reserved, must be kept at reset value.

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Bits 17:16 Reserved, must be kept at reset value.

Bits 15:14 I2C2I2S1SEL[1:0]: I2C2/I2S1 clock source selection
This bitfield is controlled by software to select I2S1/I2C2 clock source as follows:
00: PCLK/SYSCLK
01: SYSCLK/PLLPCLK
10: HSI16/HSI16
11: Reserved/I2S_CKIN
Note: On the STM32G0B0xx, the bitfield selects the clock to the I2C2 peripheral. On the other
devices, it selects the clock to the I2S1 peripheral.
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
This bitfield is controlled by software to select I2C1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 11:7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
Bits 5:4 USART3SEL[1:0]: USART3 clock source selection(1)
This bitfield is controlled by software to select USART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection(1)
This bitfield is controlled by software to select USART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
This bitfield is controlled by software to select USART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE

5.4.21 Peripherals independent clock configuration register 2

(RCC_CCIPR2)
This register is only available on STM32G0B0xx. Reserved on the other devices.
Address: 0x58
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. USBSEL(1) Res. Res. Res. Res. Res. Res. Res. Res. I2S2SEL I2S1SEL
rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral or function, otherwise reserved with zero reset value.
Refer to Section 1.4: Availability of peripherals.

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:12 USBSEL[1:0]: USB clock source selection
This bitfield is controlled by software to select the USB clock as follows:
00: Reserved
01: PLLQCLK(1)
10: HSE
11: Reserved
Bits 11:4 Reserved, must be kept at reset value.
Bits 3:2 I2S2SEL[1:0]: I2S2 clock source selection
This bitfield is controlled by software to select I2S2 clock source as follows:
00: SYSCLK
01: PLLPCLK
10: HSI16
11: External I2S clock selected as I2S2
Bits 1:0 I2S1SEL[1:0]: I2S1 clock source selection
This bitfield is controlled by software to select I2S1 clock source as follows:
00: SYSCLK
01: PLLPCLK
10: HSI16
11: External I2S clock selected as I2S1

5.4.22 RTC domain control register (RCC_BDCR)

Up to three wait states are inserted in case of successive accesses to this register. As this
register is outside of the VCORE domain, it is write-protected upon reset. The DBP bit of the
Power control register 1 (PWR_CR1) must be set to allow their modification. Refer to
Section 4.1.2: Battery backup of RTC domain on page 87 for further information.
The register bits are only reset upon RTC domain reset (see Section 5.1.3: RTC domain
reset), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC
domain power-on reset. Any internal or external reset has no effect on these bits.
Address offset: 0x5C
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCO LSCO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST
SEL EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC LSE LSE LSE LSE
Res. Res. Res. Res. Res. RTCSEL[1:0] Res. LSEDRV[1:0] LSEON
EN CSSD CSSON BYP RDY
rw rw rw r rw rw rw rw r rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LSCOSEL: Low-speed clock output selection
Set and cleared by software to select the low-speed output clock:
0: LSI
1: LSE
Bit 24 LSCOEN: Low-speed clock output (LSCO) enable
Set and cleared by software.
0: Disable
1: Enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: RTC domain software reset
Set and cleared by software to reset the RTC domain:
0: No effect
1: Reset
Bit 15 RTCEN: RTC clock enable
Set and cleared by software. The bit enables clock to RTC and TAMP.
0: Disable
1: Enable
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC as follows:
00: No clock
01: LSE
10: LSI
11: HSE divided by 32
Once the RTC clock source is selected, it cannot be changed anymore unless the RTC
domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit
can be used to reset this bitfield to 00.
Bit 7 Reserved, must be kept at reset value.
Bit 6 LSECSSD CSS on LSE failure Detection
Set by hardware to indicate when a failure is detected by the clock security system
on the external 32 kHz oscillator (LSE):
0: No failure detected
1: Failure detected

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Bit 5 LSECSSON CSS on LSE enable

Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:
0: Disable
1: Enable
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software must disable the LSECSSON bit.
Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability
Set by software to select the LSE oscillator drive capability as follows:
00: low driving capability
01: medium-low driving capability
10: medium-high driving capability
11: high driving capability
Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass the LSE oscillator (in debug mode).
0: Not bypassed
1: Bypassed
This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and
LSERDY=0).
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):
0: Not ready
1: Ready
After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software to enable LSE oscillator:
0: Disable
1: Enable

5.4.23 Control/status register (RCC_CSR)

Up to three wait states are inserted in case of successive accesses to this register. The
register is reset upon system reset, except for reset flags that are only reset upon power
reset.
Address: 0x60
Reset value: 0xXX00 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR WWDG IWWG SFT PWR PIN OBL
Res. RMVF Res. Res. Res. Res. Res. Res. Res.
RSTF RSTF RSTF RSTF RSTF RSTF RSTF
r r r r r r r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSION
RDY
r rw

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Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop or Standby mode entry.
Cleared by setting the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
This operates only if nRST_STOP or nRST_STDBY option bits are cleared.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by setting the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by setting the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by setting the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PWRRSTF: POR/PDR flag
Set by hardware when a POR/PDR occurs.
Cleared by setting the RMVF bit.
0: No POR occurred
1: POR occurred
Bit 26 PINRSTF: Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by setting the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the Option byte loading occurs.
Cleared by setting the RMVF bit.
0: No reset from Option byte loading occurred
1: Reset from Option byte loading occurred
Bit 24 Reserved, must be kept at reset value.
Bit 23 RMVF: Remove reset flags
Set by software to clear the reset flags.
0: No effect
1: Clear reset flags

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Bits 22:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):
0: Not ready
1: Ready
After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit
can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by
the Independent Watchdog or by the RTC.
Bit 0 LSION: LSI oscillator enable
Set and cleared by software to enable/disable the LSI oscillator:
0: Disable
1: Enable

5.4.24 RCC register map

The following table gives the RCC register map and the reset values.

Table 28. RCC register map and reset values

Off- Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
set

HSIDIV[2:0]

HSIKERON
HSERDY
HSEBYP
PLLRDY

HSIRDY
CSSON

HSEON
PLLON

HSION
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_CR
0x00

Reset value 0 0 0 0 0 0 0 0 0 1 0 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RCC_ICSCR HSITRIM[6:0] HSICAL[7:0]

0x04
Reset value 1 0 0 0 0 0 0 X X X X X X X X
MCO2PRE[3:0]

MCO2SEL[3:0]
MCOPRE[3:0]

MCOSEL[3:0]

HPRE[3:0]
PPRE[2:0]

SWS[2:0]

SW[2:0]
Res.

Res.
Res.

RCC_CFGR
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLLQ[2:0]
PLLR[2:0]

PLLP[4:0]
PLLQEN

PLL
PLLREN

PLLPEN

RCC_PLL PLLM
Res.
Res.

Res.

Res.

Res.
Res.

PLLN[6:0] SRC
0x0C CFGR [2:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
PLLRDYIE Res. Res.
HSERDYIE Res. Res.
HSIRDYIE Res. Res.
Res. Res.
LSERDYIE Res. Res.
LSIRDYIE Res. Res.

0x10 Reserved

0x14 Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

RCC_CIER
0x18

Reset value 0 0 0 0 0

RM0454 Rev 5 169/989

172
 set
Off-

0x38
0x34
0x30
0x28
0x24
0x20

0x2C
0x1C

170/989
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_

IOPENR
Register

AHBENR
IOPRSTR

AHBRSTR
RCC_CIFR

RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APBRSTR2
APBRSTR1
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. PWRRST Res. Res. Res. Res. 28

0 0
Reset and clock control (RCC)

Res. Res. Res. DBGRST Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. I2C3RST Res. Res. Res. Res. 23
Res. Res. Res. I2C2RST Res. Res. Res. Res. 22

0 0 0
Res. Res. Res. I2C1RST Res. Res. Res. Res. 21

0
Res. Res. ADCRST Res. Res. Res. Res. Res. 20
Res. Res. Res. USART4RST Res. Res. Res. Res. 19
Res.. Res. TIM17RST USART3RST Res.. Res. Res. Res. 18

RM0454 Rev 5
0 0 0
Res. Res. TIM16RST USART2RST Res. Res. Res. Res. 17
Res.. Res. TIM15RST Res. .Res. Res. Res. Res. 16
Res. Res. TIM14RST SPI3RST Res. Res. Res. Res. 15

0 0 0 0 0
Res. Res. USART1RST SPI2RST Res. Res. Res. Res. 14

0 0 0
Res. Res. Res. USBRST Res. Res. Res. Res. 13

0
CRCEN Res. SPI1RST Res. 0 CRCRST. Res. Res. Res. 12

0 0
Res. Res. TIM1RST Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. USART6RST Res. Res. LSECSSC LSECSSF 9
Table 28. RCC register map and reset values (continued)

0 0

1
0
0 0
0 0

FLASHEN Res. Res. USART5RST FLASHRST. Res. CSSC CSSF 8

Res. Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. GPIOFEN Res. TIM7RST Res. GPIOFRST PLLRDYC PLLRDYF 5
0 0

Res. GPIOEEN Res. TIM6RST Res. GPIOERST HSERDYC HSERDYF 4

0 0 0
0 0 0

Res. GPIODEN Res. Res. Res. GPIODRST HSIRDYC HSIRDYF 3

Res. GPIOCEN Res. TIM4RST Res. GPIOCRST Res. Res. 2
0 0

DMA2EN GPIOBEN Res. TIM3RST DMA2RST GPIOBRST LSERDYC LSERDYF 1

0 0
0 0 0 0 0 0
0
0 0
0 0 0 0 0 0
0 0
0 0
RM0454

DMA1EN GPIOAEN SYSCFGRST Res. DMA1RST GPIOARST LSIRDYC LSIRDYF 0

 set
Off-

0x54
0x50
0x48
0x44
0x40
0x3C
RM0454

RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
Register

APBENR2
APBENR1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

IOPSMENR

AHBSMENR

RCC_CCIPR
APBSMENR2
0x4C APBSMENR1
ADCSEL[1:0] Res. Res. Res. Res. Res. Res. 31

0 0
Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. PWRSMEN Res. Res. Res. PWREN 28

1 1
0 0

Res. Res. DBGSMEN Res. Res. Res. DBGEN 27

Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25

0
TIM15SEL Res. Res. Res. Res. Res. Res. 24
Res. Res. I2C3SMEN Res. Res. Res. I2C3EN 23

0
TIM1SEL Res. I2C2SMEN Res. Res. Res. I2C2EN 22

1 1 1
0 0 0

Res. I2C1SMEN Res. Res. Res. I2C1EN 21

Res.

1
0

ADCSMEN Res. Res. Res. ADCEN Res. 20

Res. Res. USART4SMEN Res. Res. Res. USART4EN 19
TIM17SMEN USART3SMEN Res.. Res. TIM17EN USART3EN 18

RM0454 Rev 5
1 1 1
0 0 0

Res. TIM16SMEN USART2SMEN Res. Res. TIM16EN USART2EN 17

Res. TIM15SMEN Res. Res.. Res. TIM15EN Res. 16
I2C2I2S1SEL[1:0] TIM14SMEN SPI3SMEN Res. Res. TIM14EN SPI3EN 15

1 1 1 1 1
0 0 0 0 0

USART1SMEN SPI2SMEN Res. Res. USART1EN SPI2EN 14

1 1 1
0 0 0

I2C1SEL[1:0] Res. USBSMEN Res. Res. Res. USBEN 13

0 0 0 0
1
SPI1SMEN Res. CRCSMEN Res. SPI1EN Res. 12

1 1
0 0

Res. TIM1SMEN Res. Res. Res. TIM1EN Res. 11

Res. Res. Res. Res. Res. Res. 10
Res. Res. USART6SMEN SRAMSMEN Res. Res. USART6EN 9
Table 28. RCC register map and reset values (continued)

1 1
0 0

1 1

Res. USART5SMEN FLASHSMEN Res. Res. USART5EN 8

Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. 6
USART3SEL[1:0] Res. TIM7SMEN Res. GPIOFSMEN Res. TIM7EN 5

1 1
0 0

Res. TIM6SMEN Res. GPIOESMEN Res. TIM6EN 4

USART2SEL[1:0] Res. Res. Res. GPIODSMEN Res. Res. 3
Res. TIM4SMEN Res. GPIOCSMEN Res. TIM4EN 2
1 1
0 0

USART1SEL[1:0] Res. TIM3SMEN DMA2SMEN GPIOBSMEN Res. TIM3EN 1

0 0 0 0 0 0
1
1 1
1 1 1 1 1 1
0
Reset and clock control (RCC)

171/989
SYSCFGSMEN Res. DMA1SMEN GPIOASMEN SYSCFGEN Res. 0

172
 set
Off-

0x60
0x58

0x5C

172/989
Register

RCC_CSR

Reset value
Reset value
Reset value

RCC_BDCR
LPWRRSTF Res. RCC_CCIPR2
Res. 31
WWDGRSTF Res. Res. 30
IWDGRSTF Res. Res. 29
SFTRSTF Res. Res. 28
Reset and clock control (RCC)

PWRRSTF Res. Res. 27

PINRSTF Res. Res. 26

0 0 0 0 0 0 0
OBLRSTF LSCOSEL Res. 25

0 0
Res. LSCOEN Res. 24

0
RMVF Res. Res. 23
Res. Res. Res. 22
Res. Res. Res. 21
Res. Res. Res. 20
Res. Res. Res. 19
Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. 17
Res. BDRST Res. 16
0 0

Res. RTCEN Res. 15

Res. Res. Res. 14
Res. Res. USBSEL[1:0] 13
0 0

Res. Res. 12
Res. Res. Res. 11
Res. Res. Res. 10
Res. RTC SEL[1:0] Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.
Table 28. RCC register map and reset values (continued)

0 0

Res. 8
Res. Res. Res. 7
Res. LSECSSD Res. 6
Res. LSECSSON Res. 5
Res. LSE DRV[1:0] Res. 4
Res. I2S2SEL[1:0] 3
Res. LSEBYP 2
LSIRDY LSERDY I2S1SEL[1:0] 1
0 0
0 0 0 0 0 0 0
0 0 0 0
RM0454

LSION LSEON 0
RM0454 General-purpose I/Os (GPIO)

6 General-purpose I/Os (GPIO)

6.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).

6.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers (at most 8 AFs possible per I/O)
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

6.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and
GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.

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General-purpose I/Os (GPIO) RM0454

Figure 13 shows the basic structures of a standard I/O port bit. Table 29 gives the possible
port bit configurations.

Figure 13. Basic structure of an I/O port bit

To/from on-chip
peripherals, Analog input/output
power control
Digital input
and EXTI Input data register
On/off
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

Alternate function VSS Push-pull,

From on-chip output open-drain
peripheral or disabled

MSv33182V2

Table 29. Port bit configuration table(1)

MODE(i) OSPEED(i) PUPD(i)
OTYPE(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved

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RM0454 General-purpose I/Os (GPIO)

Table 29. Port bit configuration table(1) (continued)

MODE(i) OSPEED(i) PUPD(i)
OTYPE(i) I/O configuration
[1:0] [1:0] [1:0]

x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

6.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA14: SWCLK in pull-down
• PA13: SWDIO in pull-up
Note: PA14 is shared with BOOT0 functionality. Caution is required as the debugging device can
manipulate BOOT0 pin value.
Upon reset, the FT_c I/O structure presents a pull-down resistor that can be disabled by
setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register.
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

6.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.

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General-purpose I/Os (GPIO) RM0454

Each I/O pin has a multiplexer with up to eight alternate function inputs (AF0 to AF7) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
– Configure the desired I/O as an alternate function in the GPIOx_MODER register.
• Additional functions:
– ADC connection can be enabled in ADC registers regardless the configured GPIO
mode. When ADC uses a GPIO, it is recommended to configure the GPIO in
analog mode, through the GPIOx_MODER register.
– For the additional functions like RTC, TAMP, WKUPx and oscillators, configure the
required function in the related RTC, TAMP, PWR and RCC registers. These
functions have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

6.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

6.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.

176/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

See Section 6.4.5: GPIO port input data register (GPIOx_IDR) (x = A to F) and
Section 6.4.6: GPIO port output data register (GPIOx_ODR) (x = A to F) for the register
descriptions.

6.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

6.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 6.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to F)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details refer to LCKR register description in Section 6.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A to F).

6.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can

RM0454 Rev 5 177/989

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General-purpose I/Os (GPIO) RM0454

thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

6.3.8 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the given pin must
not be configured in analog mode or being used as oscillator pin, so the input trigger is kept
enabled.
Refer to Section 12: Extended interrupt and event controller (EXTI).

6.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 14 shows the input configuration of the I/O port bit.

Figure 14. Input floating/pull up/pull down configurations

and EXTI
Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver
on/off Pull
down
Read/write
VSS

MSv33183V2

178/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

6.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value
Figure 15 shows the output configuration of the I/O port bit.

Figure 15. Output configuration

To / from on-chip
peripherals, Analog input/output
power control
and EXTI
Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

VSS Push-pull or
open-drain
MSv33184V3

6.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
Figure 16 shows the Alternate function configuration of the I/O port bit.

RM0454 Rev 5 179/989

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General-purpose I/Os (GPIO) RM0454

Figure 16. Alternate function configuration-

Analog input/output
To/from on-chip
peripheral Alternate function input

Input data register

On
Read

Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register
Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

VSS
From on-chip Alternate function output Push-pull
peripheral or open-drain

MSv31479V2

6.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
Figure 17 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 17. High impedance-analog configuration

To/from on-chip Analog input/output

peripheral
Input data register

Off
Read
0
Bit set/reset registers

TTL Schmitt trigger

Write
Output data register

Input driver

I/O pin
Output driver

Read/write

MSv33185V2

180/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

6.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.

6.3.14 Using the GPIO pins in the RTC domain

The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 23.3: RTC functional description.

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General-purpose I/Os (GPIO) RM0454

6.4 GPIO registers

This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 30.
The peripheral registers can be written in word, half word or byte mode.

6.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to F)
Address offset:0x00
Reset value: 0xEBFF FFFF for port A
Reset value: 0xFFFF FFFF for other ports

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE15[1:0] MODE14[1:0] MODE13[1:0] MODE12[1:0] MODE11[1:0] MODE10[1:0] MODE9[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

6.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to F)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

182/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

6.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to F)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED7 OSPEED6 OSPEED5 OSPEED4 OSPEED3 OSPEED2 OSPEED1 OSPEED0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEED[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Very low speed
01: Low speed
10: High speed
11: Very high speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..
The FT_c GPIOs cannot be set to high speed.

6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to F)
Address offset: 0x0C
Reset value: 0x2400 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

RM0454 Rev 5 183/989

188
General-purpose I/Os (GPIO) RM0454

6.4.5 GPIO port input data register (GPIOx_IDR)

(x = A to F)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

6.4.6 GPIO port output data register (GPIOx_ODR)

(x = A to F)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR register (x = A..D, F).

6.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to F)
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

184/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit

6.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to F)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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General-purpose I/Os (GPIO) RM0454

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns ‘1’ until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked

6.4.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to F)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
1000: Reserved
0000: AF0
1001: Reserved
0001: AF1
1010: Reserved
0010: AF2
1011: Reserved
0011: AF3
1100: Reserved
0100: AF4
1101: Reserved
0101: AF5
1110: Reserved
0110: AF6
1111: Reserved
0111: AF7

186/989 RM0454 Rev 5

RM0454 General-purpose I/Os (GPIO)

6.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to F)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0 1000: Reserved
0001: AF1 1001: Reserved
0010: AF2 1010: Reserved
0011: AF3 1011: Reserved
0100: AF4 1100: Reserved
0101: AF5 1101: Reserved
0110: AF6 1110: Reserved
0111: AF7 1111: Reserved

6.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to F)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

RM0454 Rev 5 187/989

188
General-purpose I/Os (GPIO) RM0454

6.4.12 GPIO register map

The following table gives the GPIO register map and reset values.

Table 30. GPIO register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MODE15[1:0]

MODE14[1:0]

MODE13[1:0]

MODE12[1:0]

MODE10[1:0]
MODE11[1:0]

MODE9[1:0]

MODE8[1:0]

MODE7[1:0]

MODE6[1:0]

MODE5[1:0]

MODE4[1:0]

MODE3[1:0]

MODE2[1:0]

MODE1[1:0]

MODE0[1:0]
GPIOx_MODER

0x00
Reset value port A 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
port B to F

GPIOx_OTYPER

OT15
OT14
OT13
OT12

OT10
OT11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
0x04 (x = A to F)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OSPEED15[1:0]

OSPEED14[1:0]

OSPEED13[1:0]

OSPEED12[1:0]

OSPEED10[1:0]
OSPEED11[1:0]

OSPEED9[1:0]

OSPEED8[1:0]

OSPEED7[1:0]

OSPEED6[1:0]

OSPEED5[1:0]

OSPEED4[1:0]

OSPEED3[1:0]

OSPEED2[1:0]

OSPEED1[1:0]

OSPEED0[1:0]
GPIOx_OSPEEDR
(x = A to F)
0x08

Reset value port A 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
port B to F
PUPD15[1:0]

PUPD14[1:0]

PUPD13[1:0]

PUPD12[1:0]

PUPD10[1:0]
PUPD11[1:0]

PUPD9[1:0]

PUPD8[1:0]

PUPD7[1:0]

PUPD6[1:0]

PUPD5[1:0]

PUPD4[1:0]

PUPD3[1:0]

PUPD2[1:0]

PUPD1[1:0]

PUPD0[1:0]
GPIOx_PUPDR
(x = A to F)
0x0C
Reset value port A 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
port B to F
GPIOx_IDR
ID15
ID14
ID13
ID12

ID10
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ID11

ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x10 (x = A to F)
Reset value x x x x x x x x x x x x x x x x
GPIOx_ODR
OD15
OD14
OD13
OD12

OD10
OD11

OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x14 (x = A to F)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BSRR
BR15
BR14
BR13
BR12

BR10

BS15
BS14
BS13
BS12

BS10
BR11

BS11
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0

BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0x18 (x = A to F)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LCK15
LCK14
LCK13
LCK12

LCK10
LCK11

GPIOx_LCKR
LCKK

LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x1C (x = A to F)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRL AFSEL7 AFSEL6 AFSEL5 AFSEL4 AFSEL3 AFSEL2 AFSEL1 AFSEL0
0x20 (x = A to F) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRH AFSEL15 AFSEL14 AFSEL13 AFSEL12 AFSEL11 AFSEL10 AFSEL9 AFSEL8
0x24 (x = A to F) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BRR
BR15
BR14
BR13
BR12

BR10
BR11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0

0x28 (where x = A..D, F))

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

188/989 RM0454 Rev 5

RM0454 System configuration controller (SYSCFG)

7 System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
• Enabling/disabling I2C Fast Mode Plus on some I/O ports
• Enabling/disabling the analog switch booster
• Configuring the IR modulation signal and its output polarity
• Remapping of some I/O ports
• Remapping the memory located at the beginning of the code area
• Flag pending interrupts from each interrupt line
• Managing robustness feature

7.1 SYSCFG registers

7.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection. After reset these bits take the value selected by the actual boot mode
configuration.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode
configuration

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

I2C3_ I2C_ I2C_ I2C_ I2C_ I2C_ I2C_

I2C2_ I2C1_
Res. Res. Res. Res. Res. Res. Res. PA10_ PA9_ PB9_ PB8_ PB7_ PB6_
FMP(1) FMP FMP
FMP FMP
FMP FMP FMP FMP
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD2_ UCPD1_
Res. Res. Res. Res. Res. STROBE STROBE BOOS IR_MOD IR_ PA12_ PA11_
Res.
MEM_MODE
(1) (1) TEN [1:0] POL RMP RMP [1:0]

w w rw rw rw rw rw rw rw

1. Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to Section 1.4:
Availability of peripherals.

RM0454 Rev 5 189/989

207
System configuration controller (SYSCFG) RM0454

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 I2C3_FMP: Fast Mode Plus (FM+) enable for I2C3(1)
This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports
configured as I2C3 through GPIOx_AFR registers.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3
can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the
speed control is ignored.
Bit 23 I2C_PA10_FMP: Fast Mode Plus (FM+) enable for PA10
This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O
port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Bit 22 I2C_PA9_FMP: Fast Mode Plus (FM+) enable for PA9
This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Bit 21 I2C2_FMP: Fast Mode Plus (FM+) enable for I2C2
This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports
configured as I2C2 through GPIOx_AFR registers.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C2
can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the
speed control is ignored.
Bit 20 I2C1_FMP: Fast Mode Plus (FM+) enable for I2C1
This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports
configured as I2C1 through GPIOx_AFR registers.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1
can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the
speed control is ignored.
Bit 19 I2C_PB9_FMP: Fast Mode Plus (FM+) enable for PB9
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.

190/989 RM0454 Rev 5

RM0454 System configuration controller (SYSCFG)

Bit 18 I2C_PB8_FMP: Fast Mode Plus (FM+) enable for PB8

This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Bit 17 I2C_PB7_FMP: Fast Mode Plus (FM+) enable for PB7
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Bit 16 I2C_PB6_FMP: Fast Mode Plus (FM+) enable for PB6
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 UCPD2_STROBE: PD0 and PD2 pull-down configuration strobe(1)
Upon power on, internal pull-down resistors on PD0 and PD2 pins are enabled (connected).
Setting this bit disables (disconnects) the internal pull-down resistors.

Bit 9 UCPD1_STROBE: PB15 and PA8 pull-down configuration strobe(1)

Upon power on, internal pull-down resistors on PB15 and PA8 pins are enabled (connected).
Setting this bit disables (disconnects) the internal pull-down resistors.

Bit 8 BOOSTEN: I/O analog switch voltage booster enable

This bit selects the way of supplying I/O analog switches:
0: VDD
1: Dedicated voltage booster (supplied by VDD)
When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low
VDD (less than 2.4 V).
Bits 7:6 IR_MOD[1:0]: IR Modulation Envelope signal selection
This bitfield selects the signal for IR modulation envelope:
00: TIM16
01: USART1
10: USART4 on STM32G070xx as well as STM32G0B0xx, USART2 on STM32G030xx as
well as STM32G050xx
11: Reserved
Bit 5 IR_POL: IR output polarity selection
0: Output of IRTIM (IR_OUT) is not inverted
1: Output of IRTIM (IR_OUT) is inverted
Bit 4 PA12_RMP: PA12 pin remapping
This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10
GPIO port, instead as PA12 GPIO port.
0: No remap (PA12)
1: Remap (PA10)

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Bit 3 PA11_RMP: PA11 pin remapping

This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9
GPIO port, instead as PA11 GPIO port.
0: No remap (PA11)
1: Remap (PA9)
Bit 2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
These bits are set and cleared by software. They control the memory internal mapping at
address 0x0000 0000. After reset these bits take on the value selected by the actual boot
mode configuration. Refer to Section 2.5: Boot configuration for more details.
x0: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000

7.1.2 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PB2_ PB1_ PB0_ PA13_ PA6_ PA5_ PA3_ PA1_
Res. Res. Res. Res. Res. Res. Res. Res. CDEN CDEN CDEN CDEN CDEN CDEN CDEN CDEN
(1) (1) (1) (1) (1) (1) (1) (1)

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM_
SRAM_ ECC_ LOCKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PARITY
PEF LOCK _LOCK
_LOCK
rc_w1 rw rw rw

1. Only significant on devices integrating switchable clamping diodes, otherwise reserved. Refer to Section 1.4: Availability of
peripherals.

Bits 31:24 Reserved, must be kept at reset value

Bit 23 PB2_CDEN: PB2 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PB2
pin.
0: Disable
1: Enable
Bit 22 PB1_CDEN: PB1 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PB1
pin.
0: Disable
1: Enable
Bit 21 PB0_CDEN: PB0 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PB0
pin.
0: Disable
1: Enable

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RM0454 System configuration controller (SYSCFG)

Bit 20 PA13_CDEN: PA13 clamping diode enable bit(1)

This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on
PA13 pin.
0: Disable
1: Enable
Bit 19 PA6_CDEN: PA6 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PA6
pin.
0: Disable
1: Enable
Bit 18 PA5_CDEN: PA5 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PA5
pin.
0: Disable
1: Enable
Bit 17 PA3_CDEN: PA3 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PA3
pin.
0: Disable
1: Enable
Bit 16 PA1_CDEN: PA1 clamping diode enable bit(1)
This bit is set and cleared by software. It enables (connects) a clamping diode to VDD on PA1
pin.
0: Disable
1: Enable
Bits 15:9 Reserved, must be kept at reset value
Bit 8 SRAM_PEF: SRAM parity error flag
This bit is set by hardware when an SRAM parity error is detected. It is cleared by software
by writing 1.
0: No SRAM parity error detected
1: SRAM parity error detected
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ECC_LOCK: ECC error lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the Flash ECC 2-bit error detection signal connection to TIM1/15/16/17 Break input.
0: ECC error disconnected from TIM1/15/16/17 Break input
1: ECC error connected to TIM1/15/16/17 Break input

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System configuration controller (SYSCFG) RM0454

Bit 2 Reserved, must be kept at reset value.

Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the SRAM parity error signal connection to TIM1/15/16/17 Break input.
0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 0 LOCKUP_LOCK: Cortex®-M0+ LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable and lock the
connection of Cortex®-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
0: Cortex®-M0+ LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex®-M0+ LOCKUP output connected to TIM1/15/16/17 Break input

7.1.3 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)

A dedicated set of registers is implemented on the device to collect all pending interrupt
sources associated with each interrupt line into a single register. This allows users to check
by single read which peripheral requires service in case more than one source is associated
to the interrupt line.
All bits in those registers are read only, set by hardware when there is corresponding
interrupt request pending and cleared by resetting the interrupt source flags in the
peripheral registers.
Address offset: 0x80
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 WWDG: Window watchdog interrupt pending flag

7.1.4 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)

Address offset: 0x88
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC TAMP
r r

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RM0454 System configuration controller (SYSCFG)

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RTC: RTC interrupt request pending (EXTI line 19)
Bit 0 TAMP: Tamper interrupt request pending (EXTI line 21)

7.1.5 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)

Address offset: 0x8C
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_ FLASH_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ECC ITF
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 FLASH_ECC: Flash interface ECC interrupt request pending
Bit 0 FLASH_ITF: Flash interface interrupt request pending

7.1.6 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)

Address offset: 0x90
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RCC
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RCC: Reset and clock control interrupt request pending

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7.1.7 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)

Address offset: 0x94
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI1 EXTI0
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI1: EXTI line 1 interrupt request pending
Bit 0 EXTI0: EXTI line 0 interrupt request pending

7.1.8 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)

Address offset: 0x98
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3 EXTI2
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI3: EXTI line 3 interrupt request pending
Bit 0 EXTI2: EXTI line 2 interrupt request pending

7.1.9 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)

Address offset: 0x9C
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. EXTI15 EXTI14 EXTI13 EXTI12 EXTI11 EXTI10 EXTI9 EXTI8 EXTI7 EXTI6 EXTI5 EXTI4
r r r r r r r r r r r r

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RM0454 System configuration controller (SYSCFG)

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 EXTI15: EXTI line 15 interrupt request pending
Bit 10 EXTI14: EXTI line 14 interrupt request pending
Bit 9 EXTI13: EXTI line 13 interrupt request pending
Bit 8 EXTI12: EXTI line 12 interrupt request pending
Bit 7 EXTI11: EXTI line 11 interrupt request pending
Bit 6 EXTI10: EXTI line 10 interrupt request pending
Bit 5 EXTI9: EXTI line 9 interrupt request pending
Bit 4 EXTI8: EXTI line 8 interrupt request pending
Bit 3 EXTI7: EXTI line 7 interrupt request pending
Bit 2 EXTI6: EXTI line 6 interrupt request pending
Bit 1 EXTI5: EXTI line 5 interrupt request pending
Bit 0 EXTI4: EXTI line 4 interrupt request pending

7.1.10 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)

Address offset: 0xA0
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. (1) Res. Res.

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of
peripherals.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 USB: USB interrupt request pending(1)
Bit 1 Reserved, must be kept at reset value.
Bit 0 Reserved, must be kept at reset value.

7.1.11 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)

Address offset: 0xA4
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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System configuration controller (SYSCFG) RM0454

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA1_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH1
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DMA1_CH1: DMA1 channel 1 interrupt request pending

7.1.12 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)

Address offset: 0xA8
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA1 DMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_CH3 _CH2
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DMA1_CH3: DMA1 channel 3 interrupt request pending
Bit 0 DMA1_CH2: DMA1 channel 2 interrupt request pending

7.1.13 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)

Address offset: 0xAC
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA2_ DMA2_ DMA2_ DMA2_ DMA2 DMA1 DMA1
CH5 CH4 CH3 CH2 _CH1 _CH7 _CH6 DMA1 DMA1
Res. Res. Res. Res. Res. Res. DMAMUX
(1) (1) (1) (1) (1) (1) (1) _CH5 _CH4

r r r r r r r r r r

1. Only significant on devices integrating the corresponding DMA instance and channel, otherwise reserved. Refer to
Section 1.4: Availability of peripherals.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 DMA2_CH5: DMA2 channel 5 interrupt request pending(1)
Bit 8 DMA2_CH4: DMA2 channel 4 interrupt request pending(1)
Bit 7 DMA2_CH3: DMA2 channel 3 interrupt request pending(1)
Bit 6 DMA2_CH2: DMA2 channel 2 interrupt request pending(1)
Bit 5 DMA2_CH1: DMA2 channel 1 interrupt request pending(1)

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RM0454 System configuration controller (SYSCFG)

Bit 4 DMA1_CH7: DMA1 channel 7 interrupt request pending(1)

Bit 3 DMA1_CH6 DMA1 channel 6 interrupt request pending(1)
Bit 2 DMA1_CH5: DMA1 channel 5 interrupt request pending
Bit 1 DMA1_CH4: DMA1 channel 4 interrupt request pending
Bit 0 DMAMUX: DMAMUX interrupt request pending

7.1.14 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)

Address offset: 0xB0
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 ADC: ADC interrupt request pending

7.1.15 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)

Address offset: 0xB4
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM1_ TIM1_ TIM1_ TIM1_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BRK UPD TRG CCU
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 TIM1_BRK: Timer 1 break interrupt request pending
Bit 2 TIM1_UPD: Timer 1 update interrupt request pending
Bit 1 TIM1_TRG: Timer 1 trigger interrupt request pending
Bit 0 TIM1_CCU: Timer 1 commutation interrupt request pending

7.1.16 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)

Address offset: 0xB8
System reset value: 0x0000 0000

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System configuration controller (SYSCFG) RM0454

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM1_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CC
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM1_CC: Timer 1 capture compare interrupt request pending

7.1.17 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)

Address offset: 0xC0
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. (1) TIM3
TIM4
r r

1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 TIM4: Timer 4 interrupt request pending
Bit 0 TIM3: Timer 3 interrupt request pending

7.1.18 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)

Address offset: 0xC4
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM6(1)
r

1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM6: Timer 6 interrupt request pending(1)

7.1.19 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)

Address offset: 0xC8

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RM0454 System configuration controller (SYSCFG)

System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM7(1)
r

1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM7: Timer 7 interrupt request pending(1)

7.1.20 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)

Address offset: 0xCC
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM14
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM14: Timer 14 interrupt request pending

7.1.21 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)

Address offset: 0xD0
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15(1)
r

1. Only significant on devices integrating TIM15, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM15: Timer 15 interrupt request pending(1)

7.1.22 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)

Address offset: 0xD4

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System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM16
r

Bits 31:3 Reserved, must be kept at reset value.

Bit 0 TIM16: Timer 16 interrupt request pending

7.1.23 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)

Address offset: 0xD8
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM17
r

Bits 31:3 Reserved, must be kept at reset value.

Bit 0 TIM17: Timer 17 interrupt request pending

7.1.24 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)

Address offset: 0xDC
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C1
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 I2C1: I2C1 interrupt request pending, combined with EXTI line 23

7.1.25 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)

Address offset: 0xE0
System reset value: 0x0000 0000

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RM0454 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C3(1) I2C2
r r

1. Only significant on devices integrating I2C3, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2C3: I2C3 interrupt request pending (EXTI line 22)(1)
Bit 0 I2C2: I2C2 interrupt request pending

7.1.26 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)

Address offset: 0xE4
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI1
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SPI1: SPI1 interrupt request pending

7.1.27 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)

Address offset: 0xE8
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI3(1) SPI2

r r

1. Only significant on devices integrating SPI3, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SPI3: SPI3 interrupt request pending(1)
Bit 0 SPI2: SPI2 interrupt request pending

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7.1.28 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)

Address offset: 0xEC
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USART1
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 USART1: USART1 interrupt request pending, combined with EXTI line 25

7.1.29 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)

Address offset: 0xF0
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USART2
r

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 USART2: USART2 interrupt request pending (EXTI line 26)

7.1.30 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)

Address offset: 0xF4
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6 USART5 USART4 USART3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. (1) (1) Res. (1) (1)

r r r r

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.

204/989 RM0454 Rev 5

 0x98
0x94
0x90
0x88
0x84
0x80
0x18
0x17
0x00

0x7F

0x8C
0x04 to

0x1D to
Offset
7.1.31
RM0454

Reserved
Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SYSCFG_CFGR2
SYSCFG_CFGR1

SYSCFG_ITLINE6
SYSCFG_ITLINE5
SYSCFG_ITLINE4
SYSCFG_ITLINE3
SYSCFG_ITLINE2
SYSCFG_ITLINE0
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
SYSCFG register map

0
Res. Res. Res. Res. Res. Res. Res. I2C3_FMP 24

0
Res. Res. Res. Res. Res. Res. Res. I2C_PA10_FMP 23

0
Res. Res. Res. Res. Res. Res. Res. I2C_PA9_FMP 22

0
Res. Res. Res. Res. Res. Res. Res. I2C2_FMP 21

0
Res. Res. Res. Res. Res. Res. Res. I2C1_FMP 20
Bits 31:5 Reserved, must be kept at reset value.

0
Bit 2 Reserved, must be kept at reset value.

Res. Res. Res. Res. Res. Res. Res. I2C_PB9_FMP 19

0
Res. Res. Res. Res. Res. Res. Res. I2C_PB8_FMP 18

RM0454 Rev 5
0
Res. Res. Res. Res. Res. Res. Res. I2C_PB7_FMP 17
Bit 1 USART4: USART4 interrupt request pending(1)
Bit 3 USART5: USART5 interrupt request pending(1)
Bit 4 USART6: USART6 interrupt request pending(1)

0
Res. Res. Res. Res. Res. Res. Res. I2C_PB6_FMP 16
Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved
Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. 12
Bit 0 USART3: USART3 interrupt request pending (EXTI line 28)(1)

Res. Res. Res. Res. Res. Res. Res. Res. 11

UCPD2_STROBE
0

Res. Res. Res. Res. Res. Res. Res.

Table 31. SYSCFG register map and reset values

10
0

Res. Res. Res. Res. Res. Res. Res. UCPD2_STROBE 9

0

0
Res. Res. Res. Res. Res. Res. SRAM_PEF BOOSTEN 8
0

Res. Res. Res. Res. Res. Res. Res. 7

The following table gives the SYSCFG register map and the reset values.

IR_MOD
0

Res. Res. Res. Res. Res. Res. Res. 6

0

Res. Res. Res. Res. Res. Res. Res. IR_POL 5

0

Res. Res. Res. Res. Res. Res. Res. PA12_RMP 4

0

Res. Res. Res. Res. Res. Res. ECC_LOCK PA11_RMP 3

Res. Res. Res. Res. Res. Res. Res. Res. 2

0
0
0
0
0

EXTI3 EXTI1 Res. FLASH_ECC RTC Res. SRAM_PARITY_LOCK 1

MEM_MODE[1:0]

0
0
0
0
0
0
0
X X

EXTI2 EXTI0 RCC FLASH_ITF TAMP WWDG LOCUP_LOCK 0

205/989
System configuration controller (SYSCFG)

207
 0xB8
0xB4
0xB0
0xA8
0xA4
0xA0
0x9C

0xD8
0xD4
0xD0
0xC8
0xC4
0xC0
0xBC
0xAC

0xCC
Offset

206/989
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SYSCFG_ITLINE9
SYSCFG_ITLINE8
SYSCFG_ITLINE7

SYSCFG_ITLINE11

SYSCFG_ITLINE22
SYSCFG_ITLINE21
SYSCFG_ITLINE20
SYSCFG_ITLINE19
SYSCFG_ITLINE18
SYSCFG_ITLINE17
SYSCFG_ITLINE16
SYSCFG_ITLINE14
SYSCFG_ITLINE13
SYSCFG_ITLINE12
SYSCFG_ITLINE10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
System configuration controller (SYSCFG)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15 11
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI14 10
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2_CH5 Res. Res. Res. EXTI13 9
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2_CH4 Res. Res. Res. EXTI12 8
Table 31. SYSCFG register map and reset values (continued)

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2_CH3 Res. Res. Res. EXTI11 7
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2_CH2 Res. Res. Res. EXTI10 6
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2_CH1 Res. Res. Res. EXTI9 5
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA1_CH7 Res. Res. Res. EXTI8 4
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. TIM1_BRK Res. DMA1_CH6 Res. Res. Res. EXTI7 3

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. TIM1_UPD Res. DMA1_CH5 Res. Res. USB EXTI6 2

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. TIM4 Res. TIM1_TRG Res. DMA1_CH4 DMA1_CH3 Res. Res. EXTI5 1

0
0
0
0
0
0
0
0
0
0
0
0
0
0

TIM17 TIM16 TIM15 TIM14 TIM7 TIM6 TIM3 TIM1_CC TIM1_CCU ADC DMAMUX DMA1_CH2 DMA1_CH1 Res. EXTI4 0
RM0454
 0xF4
0xF0

0xFF
0xE8
0xE4
0xE0

0xEC
0xDC

0xF8 -
Offset
RM0454

Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SYSCFG_ITLINE29
SYSCFG_ITLINE28
SYSCFG_ITLINE27
SYSCFG_ITLINE26
SYSCFG_ITLINE25
SYSCFG_ITLINE24
SYSCFG_ITLINE23

Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.
Res. Res. Res. Res. Res. Res. Res. 8
Table 31. SYSCFG register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. 7

Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. 5
0

USART6 Res. Res. Res. Res. Res. Res. 4

0

USART5 Res. Res. Res. Res. Res. Res. 3

Res. Res. Res. Res. Res. Res. Res. 2
0
0
0

USART4 Res. Res. SPI3 Res. I2C3 Res. 1

0
0
0
0
0
0
0

USART3 USART2 USART1 SPI2 SPI1 I2C2 I2C1 0

207/989
System configuration controller (SYSCFG)

207
Interconnect matrix RM0454

8 Interconnect matrix

8.1 Introduction
Several peripherals have direct connections between them.
This allows autonomous communication and/or synchronization between peripherals,
saving CPU resources thus power consumption.
In addition, these hardware connections remove software latency and allow design of
predictable systems.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep, Stop 0, and Stop 1 modes.
For availability of peripherals on different STM32G0x0 products, refer to Section 1.4:
Availability of peripherals.

8.2 Connection summary

Table 32. Interconnect matrix(1)(2)
Destination

DMAMUX
Source
TIM14

TIM15

TIM16

TIM17

IRTIM
TIM1

TIM3

TIM4

ADC

TIM1 - 8.3.1 8.3.1 - - - - 8.3.2 - -

TIM3 8.3.1 - - - 8.3.1 - - 8.3.2 - -

TIM4 8.3.1 - - - 8.3.1 - - 8.3.2 - -

TIM14 - 8.3.1 8.3.1 - - - - - 8.3.8 -

TIM15 8.3.1 8.3.1 8.3.1 - - - - 8.3.2 - -

TIM16 - - - - 8.3.1 - - - - 8.3.7

TIM17 8.3.1 - - - 8.3.1 - - - - 8.3.7

TIM6 - - - - - - - 8.3.2 - -

USART1 - - - - - - - - - 8.3.7

USART4 - - - - - - - - - 8.3.7

ADC 8.3.3 - - - - - - - - -

T. sensor - - - - - - - 8.3.5 - -

VBAT - - - - - - - 8.3.5 - -

VREFINT - - - - - - 8.3.5 - -

HSE - - - 8.3.4 - - 8.3.4 - - -

LSE - - - - - 8.3.4 - - - -

LSI - - - - - 8.3.4 - - - -

208/989 RM0454 Rev 5

RM0454 Interconnect matrix

Table 32. Interconnect matrix(1)(2) (continued)

Destination

DMAMUX
Source

TIM14

TIM15

TIM16

TIM17

IRTIM
TIM1

TIM3

TIM4

ADC
MCO - - - 8.3.4 - - 8.3.4 - - -

MCO2 - - - 8.3.4 - - 8.3.4 - - -

EXTI - - - - - - - 8.3.2 - -

RTC and
- - - 8.3.4 - 8.3.4 - - - -
TAMP
SYST ERR 8.3.6 8.3.6 8.3.6 - 8.3.6 8.3.6 8.3.6 - - -

1. Numbers in the table are links to corresponding sub-sections in Section 8.3: Interconnection details.
2. The “-” symbol in grayed cells means “no interconnection”.

8.3 Interconnection details

8.3.1 From TIM1, TIM3, TIM4, TIM15, TIM16, and TIM17,

to TIM1, TIM3, TIM4, and TIM15
Purpose
Some of the TIMx timers are linked together internally for timer synchronization or chaining.
When one timer is configured in master mode, it can reset, start, stop or clock the counter of
another timer configured in slave mode.
A description of the feature is provided in: Section 16.3.19: Timer synchronization.
The modes of synchronization are detailed in:
• Section 15.3.26: Timer synchronization for advanced-control timer TIM1
• Section 16.3.18: Timers and external trigger synchronization for general-purpose timer
TIM3/TIM4
• Section 19.4.19: External trigger synchronization (TIM15 only) for general-purpose
timer TIM15

Triggering signals
The output (from master) is on signal TIMx_TRGO (and TIMx_TRGOx), following a
configurable timer event.
With TIM14, TIM16, and TIM17 timers that do not have a trigger output, the output
compare 1 is used instead.
The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in Figure 55: Advanced-control timer block
diagram.

RM0454 Rev 5 209/989

212
Interconnect matrix RM0454

The possible master/slave connections are given in Table 69: TIM1 internal trigger
connection.

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.2 From TIM1, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC
Purpose
The general-purpose timers TIM3, TIM4, and TIM15, basic timer TIM6, advanced-control
timer TIM1, and EXTI can be used to generate an ADC triggering event.
TIMx synchronization is described in: Section 15.3.27: ADC synchronization.
ADC synchronization is described in: Section 14.4: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN).

Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].

The connection between timers and ADC is provided in Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.3 From ADC to TIM1

Purpose
ADC can provide trigger event through watchdog signals to the advanced-control timer
TIM1.
A description of the ADC analog watchdog setting is provided in: Section 14.7: Analog
window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR).
Trigger settings on the timer are provided in: Section 15.3.4: External trigger input.

Triggering signals
The output (from ADC) is on signals ADCn_AWDx_OUT n = 1 (for ADC) x = 1, 2, 3 (three
watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Relevant power modes

This interconnection operates in Run, Sleep, Low-power run, and Low-power sleep power
modes.

210/989 RM0454 Rev 5

RM0454 Interconnect matrix

8.3.4
From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM14,
TIM16, and TIM17
Purpose
External clocks (HSE, LSE), internal clock (LSI), microcontroller output clock (MCO and
MCO2), RTC clock, RTC wakeup interrupt, and GPIO can be selected as inputs to capture
channel 1 of some of TIM14/16/TIM17 timers.
The timers allow calibrating or precisely measuring internal clocks such as HSI16 or LSI,
using accurate clocks such as LSE or HSE/32 for timing reference. See details in
Section 5.2.15: Internal/external clock measurement with TIM14/TIM16/TIM17.
When low-speed external (LSE) oscillator is used, no additional hardware connections are
required.

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.5

From internal analog sources to ADC

Purpose
Internal temperature sensor output voltage VTS, internal reference voltage VREFINT and
VBAT monitoring channel are connected to ADC input channels.
More information is in:
• Section 14.2: ADC main features
• Section 14.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• Figure 14.9: Temperature sensor and internal reference voltage
• Figure 14.10: Battery voltage monitoring

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.6 From system errors to TIM1, TIM3, TIM4, TIM15, TIM16,

and TIM17
Purpose
CSS, CPU hardfault, RAM parity error and FLASH ECC double error detection can generate
system errors in the form of timer break toward TIM1, TIM3, TIM4, TIM15, TIM16, and
TIM17.
The purpose of the break function is to protect power switches driven by PWM signals from
the timers.

RM0454 Rev 5 211/989

212
Interconnect matrix RM0454

List of possible source of break are described in:

• Section 15.3.16: Using the break function (TIM1)
• Section 19.4.13: Using the break function (TIM15/TIM16/TIM17)
• Figure 190: TIM15 block diagram
• Figure 191: TIM16/TIM17 block diagram

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.7 From TIM16, TIM17, USART1, and USART4, to IRTIM

Purpose
TIMx_OC1 output channel of TIM17 timers, associated with USART1 or USART4
transmission signal, can generate the infrared output waveform.
The functionality is described in Section 20: Infrared interface (IRTIM).

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

8.3.8 From TIM14 to DMAMUX

Purpose
TIM14 general-purpose timer and EXTI can be used as triggering event to DMAMUX.

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.

212/989 RM0454 Rev 5

RM0454 Direct memory access controller (DMA)

9 Direct memory access controller (DMA)

9.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
Refer to Section 9.3 for information on DMA implementation.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The DMA includes an arbiter for handling the priority between DMA requests.

9.2 DMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.

RM0454 Rev 5 213/989

233
Direct memory access controller (DMA) RM0454

9.3 DMA implementation

9.3.1 DMA
The devices incorporate one or two DMA controller instances. The following implementation
table shows the number of DMA channels for either instance. A dash indicates that the
instance is not implemented.

Table 33. DMA implementation

STM32G050xx
Number of channels STM32G030xx STM32G0B0xx
STM32G070xx

DMA1 5 7 7
DMA2 - - 5

9.3.2 DMA request mapping

The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 10.3: DMAMUX
implementation.

9.4 DMA functional description

9.4.1 DMA block diagram

214/989 RM0454 Rev 5

RM0454 Direct memory access controller (DMA)

The DMA block diagram is shown in the figure below.

Figure 18. DMA block diagram

DMA

Ch 1

32-bit AHB bus

Ch 2
AHB master interface

...
Ch 7

dma_req [1..7] Arbiter

dma_ack [1..7]

32-bit AHB bus

Interrupt AHB slave interface
interface

dma_it[1..7]
MSv48187V1

The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.

9.4.2 DMA pins and internal signals

Table 34. DMA internal input/output signals

Signal name Signal type Description

dma_req[x] Input DMA channel x request

dma_ack[x] Output DMA channel x acknowledge
dma_it[x] Output DMA channel x interrupt

9.4.3 DMA transfers

The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.

RM0454 Rev 5 215/989

233
Direct memory access controller (DMA) RM0454

A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
• post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

9.4.4 DMA arbitration

The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.

216/989 RM0454 Rev 5

RM0454 Direct memory access controller (DMA)

The priorities are managed in two stages:

• software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

9.4.5 DMA channels

Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.

Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

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Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2. Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the circular mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
5. Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
The three following use cases may happen:
• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
– The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx

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register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.

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Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

9.4.6 DMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in the table below.

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Table 35. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CMARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CMARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 4
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).

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Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

9.4.7 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.

9.5 DMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.

Table 36. DMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

9.6 DMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).

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9.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 23 TEIF6: transfer error (TE) flag for channel 6
0: no TE event
1: a TE event occurred
Bit 22 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred
Bit 21 TCIF6: transfer complete (TC) flag for channel 6
0: no TC event
1: a TC event occurred
Bit 20 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred
Bit 18 HTIF5: half transfer (HT) flag for channel 5
0: no HT event
1: a HT event occurred

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Bit 17 TCIF5: transfer complete (TC) flag for channel 5

0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 12 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 10 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 9 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred
Bit 8 GIF3: global interrupt flag for channel 3
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred
Bit 6 HTIF2: half transfer (HT) flag for channel 2
0: no HT event
1: a HT event occurred
Bit 5 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 4 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 3 TEIF1: transfer error (TE) flag for channel 1
0: no TE event
1: a TE event occurred

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Bit 2 HTIF1: half transfer (HT) flag for channel 1

0: no HT event
1: a HT event occurred
Bit 1 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 0 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

9.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7

CTCIF6

CTCIF5
CHTIF7

CHTIF6

CHTIF5
CTEIF7

CTEIF6

CTEIF5
CGIF7

CGIF6

CGIF5
Res. Res. Res. Res.

w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHTIF4

CTCIF4

CHTIF3

CTCIF3

CHTIF2

CTCIF2

CHTIF1

CTCIF1
CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF4

CGIF3

CGIF2

CGIF1
w w w w w w w w w w w w w w w w

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7
Bit 23 CTEIF6: transfer error flag clear for channel 6
Bit 22 CHTIF6: half transfer flag clear for channel 6
Bit 21 CTCIF6: transfer complete flag clear for channel 6
Bit 20 CGIF6: global interrupt flag clear for channel 6
Bit 19 CTEIF5: transfer error flag clear for channel 5
Bit 18 CHTIF5: half transfer flag clear for channel 5

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Bit 17 CTCIF5: transfer complete flag clear for channel 5

Bit 16 CGIF5: global interrupt flag clear for channel 5
Bit 15 CTEIF4: transfer error flag clear for channel 4
Bit 14 CHTIF4: half transfer flag clear for channel 4
Bit 13 CTCIF4: transfer complete flag clear for channel 4
Bit 12 CGIF4: global interrupt flag clear for channel 4
Bit 11 CTEIF3: transfer error flag clear for channel 3
Bit 10 CHTIF3: half transfer flag clear for channel 3
Bit 9 CTCIF3: transfer complete flag clear for channel 3
Bit 8 CGIF3: global interrupt flag clear for channel 3
Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1

9.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2
Res. PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Bit 7 MINC: memory increment mode

Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: circular mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 4 DIR: data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: read from memory
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: transfer error interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

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RM0454 Direct memory access controller (DMA)

Bit 2 HTIE: half transfer interrupt enable

0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: disabled
1: enabled
Note: this bit is set and cleared by software.

9.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: number of data to transfer (0 to 216 - 1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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9.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PA[31:0]: peripheral address

It contains the base address of the peripheral data register from/to which the data will be
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

9.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data will be read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

9.6.7 DMA register map

The table below gives the DMA register map and reset values.

Table 37. DMA register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF7
TCIF7

HTIF6
TCIF6

HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1
TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1
Res.
Res.
Res.
Res.

DMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHTIF7
CTCIF7

CHTIF6
CTCIF6

CHTIF5
CTCIF5

CHTIF4
CTCIF4

CHTIF3
CTCIF3

CHTIF2
CTCIF2

CHTIF1
CTCIF1
CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
Res.
Res.
Res.
Res.

DMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR1
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR1 NDTR[15:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR1 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR2
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR2 NDTR[15:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR2 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved Reserved.

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Table 37. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR3
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR3 NDTR[15:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR3 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR4
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR4 NDTR[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR4 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR5
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR5 NDTR[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR5 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x068 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR6
0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR6 NDTR[15:0]
0x070
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR6 PA[31:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR6 MA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x07C Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR7
0x080

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0454 Direct memory access controller (DMA)

Table 37. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR7 NDTR[15:0]
0x084
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR7 PA[31:0]
0x088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR7 MA[31:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 for the register boundary addresses.

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10 DMA request multiplexer (DMAMUX)

10.1 Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until it is served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 10.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend on the product
implementation, and are detailed inSection 10.3.2.

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10.2 DMAMUX main features

• up to 12-channel programmable DMA request line multiplexer output
• 4-channel DMA request generator
• 21 trigger inputs to DMA request generator
• 21 synchronization inputs
• Per DMA request generator channel:
– DMA request trigger input selector
– DMA request counter
– Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
– up to 55 input DMA request lines from peripherals
– One DMA request line output
– Synchronization input selector
– DMA request counter
– Event overrun flag for selected synchronization input
– One event output, for DMA request chaining

10.3 DMAMUX implementation

10.3.1 DMAMUX instantiation

DMAMUX is instantiated with the hardware configuration parameters listed in the following
table.

Table 38. DMAMUX instantiation

Feature DMAMUX

Number of DMAMUX output request channels 12/7/5(1)

Number of DMAMUX request generator channels 4
Number of DMAMUX request trigger inputs 23
Number of DMAMUX synchronization inputs 23
Number of DMAMUX peripheral request inputs up to 55(2)
1. 12 for STM32G0B0xx, seven for STM32G070xx as well as for STM32G050xx, and five for STM32G030xx
devices.
2. Depending on peripherals available on the device.

10.3.2 DMAMUX mapping

The mapping of resources to DMAMUX is hardwired.

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249
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Table 39. DMAMUX: assignment of multiplexer inputs to resources

DMA DMA DMA
request request request
Resource Resource Resource
MUX MUX MUX
input input input

1 dmamux_req_gen0 27 Reserved 53 USART2_TX

2 dmamux_req_gen1 28 Reserved 54 USART3_RX
3 dmamux_req_gen2 29 Reserved 55 USART3_TX
4 dmamux_req_gen3 30 Reserved 56 USART4_RX
5 ADC 31 Reserved 57 USART4_TX
6 Reserved 32 TIM3_CH1 58 Reserved
7 Reserved 33 TIM3_CH2 59 Reserved
8 Reserved 34 TIM3_CH3 60 Reserved
9 Reserved 35 TIM3_CH4 61 Reserved
10 I2C1_RX 36 TIM3_TRIG 62 I2C3_RX
11 I2C1_TX 37 TIM3_UP 63 I2C3_TX
12 I2C2_RX 38 TIM6_UP 64 Reserved
13 I2C2_TX 39 TIM7_UP 65 Reserved
14 Reserved 40 TIM15_CH1 66 SPI3_RX
15 Reserved 41 TIM15_CH2 67 SPI3_TX
16 SPI1_RX 42 TIM15_TRIG_COM 68 TIM4_CH1
17 SPI1_TX 43 TIM15_UP 69 TIM4_CH2
18 SPI2_RX 44 TIM16_CH1 70 TIM4_CH3
19 SPI2_TX 45 TIM16_COM 71 TIM4_CH4
20 TIM1_CH1 46 TIM16_UP 72 TIM4_TRIG
21 TIM1_CH2 47 TIM17_CH1 73 TIM4_UP
22 TIM1_CH3 48 TIM17_COM 74 USART5_RX
23 TIM1_CH4 49 TIM17_UP 75 USART5_TX
24 TIM1_TRIG_COM 50 USART1_RX 76 USART6_RX
25 TIM1_UP 51 USART1_TX 77 USART6_TX
26 Reserved 52 USART2_RX - -

Table 40. DMAMUX: assignment of trigger inputs to resources

Trigger input Resource Trigger input Resource

0 EXTI LINE0 12 EXTI LINE12

1 EXTI LINE1 13 EXTI LINE13
2 EXTI LINE2 14 EXTI LINE14
3 EXTI LINE3 15 EXTI LINE15
4 EXTI LINE4 16 dmamux_evt0
5 EXTI LINE5 17 dmamux_evt1

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RM0454 DMA request multiplexer (DMAMUX)

Table 40. DMAMUX: assignment of trigger inputs to resources (continued)

Trigger input Resource Trigger input Resource

6 EXTI LINE6 18 dmamux_evt2

7 EXTI LINE7 19 dmamux_evt3
8 EXTI LINE8 20 Reserved
9 EXTI LINE9 21 Reserved
10 EXTI LINE10 22 TIM14_OC
11 EXTI LINE11 23 Reserved

Table 41. DMAMUX: assignment of synchronization inputs to resources

Sync. input Resource Sync. input Resource

0 EXTI LINE0 12 EXTI LINE12

1 EXTI LINE1 13 EXTI LINE13
2 EXTI LINE2 14 EXTI LINE14
3 EXTI LINE3 15 EXTI LINE15
4 EXTI LINE4 16 dmamux_evt0
5 EXTI LINE5 17 dmamux_evt1
6 EXTI LINE6 18 dmamux_evt2
7 EXTI LINE7 19 dmamux_evt3
8 EXTI LINE8 20 Reserved
9 EXTI LINE9 21 Reserved
10 EXTI LINE10 22 TIM14_OC
11 EXTI LINE11 23 Reserved

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10.4 DMAMUX functional description

10.4.1 DMAMUX block diagram

Figure 19 shows the DMAMUX block diagram.

Figure 19. DMAMUX block diagram

32-bit AHB bus
dmamux_hclk

DMAMUX Request multiplexer

AHB slave
interface Channel m
DMAMUX_CmCR

p Channel 1
Channel 0

x
DMA requests eq
_r
DMAMUX_C0CR
from peripherals: 1
ux
am

dmamux_req_inx Channel Ctrl

0
dm

select
n+p+2 m DMA requests
1 to DMA controllers:
0
Request generator dmamux_req_outx
n+3
Channel n n
Sync
dmamux_req_genx

DMAMUX_RGCnCR n+2 m
DMA channels
1 events:
n+1 0
dmamux_evtx
s 1 0
Channel 1 1 2
DMAMUX_RGC1CR
1
Channel 0 0
DMAMUX_RGC0CR

Interrupt
interface
t 1 0 s 1 0

Control registers Trigger inputs: Interrupt: Synchronization inputs:

dmamux_trgx dmamux_ovr_it dmamux_syncx
MSv39745V1

DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
• DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
• Internal or external signals to DMA request trigger inputs (dmamux_trgx)
• Internal or external signals to synchronization inputs (dmamux_syncx)

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RM0454 DMA request multiplexer (DMAMUX)

10.4.2 DMAMUX signals

Table 42 lists the DMAMUX signals.

Table 42. DMAMUX signals

Signal name Description

dmamux_hclk DMAMUX AHB clock

dmamux_req_inx DMAMUX DMA request line inputs from peripherals
dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block)
dmamux_req_genx DMAMUX request generator sub-block channels outputs
DMAMUX request multiplexer sub-block inputs (from peripheral
dmamux_reqx
requests and request generator channels)
dmamux_syncx DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx DMAMUX requests outputs (to DMA controllers)
dmamux_evtx DMAMUX events outputs
dmamux_ovr_it DMAMUX overrun interrupts

10.4.3 DMAMUX channels

A DMAMUX channel is a DMAMUX request multiplexer channel that may include,
depending on the selected input of the request multiplexer, an additional DMAMUX request
generator channel.
A DMAMUX request multiplexer channel is connected and dedicated to one single channel
of DMA controller(s).

Channel configuration procedure

Follow the sequence below to configure both a DMAMUX x channel and the related DMA
channel y:
1. Set and configure completely the DMA channel y, except enabling the channel y.
2. Set and configure completely the related DMAMUX y channel.
3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

10.4.4 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.
A DMA request is sourced either from the peripherals or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.
Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected.

RM0454 Rev 5 239/989

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DMA request multiplexer (DMAMUX) RM0454

Caution: A same non-null DMAREQ_ID can be assigned to two different channels only if the
application ensures that these channels are not requested to be served at the same time. In
other words, if two different channels receive a same asserted hardware request at the
same time, an unpredictable DMA hardware behavior occurs.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once is detected a programmable
rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, there is a programmable DMA request counter, internally to the DMAMUX
request multiplexer, which may be used for the channel request output generation and also
possibly for an event generation. An event generation on the channel x output is enabled
through the EGE bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 21, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note: If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in NBREQ
field of the DMAMUX_CxCR register and the input DMA request line is disconnected from
the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in NBREQ field, plus one.
Note: The NBREQ field value shall only be written by software when both synchronization enable
bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are
disabled.

240/989 RM0454 Rev 5

RM0454 DMA request multiplexer (DMAMUX)

Figure 20. Synchronization mode of the DMAMUX request line multiplexer channel

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Selected
dmamux_reqx
Not pending

dmamux_syncx

dmamux_req_outx

DMA request counter 4 3 2 1 0 4

dmamux_evtx

DMA request counter underrun

Synchronization event
DMA request counter auto-reload to NBREQ
Input DMA request line connected to output
Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Figure 21. Event generation of the DMA request line multiplexer channel

Selected DMA request line transferred to the output

DMA request pending

Selected
dmamux_reqx Not pending

dmamux_req_outx

DMA request counter 3 2 1 0 3 2 1 0 3 2 1 0

SE

EGE

dmamux_evtx

DMA request counter reaches zero

Event is generated on the output
DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 20 and Figure 21.

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DMA request multiplexer (DMAMUX) RM0454

Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note: A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.
Note: The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA
controller. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

10.4.5 DMAMUX request generator

The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

242/989 RM0454 Rev 5

RM0454 DMA request multiplexer (DMAMUX)

Note: The GNBREQ field value must be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the status
DMAMUX_RGSR register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the
completion of the usage of the related channel of the DMA controller. Else, upon a new
detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that
is, no served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

10.5 DMAMUX interrupts

An interrupt can be generated upon:
• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel
For each case, per-channel individual interrupt enable, status and clear flag register bits are
available.

Table 43. DMAMUX interrupts

Interrupt signal Interrupt event Event flag Clear bit Enable bit

Synchronization event overrun

on channel x of the SOFx CSOFx SOIE
DMAMUX request line multiplexer
dmamuxovr_it
Trigger event overrun
on channel x of the OFx COFx OIE
DMAMUX request generator

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10.6 DMAMUX registers

Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word.
The address must be aligned with the data size.

10.6.1 DMAMUX request line multiplexer channel x configuration register

(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 11)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SYNC_ID[4:0] NBREQ[4:0] SPOL[1:0] SE
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EGE SOIE Res. DMAREQ_ID[6:0]
rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see Table 41: DMAMUX: assignment of synchronization
inputs to resources).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event, i.e. no synchronization nor detection.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: synchronization disabled
1: synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: event generation disabled
1: event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: interrupt disabled
1: interrupt enabled

244/989 RM0454 Rev 5

RM0454 DMA request multiplexer (DMAMUX)

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.

10.6.2 DMAMUX request line multiplexer interrupt channel status register

(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 SOF[11:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.

10.6.3 DMAMUX request line multiplexer interrupt clear flag register

(DMAMUX_CFR)
Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF
Res. Res. Res. Res.
11 10 9 8 7 6 5 4 3 2 1 0
w w w w w w w w w w w w

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 CSOF[11:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.

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DMA request multiplexer (DMAMUX) RM0454

10.6.4 DMAMUX request generator channel x configuration register

(DMAMUX_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. SIG_ID[4:0]
rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field must be written only when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: No event, i.e. no trigger detection nor generation.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: Interrupt on a trigger overrun event occurrence is disabled
1: Interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator

246/989 RM0454 Rev 5

RM0454 DMA request multiplexer (DMAMUX)

10.6.5 DMAMUX request generator interrupt status register

(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OF3 OF2 OF1 OF0
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.

10.6.6 DMAMUX request generator interrupt clear flag register

(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COF3 COF2 COF1 COF0
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.

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DMA request multiplexer (DMAMUX) RM0454

10.6.7 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.

Table 44. DMAMUX register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C0CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C1CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C2CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C3CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C4CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C5CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C6CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C7CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x01C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C8CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C9CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C10CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C11CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x030-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SOF11 Res.
SOF10 Res.
SOF9 Res.
SOF8 Res.
SOF7 Res.
SOF6 Res.
SOF5 Res.
SOF4 Res.
SOF3 Res.
SOF2 Res.
SOF1 Res.
SOF0 Res.

Reserved
0x07C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMAMUX_CSR
0x080
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
CSOF10
CSOF11

CSOF9
CSOF8
CSOF7
CSOF6
CSOF5
CSOF4
CSOF3
CSOF2
CSOF1
CSOF0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMAMUX_CFR
0x084

Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x088 -
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Res.
Res.
Res.
GPOL Res.
[1:0] Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
OIE Res.
Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x0FC
GE

DMAMUX_RG0CR GNBREQ[4:0] SIG_ID[4:0]

0x100
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

248/989 RM0454 Rev 5

 0x144
0x140
0x108
0x104

0x13C
0x10C

0x3FC
0x110 -
Offset

0x148 -
RM0454

Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value

DMAMUX_RGSR
DMAMUX_RG3CR
DMAMUX_RG2CR
DMAMUX_RG1CR

DMAMUX_RGCFR
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
0
0
0

Res. Res. Res. Res. 23

0
0
0

Res. Res. Res. Res. 22

0
0
0

Res. Res. Res. Res. 21

0
0
0

Res. Res. Res. Res. 20

GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]

0
0
0

Res. Res. Res. Res. 19

0
0
0

Res. Res. Res. Res. GPOL GPOL GPOL 18

RM0454 Rev 5
[1:0] [1:0] [1:0]
0
0
0

Res. Res. Res. Res. 17

0
0
0

Res. Res. Res. Res. GE GE GE 16

Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res.
Table 44. DMAMUX register map and reset values

10
Res. Res. Res. Res. Res. Res. Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.
0
0
0

Res. Res. Res. Res. OIE OIE OIE 8

Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. 5
0
0
0

Res. Res. Res. Res. 4

0
0
0

0
0

Res. COF3 OF3 Res. 3

0
0
0

0
0

Res. COF2 OF2 Res. 2

0
0
0

0
0

Res. COF1 OF1 Res. 1

SIG_ID[4:0]
SIG_ID[4:0]
SIG_ID[4:0]

0
0
0

0
0

Res. COF0 OF0 Res. 0

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DMA request multiplexer (DMAMUX)

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Nested vectored interrupt controller (NVIC) RM0454

11 Nested vectored interrupt controller (NVIC)

11.1 Main features

• 32 maskable interrupt channels (not including the sixteen Cortex®-M0+ interrupt lines)
• 4 programmable priority levels (2 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the programming manual PM0223.

11.2 SysTick calibration value register

The SysTick calibration value is set to 6500, which gives a reference time base of 1 ms with
the SysTick clock set to 6.5 MHz (max fHCLK/8).

11.3 Interrupt and exception vectors

Table 45 is the vector table. Information pertaining to a peripheral only applies to devices
containing that peripheral.

Table 45. Vector table(1)

Type of
Position Priority Acronym Description Address
priority

- - - - Reserved 0x0000_0000
- -3 fixed Reset Reset 0x0000_0004
Non maskable interrupt. The SRAM
parity err., Flash ECC double err.,
- -2 fixed NMI_Handler 0x0000_0008
HSE CSS and LSE CSS are linked
to the NMI vector.
- -1 fixed HardFault_Handler All class of fault 0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
- - - - Reserved 0x0000_001C
0x0000_0020
0x0000_0024
0x0000_0028
System service call via SWI
- 3 settable SVC_Handler 0x0000_002C
instruction

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Table 45. Vector table(1) (continued)

Type of
Position Priority Acronym Description Address
priority

0x0000_0030
- - - - Reserved
0x0000_0034
- 5 settable PendSV_Handler Pendable request for system service 0x0000_0038
- 6 settable SysTick_Handler System tick timer 0x0000_003C
0 7 settable WWDG Window watchdog interrupt 0x0000_0040
1 - - - Reserved 0x0000_0044
RTC and TAMP interrupts
2 9 settable RTC / TAMP 0x0000_0048
(combined EXTI lines 19 & 21)
3 10 settable FLASH Flash global interrupt 0x0000_004C
4 11 settable RCC RCC global interrupt 0x0000_0050
5 12 settable EXTI0_1 EXTI line 0 & 1 interrupt 0x0000_0054
6 13 settable EXTI2_3 EXTI line 2 & 3 interrupt 0x0000_0058
7 14 settable EXTI4_15 EXTI line 4 to 15 interrupt 0x0000_005C
8 - - - Reserved 0x0000_0060
9 16 settable DMA1_Channel1 DMA1 channel 1 interrupt 0x0000_0064
10 17 settable DMA1_Channel2_3 DMA1 channel 2 & 3 interrupts 0x0000_0068
DMA1_Channel4_5_6
_7 / DMAMUX / DMA1 channel 4, 5, 6, 7, DMAMUX,
11 18 settable 0x0000_006C
DMA2_Channel1_2_3 DMA2 channel 1, 2, 3, 4, 5 interrupts
_4_5
ADC interrupt (ADC combined with
12 19 settable ADC 0x0000_0070
EXTI 17 & 18)
TIM1_BRK_UP_TRG TIM1 break, update, trigger and
13 20 settable 0x0000_0074
_COM commutation interrupts
14 21 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_0078
15 - - - Reserved 0x0000_007C
16 23 settable TIM3+TIM4 TIM3 global interrupt 0x0000_0080
17 24 settable TIM6 TIM6 global interrupt 0x0000_0084
18 25 settable TIM7 TIM7 global interrupt 0x0000_0088
19 26 settable TIM14 TIM14 global interrupt 0x0000_008C
20 27 settable TIM15 TIM15 global interrupt 0x0000_0090
21 28 settable TIM16 TIM16 global interrupt 0x0000_0094
22 29 settable TIM17 TIM17 global interrupt 0x0000_0098
I2C1 global interrupt (combined with
23 30 settable I2C1 0x0000_009C
EXTI 23)
24 31 settable I2C2 / I2C3 I2C2 and I2C3 global interrupt 0x0000_00A0
25 32 settable SPI1 SPI1 global interrupt 0x0000_00A4

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Table 45. Vector table(1) (continued)

Type of
Position Priority Acronym Description Address
priority

26 33 settable SPI2 / SPI3 SPI2 global interrupt 0x0000_00A8

USART1 global interrupt (combined
27 34 settable USART1 0x0000_00AC
with EXTI 25)
USART2 global interrupt (combined
28 35 settable USART2 0x0000_00B0
with EXTI 26)
USART3 / USART4 / USART3/4/5/6 global interrupt
29 36 settable 0x0000_00B4
USART5 / USART6 (combined with EXTI 28)
30 - - - Reserved 0x0000_00B8
31 - - - Reserved 0x0000_00BC
®
1. The grayed cells correspond to the Cortex -M0+ interrupts.

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12 Extended interrupt and event controller (EXTI)

The Extended interrupt and event controller (EXTI) manages the CPU and system wakeup
through configurable and direct event inputs (lines). It provides wakeup requests to the
power control, and generates an interrupt request to the CPU NVIC and events to the CPU
event input. For the CPU an additional event generation block (EVG) is needed to generate
the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI I/O port mux.

12.1 EXTI main features

The EXTI main features are the following:
• System wakeup upon event on any input
• Wakeup flag and CPU interrupt generation for events not having a wakeup flag in their
source peripheral
• Configurable events (from I/Os, peripherals not having an associated interrupt pending
status bit, or peripherals generating a pulse)
– Selectable active trigger edge
– Independent rising and falling edge interrupt pending status bits
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation
– SW trigger possibility
• Direct events (from peripherals having an associated flag and interrupt pending status
bit)
– Fixed rising edge active trigger
– No interrupt pending status bit in the EXTI
– Individual interrupt and event generation mask for conditioning the CPU wakeup
and event generation
– No SW trigger possibility
• I/O port selector

12.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger
block, the masking block, and EXTI mux as shown in Figure 22.
The register block contains all the EXTI registers.
The event input trigger block provides an event input edge trigger logic.
The masking block provides the event input distribution to the different wakeup, interrupt
and event outputs, and the masking of these.
The EXTI mux provides the I/O port selection on to the EXTI event signal.

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Figure 22. EXTI block diagram

AHB interface
Registers
hclk
exti[15:0]
To interconnect

EXTImux
GPIO

IOPort sys_wakeup
c_wakeup PWR
Configurable event(15:0)
it_exti_per(y)*
Direct event(x) or
configurable event(y) Event
Peripherals

Wakeup
c_evt_exti c_event
Trigger events Masking Pulse rxev
c_evt_rst
c_fclk CPU
Interrupt Direct event(x)
EVG

EXTI
* it_exti_per(y) are only available for configurable events (y)
MS44733V2

Table 46. EXTI signal overview

Signal name I/O Description

EXTI register bus interface. When one event is configured to allow

AHB interface I/O
security, the AHB interface support secure accesses
hclk I AHB bus clock and EXTI system clock
Configurable Asynchronous wakeup events from peripherals that do not have an
I
event(y) associated interrupt and flag in the peripheral
Synchronous and asynchronous wakeup events from peripherals having
Direct event(x) I
an associated interrupt and flag in the peripheral
IOPort(n) I GPIO ports[15:0]
exti[15:0] O EXTI output port to trigger other IPs
it_exti_per (y) O Interrupts to the CPU associated with configurable event (y)
c_evt_exti O High-level sensitive event output for CPU synchronous to hclk
c_evt_rst I Asynchronous reset input to clear c_evt_exti
sys_wakeup O Asynchronous system wakeup request to PWR for ck_sys and hclk
c_wakeup O Wakeup request to PWR for CPU, synchronous to hclk

Table 47. EVG pin overview

Pin name I/O Description

c_fclk I CPU free-running clock

c_evt_in I High-level sensitive event input from EXTI, asynchronous to CPU clock
c_event O Event pulse, synchronous to CPU clock
c_evt_rst O Event reset signal, synchronous to CPU clock

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12.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in Stop
mode are connected to the EXTI.
• Peripheral wakeup signals that generate a pulse or that do not have an interrupt status
bits in the peripheral, are connect to an EXTI configurable line. For these events the
EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt
associated with the status bit that interrupts the CPU.
• Peripheral interrupt and wakeup signals that have a status bit in the peripheral which
requires to be cleared in the peripheral, are connected to an EXTI direct line. There is
no status pending bit within the EXTI. The interrupt or wakeup is cleared by the CPU in
the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
• All GPIO ports input to the EXTI multiplexer, allowing to select a port to wake up the
system via a configurable event.
The EXTI configurable event interrupts are connected to the NVIC(a) of the CPU.
The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.
The EXTI CPU wakeup signals are connected to the PWR block, and are used to wake up
the system and CPU sub-system bus clocks.

12.3 EXTI functional description

Depending on the EXTI line type and wakeup target(s), different logic implementations are
used. The applicable features and control or status registers are:
• rising and falling edge event enable through
– EXTI rising trigger selection register (EXTI_RTSR1)
– EXTI falling trigger selection register 1 (EXTI_FTSR1)
• software trigger through EXTI software interrupt event register 1 (EXTI_SWIER1)
• pending interrupt flagging through
– EXTI rising edge pending register 1 (EXTI_RPR1)
– EXTI falling edge pending register 1 (EXTI_FPR1)
– EXTI external interrupt selection register (EXTI_EXTICRx)
• CPU wakeup and interrupt enable through
– EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)
• CPU wakeup and event enable through
– EXTI CPU wakeup with event mask register (EXTI_EMR1)

Table 48. EXTI event input configurations and register control

EXTI_SWIER1

EXTI_R/FPR1
EXTI_RTSR1

EXTI_FTSR1

EXTI_EMR1
EXTI_IMR1

Event input
Logic implementation
type

Configurable Configurable event input wakeup logic x x x x x x

Direct Direct event input wakeup logic - - - - x x

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12.3.1 EXTI configurable event input wakeup

Figure 23 is a detailed representation of the logic associated with configurable event inputs
which wake up the CPU sub-system bus clocks and generated an EXTI pending flag and
interrupt to the CPU and or a CPU wakeup event.

Figure 23. Configurable event trigger logic CPU wakeup

AHB Peripheral interface

interface Falling Rising Software CPU CPU
interrupt Pending
trigger trigger Event Interrupt request
selection selection event mask mask register
hclk register register register register register
it_exti_per(y)
hclk
Same circuit for Configurable
and Direct events EVG
Delay

Configurable Asynchronous Edge Rising Edge

detect Pulse ck_fclk_c
Event input(y) detection circuit hclk
generator
rst (1) c_evt_rst
CPU Event(y) Rising CPU
Rising Edge
c_event
Other CPU Events(x,y) Edge c_evt_exti
detect rst detect Pulse
generator
hclk

Synch
Other CPU Wakeups c_wakeup
CPU Wakeup(y)

Other Wakeups sys_wakeup

Wakeup(y)
EXTI
MS46537V1

The software interrupt event register allows triggering configurable events by software,
writing the corresponding register bit, irrespective of the edge selection setting.
The rising edge and falling edge selection registers allow to enable and select the
configurable event active trigger edge or both edges.
The CPU has its dedicated interrupt mask register and a dedicated event mask registers.
The enabled event allows generating an event on the CPU. All events for a CPU are OR-ed
together into a single CPU event signal. The event pending registers (EXTI_RPR1 and
EXTI_FPR1) is not set for an unmasked CPU event.
The configurable events have unique interrupt pending request registers, shared by the
CPU. The pending register is only set for an unmasked interrupt. Each configurable event
provides a common interrupt to the CPU. The configurable event interrupts need to be
acknowledged by software in the EXTI_RPR1 and/or EXTI_FPR1 registers.
When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is
reset by the clocked delay and rising edge detect pulse generator. This guarantees the
wakeup of the EXTI hclk clock before the asynchronous edge detection circuit is reset.
Note: A detected configurable event interrupt pending request can be cleared by the CPU. The
system cannot enter low-power modes as long as an interrupt pending request is active.

12.3.2 EXTI direct event input wakeup

Figure 24 is a detailed representation of the logic associated with direct event inputs waking
up the system.
The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the
system and CPU sub-system clocks and may generate a CPU wakeup event. The
peripheral synchronous interrupt, associated with the direct wakeup event wakes up the
CPU.

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The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU.
The CPU event may occur before the interrupt flag of the associated peripheral is set.

Figure 24. Direct event trigger logic CPU wakeup

AHB interface Peripheral interface

hclk CPU CPU
Interrupt Event
Same circuit for Configurable
hclk
mask mask and Direct events EVG
register register ck_fclk_c
hclk
(1) Rising
c_evt_rst
CPU
Delay

CPU Event(x) c_event

Edge Rising Edge
Other CPU Events(x,y) detect c_evt_exti detect Pulse
rst
Direct generator
Event
Asynchronous
input(x) hclk
Rising Edge
detect circuit

Synch
rst CPU Wakeup(x) c_wakeup

Other CPU Wakeups

Falling Edge
detect sys_wakeup
Pulse Other Wakeups
generator Wakeup(x)

EXTI hclk

MS46536V1

12.3.3 EXTI mux

The EXTI mux allows selecting GPIOs as interrupts and wakeup. The GPIOs are connected
via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The selection of
GPIO port as EXTI mux output is controlled through the EXTI external interrupt selection
register (EXTI_EXTICRx) register.

Figure 25. EXTI GPIO mux

EXTI_EXTICR1.EXTI0 EXTI_EXTICR1.EXTI1 EXTI_EXTICR4.EXTI15

PA0 PA1 PA15

PB0 PB1 PB15

PC0 PC1 PC15

EXTI0 EXTI1 EXTI15

Px0 Px1 Px15

MS44726V1

The EXTIs mux outputs are available as output signals from the EXTI, to trigger other
functional blocks. The EXTI mux outputs are available independently of mask setting
through the EXTI_IMR and EXTI_EMR registers.
The EXTI lines (event inputs) are connected as shown in the following table.

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Table 49. EXTI line connections

EXTI line Line source Line type

0-15 GPIO Configurable

16 Reserved -
17 Reserved -
18 Reserved -
19 RTC Direct
20 Reserved -
21 TAMP Direct
22 I2C2 wakeup Direct
23 I2C1 wakeup Direct
24 USART3 wakeup Direct
25 USART1 wakeup Direct
26 USART2 wakeup Direct
27 Reserved -
28 Reserved -
29 Reserved -
30 Reserved -
31 LSE_CSS Direct
32 Reserved -
33 Reserved -

12.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup
event. The configurable events are enabled by enabling at least one of the trigger edges.
Once an event input is enabled, the generation of a CPU wakeup is conditioned by the CPU
interrupt mask and CPU event mask.

Table 50. Masking functionality

Configurable
CPU interrupt
CPU event enable event inputs exti(n) CPU
enable CPU wakeup
EXTI_EMR.EMn EXTI_RPR.RPIFn interrupt(1) event
EXTI_IMR.IMn
EXTI_FPR.FPIFn

0 No Masked Masked Masked

0
1 No Masked Yes Yes
0 Status latched Yes Masked Yes(2)
1
1 Status latched Yes Yes Yes
1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU, the exti(n) interrupt must be masked in the
CPU NVIC.

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2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, upon an edge on the event input, an event request is
generated if that edge (rising or/and falling) is enabled. When the associated CPU interrupt
is unmasked, the corresponding RPIFn and/or FPIFn bit is/are set in the EXTI_RPR or/and
EXTI_FPR register, waking up the CPU subsystem and activating CPU interrupt signal. The
RPIFn and/or FPIFn pending bit is cleared by writing 1 to it, which clears the CPU interrupt
request.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.
When the associated CPU interrupt is unmasked, the corresponding CPU subsystem is
woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.
The CPU event must be unmasked to generate an event. Upon an enabled edge occurring
on an event input, a CPU event pulse is generated. There is no event pending bit.
For the configurable event inputs, the software can generate an event request by setting the
corresponding bit of the software interrupt/event register EXTI_SWIER1, which has the
effect of a rising edge on the event input. The pending rising edge event flag is set in the
EXTI_RPR1 register, irrespective of the EXTI_RTSR1 register setting.

12.5 EXTI registers

The EXTI register map is divided in the following sections:

Table 51. EXTI register map sections

Address Description

0x000 - 0x01C General configurable event [31:0] configuration

0x060 - 0x06C EXTI I/O port multiplexer
0x080 - 0x0BC CPU input event configuration

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.

12.5.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RTx: Rising trigger event configuration bit of configurable line x (x = 15 to 0)(1)
Each bit enables/disables the rising edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.

12.5.2 EXTI falling trigger selection register 1 (EXTI_FTSR1)

Address offset: 0x004
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 FTx: Falling trigger event configuration bit of configurable line x (x = 15 to 0)(1).
Each bit enables/disables the falling edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.

12.5.3 EXTI software interrupt event register 1 (EXTI_SWIER1)

Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI SWI SWI SWI SWI SWI
SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0
15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SWIx: Software rising edge event trigger on line x (x = 15 to 0)
Setting of any bit by software triggers a rising edge event on the corresponding line x,
resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits
are automatically cleared by HW. Reading of any bit always returns 0.
0: No effect
1: Rising edge event generated on the corresponding line, followed by an interrupt

12.5.4 EXTI rising edge pending register 1 (EXTI_RPR1)

Address offset: 0x00C
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RPIF15 RPIF14 RPIF13 RPIF12 RPIF11 RPIF10 RPIF9 RPIF8 RPIF7 RPIF6 RPIF5 RPIF4 RPIF3 RPIF2 RPIF1 RPIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RPIFx: Rising edge event pending for configurable line x (x = 15 to 0)
Each bit is set upon a rising edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred

12.5.5 EXTI falling edge pending register 1 (EXTI_FPR1)

Address offset: 0x010
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FPIF15 FPIF14 FPIF13 FPIF12 FPIF11 FPIF10 FPIF9 FPIF8 FPIF7 FPIF6 FPIF5 FPIF4 FPIF3 FPIF2 FPIF1 FPIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 FPIFx: Falling edge event pending for configurable line x (x = 15 to 0)
Each bit is set upon a falling edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred

12.5.6 EXTI external interrupt selection register (EXTI_EXTICRx)

Address offset: 0x060 + 0x4 * (x - 1), (x = 1 to 4)
Reset value: 0x0000 0000
EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXTIm+3[7:0] EXTIm+2[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTIm+1[7:0] EXTIm[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 EXTIm+3[7:0]: EXTIm+3 GPIO port selection (m = 4 * (x - 1))

These bits are written by software to select the source input for EXTIm+3 external interrupt.
0x00: PA[m+3] pin
0x01: PB[m+3] pin
0x02: PC[m+3] pin
0x03: PD[m+3] pin
0x04: reserved
0x05: PF[m+3] pin
Others reserved
Bits 23:16 EXTIm+2[7:0]: EXTIm+2 GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm+2 external interrupt.
0x00: PA[m+2] pin
0x01: PB[m+2] pin
0x02: PC[m+2] pin
0x03: PD[m+2] pin
0x04: reserved
0x05: PF[m+2] pin
Others reserved
Bits 15:8 EXTIm+1[7:0]: EXTIm+1 GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm+1 external interrupt.
0x00: PA[m+1] pin
0x01: PB[m+1] pin
0x02: PC[m+1] pin
0x03: PD[m+1] pin
0x04: reserved
0x05: PF[m+1] pin
Others reserved

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Bits 7:0 EXTIm[7:0]: EXTIm GPIO port selection (m = 4 * (x - 1))

These bits are written by software to select the source input for EXTIm external interrupt.
0x00: PA[m] pin
0x01: PB[m] pin
0x02: PC[m] pin
0x03: PD[m] pin
0x04: reserved
0x05: PF[m] pin
Others reserved

12.5.7 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080 (EXTI_IMR1)
Reset value: 0xFFF8 0000
Contains register bits for configurable events and direct events.
The reset value is set such as to, by default, enable interrupt from direct lines, and disable
interrupt from configurable lines.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IM31 Res. Res. Res. Res. IM26 IM25 IM24 IM23 IM22 IM21 Res. IM19 Res. Res. Res.

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 IM31: CPU wakeup with interrupt mask on line 31

Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the
corresponding line.
0: wakeup with interrupt masked
1: wakeup with interrupt unmasked
Bits 30:27 Reserved, must be kept at reset value.
Bits 26:21 IMx: CPU wakeup with interrupt mask on line x (x = 26 to 21)
Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the
corresponding line.
0: wakeup with interrupt masked
1: wakeup with interrupt unmasked
The IM24 and IM22 bits are only available in STM32G0B0xx. They are reserved in
STM32G030xx as well as STM32G050xx as well as STM32G070xx.
Bit 20 Reserved, must be kept at reset value.

RM0454 Rev 5 263/989

266
Extended interrupt and event controller (EXTI) RM0454

Bit 19 IM19: CPU wakeup with interrupt mask on line 19

Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the
corresponding line.
0: wakeup with interrupt masked
1: wakeup with interrupt unmasked
Bits 18:16 Reserved, must be kept at reset value.
Bits 15:0 IMx: CPU wakeup with interrupt mask on line x (x = 15 to 0)
Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the
corresponding line.
0: wakeup with interrupt masked
1: wakeup with interrupt unmasked

12.5.8 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084 (EXTI_EMR1)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EM31 Res. Res. Res. Res. EM26 EM25 EM24 EM23 EM22 EM21 Res. EM19 Res. Res. Res.

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 EM31 CPU wakeup with event generation mask on line 31

Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the
corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked
Bit 30:27 Reserved, must be kept at reset value.
Bits 26:21 EMx: CPU wakeup with event generation mask on line x (x = 26 to 21)
Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the
corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked
The EM24 and EM22 bits are only available in STM32G0B0xx. They are reserved in
STM32G030xx as well as STM32G050xx as well as STM32G070xx.
Bit 20 Reserved, must be kept at reset value.

264/989 RM0454 Rev 5

RM0454 Extended interrupt and event controller (EXTI)

Bit 19 EM19 CPU wakeup with event generation mask on line 19

Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the
corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked
Bits 18:16 Reserved, must be kept at reset value.
Bits 15:0 EMx: CPU wakeup with event generation mask on line x (x = 15 to 0)
Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the
corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked

12.5.9 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 52. EXTI controller register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_RTSR1 RT[15:0]
0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_FTSR1 FT[15:0]
0x004

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_SWIER1 SWI[15:0]
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_RPR1 RPIF[15:0]
0x00C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_FPR1 FPIF[16:0]
0x010

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x014-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x05C

EXTI_EXTICR1 EXTI3[7:0] EXTI2[7:0] EXTI1[7:0] EXTI0[7:0]

0x060

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR2 EXTI7[7:0] EXTI6[7:0] EXTI5[7:0] EXTI4[7:0]

0x064

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR3 EXTI11[7:0] EXTI10[7:0] EXTI9[7:0] EXTI8[7:0]

0x068

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR4 EXTI15[7:0] EXTI14[7:0] EXTI13[7:0] EXTI12[7:0]

0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x070-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x07C

RM0454 Rev 5 265/989

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Extended interrupt and event controller (EXTI) RM0454

Table 52. EXTI controller register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
IM31

IM26
IM25
IM24
IM23
IM22
IM21

IM19
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
EXTI_IMR1 IM[15:0]
0x080

Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EM31

EM26
EM25
EM24
EM23
EM22
EM21

EM19
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
EXTI_EMR1 EM[15:0]
0x084

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x088-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x08C

Refer to Section 2.2 on page 44 for the register boundary addresses.

266/989 RM0454 Rev 5

RM0454 Cyclic redundancy check calculation unit (CRC)

13 Cyclic redundancy check calculation unit (CRC)

13.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

13.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data

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13.3 CRC functional description

13.3.1 CRC block diagram

Figure 26. CRC calculation unit block diagram

32-bit AHB bus

32-bit (read access)

Data register (output)
crc_hclk

CRC computation

32-bit (write access)

Data register (input)

MS19882V2

13.3.2 CRC internal signals

Table 53. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

13.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32-bit
• 2 AHB clock cycles for 16-bit
• 1 AHB clock cycles for 8-bit
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.

268/989 RM0454 Rev 5

RM0454 Cyclic redundancy check calculation unit (CRC)

The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

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13.4 CRC registers

13.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.

13.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IDR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits

These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register

270/989 RM0454 Rev 5

RM0454 Cyclic redundancy check calculation unit (CRC)

13.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] POLYSIZE[1:0] Res. Res. RESET
OUT
rw rw rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware

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13.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

13.4.5 CRC polynomial (CRC_POL)

Address offset: 0x14
Reset value: 0x04C1 1DB7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

POL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

POL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0]: Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.

272/989 RM0454 Rev 5

RM0454 Cyclic redundancy check calculation unit (CRC)

13.4.6 CRC register map

Table 54. CRC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_IDR IDR[31:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POLYSIZE[1:0]
REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_CR
0x08

Reset value 0 0 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_POL POL[31:0]
0x14
Reset value 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.2 on page 44 for the register boundary addresses.

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273
Analog-to-digital converter (ADC) RM0454

14 Analog-to-digital converter (ADC)

14.1 Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external and 3 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
A built-in hardware oversampler allows analog performances to be improved while off-
loading the related computational burden from the CPU.

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RM0454 Analog-to-digital converter (ADC)

14.2 ADC main features

• High performance
– 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
– ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion
times can be obtained by lowering resolution.
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 0.4 µs conversion time is kept,
whatever the PCLK frequency)
– Wait mode: prevents ADC overrun in applications with low PCLK frequency
– Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
– 16 external analog inputs
– 1 channel for internal temperature sensor (VSENSE)
– 1 channel for internal reference voltage (VREFINT)
– 1 channel for monitoring external VBAT power supply pin
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)
• Conversion modes
– Can convert a single channel or can scan a sequence of channels.
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256x
– Programmable data shift up to 8-bits
• ADC supply requirements: 1.62 to 3.6 V
• ADC input range: VSSA ≤ VIN ≤ VREF+

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14.3 ADC functional description

Figure 27 shows the ADC block diagram and Table 55 gives the ADC pin description.

Figure 27. ADC block diagram

VDD/VDDA VREF+

AREADY
EOSMP ADC interrupt IRQ
SCANDIR AUTOFF EOSEQ
EOC CPU
up/down Auto-off mode
ADEN/ADDIS OVR Master
DATA[15:0] AWD

AHB
CH_SEL[18:0] AHB
Supply & to slave
CONT LFTRIG APB
reference APB Master
single/cont. ADCAL self interface
VBAT Input calibration DMA
VREFINT selection SAR ADC DMA request
VSENSE VIN
ADC_IN & scan SMP[2:0] DMAEN
[18:15, 11:0] VIN[x] control sampling CONVERTED Oversa DMACFG
time start DATA mpler

Start & stop

control
OVRMODE ADC_AWDx_OUT
AUTDLY (overrun mode) To analog watchdog
Auto-delayed ADSTART
SW trigger ALIGN (left/right) AWDxEN
conversion
RES[1:0] AWDxSGL
ADSTP (12, 10, 8 bits) AWDCHx[4:0]
stop conversion JOFFSETx[11:0] LTx[11:0]
JOFFSETx_ TOVS HTx[11:0]
CH[11:0] OVSS[3:0]
TIM1_TRGO2
OVSR[3:0]
TIM1_CC4
HW OVSE
TIM3_TRGO EXTEND[1:0] trigger
Trigger enable DISCEN
TIM15_TRGO and edge Discontinuous
selection mode
TIM6_TRGO

EXTSEL[1:0]
Trigger selection
MSv47998V3

14.3.1 ADC pins and internal signals

Table 55. ADC input/output pins

Name Signal type Remarks

Input, analog power Analog power supply and positive reference voltage
VDDA
supply for the ADC, VDDA ≥ VDD
Input, analog supply Ground for analog power supply. Must be at VSS
VSSA
ground potential
Input, analog reference
VREF+ The higher/positive reference voltage for the ADC.
positive
ADC_INx Analog input signals 16 external analog input channels

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RM0454 Analog-to-digital converter (ADC)

Table 56. ADC internal input/output signals

Internal signal
Signal type Description
name

Analog Input Connected either to internal channels or to ADC_INi

VIN[x]
channels external channels
TRGx Input ADC conversion triggers
VSENSE Input Internal temperature sensor output voltage
VREFINT Input Internal voltage reference output voltage
VBAT/3 Input VBAT pin input voltage divided by 3
Internal analog watchdog output signal connected to on-
ADC_AWDx_OUT Output
chip timers (x = Analog watchdog number = 1,2,3)

Table 57. External triggers

Name Source EXTSEL[2:0]

TRG0 TIM1_TRGO2 000

TRG1 TIM1_CC4 001
TRG2 Reserved 010
TRG3 TIM3_TRGO 011
TRG4 TIM15_TRGO 100
TRG5 TIM6_TRGO 101
TRG6 TIM4_TRGO 110
TRG7 EXTI11 111

14.3.2 ADC voltage regulator (ADVREGEN)

The ADC has a specific internal voltage regulator which must be enabled and stable before
using the ADC.
The ADC internal voltage regulator can be enabled by setting ADVREGEN bit to 1 in the
ADC_CR register. The software must wait for the ADC voltage regulator startup time
(tADCVREG_SETUP) before launching a calibration or enabling the ADC. This delay must be
managed by software (for details on tADCVREG_SETUP, refer to the device datasheet).
After ADC operations are complete, the ADC is disabled (ADEN = 0). It is then possible to
save additional power by disabling the ADC voltage regulator (refer to Section : ADC
voltage regulator disable sequence).
Note: When the internal voltage regulator is disabled, the internal analog calibration is kept.

Analog reference from the power control unit

The internal ADC voltage regulator internally uses an analog reference delivered by the
power control unit through a buffer. This buffer is always enabled when the main voltage
regulator of the power control unit operates in normal Run mode (refer to Reset and clock
control and power control sections).

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If the main voltage regulator enters low-power mode (such as Low-power run mode), this
buffer is disabled and the ADC cannot be used.

ADC Voltage regulator enable sequence

To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.

ADC voltage regulator disable sequence

To disable the ADC voltage regulator, follow the sequence below:
1. Make sure that the ADC is disabled (ADEN = 0).
2. Clear ADVREGEN bit in ADC_CR register.

14.3.3 Calibration (ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL = 1. Calibration can only be
initiated when the ADC voltage regulator is enabled (ADVREGEN = 1 and tADCVREG_SETUP
has elapsed) and the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. After
this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC
operating conditions change (VDDA changes are the main contributor to ADC offset
variations and temperature change to a lesser extend), it is recommended to re-run a
calibration cycle.
The calibration factor is lost in the following cases:
• The power supply is removed from the ADC (for example when the product enters
STANDBY or VBAT mode)
• The ADC peripheral is reset.
The calibration factor is lost each time power is removed from the ADC (for example when
the product enters Standby or VBAT mode). Still, it is possible to save and restore the
calibration factor by software to save time when re-starting the ADC (as long as temperature
and voltage are stable during the ADC power-down).
The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and
ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically
injected into the analog ADC. This loading is transparent and does not add any cycle
latency to the start of the conversion.
Software calibration procedure
1. Ensure that ADEN = 0, ADVREGEN = 1 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the
interrupt is enabled by setting the EOCALIE bit in the ADC_IER register
4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT
registers.

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Figure 28. ADC calibration

t CAB

ADCAL

ADC State OFF Startup CALIBRATE OFF

CALIBRATION
ADC_DR[6:0] 0x00 FACTOR
ADC_CALFACT[6:0]
by S/W by H/W
MS33703V1

Calibration factor forcing Software Procedure

1. Ensure that ADEN = 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2. Write ADC_CALFACT with the saved calibration factor
3. The calibration factor is used as soon as a new conversion is launched.

Figure 29. Calibration factor forcing

ADC state Ready (not converting) Converting channel Ready Converting channel
Updating (Single ended) (Single ended)
calibration
Internal
calibration factor[6:0] F1 F2
Start conversion
(hardware or software)

WRITE ADC_CALFACT

CALFACT[6:0] F2

by S/W by H/W
MS31925V1

14.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
As shown in Figure 30, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
Conversion can then start either by setting ADSTART to 1 (refer to Section 14.4: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN) on page 289) or when an external
trigger event occurs if triggers are enabled.

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Follow this procedure to enable the ADC:

1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
Follow this procedure to disable the ADC:
1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating
that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

Figure 30. Enabling/disabling the ADC

ADEN
t STAB

ADR DY

ADDIS

ADC
OFF Startup RDY CONVERTING CH RDY REQ
stat -OF OFF

by S/W by H/W
MS30264V2

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.

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14.3.5 ADC clock (CKMODE, PRESC[3:0])

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 31. ADC clock scheme

RCC ADITF
(Reset & Clock Controller)
APB interface
PCLK
Bits CKMODE[1:0]
of ADC_CFGR2

/1 or /2 or /4 Others
Analog ADC_CK Analog
ADC
00
ADC /1,2,4,6,8,10,12
asynchronous 16,32,64,128,256
clock Bits CKMODE[1:0]
of ADC_CFGR2
Bits PRESC[3:0]
of ADC_CCR

MSv31926V2

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are
enabled.
The input clock of the analog ADC can be selected between two different clock sources (see
Figure 31: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock
are enabled):
a) The ADC clock can be a specific clock source, named “ADC asynchronous clock“
which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
b) The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,
10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR
register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).

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Table 58. Latency between trigger and start of conversion(1)(2)

Latency between the trigger event
ADC clock source CKMODE[1:0]
and the start of conversion

HSI16, SYSCLK, or
00 Latency is not deterministic (jitter)
PLLPCLK(3)
Latency is deterministic (no jitter) and equal to
PCLK divided by 2 01
3.25 ADC clock cycles
Latency is deterministic (no jitter) and equal to
PCLK divided by 4 10
3.125 ADC clock cycles
Latency is deterministic (no jitter) and equal to
PCLK divided by 1 11
3.5 ADC clock cycles
1. Refer to the device datasheet for the maximum ADC_CLK frequency.
2. If the trigger is generated by TIM1 or TIM15 clocked at twice the CPU clock frequency, then the latency is
not deterministic and can be increased by one TIM1 or TIM15 clock cycle.
3. Selected with ADCSEL bitfield of the RCC_CCIPR register.

Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the
PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle
and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and
clock controller section). If an internal source clock is selected, the AHB and APB prescalers
do not divide the clock.

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14.3.6 ADC connectivity

ADC inputs are connected to the external channels as well as internal sources as described
in Figure 32.

Figure 32. ADC connectivity

STM32G0xx
ADC
Channel selection
VIN[0]
ADC_IN0

VIN[1]
ADC_IN1

VIN[2]
ADC_IN2

VIN[3]
ADC_IN3

VIN[4]
ADC_IN4

VIN[5]
ADC_IN5

VIN[6]
ADC_IN6

VIN[7] VREF+
ADC_IN7

VIN[8]
ADC_IN8
VIN
SAR
VIN[9]
ADC_IN9 ADC1

VIN[10]
ADC_IN10

VIN[11] VREF-
ADC_IN11

VIN[12]
VSENSE

VIN[13]
VREFINT

VIN[14]
VBAT/3

VIN[15]
ADC_IN15

VIN[16]
ADC_IN16

VIN[17]
ADC_IN17

VIN[18]
ADC_IN18

MSv45361V3

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14.3.7 Configuring the ADC

Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is
disabled (ADEN must be 0).
Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if
the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_CHSELR
and ADC_CCR registers, refer to the description of the corresponding control bit in
Section 14.12: ADC registers.
ADC_AWDTRx registers can be modified when conversion is ongoing.
Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0).
Note: There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN = 0 and all the bits in the ADC_CR register).

14.3.8 Channel selection (CHSEL, SCANDIR, CHSELRMOD)

There are up to 19 multiplexed channels:
• 16 analog inputs from GPIO pins (ADC_INx)
• 3 internal analog inputs (Temperature Sensor, Internal Reference Voltage, VBAT
channel)
It is possible to convert a single channel or a sequence of channels.
The sequence of the channels to be converted can be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSELx).
The ADC scan sequencer can be used in two different modes:
• Sequencer not fully configurable:
The order in which the channels are scanned is defined by the channel number
(CHSELRMOD bit must be cleared in ADC_CFGR1 register):
– Sequence length configured through CHSELx bits in ADC_CHSELR register
– Sequence direction: the channels are scanned in a forward direction (from the
lowest to the highest channel number) or backward direction (from the highest to
the lowest channel number) depending on the value of SCANDIR bit
(SCANDIR = 0: forward scan, SCANDIR = 1: backward scan)

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– Any channel can belong to in these sequences

• Sequencer fully configurable
The CHSELRMOD bit is set in ADC_CFGR1 register.
– Sequencer length is up to 8 channels
– The order in which the channels are scanned is independent from the channel
number. Any order can be configured through SQ1[3:0] to SQ8[3:0] bits in
ADC_CHSELR register.
– Only channel 0 to channel 14 can be selected in this sequence
– If the sequencer detects SQx[3:0] = 0b1111, the following SQx[3:0] registers are
ignored.
– If no 0b1111 is programmed in SQx[3:0], the sequencer scans full eight channels.
After programming ADC CHSELR, SCANDIR and CHSELRMOD bits, it is mandatory to wait
for CCRDY flag before starting conversions. It indicates that the new channel setting has
been applied. If a new configuration is required, the CCRDY flag must be cleared prior to
starting the conversion.
The software is allowed to program the CHSEL, SCANDIR, CHSELRMOD bits only when
ADSTART bit is cleared to 0 (which ensures that no conversion is ongoing).

Temperature sensor, VREFINT and VBAT internal channels

The temperature sensor is connected to channel ADC VIN[12].
The internal voltage reference VREFINT is connected to channel ADC VIN[13].
The VBAT channel is connected to ADC VIN[14] channel.

14.3.9 Programmable sampling time (SMPx[2:0])

Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP1[2:0] and SMP2[2:0] bits in the ADC_SMPR register.
Each channel can choose one out of two sampling times configured in SMP1[2:0] and
SMP2[2:0] bitfields, through SMPSELx bits in ADC_SMPR register.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.

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14.3.10 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note: To convert a single channel, program a sequence with a length of 1.

14.3.11 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

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14.3.12 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.
When ADSTART is set, the conversion:
• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
• In single mode with software trigger (CONT = 0, EXTEN = 00)
– At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
– At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
– After execution of the ADSTP procedure invoked by software (see
Section 14.3.14: Stopping an ongoing conversion (ADSTP) on page 289)
Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the
EOS flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01),
ADSTART is not cleared by hardware when the EOS flag is set. This avoids the need for
software having to set the ADSTART bit again and ensures the next trigger event is not
missed.
After changing channel selection configuration (by programming ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), it is mandatory to wait until CCRDY flag is asserted
before asserting ADSTART, otherwise the value written to ADSTART is ignored.

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14.3.13 Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

tCONV = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x tADC_CLK

tCONV = tSMPL + tSAR = 42.9 ns |min + 357.1 ns |12bit = 0.400 µs |min (for fADC_CLK = 35 MHz)

Figure 33. Analog to digital conversion time

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) SAMPLING CH(N+1)

Analog
CH(N) CH(N+1)
channel
Internal S/H Sample AIN(N+1) Hold AIN(N) Sample AIN(N+1)
t SMPL (1) t SAR(2)
set
by SW
ADSTART
set by HW cleared by SW
EOSMP set cleared
EOC by HW by SW

ADC_DR DATA N-1 DATA N

(1) t SMPL depends on SMP[2:0]

(2) t SAR depends on RES[2:0] MS30336V1

Figure 34. ADC conversion timings

ADSTART(1) tLATENCY (2)

ADC state Ready S0 Conversion 0 S1 Conversion 1 S2 Conversion 2 S3 Conversion 3

(3) (3)
WLATENCY WLATENCY WLATENCY (3)
ADC_DR

Data 0 Data 1 Data 2

MSv33174V1

1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

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14.3.14 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the
ADC_CR register.
This resets the ADC operation and the ADC is idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would re-
start a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 35. Stopping an ongoing conversion

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) RDY

ADSTART set by SW cleared by HW

set by SW cleared by HW
ADSTOP
ADC_DR DATA N-1

MS30337V1

14.4 Conversion on external trigger and trigger polarity (EXTSEL,

EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Table 59 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.

Table 59. Configuring the trigger polarity

Source EXTEN[1:0]

Trigger detection disabled 00

Detection on rising edge 01
Detection on falling edge 10
Detection on both rising and falling edges 11

Note: The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART = 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.

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Refer to Table 57: External triggers in Section 14.3.1: ADC pins and internal signals for the
list of all the external triggers that can be used for regular conversion.
The software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

14.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
• DISCEN = 1, channels to be converted = 0, 3, 7, 10
– 1st trigger: channel 0 is converted and an EOC event is generated
– 2nd trigger: channel 3 is converted and an EOC event is generated
– 3rd trigger: channel 7 is converted and an EOC event is generated
– 4th trigger: channel 10 is converted and both EOC and EOS events are
generated.
– 5th trigger: channel 0 is converted an EOC event is generated
– 6th trigger: channel 3 is converted and an EOC event is generated
– ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
– 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOS
event.
– Any subsequent trigger events restarts the complete sequence.
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

14.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 60.

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Table 60. tSAR timings depending on resolution

tSAR tSMPL (min) tCONV
RES[1:0] tSAR (ns) at tCONV (ns) at
(ADC clock (ADC clock (ADC clock cycles)
bits fADC = 35 MHz fADC = 35 MHz
cycles) cycles) (with min. tSMPL)

12 12.5 357 1.5 14 400

10 10.5 300 1.5 12 343
8 8.5 243 1.5 10 286
6 6.5 186 1.5 8 229

14.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note: As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.

14.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.

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14.4.5 Example timing diagrams (single/continuous modes

hardware/software triggers)

Figure 36. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 RDY CH17 CH10 CH9 CH0 RDY

ADC_DR D0 D9 D10 D17 D17 D10 D9 D0

by S/W by H/W

MSv30338V3

1. EXTEN = 00, CONT = 0

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

Figure 37. Continuous conversion of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADSTP

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 CH0 CH9 CH10 STP RDY CH17 CH10

ADC_DR D0 D9 D10 D17 D0 D9 D17

by S/W by H/W

MSv30339V2

1. EXTEN = 00, CONT = 1,

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

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Figure 38. Single conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 RDY CH0 CH1 CH2 CH3 RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30340V2

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

Figure 39. Continuous conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

ADSTP

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 STOP RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30341V2

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

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14.4.6 Low frequency trigger mode

Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start
a new conversion. The ADC needs to be started at a predefined time (tidle) otherwise ADC
converted data might be corrupted due to the transistor leakage (refer to the device
datasheet for the maximum value of tidle).
If the application has to support a time longer than the maximum tidle value (between one
trigger to another for single conversion mode or between the ADC enable and the first ADC
conversion), then the ADC internal state needs to be rearmed. This mechanism can be
enabled by setting LFTRIG bit to 1 in ADC_CFGR2 register. By setting this bit, any trigger
(software or hardware) sends a rearm command to ADC. The conversion is started after a
two ADC clock cycle delay compared to LFTRIG set to 0.
It is not necessary to use this mode when AUTOFF bit is set to 1. For Wait mode, only the
first trigger generates an internal rearm command.

14.5 Data management

14.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 40.

Figure 40. Data alignment and resolution (oversampling disabled: OVSE = 0)

ALIGN RES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0x0 0x0 DR[11:0]

0x1 0x00 DR[9:0]
0x2 0x00 DR[7:0]
0x3 0x00 DR[5:0]
1 0x0 DR[11:0] 0x0
0x1 DR[9:0] 0x00
0x2 DR[7:0] 0x00
0x3 0x00 DR[5:0] 0x0

MS30342V1

14.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.

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When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
• OVRMOD = 0
– An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
– The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.

Figure 41. Example of overrun (OVR)

ADSTART(1)

EOC

EOS

OVR

ADSTP

TRGx(1)

ADC state(2)
RDY CH0 CH1 CH2 CH0 CH1 CH2 CH0 STOP RDY

ADC_DR read OVERRUN

access

ADC_DR
(OVRMOD=0) D0 D1 D2 D0

ADC_DR
(OVRMOD=1) D0 D1 D2 D0 D1 D2

by S/W by H/W
triggered

MSv30343V3

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14.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.

14.5.4 Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.

14.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA
request is generated after the conversion of each channel. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 14.5.2: ADC overrun (OVR, OVRMOD) on page 294).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a DMA_EOT interrupt occurs, see Section 9: Direct memory access
controller (DMA) on page 213) even if a conversion has been started again.

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When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.

14.6 Low-power features

14.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only
if the previous data has been treated, once the ADC_DR register has been read or if the
EOC bit has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.

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Figure 42. Wait mode conversion (continuous mode, software trigger)

ADSTART

EOC

EOS

ADSTP

ADC_DR Read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by S/W by H/W

MSv30344V2

1. EXTEN = 00, CONT = 1

2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0

14.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.
When AUTOFF = 1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 44: Behavior with WAIT = 1, AUTOFF = 1).
Note: Please refer to the Section Reset and clock control (RCC) for the description of how to
manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically
switch ON/OFF the 14 MHz internal oscillator to save power.

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Figure 43. Behavior with WAIT = 0, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access

ADC state RDY Startup CH1 CH2 CH3 CH4 OFF Startup

ADC_DR D1 D2 D3 D4

by S/W by H/W
triggered

MSv30345V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1

Figure 44. Behavior with WAIT = 1, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access DLY DLY DLY DLY
OFF

OFF

ADC state RDY Startup CH1 OFF Startup CH2 Startup CH3 OFF Startup CH1 CH2

D1 D2 D3 D4
ADC_DR

by S/W by H/W
triggered

MSv30346V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1

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14.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH,

ADC_AWDxCR, ADC_AWDxTR)
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).

14.7.1 Description of analog watchdog 1

AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register.
It is used to monitor that either one selected channel or all enabled channels (see Table 62:
Analog watchdog 1 channel selection) remain within a configured voltage range (window) as
shown in Figure 45.
The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
HT1[11:0] and LT1[11:0] bits of ADC_AWD1TR register. An interrupt can be enabled by
setting the AWD1IE bit in the ADC_IER register.
The AWD1 flag is cleared by software by programing it to 1.
When converting data with a resolution of less than 12-bit (according to bits DRES[1:0]), the
LSB of the programmed thresholds must be kept cleared because the internal comparison
is always performed on the full 12-bit raw converted data (left aligned).
Table 61 describes how the comparison is performed for all the possible resolutions.
Table 61. Analog watchdog comparison

Resolution Analog Watchdog comparison between:

bits Comments
Raw converted
RES[1:0] Thresholds
data, left aligned(1)

00: 12-bit DATA[11:0] LTx[11:0] and HTx[11:0] -

01: 10-bit DATA[11:2],00 LTx[11:0] and HTx[11:0] The user must configure LTx[1:0] and HTx[1:0] to “00”
The user must configure LTx[3:0] and HTx[3:0] to
10: 8-bit DATA[11:4],0000 LTx[11:0] and HTx[11:0]
“0000”
The user must configure LTx[5:0] and HTx[5:0] to
11: 6-bit DATA[11:6],000000 LTx[11:0] and HTx[11:0]
“000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 62 shows how to configure the AWD1SGL and AWD1EN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.

Figure 45. Analog watchdog guarded area

Analog voltage

Higher threshold HTx

Guarded area
Lower threshold LTx

MS45396V1

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Table 62. Analog watchdog 1 channel selection

Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit

None x 0
All channels 0 1
(1)
Single channel 1 1
1. Selected by the AWD1CH[4:0] bits

14.7.2 Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
The corresponding watchdog is enabled when any AWDxCHy bit (x = 2,3) is set in
ADC_AWDxCR register.
When converting data with a resolution of less than 12 bits (configured through DRES[1:0]
bits), the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 61 describes how the comparison is performed for all the possible resolutions.
The AWD2/3 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in
HTx[11:0] and LTx[11:0] of ADC_AWDxTR registers (x = 2 or 3). An interrupt can be
enabled by setting the AWDxIE bit in the ADC_IER register.
The AWD2 and ADW3 flags are cleared by software by programming them to 1.

14.7.3 ADC_AWDx_OUT output signal generation

Each analog watchdog is associated to an internal hardware signal, ADC_AWDx_OUT (x
being the watchdog number) that is directly connected to the ETR input (external trigger) of
some on-chip timers (refer to the timers section for details on how to select the
ADC_AWDx_OUT signal as ETR).
ADC_AWDx_OUT is activated when the associated analog watchdog is enabled:
• ADC_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADC_AWDx_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
• ADC_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set to 1), might clear the ADC_AWDx_OUT
state.
• ADC_AWDx_OUT state does not change when the ADC converts the none-guarded
channel (see Figure 48)
AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADC_AWDx_OUT (as an example, ADC_AWDx_OUT can toggle while AWDx
flag remains at 1 if the software has not cleared the flag).
The ADC_AWDx_OUT signal is generated by the ADC_CLK domain. This signal can be
generated even the APB clock is stopped.

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The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.

Figure 46. ADC_AWDx_OUT signal generation

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
inside outside inside outside outside outside inside
EOC FLAG

Cleared Cleared Cleared Cleared

AWDx FLAG by SW by SW by SW by SW

ADC_AWDx_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7

MSv45362V1

Figure 47. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7

inside outside inside outside outside outside inside

EOC FLAG

not cleared by SW
AWDx FLAG

ADC_AWDx_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7
MSv45363V1

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Figure 48. ADC_AWDx_OUT signal generation (on a single channel)

ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2

outside inside outside outside

EOC FLAG

EOS FLAG
Cleared Cleared
by SW by SW
AWDx FLAG

ADCy_AWDx_OUT

- Converted channels: 1 and 2

- Only channel 1 is guarded

MSv45364V1

14.7.4 Analog Watchdog threshold control

LTx[11:0] and HTx[11:0] can be changed during an analog-to-digital conversion (that is
between the start of the conversion and the end of conversion of the ADC internal state). If
HTx and LTx bits are programmed during the ADC guarded channel conversion, the
watchdog function is masked for this conversion. This mask is cleared when starting a new
conversion, and the resulting new AWD threshold is applied starting the next ADC
conversion result. AWD comparison is performed at each end of conversion. If the current
ADC data are out of the new threshold interval, this does not generated any interrupt or an
ADC_AWDx_OUT signal. The Interrupt and the ADC_AWDx_OUT generation only occurs
at the end of the ADC conversion that started after the threshold update. If
ADC_AWDx_OUT is already asserted, programming the new threshold does not deassert
the ADC_AWDx_OUT signal.

Figure 49. Analog watchdog threshold update

ADC state Conversion Conversion Conversion Conversion

Threshould updated

LTx, HTx XXXX XXXY XXXZ

Comparison Active Masked Active

MSv45365V1

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14.8 Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:

n = N–1
1
Result = ----- ×
M  Conversion ( t n )
n=0

It allows the following functions to be performed by hardware: averaging, data rate

reduction, SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.

Figure 50. 20-bit to 16-bit result truncation

19 15 11 7 3 0
Raw 20-bit data

Shifting

15 0
Truncation
and rounding

MS31928V2

The Figure 51 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.

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Figure 51. Numerical example with 5-bits shift and rounding

19 15 11 7 3
Raw 20-bit data: 3 B 7 D 7

15 0
Final result after 5-bits shift
and rounding to nearest 1 D B F

MS31929V1

The Table 63 below gives the data format for the various N and M combination, for a raw
conversion data equal to 0xFFF.

Table 63. Maximum output results vs N and M. Grayed values indicates truncation
1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit
Oversa No-shift
Max shift shift shift shift shift shift shift shift
mpling OVSS =
ratio Raw data OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS =
0000
0001 0010 0011 0100 0101 0110 0111 1000

2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020
4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040
8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080
16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100
32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200
64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400
128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800
256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

The conversion timings in oversampled mode do not change compared to standard

conversion mode: the sample time is maintained equal during the whole oversampling
sequence. New data are provided every N conversion, with an equivalent delay equal to N x
tCONV = N x (tSMPL + tSAR). The flags features are raised as following:
• the end of the sampling phase (EOSMP) is set after each sampling phase
• the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
• the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)

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14.8.1 ADC operating modes supported when oversampling

In oversampling mode, most of the ADC operating modes are available:
• Single or continuous mode conversions, forward or backward scanned sequences and
up to 8 channels programmed sequence
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (WAIT, AUTOFF)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.

14.8.2 Analog watchdog

The analog watchdog functionality is available (AWDxSGL, AW1DEN and AWDxCH bits),
with the following differences:
• the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits
values HTx[11:0] and LTx[11:0]
• the comparison is performed on the most significant 12 bits of the 16 bits oversampled
results ADC_DR[15:4]
Note: Care must be taken when using high shifting values. This reduces the comparison range.
For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data right-
aligned, the affective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HTx[7:0] / LTx[[7:0], and HTx[11:8] /
LTx[11:8] must be kept reset.

14.8.3 Triggered mode

The averager can also be used for basic filtering purposes. Although not a very efficient filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS
bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and
independent from the conversion time itself.
Figure 52 below shows how conversions are started in response to triggers in discontinuous
mode.
If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

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Figure 52. Triggered oversampling mode (TOVS bit = 1)

Trigger Trigger

CONT = 0 Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N)

(DISCEN = 1)* 0 1 2 3 0 1 2 3
TOVS = 0
EOC flag set
Trigger Trigger Trigger Trigger Trigger Trigger Trigger
CONT = 0
(DISCEN = 1)* Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N)
TOVS = 1 0 1 2 3 0 1 2

EOC flag set

(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set

MS33700V1

14.9 Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC VIN[12] input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC VIN[13] input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area.
Figure 53 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC VIN[12] (temperature sensor)
and the VREFEN bit must be set to enable the conversion of ADC VIN[13] (VREFINT).
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).
The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference. Refer to the datasheet for additional information.

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Main features
• Supported temperature range: –40 to 125 °C
• Linearity: ±2 °C max., precision depending on calibration

Figure 53. Temperature sensor and VREFINT channel block diagram

TSEN control bit

Temperature + VSENSE
sensor ADC VIN[12]
-

Address/data bus
converted data
VREFEN control bit
ADC

+ VREFINT
Internal power ADC VIN[13]
block -

MSv62466V1

Reading the temperature

1. Select the ADC VIN[12] input channel
2. Select an appropriate sampling time specified in the device datasheet (TS_temp).
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART).
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger)
5. Read the resulting VSENSE data in the ADC_DR register
6. Calculate the temperature using the following formula

TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = ---------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + TS_CAL1_TEMP
TS_CAL2 – TS_CAL1

Where:
• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP
(refer to the datasheet for TS_CAL2 value)
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
(refer to the datasheet for TS_CAL1 value)
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and
TS_CAL2 calibration points.
Note: The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.

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Calculating the actual VREF+ voltage using the internal reference voltage
VREF+ voltage may be subject to variation or not precisely known. The embedded internal
reference voltage (VREFINT) and its calibration data acquired by the ADC during the
manufacturing process at VREF+_charac can be used to evaluate the actual VREF+ voltage
level.
The following formula gives the actual VREF+ voltage supplying the device:

V REF+ = V REF + _Charac × VREFINT_CAL ⁄ VREFINT_DATA

Where:
• VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VREF+. For
applications where VREF+ is known and ADC converted values are right-aligned you can
use the following formula to get this absolute value:
V REF+
V CHANNELx = ------------------------------------- × ADC_DATA x
FULL_SCALE

For applications where VREF+ value is not known, you must use the internal voltage
reference and VREF+ can be replaced by the expression provided in Section : Calculating
the actual VREF+ voltage using the internal reference voltage, resulting in the following
formula:
V REF+_Charac × VREFINT_CAL × ADC_DATA x
V CHANNELx = -------------------------------------------------------------------------------------------------------------------------
VREFINT_DATA × FULL_SCALE

Where:
• VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• ADC_DATAx is the value measured by the ADC on channelx (right-aligned)
• VREFINT_DATA is the actual VREFINT output value converted by the ADC
• full_SCALE is the maximum digital value of the ADC output. For example with 12-bit
resolution, it is 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.
Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.

14.10 Battery voltage monitoring

The VBATEN bit in the ADC_CCR register allows the application to measure the backup
battery voltage on the VBAT pin. As the VBAT voltage could be higher than VREF+, to ensure

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the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider.
This bridge is automatically enabled when VBATEN is set, to connect VBAT to the ADC
VIN[14] input channel. As a consequence, the converted digital value is half the VBAT
voltage. To prevent any unwanted consumption on the battery, it is recommended to enable
the bridge divider only when needed for ADC conversion.

Figure 54. VBAT channel block diagram

VBAT VBATEN control bit

Address/data bus
ADC

VBAT/3
+
ADC VIN[14]
-

MSv45367V2

14.11 ADC interrupts

An interrupt can be generated by any of the following events:
• End Of Calibration (EOCAL flag)
• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
• When the Channel configuration is ready (CCRDY flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.

Table 64. ADC interrupts

Interrupt event Event flag Enable control bit

End Of Calibration EOCAL EOCALIE

ADC ready ADRDY ADRDYIE
End of conversion EOC EOCIE
End of sequence of conversions EOS EOSIE
Analog watchdog 1 status bit is set AWD1 AWD1IE

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Table 64. ADC interrupts (continued)

Interrupt event Event flag Enable control bit

Analog watchdog 2 status bit is set AWD2 AWD2IE

Analog watchdog 3 status bit is set AWD3 AWD3IE
Channel Configuration Ready CCRDY CCRDYIE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE

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14.12 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

14.12.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. CCRDY Res. EOCAL Res. AWD3 AWD2 AWD1 Res. Res. OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 CCRDY: Channel Configuration Ready flag
This flag bit is set by hardware when the channel configuration is applied after programming to
ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by
programming it to it.
0: Channel configuration update not applied.
1: Channel configuration update is applied.
Note: When the software configures the channels (by programming ADC_CHSELR or changing
CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again
or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the
flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY
flag before proceeding with a new configuration.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred

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Bit 7 AWD1: Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1
and ADC_HR1 registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a
state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

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14.12.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCRD EOCAL AWD3I AWD2I AWD1I EOSMP ADRDY
Res. Res. Res. Res. Res. Res. OVRIE EOSIE EOCIE
YIE IE E E E IE IE
rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 CCRDYIE: Channel Configuration Ready Interrupt enable
This bit is set and cleared by software to enable/disable the channel configuration ready interrupt.
0: Channel configuration ready interrupt disabled
1: Channel configuration ready interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bits 6:5 Reserved, must be kept at reset value.

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Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 3 EOSIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).

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14.12.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADVR
ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EGEN
rs rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSTA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP Res. ADDIS ADEN
RT
rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 ADVREGEN: ADC Voltage Regulator Enable
This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output
is available after tADCVREG_SETUP.
It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0.
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.

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Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits,
a conversion either starts immediately (software trigger configuration) or once a hardware trigger
event occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled
and there is no pending request to disable the ADC).
After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is
mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value
written to ADSTART is ignored.
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0,
ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

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14.12.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1E AWD1SG CHSEL
Res. AWD1CH[4:0] Res. Res. Res. Res. Res. Res. DISCEN
N L RMOD
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAND DMAC
AUTOFF WAIT CONT OVRMOD EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0] DMAEN
IR FG
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWD1CH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
10010: ADC analog input Channel 18 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWD1EN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog 1 disabled
1: Analog watchdog 1 enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 22 AWD1SGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).

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Bit 21 CHSELRMOD: Mode selection of the ADC_CHSELR register

This bit is set and cleared by software to control the ADC_CHSELR feature:
0: Each bit of the ADC_CHSELR register enables an input
1: ADC_CHSELR register is able to sequence up to 8 channels
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 DISCEN: Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).

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Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable
the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 9 Reserved, must be kept at reset value.
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 57:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 40:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 294
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: The software is allowed to write these bits only when ADEN = 0.

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Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence. It is effective only if CHSELMOD bit is cleared to 0.
0: Upward scan (from CHSEL0 to CHSEL18)
1: Backward scan (from CHSEL18 to CHSEL0)
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 14.5.5: Managing converted data using the DMA on
page 296
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 14.5.5: Managing converted data using the DMA on page 296.
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).

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14.12.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMODE[1:0] LFTRIG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. TOVS OVSS[3:0] OVSR[2:0] Res. OVSE

rw rw rw rw rw rw rw rw rw

Bits 31:30 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bit 29 LFTRIG: Low frequency trigger mode enable
This bit is set and cleared by software.
0: Low Frequency Trigger Mode disabled
1: Low Frequency Trigger Mode enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bits 28:10 Reserved, must be kept at reset value.
Bit 9 TOVS: Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each oversampled conversion for a channel needs a trigger
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

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Bits 8:5 OVSS[3:0]: Oversampling shift

This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Others: Reserved
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 4:2 OVSR[2:0]: Oversampling ratio
This bit filed defines the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 1 Reserved, must be kept at reset value.
Bit 0 OVSE: Oversampler Enable
This bit is set and cleared by software.
0: Oversampler disabled
1: Oversampler enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).

14.12.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
Res. Res. Res. Res. Res.
L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
Res. SMP2[2:0] Res. SMP1[2:0]
L7 L6 L5 L4 L3 L2 L1 L0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0454 Rev 5 323/989

334
Analog-to-digital converter (ADC) RM0454

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:8 SMPSEL[18:0] Channel-x sampling time selection
These bits are written by software to define which sampling time is used.
0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 SMP2[2:0]: Sampling time selection 2
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMP1[2:0]: Sampling time selection 1
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

14.12.7 ADC watchdog threshold register (ADC_AWD1TR)

Address offset: 0x20
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

324/989 RM0454 Rev 5

RM0454 Analog-to-digital converter (ADC)

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.

14.12.8 ADC watchdog threshold register (ADC_AWD2TR)

Address offset: 0x24
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT2[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT2[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT2[11:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT2[11:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.

RM0454 Rev 5 325/989

334
Analog-to-digital converter (ADC) RM0454

14.12.9 ADC channel selection register [alternate] (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current
section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in ADC_CFGR1). Refer to
next section.
CHSELRMOD = 0 in ADC_CFGR1:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL CHSEL CHSEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
18 17 16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 CHSEL[18:0]: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels to
be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.

326/989 RM0454 Rev 5

RM0454 Analog-to-digital converter (ADC)

14.12.10 ADC channel selection register [alternate] (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current
previous section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in ADC_CFGR1). Refer to
this section.
CHSELRMOD = 1 in ADC_CFGR1:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SQ8[3:0] SQ7[3:0] SQ6[3:0] SQ5[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SQ4[3:0] SQ3[3:0] SQ2[3:0] SQ1[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 SQ8[3:0]: 8th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates the end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
0000: CH0
0001: CH1
...
1100: CH12
1101: CH13
1110: CH14
1111: No channel selected (End of sequence)
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 27:24 SQ7[3:0]: 7th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 23:20 SQ6[3:0]: 6th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

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Analog-to-digital converter (ADC) RM0454

Bits 19:16 SQ5[3:0]: 5th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 15:12 SQ4[3:0]: 4th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 11:8 SQ3[3:0]: 3rd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 7:4 SQ2[3:0]: 2nd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 3:0 SQ1[3:0]: 1st conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

328/989 RM0454 Rev 5

RM0454 Analog-to-digital converter (ADC)

14.12.11 ADC watchdog threshold register (ADC_AWD3TR)

Address offset: 0x2C
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT3[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT3[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT3[11:0]: Analog watchdog 3lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 300.

14.12.12 ADC data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The data
are left- or right-aligned as shown in Figure 40: Data alignment and resolution (oversampling disabled:
OVSE = 0) on page 294.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.

RM0454 Rev 5 329/989

334
Analog-to-digital converter (ADC) RM0454

14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)

Address offset: 0xA0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2 AWD2 AWD2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH18 CH17 CH16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 2 (AWD2).
0: ADC analog channel-x is not monitored by AWD2
1: ADC analog channel-x is monitored by AWD2
Note: The channels selected through ADC_AWD2CR must be also configured into the
ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is
allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is
ongoing).

14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)

Address offset: 0xA4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3 AWD3 AWD3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH18 CH17 CH16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3 AWD3
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 3 (AWD3).
0: ADC analog channel-x is not monitored by AWD3
1: ADC analog channel-x is monitored by AWD3
Note: The channels selected through ADC_AWD3CR must be also configured into the
ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is
allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

330/989 RM0454 Rev 5

RM0454 Analog-to-digital converter (ADC)

14.12.15 ADC Calibration factor (ADC_CALFACT)

Address offset: 0xB4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT[6:0]

rw rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT[6:0]: Calibration factor
These bits are written by hardware or by software.
– Once a calibration is complete, they are updated by hardware with the calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it is then applied once a new calibration is
launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.
Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing
and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.

14.12.16 ADC common configuration register (ADC_CCR)

Address offset: 0x308
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBAT VREF
Res. Res. Res. Res. Res. Res. Res. TSEN PRESC[3:0] Res. Res.
EN EN
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0454 Rev 5 331/989

334
Analog-to-digital converter (ADC) RM0454

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 VBATEN: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
Other: Reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 17:0 Reserved, must be kept at reset value.

332/989 RM0454 Rev 5

 0x28
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
Offset
14.13
RM0454

1)
0)
ADC_CR

Reserved
Reserved
ADC_IER
ADC_ISR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

ADC_SMPR
ADC_CFGR2
ADC_CFGR1

ADC_CHSELR
ADC_CHSELR

ADC_AWD3TR
ADC_AWD2TR
ADC_AWD1TR

(CHSELRMOD=
(CHSELRMOD=

0
0
0
Res. Res. Res. Res. Res.. Res. ADCAL Res. Res. 31
CKMODE[1:0]

0
0
0
Res. Res. Res. Res. Res.. Res. Res. Res. 30

0
0
0
Res. Res. Res. Res. Res.. LFTRIG Res. Res. Res. 29

SQ8[3:0]

0
0
0
Res. Res. Res. Res. Res.. Res. ADVREGEN Res. Res. 28

1
0
1
1
0
Res. Res.. Res. Res. Res. Res. 27

AWDCH[4:0]

1
0
1
1
0
0
Res. SMPSEL18. Res. Res. Res. Res. 26

1
0
1
1
0
Res. SMPSEL17 Res. Res. Res. Res. Res. 25

SQ7[3:0]
ADC register map

1
0
1
1
0
Res. SMPSEL16 Res. Res. Res. Res. Res. 24

1
0
1
1
0
0
Res SMPSEL15 Res. AWD1EN Res. Res. Res. 23

1
0
1
1
0
0
Res SMPSEL14 Res. AWD1SGL Res. Res. Res. 22

1
0
1
1
0
0
Res SMPSEL13 Res. CHSELRMOD Res. Res. Res. 21

SQ6[3:0]

HT3[11:0]
HT2[11:0]
HT1[11:0]

1
0
1
1
0
Res SMPSEL12 Res. Res. Res. Res. Res. 20

1
0
1
1
0
Res SMPSEL11 Res. Res. Res. Res. Res. 19

1
0
1
1
0

0
CHSEL18 SMPSEL10 Res. Res. Res. Res. Res. 18

1
0
1
1

RM0454 Rev 5
CHSEL17 SMPSEL9 Res. Res. Res. Res. Res. 17

SQ5[3:0]

1
0
1
1

0
0
CHSEL16 SMPSEL8 Res. DISCEN Res. Res. Res. 16
The following table summarizes the ADC registers.

0
0
0
Res. CHSEL15 Res. Res. SMPSEL7 Res. AUTOFF Res. Res. Res. 15

Reserved
Reserved

0
0 0 0 0

0
0
Res. CHSEL14 Res. Res. SMPSEL6 Res. WAIT Res. Res. Res. 14

0
0

0
0
0
0

Res. CHSEL13 Res. Res. SMPSEL5 Res. CONT Res. CCRDYIE. CCRDY. 13

SQ4[3:0]

0
0

0
0
Res. CHSEL12 Res. Res. SMPSEL4 Res. OVRMOD Res. Res. Res. 12
EOCALIE EOCAL

0
0
0
0
0
0
0
0

CHSEL11 SMPSEL3 Res. Res.

Table 65. ADC register map and reset values

EXTEN[1:0]
11

0
0
0
0
0
0
CHSEL10 SMPSEL2 Res. Res. Res. Res. 10

0
0
0
0
0
0
0
0

CHSEL9 SMPSEL1 TOVS Res. Res. AWD3IE AWD3 9

SQ3[3:0]

0
0
0
0
0
0
0
0
0

CHSEL8 SMPSEL0 Res. AWD2IE AWD2 8

0
0
0
0
0
0
0
0

CHSEL7 Res. Res. AWD1IE AWD1 7

[2:0]

OVSS[3:0]
EXTSEL

0
0
0
0
0
0
0

CHSEL6 Res. Res. Res. 6

0
0
0
0
0
0
0

CHSEL5 ALIGN Res. Res. Res. 5

[2:0]

LT3[11:0]
LT2[11:0]
LT1[11:0]

SQ2[3:0]
SMP2

0
0
0
0
0
0
0
0
0
0

CHSEL4 ADSTP OVRIE OVR 4

[1:0]
RES

0
0
0
0
0
0
0
0

CHSEL3 Res. OVSR[2:0] Res. EOSIE EOS 3

0
0
0
0
0
0
0
0
0

CHSEL2 SCANDIR ADSTART EOCIE EOC 2

0
0
0
0
0
0
0
0
0

CHSEL1 Res. DMACFG ADDIS EOSMPIE EOSMP 1

[2:0]

SQ1[3:0]
SMP1

0 OVSE

0
0
0
0
0
0
0
0
0

CHSEL0 DMAEN ADEN ADRDYIE ADRDY 0

333/989
Analog-to-digital converter (ADC)

334
 ...
...
...
0x40
0x38
0x34
0x30

0xB4
0xA4
0xA0
0x3C

0x308
Offset

334/989
ADC_DR

Reserved
Reserved
Reserved
Reserved

ADC_CCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

ADC_AWD3CR
ADC_AWD2CR

ADC_CALFACT
Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. 26
Analog-to-digital converter (ADC)

Res. Res. Res. Res. Res. 25

0
VBATEN Res. Res. Res. Res. 24

0
TSEN Res. Res Res Res. 23

0
VREFEN Res. Res Res Res. 22

0
PRESC3 Res. Res Res Res. 21

0
PRESC2 Res. Res Res Res. 20

0
PRESC1 Res. Res Res Res. 19

0
0
0

PRESC0 Res. AWD3CH18s AWD2CH18s Res. 18

0

RM0454 Rev 5
Res. Res. AWD3CH17 AWD2CH17 Res. 17
0

Res. Res. AWD3CH16 AWD2CH16 Res. 16

0

Res. Res. AWD3CH15 AWD2CH15 15

Reserved
Reserved
Reserved
Reserved

0 0 0 0
0
0 0

Res. Res. AWD3CH14 AWD2CH14 14

0
0
0

Res. Res. AWD3CH13 AWD2CH13 13

0
0
0

Res. Res. AWD3CH12 AWD2CH12 12

0
0
0

Res. Res. AWD3CH11 AWD2CH11 11

0
0
0

Res. Res. AWD3CH10 AWD2CH10 10

0
0
0

Res. Res. AWD3CH9 AWD2CH9 9

Refer to Section 2.2 on page 44 for the register boundary addresses.

0
0
0

Res. Res. AWD3CH8 AWD2CH8

Table 65. ADC register map and reset values (continued)

8
0
0
0

Res. Res. AWD3CH7 AWD2CH7 7

DATA[15:0]

0
0

0
0

Res. AWD3CH6 AWD2CH6 6

0
0

0
0

Res. AWD3CH5 AWD2CH5 5

0
0

0
0

Res. AWD3CH4 AWD2CH4 4

0
0

0
0

Res. AWD3CH3 AWD2CH3 3

0
0

0
0

Res. AWD3CH2 AWD2CH2 2

CALFACT[6:0]
0
0

0
0

Res. AWD3CH1 AWD2CH1 1

0
0

0
0

Res. AWD3CH0 AWD2CH0 0

RM0454
RM0454 Advanced-control timer (TIM1)

15 Advanced-control timer (TIM1)

In this section, “TIMx” should be understood as “TIM1” since there is only one instance of
this type of timer for the products to which this reference manual applies.

15.1 TIM1 introduction

The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMy) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 15.3.26: Timer synchronization.

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15.2 TIM1 main features

TIM1 timer features include:
• 16-bit up, down, up/down auto-reload counter.
• 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65536.
• Up to 6 independent channels for:
– Input Capture (but channels 5 and 6)
– Output Compare
– PWM generation (Edge and Center-aligned Mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
• Repetition counter to update the timer registers only after a given number of cycles of
the counter.
• 2 break inputs to put the timer’s output signals in a safe user selectable configuration.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Supports incremental (quadrature) encoder and Hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management

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RM0454 Advanced-control timer (TIM1)

Figure 55. Advanced-control timer block diagram

Internal clock (CK_INT)
from RCC
Trigger
ETRF controller TRGO
TIMx_ETR ETRP to other timers
ETR Polarity selection & Input to peripherals
edgedetector & prescaler filter

On-chip ETR ITR[0..15] TRG

sources ITR
Slave Reset, enable, up/down, count
TRC TRGI
controller
mode
TI1F_ED

TI1FP1 Encoder
TI2FP2 Interface

REP register
U UI
Auto-reload register
Repetition
Stop, clear or up/down U
counter
CK_PSC PSC CK_CNT +/-
XOR CNT counter
prescaler DTG registers
CC1I U CC1I
TI1[0] TI1 Input TIMx_CH1
TIMx_CH1 TI1FP1 OC1REF
filter & IC1 IC1PS Output OC1
TI1FP2 Prescaler Capture/Compare 1 register
TI1[1..15] edge DTG
control TIMx_CH1N
detector TRC
CC2I OC1N
U CC2I TIMx_CH2
TI2[0] Input TI2FP1
TIMx_CH2 IC2 OC2
TI2 filter & TI2FP2 Output
Prescaler
IC2PS Capture/Compare 2 register OC2REF
TI2[1..15] edge DTG control TIMx_CH2N
detector TRC OC2N

TI3[0] CC3I U CC3I

Input TIMx_CH3
TIMx_CH3 TI3FP3
TI3 filter & IC3 IC3PS OC3REF
Output OC3
TI3[1..15] edge TI3FP4 Prescaler Capture/Compare 3 register TIMx_CH3N
DTG
detector TRC control
CC4I OC3N
U CC4I
TI4[0] Input
TIMx_CH4 TI4FP3
TI4 filter & TI4FP4 IC4 Output OC4
Prescaler
IC4PS Capture/Compare 4 register OC4REF TIMx_CH4
TI4[1..15] edge control
detector TRC

Output OC5
Capture/Compare 5 register OC5REF
control

Output OC6
Capture/Compare 6 register OC6REF
control
Internal
sources SBIF
ETRF
BIF
TIMx_BKIN BRK request

Break and Break2 circuitry (1)

B2IF
BRK2 request
TIMx_BKIN2

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MSv40115V3

1. The internal break event source can be:

- A clock failure event generated by CSS. For further information on the CSS, refer to Section 5.2.8:
Clock security system (CSS)
- SRAM parity error signal
- Cortex®-M0+ LOCKUP (Hardfault) output.

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433
Advanced-control timer (TIM1) RM0454

15.3 TIM1 functional description

15.3.1 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
• Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 56 and Figure 57 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

338/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 56. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 57. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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Advanced-control timer (TIM1) RM0454

15.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR) + 1. Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register,
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

340/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 58. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

Figure 59. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

RM0454 Rev 5 341/989

433
Advanced-control timer (TIM1) RM0454

Figure 60. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

Figure 61. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

342/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 62. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

MS31082V3

Figure 63. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

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433
Advanced-control timer (TIM1) RM0454

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR) + 1. Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register.
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

344/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 64. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 65. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

RM0454 Rev 5 345/989

433
Advanced-control timer (TIM1) RM0454

Figure 66. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31186V1

Figure 67. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

346/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 68. Counter timing diagram, update event when repetition counter is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or

RM0454 Rev 5 347/989

433
Advanced-control timer (TIM1) RM0454

DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 69. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31189V3

1. Here, center-aligned mode 1 is used (for more details refer to Section 15.4: TIM1 registers).

348/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 70. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 71. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

RM0454 Rev 5 349/989

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Advanced-control timer (TIM1) RM0454

Figure 72. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 73. Counter timing diagram, update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

350/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 74. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

15.3.3 Repetition counter

Section 15.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:
• At each counter overflow in upcounting mode,
• At each counter underflow in downcounting mode,
• At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 32768 PWM cycles, it makes
it possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 75). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

RM0454 Rev 5 351/989

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Advanced-control timer (TIM1) RM0454

In Center aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was launched: if the RCR was written before launching the counter, the UEV
occurs on the underflow. If the RCR was written after launching the counter, the UEV occurs
on the overflow.
For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event
depending on when the RCR was written.

Figure 75. Update rate examples depending on mode and TIMx_RCR register settings

Counter-aligned mode Edge-aligned mode

Counter Upcounting Downcounting
TIMx_CNT

TIMx_RCR = 0
UEV

TIMx_RCR = 1
UEV

UEV
TIMx_RCR = 2

TIMx_RCR = 3 UEV

TIMx_RCR = 3
and
UEV
re-synchronization
(by SW) (by SW) (by SW)

UEV Update event: Preload registers transferred to active registers and update interrupt generated
Update Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.

MSv31195V1

352/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

15.3.4 External trigger input

The timer features an external trigger input ETR. It can be used as:
• external clock (external clock mode 2, see Section 15.3.5)
• trigger for the slave mode (see Section 15.3.26)
• PWM reset input for cycle-by-cycle current regulation (see Section 15.3.7)
Figure 76 below describes the ETR input conditioning. The input polarity is defined with the
ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed
by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.

Figure 76. External trigger input block

ETR
ETR input 0 ETRP To the Output mode controller
Divider Filter
To the CK_PSC circuitry
1 /1, /2, /4, /8 fDTS downcounter
To the Slave mode controller

ETP ETPS[1:0] ETF[3:0]

TIMx_SMCR TIMx_SMCR TIMx_SMCR
MS34403V2

The ETR input comes from multiple sources: input pins (default configuration) and analog
watchdogs. The selection is done with the ETRSEL[3:0] bitfield.

Figure 77. TIM1 ETR input circuitry

TIM1_AF1[17:14]

ETR inputs from AF controller

ADC1 AWD1
ADC1 AWD2
ADC1 AWD3

ETR input

NC

MSv50978V1

RM0454 Rev 5 353/989

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Advanced-control timer (TIM1) RM0454

15.3.5 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin
• External clock mode2: external trigger input ETR
• Encoder mode

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 78 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 78. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

354/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Figure 79. TI2 external clock connection example

TIMx_SMCR
TS[4:0]

or TI2F or
TI1F or Encoder
ITRx mode
000xx
TIMx_CH2 TI1_ED TRGI External clock
00100
TI1FP1 00101 mode 1 CK_PSC
TI2[0]
TI2F_Rising
TI2 Edge 0 TI2FP2 00110 ETRF External clock
TI2[1..15] Filter
detector 1 ETRF 00111 mode 2
TI2F_Falling
(1) CK_INT Internal clock
ICF[3:0] CC2P (internal clock) mode
TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR
MSv40117V1

1. Codes ranging from 01000 to 11111 are reserved

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
6. Select TI2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register.
7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so the user does not need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

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Figure 80. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 81 gives an overview of the external trigger input block.

Figure 81. External trigger input block

or TI2F or
TI1F or Encoder
mode
TIMx_AF1[17:14]
TRGI
External clock
ETR pin ETR mode 1 CK_PSC
0
Divider ETRP ETRF External clock
Filter
1 /1, /2, /4, /8 f downcounter mode 2
(1) DTS

CK_INT Internal clock

ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ECE SMS[2:0]
TIMx_SMCR
MSv40118V1

1. Refer to Figure 77: TIM1 ETR input circuitry.

For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:

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RM0454 Advanced-control timer (TIM1)

1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency
which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When
the ETRP signal is faster, the user should apply a division of the external signal by proper
ETPS prescaler setting.

Figure 82. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_CNT =CK_PSC

Counter register 34 35 36

MSv33111V3

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15.3.6 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler,
except for channels 5 and 6) and an output stage (with comparator and output control).
Figure 83 to Figure 86 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 83. Capture/compare channel (example: channel 1 input stage)

TIMx_TISEL[3:0]

TI1F_ED
TI1[0]
TIMx_CH1 To the slave mode controller

TI1[1..15]
Filter TI1F_Rising
downcounter TI1F Edge 0 TI1FP1
fDTS TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10 /1, /2, /4, /8
ICF[3:0] CC1P/CC1NP
TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MSv40120V2

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 84. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
(from time TIMx_CCMR1
Comparator
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

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Figure 85. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)

TIMx_SMCR
OCCS
OCREF_CLR To the master mode
0
controller
ETRF 0 Output
1 OC1
enable
‘0’ 1
x0 circuit
ocref_clr_int OC1REF OC1REFC
01
OC1_DT CC1P
CNT>CCR1 Output 11
Output Dead-time TIM1_CCER
mode
CNT=CCR1 selector generator
controller OC1N_DT
11
10 0
(1) Output OC1N
OCxREF ‘0’ 0x enable
OC5REF 1 circuit

CC1NE CC1E TIM1_CCER

OC1CE OC1M[3:0] DTG[7:0] CC1NE CC1E CC1NP MOE OSSI OSSR

TIM1_CCMR1 TIM1_BDTR TIM1_CCER TIM1_CCER TIM1_BDTR

OIS1 OIS1N
TIM1_CR2
MS31199V2

1. OCxREF, where x is the rank of the complementary channel

Figure 86. Output stage of capture/compare channel (channel 4)

TIMx_SMCR
OCCS

OCREF_CLR 0 To the master

mode controller
ETRF 1
OC4REFC
ocref_clr_int OC4REF
‘0’ 0 0
CNT > CCR4 Output OC4
Output enable
mode Output 1 1
CNT = CCR4 circuit
controller selector

CC4E CC4P
OC3REF
TIM1_CCER TIM1_CCER CC4E TIM1_CCER

OC4CE OC4M[3:0] MOE OSSI TIM1_BDTR

TIM1_CCMR2
OIS4 TIM1_CR2
MS33100V2

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Figure 87. Output stage of capture/compare channel (channel 5, idem ch. 6)

TIMx_SMCR
OCCS

OCREF_CLR 0 To the master

mode controller
ETRF 1

ocref_clr_int
‘0’ 0 0 (1)
CNT > CCR5 Output OC5
Output enable
OC5REF
mode 1 1 circuit
CNT = CCR5
controller
CC5E CC5P
TIM1_CCER TIM1_CCER CC5E TIM1_CCER
OC5CE OC5M[3:0]
MOE OSSI TIM1_BDTR
TIM1_CCMR2
OIS5 TIM1_CR2
MS33101V2

1. Not available externally.

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

15.3.7 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when written with ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
3. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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RM0454 Advanced-control timer (TIM1)

detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
4. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
bits to 0 in the TIMx_CCER register (rising edge in this case).
5. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
6. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
7. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

15.3.8 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle
(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure
(depending on CK_INT frequency and prescaler value):

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1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).
4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
and CC2NP bits to CC2P/CC2NP=’10’ (active on falling edge).
6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register
(TI1FP1 selected).
7. Configure the slave mode controller in reset mode: write the SMS bits to 0100 in the
TIMx_SMCR register.
8. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 88. PWM input mode timing

15.3.9 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, user just needs to
write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is
forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity
bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the
TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

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15.3.10 Output compare mode

This function is used to control an output waveform or indicate when a period of time has
elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the
device (for instance, for compound waveform generation or for ADC triggering).
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=0000), be set
active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on
match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).

Procedure
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 89.

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Figure 89. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

15.3.11 PWM mode

Pulse Width Modulation mode allows a signal to be generated with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

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RM0454 Advanced-control timer (TIM1)

PWM edge-aligned mode

• Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 340.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 90 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.

Figure 90. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

• Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 344
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

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TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 347.
Figure 91 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

Figure 91. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

Hints on using center-aligned mode

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit

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in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

15.3.12 Asymmetric PWM mode

Asymmetric mode allows two center-aligned PWM signals to be generated with a
programmable phase shift. While the frequency is determined by the value of the
TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of
TIMx_CCRx register. One register controls the PWM during up-counting, the second during
down counting, so that PWM is adjusted every half PWM cycle:
– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
Asymmetric PWM mode can be selected independently on two channel (one OCx output
per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’
(Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
When a given channel is used as asymmetric PWM channel, its complementary channel
can also be used. For instance, if an OC1REFC signal is generated on channel 1
(Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2,
or an OC2REFC signal resulting from asymmetric PWM mode 1.
Figure 92 represents an example of signals that can be generated using Asymmetric PWM
mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Together with the
deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be
controlled.

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Figure 92. Generation of 2 phase-shifted PWM signals with 50% duty cycle

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OC1REFC
CCR1=0
CCR2=8
OC3REFC
CCR3=3
CCR4=5

MS33117V1

15.3.13 Combined PWM mode

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with
programmable delay and phase shift between respective pulses. While the frequency is
determined by the value of the TIMx_ARR register, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or
AND logical combination of two reference PWMs:
– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
Combined PWM mode can be selected independently on two channels (one OCx output per
pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM
mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as combined PWM channel, its complementary channel must
be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and
the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 93 represents an example of signals that can be generated using Asymmetric PWM
mode, obtained with the following configuration:
– Channel 1 is configured in Combined PWM mode 2,
– Channel 2 is configured in PWM mode 1,
– Channel 3 is configured in Combined PWM mode 2,
– Channel 4 is configured in PWM mode 1.

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RM0454 Advanced-control timer (TIM1)

Figure 93. Combined PWM mode on channel 1 and 3

OC2’
OC1’

OC2

OC1

OC1REF
OC2REF

OC1REF’
OC2REF’

OC1REFC

OC1REFC’

OC1REFC = OC1REF AND OC2REF

OC1REFC’ = OC1REF’ OR OC2REF’

MS31094V1

15.3.14 Combined 3-phase PWM mode

Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be
generated with a single programmable signal ANDed in the middle of the pulses. The
OC5REF signal is used to define the resulting combined signal. The 3-bits GC5C[3:1] in the
TIMx_CCR5 allow selection on which reference signal the OC5REF is combined. The
resulting signals, OCxREFC, are made of an AND logical combination of two reference
PWMs:
– If GC5C1 is set, OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5
– If GC5C2 is set, OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5
– If GC5C3 is set, OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5
Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting
at least one of the 3-bits GC5C[3:1].

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Figure 94. 3-phase combined PWM signals with multiple trigger pulses per period

ARR
OC5
OC6
OC1
OC4
OC2

OC3
Counter

OC5ref

OC1refC

OC2refC
GC5C[3:0]

OC3refC

Preload 100 xxx xxx

Active 001 100

OC4ref

OC6ref

TRGO2

MS33102V1

The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM
signals. Refer to Section 15.3.27: ADC synchronization for more details.

15.3.15 Complementary outputs and dead-time insertion

The advanced-control timers (TIM1) can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and it has to be adjusted depending on the
devices that are connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
The polarity of the outputs (main output OCx or complementary OCxN) can be selected
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 70: Output control bits for complementary OCx and OCxN channels with break feature
on page 416 for more details. In particular, the dead-time is activated when switching to the
idle state (MOE falling down to 0).

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Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
• The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
• The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

Figure 95. Complementary output with dead-time insertion

OCxREF

OCx
delay
OCxN
delay

MS31095V1

Figure 96. Dead-time waveforms with delay greater than the negative pulse

OCxREF

OCx

delay
OCxN

MS31096V1

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Figure 97. Dead-time waveforms with delay greater than the positive pulse

OCxREF

OCx

OCxN

delay

MS31097V1

The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 15.4.20: TIM1 break and dead-time
register (TIM1_BDTR) for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows a specific waveform to be sent (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

15.3.16 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals
generated with the TIM1 timer. The two break inputs are usually connected to fault outputs
of power stages and 3-phase inverters. When activated, the break circuitry shuts down the
PWM outputs and forces them to a predefined safe state. A number of internal MCU events
can also be selected to trigger an output shut-down.
The break features two channels. A break channel which gathers both system-level fault
(clock failure, parity error,...) and application fault (from input pins), and can force the
outputs to a predefined level (either active or inactive) after a deadtime duration. A break2
channel which only includes application faults and is able to force the outputs to an inactive
state.

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The output enable signal and output levels during break are depending on several control
bits:
– the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by
software and is reset in case of break or break2 event.
– the OSSI bit in the TIMx_BDTR register defines whether the timer controls the
output in inactive state or releases the control to the GPIO controller (typically to
have it in Hi-Z mode)
– the OISx and OISxN bits in the TIMx_CR2 register which are setting the output
shut-down level, either active or inactive. The OCx and OCxN outputs cannot be
set both to active level at a given time, whatever the OISx and OISxN values.
Refer to Table 70: Output control bits for complementary OCx and OCxN channels
with break feature on page 416 for more details.
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
functions can be enabled by setting the BKE and BK2E bits in the TIMx_BDTR register. The
break input polarities can be selected by configuring the BKP and BK2P bits in the same
register. BKE/BK2E and BKP/BK2P can be modified at the same time. When the BKE/BK2E
and BKP/BK2P bits are written, a delay of 1 APB clock cycle is applied before the writing is
effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the
bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
The break can be generated from multiple sources which can be individually enabled and
with programmable edge sensitivity, using the TIMx_OR2 and TIMx_OR3 registers.
The sources for break (BRK) channel are:
• An external source connected to one of the BKIN pin (as per selection done in the
AFIO controller), with polarity selection and optional digital filtering
• An internal source:
– the Cortex®-M0+ LOCKUP output
– the SRAM parity error signal
– a Flash memory ECC dual error detection
– a clock failure event generated by the CSS detector
The source for break2 (BRK2) is an external source connected to one of the BKIN pin (as
per selection done in the AFIO controller), with polarity selection and optional digital filtering.
Break events can also be generated by software using BG and B2G bits in the TIMx_EGR
register. The software break generation using BG and B2G is active whatever the BKE and
BK2E enable bits values.
All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 98
below.

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Figure 98. Break and Break2 circuitry overview

Lockup LOCK
Core Lockup

System break requests

SBIF flag

Parity LOCK
RAM parity Error

ECC LOCK
Double ECC Error

CSS
Software break requests: BG

BIF flag
BKE

BKINP BKF[3:0] BKP BRK request

BKIN inputs BKINE
from AF Filter
controller

Application break requests

Software break requests: B2G

B2IF flag
BK2E

BK2INP BK2F[3:0] BK2P

BRK2 request
BKIN2 inputs BK2INE
from AF
Filter
controller

Application break requests

MSv50979V2

Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or
the CSS) must be used to guarantee that break events are handled.
When one of the breaks occurs (selected level on one of the break inputs):
• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or even releasing the control to the GPIO controller (selected by the OSSI bit). This
feature is enabled even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control
(taken over by the GPIO controller), otherwise the enable output remains high.
• When complementary outputs are used:
– The outputs are first put in inactive state (depending on the polarity). This is done
asynchronously so that it works even if no clock is provided to the timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their

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active level together. Note that because of the resynchronization on MOE, the
dead-time duration is slightly longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0, the timer releases the output control (taken over by the GPIO controller
which forces a Hi-Z state), otherwise the enable outputs remain or become high as
soon as one of the CCxE or CCxNE bits is high.
• The break status flag (SBIF, BIF and B2IF bits in the TIMx_SR register) is set. An
interrupt is generated if the BIE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event (UEV). As an example, this can be used to perform a
regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this
case, it can be used for security and the break input can be connected to an alarm from
power drivers, thermal sensors or any security components.
Note: The break inputs are active on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF
cannot be cleared.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows the configuration
of several parameters to be freezed (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The application can
choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register.
Refer to Section 15.4.20: TIM1 break and dead-time register (TIM1_BDTR). The LOCK bits
can be written only once after an MCU reset.
Figure 99 shows an example of behavior of the outputs in response to a break.

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Figure 99. Various output behavior in response to a break event on BRK (OSSI = 1)

BREAK (MOE )

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

OCx

OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

MS31098V1

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The two break inputs have different behaviors on timer outputs:

– The BRK input can either disable (inactive state) or force the PWM outputs to a
predefined safe state.
– BRK2 can only disable (inactive state) the PWM outputs.
The BRK has a higher priority than BRK2 input, as described in Table 66.
Note: BRK2 must only be used with OSSR = OSSI = 1.

Table 66. Behavior of timer outputs versus BRK/BRK2 inputs

Typical use case
Timer outputs
BRK BRK2
state OCxN output OCx output
(low side switches) (high side switches)

– Inactive then
forced output
state (after a
deadtime)
ON after deadtime
Active X – Outputs disabled OFF
insertion
if OSSI = 0
(control taken
over by GPIO
logic)
Inactive Active Inactive OFF OFF

Figure 100 gives an example of OCx and OCxN output behavior in case of active signals on
BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP =
CCxNP = 0 in TIMx_CCER register).

Figure 100. PWM output state following BRK and BRK2 pins assertion (OSSI=1)

BRK2

BRK

OCx
Deadtime Deadtime

I/O state

Active Inactive Idle

MS34106V1

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Figure 101. PWM output state following BRK assertion (OSSI=0)

BRK

OCx I/O state defined by the GPIO controller (HI-Z)

Deadtime

I/O state I/O state defined by the GPIO controller (HI-Z)

Active Inactive Disabled

MS34107V1

15.3.17 Bidirectional break inputs

The TIM1 are featuring bidirectional break I/Os, as represented on Figure 102.
They allow the following:
• A board-level global break signal available for signaling faults to external MCUs or gate
drivers, with a unique pin being both an input and an output status pin
• Internal break sources and multiple external open drain comparator outputs ORed
together to trigger a unique break event, when multiple internal and external break
sources must be merged
The break and break2 inputs are configured in bidirectional mode using the BKBID and
BK2BID bits in the TIMxBDTR register. The BKBID programming bits can be locked in read-
only mode using the LOCK bits in the TIMxBDTR register (in LOCK level 1 or above).
The bidirectional mode is available for both the break and break2 inputs, and require the I/O
to be configured in open-drain mode with active low polarity (using BKINP, BKP, BK2INP
and BK2P bits). Any break request coming either from system (e.g. CSS), from on-chip
peripherals or from break inputs forces a low level on the break input to signal the fault
event. The bidirectional mode is inhibited if the polarity bits are not correctly set (active high
polarity), for safety purposes.
The break software events (BG and B2G) also cause the break I/O to be forced to '0' to
indicate to the external components that the timer has entered in break state. However, this
is valid only if the break is enabled (BK(2)E = 1). When a software break event is generated
with BK(2)E = 0, the outputs are put in safe state and the break flag is set, but there is no
effect on the break(2) I/O.
A safe disarming mechanism prevents the system to be definitively locked-up (a low level on
the break input triggers a break which enforces a low level on the same input).
When the BKDSRM (BK2DSRM) bit is set to 1, this releases the break output to clear a fault
signal and to give the possibility to re-arm the system.
At no point the break protection circuitry can be disabled:
• The break input path is always active: a break event is active even if the BKDSRM
(BK2DSRM) bit is set and the open drain control is released. This prevents the PWM
output to be re-started as long as the break condition is present.
• The BK(2)DSRM bit cannot disarm the break protection as long as the outputs are
enabled (MOE bit is set) (see Table 67)

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Table 67. Break protection disarming conditions

BKDIR BKDSRM
MOE Break protection state
(BK2DIR) (BK2DSRM)

0 0 X Armed
0 1 0 Armed
0 1 1 Disarmed
1 X X Armed

Arming and re-arming break circuitry

The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset
configuration).
The following procedure must be followed to re-arm the protection after a break (break2)
event:
• The BKDSRM (BK2DSRM) bit must be set to release the output control
• The software must wait until the system break condition disappears (if any) and clear
the SBIF status flag (or clear it systematically before re-arming)
• The software must poll the BKDSRM (BK2DSRM) bit until it is cleared by hardware
(when the application break condition disappears)
From this point, the break circuitry is armed and active, and the MOE bit can be set to re-
enable the PWM outputs.

Figure 102. Output redirection (BRK2 request not represented)

System break request
SBIF flag
Software break
requests: BG

Peripheral BKE BIF flag

Other break inputs
break sources BKF[3:0] BKP BRK
request
AF input Filter
AF
(active low)
controller
Bidirectional BKIN inputs from Application break requests
Break I/O AF controller

AF output
(open drain)

Bidirectional System break request

mode control logic
Vss
BRK request

MOE BKBID BKBDSRM

MSv42028V2

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15.3.18 Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
OCxREF remains low until the next update event (UEV) occurs. This function can only be
used in Output compare and PWM modes. It does not work in Forced mode. ocref_clr_int
input can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by
configuring the OCCS bit in the TIMx_SMCR register.
When ETRF is chosen, ETR must be configured as follows:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 103 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.

Figure 103. Clearing TIMx OCxREF

(CCRx)
Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

ocref_clr_int ocref_clr_int
becomes high still high
MS33105V2

Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.

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15.3.19 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus one can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
The Figure 104 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.

Figure 104. 6-step generation, COM example (OSSR=1)

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15.3.20 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
• In downcounting: CNT > CCRx

Figure 105. Example of one pulse mode.

TI2

OC1REF
OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY tPULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
1. Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
3. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=00110
in the TIMx_SMCR register.
5. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
• Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

15.3.21 Retriggerable one pulse mode

This mode allows the counter to be started in response to a stimulus and to generate a
pulse with a programmable length, but with the following differences with Non-retriggerable
one pulse mode described in Section 15.3.20:
– The pulse starts as soon as the trigger occurs (no programmable delay)
– The pulse is extended if a new trigger occurs before the previous one is completed
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger
mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for
Retrigerrable OPM mode 1 or 2.
If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0
(the ARR register sets the pulse length). If the timer is configured in Down-counting mode,
CCRx must be above or equal to ARR.
Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit are not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.

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Figure 106. Retriggerable one pulse mode

TRGI

Counter

Output

MS33106V1

15.3.22 Encoder interface mode

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, the input filter can be programmed as well. CC1NP and CC2NP
must be kept low.
The two inputs TI1 and TI2 are used to interface to a quadrature encoder. Refer to Table 68.
The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input
filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not
filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written
to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count
pulses as well as the direction signal. Depending on the sequence the counter counts up or
down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit
is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on
TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
Note: The prescaler must be set to zero when encoder mode is enabled
In this mode, the counter is modified automatically following the speed and the direction of
the quadrature encoder and its content, therefore, always represents the encoder’s position.
The count direction correspond to the rotation direction of the connected sensor. The table
summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same
time.

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Table 68. Counting direction versus encoder signals

Level on TI1FP1 signal TI2FP2 signal
opposite
signal (TI1FP1
Active edge
for TI2,
Rising Falling Rising Falling
TI2FP2 for
TI1)

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

A quadrature encoder can be connected directly to the MCU without external interface logic.
However, comparators are normally be used to convert the encoder’s differential outputs to
digital signals. This greatly increases noise immunity. The third encoder output which
indicate the mechanical zero position, may be connected to an external interrupt input and
trigger a counter reset.
The Figure 107 gives an example of counter operation, showing count signal generation
and direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
• CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
• CC1P=’0’ and CC1NP=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
• CC2P=’0’ and CC2NP=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
• SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
• CEN=’1’ (TIMx_CR1 register, Counter enabled).

Figure 107. Example of counter operation in encoder interface mode.

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

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Figure 108 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).

Figure 108. Example of encoder interface mode with TI1FP1 polarity inverted.

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request.
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update
interrupt flag (UIF) into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both
the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read
in an atomic way. It eases the calculation of angular speed by avoiding race conditions
caused, for instance, by a processing shared between a background task (counter reading)
and an interrupt (update interrupt).
There is no latency between the UIF and UIFCPY flag assertions.
In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is
overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only
accessible in write mode).

15.3.23 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both
the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read
in an atomic way. In particular cases, it can ease the calculations by avoiding race
conditions, caused for instance by a processing shared between a background task
(counter reading) and an interrupt (Update Interrupt).
There is no latency between the UIF and UIFCPY flags assertion.

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RM0454 Advanced-control timer (TIM1)

15.3.24 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. It is convenient to measure the interval between edges on two input signals, as per
Figure 109 below.

Figure 109. Measuring time interval between edges on 3 signals

TI1
TI2

TI3

XOR

TIMx
Counter

MS33109V1

15.3.25 Interfacing with Hall sensors

This is done using the advanced-control timer (TIM1) to generate PWM signals to drive the
motor and another timer TIMx (TIM3, TIM4(a)) referred to as “interfacing timer” in
Figure 110. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3)
connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the
TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (See Figure 83: Capture/compare channel (example: channel 1 input
stage) on page 358). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM
event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the
interfacing timer channel must be programmed so that a positive pulse is generated after a
programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-
control timer (TIM1) through the TRGO output.

a. TIM4 is available on STM32G0B0xx salestypes only.

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Example: one wants to change the PWM configuration of the advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one of
the TIMx timers.
• Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,
• Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
• Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘01’. The digital filter can also be programmed if needed,
• Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to
‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,
• Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the
timer is programmed to generate PWM signals, the capture/compare control signals are
preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are
written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF).
The Figure 110 describes this example.

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RM0454 Advanced-control timer (TIM1)

Figure 110. Example of Hall sensor interface

TIH1

TIH2
Interfacing timer

TIH3

Counter (CNT)

(CCR2)

CCR1 C7A3 C7A8 C794 C7A5 C7AB C796

TRGO=OC2REF

COM

OC1
Advanced-control timers (TIM1)

OC1N

OC2

OC2N

OC3

OC3N

Write CCxE, CCxNE

and OCxM for next step

MS32672V1

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15.3.26 Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 16.3.19: Timer synchronization for details. They can be synchronized in several
modes: Reset mode, Gated mode, and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
• Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 111. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V1

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 112. Control circuit in Gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC2S bits
are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1

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register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity
(and detect low level only).
• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=00110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 113. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

Slave mode: Combined reset + trigger mode

In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter,
generates an update of the registers, and starts the counter.
This mode is used for one-pulse mode.

Slave mode: external clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.

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RM0454 Advanced-control timer (TIM1)

In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS = 00: prescaler disabled
– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F = 0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S = 01in TIMx_CCMR1 register to select only the input capture source
– CC1P = 0 and CC1NP = 0 in TIMx_CCER register to validate the polarity (and
detect rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 114. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.

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15.3.27 ADC synchronization

The timer can generate an ADC triggering event with various internal signals, such as reset,
enable or compare events. It is also possible to generate a pulse issued by internal edge
detectors, such as:
– Rising and falling edges of OC4ref
– Rising edge on OC5ref or falling edge on OC6ref
The triggers are issued on the TRGO2 internal line which is redirected to the ADC. There is
a total of 16 possible events, which can be selected using the MMS2[3:0] bits in the
TIMx_CR2 register.
An example of an application for 3-phase motor drives is given in Figure 94 on page 370.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
Note: The clock of the ADC must be enabled prior to receive events from the master timer, and
must not be changed on-the-fly while triggers are received from the timer.

15.3.28 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event.
The main purpose is to be able to re-program part of the timer multiple times without
software overhead, but it can also be used to read several registers in a row, at regular
intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.
On a given timer event, the timer launches a sequence of DMA requests (burst). Each write
into the TIMx_DMAR register is actually redirected to one of the timer registers.
The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the
number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA
transfers (when read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register:
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
As an example, the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the
CCRx registers.

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This is done in the following steps:

1. Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.

15.3.29 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.
For safety purposes, when the counter is stopped, the outputs are disabled (as if the MOE
bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have
their control taken over by the GPIO controller (OSSI bit = 0), typically to force a Hi-Z.
For more details, refer to section Debug support (DBG).

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15.4 TIM1 registers

Refer to for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

15.4.1 TIM1 control register 1 (TIM1_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
MAP
rw rw rw rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx):
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set both when the counter is counting up or down.
Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is
enabled (CEN=1) is not allowed

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Bit 4 DIR: Direction

0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit
is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.

15.4.2 TIM1 control register 2 (TIM1_CR2)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. MMS2[3:0] Res. OIS6 Res. OIS5
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 MMS2[3:0]: Master mode selection 2
These bits allow the information to be sent to ADC for synchronization (TRGO2) to be
selected. The combination is as follows:
0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If
the reset is generated by the trigger input (slave mode controller configured in reset
mode), the signal on TRGO2 is delayed compared to the actual reset.
0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is
useful to start several timers at the same time or to control a window in which a slave
timer is enabled. The Counter Enable signal is generated by a logic AND between the
CEN control bit and the trigger input when configured in Gated mode. When the
Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2,
except if the Master/Slave mode is selected (see the MSM bit description in
TIMx_SMCR register).
0010: Update - the update event is selected as trigger output (TRGO2). For instance, a
master timer can then be used as a prescaler for a slave timer.
0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to
be set (even if it was already high), as soon as a capture or compare match occurs
(TRGO2).
0100: Compare - OC1REFC signal is used as trigger output (TRGO2)
0101: Compare - OC2REFC signal is used as trigger output (TRGO2)
0110: Compare - OC3REFC signal is used as trigger output (TRGO2)
0111: Compare - OC4REFC signal is used as trigger output (TRGO2)
1000: Compare - OC5REFC signal is used as trigger output (TRGO2)
1001: Compare - OC6REFC signal is used as trigger output (TRGO2)
1010: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
1011: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
1100: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
1101: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on
TRGO2
1110: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
1111: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on
TRGO2
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bit 19 Reserved, must be kept at reset value.
Bit 18 OIS6: Output Idle state 6 (OC6 output)
Refer to OIS1 bit
Bit 17 Reserved, must be kept at reset value.
Bit 16 OIS5: Output Idle state 5 (OC5 output)
Refer to OIS1 bit
Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4: Output Idle state 4 (OC4 output)
Refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
Refer to OIS1N bit

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Bit 12 OIS3: Output Idle state 3 (OC3 output)

Refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
Refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
Refer to OIS1 bit
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow selected information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic AND between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the
master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REFC signal is used as trigger output (TRGO)
101: Compare - OC2REFC signal is used as trigger output (TRGO)
110: Compare - OC3REFC signal is used as trigger output (TRGO)
111: Compare - OC4REFC signal is used as trigger output (TRGO)
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs

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Bit 2 CCUS: Capture/compare control update selection

0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.

15.4.3 TIM1 slave mode control register (TIM1_SMCR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] OCCS SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=00111).
It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 00111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.

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Bits 13:12 ETPS[1:0]: External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if
we want to synchronize several timers on a single external event.
Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
00000: Internal Trigger 0 (ITR0)
00001: Internal Trigger 1 (ITR1)
00010: Internal Trigger 2 (ITR2)
00011: Internal Trigger 3 (ITR3)
00100: TI1 Edge Detector (TI1F_ED)
00101: Filtered Timer Input 1 (TI1FP1)
00110: Filtered Timer Input 2 (TI2FP2)
00111: External Trigger input (ETRF)
Others: Reserved
See Table 69: TIM1 internal trigger connection on page 402 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection
This bit is used to select the OCREF clear source.
0: OCREF_CLR_INT is not connected (reserved configuration)
1: OCREF_CLR_INT is connected to ETRF

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Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Codes above 1000: Reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.

Table 69. TIM1 internal trigger connection

Slave TIM ITR0 (TS = 00000) ITR1 (TS = 00001) ITR2 (TS = 00010) ITR3 (TS = 00011)

TIM1 TIM15 Not connected TIM3 TIM17 OC1

15.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled

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Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

15.4.5 TIM1 status register (TIM1_SR)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6IF CC5IF
rc_w0 rc_w0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. SBIF CC4OF CC3OF CC2OF CC1OF B2IF BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 CC6IF: Compare 6 interrupt flag
Refer to CC1IF description (Note: Channel 6 can only be configured as output)
Bit 16 CC5IF: Compare 5 interrupt flag
Refer to CC1IF description (Note: Channel 5 can only be configured as output)
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 SBIF: System Break interrupt flag
This flag is set by hardware as soon as the system break input goes active. It can be
cleared by software if the system break input is not active.
This flag must be reset to re-start PWM operation.
0: No break event occurred.
1: An active level has been detected on the system break input. An interrupt is generated if
BIE=1 in the TIMx_DIER register.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Refer to CC1OF description

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Bit 9 CC1OF: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 B2IF: Break 2 interrupt flag
This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by
software if the break 2 input is not active.
0: No break event occurred.
1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1
in the TIMx_DIER register.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in
the TIMx_DIER register.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode. It is set when the
counter starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare
mode) or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred.
If channel CC1 is configured as output: this flag is set when he content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer
to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

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Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 15.4.3: TIM1 slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

15.4.6 TIM1 event generation register (TIM1_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. B2G BG TG COMG CC4G CC3G CC2G CC1G UG
w w w w w w w w w

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 B2G: Break 2 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt
can occur if enabled.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
Refer to CC1G description

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Bit 2 CC2G: Capture/Compare 2 generation

Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. The prescaler internal
counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the
center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

15.4.7 TIM1 capture/compare mode register 1 [alternate]

(TIM1_CCMR1)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function for input capture and for
output compare modes. It is possible to combine both modes independently (e.g. channel 1
in input capture mode and channel 2 in output compare mode).
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F[3:0] IC2PSC[1:0] CC2S[1:0] IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0]: Input capture 2 filter
Refer to IC1F[3:0] description.
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Refer to IC1PSC[1:0] description.

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Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N consecutive events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as
soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

15.4.8 TIM1 capture/compare mode register 1 [alternate]

(TIM1_CCMR1)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the

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RM0454 Advanced-control timer (TIM1)

corresponding CCxS bits. All the other bits of this register have a different function for input
capture and for output compare modes. It is possible to combine both modes independently
(e.g. channel 1 in input capture mode and channel 2 in output compare mode).
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. OC1M[3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC2 OC1 OC1 OC1
OC2M[2:0] CC2S[1:0] OC1M[2:0] CC1S[1:0]
CE PE FE CE PE FE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC2CE: Output Compare 2 clear enable
Refer to OC1CE description.
Bits 24, 14:12 OC2M[3:0]: Output Compare 2 mode
Refer to OC1M[3:0] description.
Bit 11 OC2PE: Output Compare 2 preload enable
Refer to OC1PE description.
Bit 10 OC2FE: Output Compare 2 fast enable
Refer to OC1FE description.
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
0: OC1Ref is not affected by the ocref_clr_int signal
1: OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal
(OCREF_CLR input or ETRF input)

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Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a
timing base).
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger
event is detected (on TRGI signal). Then, a comparison is performed as in PWM
mode 1 and the channels becomes active again at the next update. In down-counting
mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then,
a comparison is performed as in PWM mode 1 and the channels becomes inactive
again at the next update.
1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a
trigger event is detected (on TRGI signal). Then, a comparison is performed as in
PWM mode 2 and the channels becomes inactive again at the next update. In down-
counting mode, the channel is active until a trigger event is detected (on TRGI
signal). Then, a comparison is performed as in PWM mode 1 and the channels
becomes active again at the next update.
1010: Reserved,
1011: Reserved,
1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.
OC1REFC is the logical OR between OC1REF and OC2REF.
1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.
OC1REFC is the logical AND between OC1REF and OC2REF.
1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.
OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is
counting down.
1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.
OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is
counting down.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note: In PWM mode, the OCREF level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM”
mode.
Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit
is set in the TIMx_CR2 register then the OC1M active bits take the new value from the
preloaded bits only when a COM event is generated.
Note: The OC1M[3] bit is not contiguous, located in bit 16.

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Bit 3 OC1PE: Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE
acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

15.4.9 TIM1 capture/compare mode register 2 [alternate]

(TIM1_CCMR2)
Address offset: 0x1C
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function for input capture and for
output compare modes. It is possible to combine both modes independently (e.g. channel 1
in input capture mode and channel 2 in output compare mode).
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F[3:0] IC4PSC[1:0] CC4S[1:0] IC3F[3:0] IC3PSC[1:0] CC3S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC4F[3:0]: Input capture 4 filter
Refer to IC1F[3:0] description.
Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler
Refer to IC1PSC[1:0] description.
Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bits 7:4 IC3F[3:0]: Input capture 3 filter
Refer to IC1F[3:0] description.
Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler
Refer to IC1PSC[1:0] description.
Bits 1:0 CC3S[1:0]: Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

15.4.10 TIM1 capture/compare mode register 2 [alternate]

(TIM1_CCMR2)
Address offset: 0x1C
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function for input
capture and for output compare modes. It is possible to combine both modes independently
(e.g. channel 1 in input capture mode and channel 2 in output compare mode).
Output compare mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Res. OC3M[3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4 OC4 OC4 OC3 OC3 OC3
OC4M[2:0] CC4S[1:0] OC3M[2:0] CC3S[1:0]
CE PE FE CE PE FE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0454 Advanced-control timer (TIM1)

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC4CE: Output compare 4 clear enable
Refer to OC1CE description.
Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode
Refer to OC3M[3:0] description.
Bit 11 OC4PE: Output compare 4 preload enable
Refer to OC1PE description.
Bit 10 OC4FE: Output compare 4 fast enable
Refer to OC1FE description.
Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Refer to OC1CE description.
Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode
Refer to OC1M[3:0] description.
Bit 3 OC3PE: Output compare 3 preload enable
Refer to OC1PE description.
Bit 2 OC3FE: Output compare 3 fast enable
Refer to OC1FE description.
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

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15.4.11 TIM1 capture/compare enable register

(TIM1_CCER)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP Res. CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 CC6P: Capture/Compare 6 output polarity
Refer to CC1P description
Bit 20 CC6E: Capture/Compare 6 output enable
Refer to CC1E description
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CC5P: Capture/Compare 5 output polarity
Refer to CC1P description
Bit 16 CC5E: Capture/Compare 5 output enable
Refer to CC1E description
Bit 15 CC4NP: Capture/Compare 4 complementary output polarity
Refer to CC1NP description
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output polarity
Refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable
Refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 complementary output polarity
Refer to CC1NP description
Bit 10 CC3NE: Capture/Compare 3 complementary output enable
Refer to CC1NE description
Bit 9 CC3P: Capture/Compare 3 output polarity
Refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable
Refer to CC1E description
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
Refer to CC1NP description
Bit 6 CC2NE: Capture/Compare 2 complementary output enable
Refer to CC1NE description

414/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Bit 5 CC2P: Capture/Compare 2 output polarity

Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to CC1P description.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (channel configured as output).
On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the
TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only
when a Commutation event is generated.
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the
TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only
when a Commutation event is generated.
Bit 1 CC1P: Capture/Compare 1 output polarity
0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity
of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising
and falling edges (capture or trigger operations in reset, external clock
or trigger mode), TIxFP1is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0: The configuration is reserved, it must not be used.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.

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Bit 0 CC1E: Capture/Compare 1 output enable

0: Capture mode disabled / OC1 is not active (see below)
1: Capture mode enabled / OC1 signal is output on the corresponding output pin
When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 70
for details.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
preloaded bit only when a Commutation event is generated.

Table 70. Output control bits for complementary OCx and OCxN channels with break feature
Control bits Output states(1)

MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state

Output disabled (not driven by the timer: Hi-Z)

X 0 0
OCx=0, OCxN=0
Output disabled (not driven
OCxREF + Polarity
0 0 1 by the timer: Hi-Z)
OCxN = OCxREF xor CCxNP
OCx=0
Output Disabled (not driven by
OCxREF + Polarity
0 1 0 the timer: Hi-Z)
OCx=OCxREF xor CCxP
OCxN=0
1 X
OCREF + Polarity + dead- Complementary to OCREF (not
X 1 1
time OCREF) + Polarity + dead-time
Off-State (output enabled
OCxREF + Polarity
1 0 1 with inactive state)
OCxN = OCxREF x or CCxNP
OCx=CCxP
Off-State (output enabled with
OCxREF + Polarity
1 1 0 inactive state)
OCx=OCxREF xor CCxP
OCxN=CCxNP
0 X X
Output disabled (not driven by the timer: Hi-Z).
0 0
0 1 Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCxN=CCxNP (if BRK or
1 0
BRK2 is triggered).
0 X
1 Then (this is valid only if BRK is triggered), if the clock is
present: OCx=OISx and OCxN=OISxN after a dead-time,
assuming that OISx and OISxN do not correspond to OCX
1 1
and OCxN both in active state (may cause a short circuit
when driving switches in half-bridge configuration).
Note: BRK2 can only be used if OSSI = OSSR = 1.
1. When both outputs of a channel are not used (control taken over by GPIO), the OISx, OISxN, CCxP and CCxNP bits must
be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.

416/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

15.4.12 TIM1 counter (TIM1_CNT)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UIFCPY: UIF copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value

15.4.13 TIM1 prescaler (TIM1_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

15.4.14 TIM1 auto-reload register (TIM1_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 15.3.1: Time-base unit on page 338 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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15.4.15 TIM1 repetition counter register (TIM1_RCR)

Address offset: 0x30
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 REP[15:0]: Repetition counter value

These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
the number of PWM periods in edge-aligned mode
the number of half PWM period in center-aligned mode.

15.4.16 TIM1 capture/compare register 1 (TIM1_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual
capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input: CR1 is the counter value transferred by the last
input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be
programmed.

418/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

15.4.17 TIM1 capture/compare register 2 (TIM1_CCR2)

Address offset: 0x38
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value

If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual
capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC2 output.
If channel CC2 is configured as input: CCR2 is the counter value transferred by the last
input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be
programmed.

15.4.18 TIM1 capture/compare register 3 (TIM1_CCR3)

Address offset: 0x3C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR3[15:0]: Capture/Compare value

If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual
capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.

If channel CC3 is configured as input: CCR3 is the counter value transferred by the last
input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be
programmed.

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15.4.19 TIM1 capture/compare register 4 (TIM1_CCR4)

Address offset: 0x40
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR4[15:0]: Capture/Compare value

If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual
capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input: CCR4 is the counter value transferred by the last
input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be
programmed.

15.4.20 TIM1 break and dead-time register

(TIM1_BDTR)
Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2 BK
Res. Res. BK2BID BKBID BK2P BK2E BK2F[3:0] BKF[3:0]
DSRM DSRM

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0],
AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK
configuration, it can be necessary to configure all of them during the first write access to the
TIMx_BDTR register.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 BK2BID: Break2 bidirectional
Refer to BKBID description

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RM0454 Advanced-control timer (TIM1)

Bit 28 BKBID: Break Bidirectional

0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 27 BK2DSRM: Break2 Disarm
Refer to BKDSRM description
Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 25 BK2P: Break 2 polarity
0: Break input BRK2 is active low
1: Break input BRK2 is active high
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 24 BK2E: Break 2 enable
0: Break input BRK2 disabled
1: Break input BRK2 enabled
Note: The BRK2 must only be used with OSSR = OSSI = 1.
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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Advanced-control timer (TIM1) RM0454

Bits 23:20 BK2F[3:0]: Break 2 filter

This bit-field defines the frequency used to sample BRK2 input and the length of the digital
filter applied to BRK2. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:
0000: No filter, BRK2 acts asynchronously
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample BRK input and the length of the digital
filter applied to BRK. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:
0000: No filter, BRK acts asynchronously
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).

422/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as one of the break inputs is active
(BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting
only on the channels which are configured in output.
0: In response to a break 2 event. OC and OCN outputs are disabled
In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled
or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details (Section 15.4.11: TIM1 capture/compare
enable register (TIM1_CCER)).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if none of the break
inputs BRK and BRK2 is active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
This bit enables the complete break protection (including all sources connected to bk_acth
and BKIN sources, as per Figure 98: Break and Break2 circuitry overview).
0: Break function disabled
1: Break function enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 15.4.11: TIM1 capture/compare
enable register (TIM1_CCER)).
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
is taken over by the GPIO logic, which forces a Hi-Z state).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).

RM0454 Rev 5 423/989

433
Advanced-control timer (TIM1) RM0454

Bit 10 OSSI: Off-state selection for Idle mode

This bit is used when MOE=0 due to a break event or by a software write, on channels
configured as outputs.
See OC/OCN enable description for more details (Section 15.4.11: TIM1 capture/compare
enable register (TIM1_CCER)).
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
is taken over by the GPIO logic and which imposes a Hi-Z state).
1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their
idle level after the deadtime. The timer maintains its control over the output.
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0],
AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer
be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x tDTG with tDTG = tDTS.
DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x tDTG with tDTG = 2 x tDTS.
DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 8 x tDTS.
DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 16 x tDTS.
Example if tDTS = 125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 μs to 31750 ns by 250 ns steps,
32 μs to 63 μs by 1 μs steps,
64 μs to 126 μs by 2 μs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

15.4.21 TIM1 DMA control register (TIM1_DCR)

Address offset: 0x48
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

424/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Bits 12:8 DBL[4:0]: DMA burst length

This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1.
– If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be
transferred, the address of the transfer should be given by the following equation:
(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL
In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the
address from/to which the data is copied. In this case, the transfer is done to 7 registers
starting from the following address: (TIMx_CR1 address) + DBA
According to the configuration of the DMA Data Size, several cases may occur:
– If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7
registers.
– If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the
first register contains the first MSB byte, the second register, the first LSB byte and so on.
So with the transfer Timer, one also has to specify the size of data transferred by DMA.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...

15.4.22 TIM1 DMA address for full transfer

(TIM1_DMAR)
Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0454 Rev 5 425/989

433
Advanced-control timer (TIM1) RM0454

Bits 31:0 DMAB[31:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

15.4.23 TIM1 capture/compare mode register 3

(TIM1_CCMR3)
Address offset: 0x54
Reset value: 0x0000 0000
The channels 5 and 6 can only be configured in output.
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. OC6M[3] Res. Res. Res. Res. Res. Res. Res. OC5M[3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6 OC6 OC5
OC6M[2:0] OC6FE Res. Res. OC5M[2:0] OC5PE OC5FE Res. Res.
CE PE CE
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC6CE: Output compare 6 clear enable
Refer to OC1CE description.
Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode
Refer to OC1M description.
Bit 11 OC6PE: Output compare 6 preload enable
Refer to OC1PE description.
Bit 10 OC6FE: Output compare 6 fast enable
Refer to OC1FE description.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 OC5CE: Output compare 5 clear enable
Refer to OC1CE description.
Bits 16, 6, 5, 4 OC5M[3:0]: Output compare 5 mode
Refer to OC1M description.
Bit 3 OC5PE: Output compare 5 preload enable
Refer to OC1PE description.
Bit 2 OC5FE: Output compare 5 fast enable
Refer to OC1FE description.
Bits 1:0 Reserved, must be kept at reset value.

426/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

15.4.24 TIM1 capture/compare register 5 (TIM1_CCR5)

Address offset: 0x58
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3 GC5C2 GC5C1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 GC5C3: Group Channel 5 and Channel 3

Distortion on Channel 3 output:
0: No effect of OC5REF on OC3REFC
1: OC3REFC is the logical AND of OC3REFC and OC5REF
This bit can either have immediate effect or be preloaded and taken into account after an
update event (if preload feature is selected in TIMxCCMR2).
Note: it is also possible to apply this distortion on combined PWM signals.
Bit 30 GC5C2: Group Channel 5 and Channel 2
Distortion on Channel 2 output:
0: No effect of OC5REF on OC2REFC
1: OC2REFC is the logical AND of OC2REFC and OC5REF
This bit can either have immediate effect or be preloaded and taken into account after an
update event (if preload feature is selected in TIMxCCMR1).
Note: it is also possible to apply this distortion on combined PWM signals.
Bit 29 GC5C1: Group Channel 5 and Channel 1
Distortion on Channel 1 output:
0: No effect of OC5REF on OC1REFC5
1: OC1REFC is the logical AND of OC1REFC and OC5REF
This bit can either have immediate effect or be preloaded and taken into account after an
update event (if preload feature is selected in TIMxCCMR1).
Note: it is also possible to apply this distortion on combined PWM signals.
Bits 28:16 Reserved, must be kept at reset value.
Bits 15:0 CCR5[15:0]: Capture/Compare 5 value
CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC5 output.

RM0454 Rev 5 427/989

433
Advanced-control timer (TIM1) RM0454

15.4.25 TIM1 capture/compare register 6 (TIM1_CCR6)

Address offset: 0x5C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR6[15:0]: Capture/Compare 6 value

CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC6 output.

15.4.26 TIM1 alternate function option register 1 (TIM1_AF1)

Address offset: 0x60
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL[1:0] Res. Res. Res. Res. BKINP Res. Res. Res. Res. Res. Res. Res. Res. BKINE
rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: ETR legacy mode
0011: ADC1 AWD1
0100: ADC1 AWD2
0101: ADC1 AWD3
Others: Reserved
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)
1: BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:1 Reserved, must be kept at reset value.

428/989 RM0454 Rev 5

RM0454 Advanced-control timer (TIM1)

Bit 0 BKINE: BRK BKIN input enable

This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is
‘ORed’ with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

Note: Refer to Figure 77: TIM1 ETR input circuitry and to Figure 98: Break and Break2 circuitry
overview.

15.4.27 TIM1 Alternate function register 2 (TIM1_AF2)

Address offset: 0x64
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BK2INE
INP
rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 BK2INP: BRK2 BKIN2 input polarity
This bit selects the BKIN2 alternate function input sensitivity. It must be programmed
together with the BK2P polarity bit.
0: BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
1: BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:1 Reserved, must be kept at reset value.
Bit 0 BK2INE: BRK2 BKIN input enable
This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is
‘ORed’ with the other BRK2 sources.
0: BKIN2 input disabled
1: BKIN2 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

Note: Refer to Figure 98: Break and Break2 circuitry overview.

RM0454 Rev 5 429/989

433
Advanced-control timer (TIM1) RM0454

15.4.28 TIM1 timer input selection register (TIM1_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TI4SEL[3:0] Res. Res. Res. Res. TI3SEL[3:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input
0000: TIM1_CH4 input
Others: Reserved
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input
0000: TIM1_CH3 input
Others: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input
0000: TIM1_CH2 input
Others: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM1_CH1 input
Others: Reserved

430/989 RM0454 Rev 5

 0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0454

15.4.29

mode
mode

Output
Output
name

TIM1_SR
TIM1_CR2
TIM1_CR1

TIM1_EGR
Register

TIM1_DIER

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM1_CCER
TIM1_SMCR

Input Capture
Input Capture

TIM1_CCMR2
TIM1_CCMR2
TIM1_CCMR1
TIM1_CCMR1

Compare mode
Compare mode
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
TIM1 register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
Res. Res. OC4M[3] Res. OC2M[3] Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 0
0 Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0

0
CC6P Res. Res. Res. Res. Res. Res. Res. TS Res. 21
MMS2[3:0]

[4:3]

0
0
0

CC6E Res. Res. Res. Res. Res. Res. Res. Res. 20

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. OIS6 Res. 18

0
0

RM0454 Rev 5
CC5P Res. Res. Res. Res. Res. CC6IF Res. Res. Res. Res. 17

0
0
0
0
0
0

CC5E Res. OC3M[3] Res. OC1M[3] Res. CC5IF Res. SMS[3] OIS5 Res. 16

0
0
0
0
0
0

CC4NP OC4CE OC2CE Res. Res. Res. ETP Res. Res. 15

0
0
0
0
0
0

Res. Res. Res. TDE ECE OIS4 Res. 14

0
0
0
0
0
0
0

0
0

CC4P Res. SBIF COMDE OIS3N Res. 13

[2:0]
[2:0]
S

IC4F[3:0]
IC2F[3:0]

OC4M
OC2M
[1:0]
ETP

0
0
0
0
0
0
0
0
0

CC4E Res. CC4OF CC4DE OIS3 Res. 12

0
0
0
0
0
0
0
0
0
0

CC3NP OC4PE OC2PE Res. CC3OF CC3DE OIS2N UIFREMAP 11

Table 71. TIM1 register map and reset values

IC4
IC2

[1:0]
[1:0]

PSC
PSC

0
0
0
0
0
0
0
0

CC3NE OC4FE OC2FE Res. CC2OF CC2DE OIS2 Res. 10

0
0
0
0
0
0
0
0
0
0

CC3P Res. CC1OF CC1DE OIS1N 9

ETF[3:0]

S
S
S
S

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]

CC4
CC4
CC2
CC2
CKD

0
0
0
0
0
0
0
0
0

0
0

CC3E B2G B2IF UDE OIS1 8

0
0
0
0
0
0
0
0

0
0

CC2NP OC3CE OC1CE BG BIF BIE MSM TI1S ARPE 7

0
0
0
0
0
0
0
0
0

0
0

CC2NE TG TIF TIE 6

[1:0]
CMS

0
0
0
0
0
0

0
0
0
0
0

CC2P COMG COMIF COMIE 5

[2:0]
[2:0]
[2:0]
MMS

IC3F[3:0]
IC1F[3:0]

OC3M
OC1M
TS[2:0]

0
0
0
0
0
0
0
0
0
0
0

CC2E CC4G CC4IF CC4IE DIR 4

0
0
0
0
0
0
0
0
0
0

CC1NP OC3PE OC1PE CC3G CC3IF CC3IE OCCS CCDS OPM 3

IC3
IC1

[1:0]
[1:0]

PSC
PSC

0
0
0
0
0
0
0
0
0
0
0

CC1NE OC3FE OC1FE CC2G CC2IF CC2IE CCUS URS 2

0
0
0
0
0
0
0
0
0
0

CC1P CC1G CC1IF CC1IE Res. UDIS 1

S
S
S
S

[1:0]
[1:0]
[1:0]
[1:0]

CC3
CC3
CC1
CC1

0
0
0
0
0
0

0
0
0
0

0
SMS[2:0]

CC1E UG UIF UIE CCPC CEN

TIM1 registers are mapped as 16-bit addressable registers as described in the table below:

0
Advanced-control timer (TIM1)

431/989
433
 0x58
0x54
0x50
0x48
0x44
0x40
0x38
0x34
0x30
0x28
0x24

0x4C
0x3C
0x2C
Offset

432/989
Output
name

Reserved
TIM1_PSC
TIM1_CNT

TIM1_DCR
TIM1_RCR
TIM1_ARR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM1_CCR5
TIM1_CCR4
TIM1_CCR3
TIM1_CCR2
TIM1_CCR1

TIM1_BDTR

TIM1_DMAR

TIM1_CCMR3

Compare mode

0
GC5C3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 UIFCP 31

0
GC5C2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
GC5C1 Res. Res. BK2BID Res. Res. Res. Res. Res. Res. Res. Res. 29

0
Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. BK2DSRM Res. Res. Res. Res. Res. Res. Res. Res.
Advanced-control timer (TIM1)

27

0
Res. Res. Res. BKDSRM Res. Res. Res. Res. Res. Res. Res. Res. 26

0
Res. Res. Res. BK2P Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
Res. OC6M[3] Res. BK2E Res. Res. Res. Res. Res. Res. Res. Res. 24

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

BK2F[3:0]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

BKF[3:0]

0
0
Res. OC5M[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0

0
0
0
0
0
0
1
0
0

OC6CE Res. MOE

Res.
15

DMAB[31:0]

0
0
0

0
0
0
0
0
0
1
0
0

Res. AOE 14

0
0
0

0
0
0
0
0
0
1
0
0

Res. BKP 13

[2:0]
OC6M

0
0
0

0
0
0
0
0
0
0
1
0
0

BKE 12

0
0
0

0
0
0
0
0
0
0
1
0
0

OC6PE OSSR 11

0
0
0

0
0
0
0
0
0
0
1
0
0

OC6FE OSSI 10

DBL[4:0]

0
0

0
0
0
0
0
0
0
1
0
0

Res. 9

K
[1:0]
LOC

0
0

0
0
0
0
0
0
0
1
0
0
Table 71. TIM1 register map and reset values (continued)

Res. 8

0
0

0
0
0
0
0
0
0
1
0
0

OC5CE Res. 7
REP[15:0]
PSC[15:0]
CNT[15:0]

ARR[15:0]

CCR5[15:0]
CCR4[15:0]
CCR3[15:0]
CCR2[15:0]
CCR1[15:0]

0
0

0
0
0
0
0
0
0
1
0
0

Res. 6

0
0

0
0
0
0
0
0
0
1
0
0

Res. 5

[2:0]
OC5M

0
0

0
0
0
0
0
0
0
0
1
0
0

0
0

0
0
0
0
0
0
0
0
1
0
0

OC5PE 3
DT[7:0]

0
0

0
0
0
0
0
0
0
0
1
0
0

OC5FE 2

0
0

0
0
0
0
0
0
0
1
0
0

DBA[4:0]
Res. 1

0
0

0
0
0
0
0
0
0
1
0
0

Res. 0
RM0454
 0x68
0x64
0x60
0x5C
Offset
RM0454

name

TIM1_AF2
TIM1_AF1
Register

Reset value
Reset value
Reset value
Reset value
TIM1_CCR6

TIM1_TISEL
Res. Res. Res. Res. 31
Res. Res. Res. Res. 30
Res. Res. Res. Res. 29
Res. Res. Res. Res. 28

0
Res. Res. Res. 27

0
Res. Res. Res. 26

0
Res. Res. Res. 25

TI4SEL[3:0]

0
Res. Res. Res. 24
Res. Res. Res. Res. 23
Res. Res. Res. Res. 22
Res. Res. Res. Res. 21
Res. Res. Res. Res. 20
0
Res. Res. Res. 19
0

Res. Res. Res. 18

0
0

RM0454 Rev 5
Res. Res. 17
TI3SEL[3:0]

0
0

Res. Res. 16
Res

[3:0]

0
0

Res. Res. 15
ETRSEL
0

Res. Res. 14
0

Res. Res. Res. 13

0

Res. Res. Res. 12

0
0

Res. Res. 11
0

Res. Res. 10
0
0

0
0

BK2INP BKINP 9
Refer to Section 2.2 on page 44 for the register boundary addresses.
TI2SEL[3:0]

0
0
Table 71. TIM1 register map and reset values (continued)

Res. Res. 8
0

Res. Res. Res. 7

CCR6[15:0]

Res. Res. Res. 6

0

Res. Res. Res. 5

0

Res. Res. Res. 4

0

Res. Res. 3
0
0

Res. Res. 2
0
0

Res. Res. 1
TI1SEL[3:0]
0

0
1
1

BK2INE BKINE 0
Advanced-control timer (TIM1)

433/989
433
General-purpose timers (TIM3/TIM4) RM0454

16 General-purpose timers (TIM3/TIM4)

16.1 TIM3/TIM4 introduction

The general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 16.3.19: Timer synchronization.

16.2 TIM3/TIM4 main features

General-purpose TIMx timer features include:
• 16-bit TIM3, TIM4(a) up, down, up/down auto-reload counter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.
• Up to 4 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge- and Center-aligned modes)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management

a. TIM4 is available on STM32G0B0xx salestypes only).

434/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 115. General-purpose timer block diagram

Internal clock (CK_INT)

From RCC
Trigger
ETRF controller
TIMx_ETR TRGO
ETR Polarity selection & edge ETRP
Input filter
detector & prescaler to other timers
to peripherals
On-chip ETR TRG
sources ITR[0..15]
ITR
Slave
TRC TRGI controller Reset, enable, count
mode
TI1F_ED

TI1FP1 Encoder
TI2FP2 interface

U
Auto-reload register UI
Stop, clear or up/down
U
CK_PSC PSC CK_CNT +/- CNT counter
XOR prescaler
CC1I U CC1I
TI1[0] TI1 Input
TIMx_CH1 TI1FP1 OC1REF
filter & IC1 IC1PS Output OC1 TIMx_CH1
TI1FP2 Prescaler Capture/Compare 1 register
TI1[1..15] edge control
detector TRC
CC2I
U CC2I
TI2[0] Input
TIMx_CH2 TI2FP1
IC2 Output OC2
TI2 filter & TI2FP2 Prescaler
IC2PS Capture/Compare 2 register OC2REF TIMx_CH2
TI2[1..15] edge control
detector TRC
CC3I CC3I
TI3[0] Input U
TIMx_CH3 TI3FP3
TI3 filter & TI3FP4 IC3 OC3REF Output OC3
IC3PS Capture/Compare 3 register TIMx_CH3
TI3[1..15] edge Prescaler control
detector TRC
CC4I
U CC4I
TI4[0] Input
TIMx_CH4 TI4FP3
TI4 filter & TI4FP4 IC4 IC4PS OC4REF Output OC4
Prescaler Capture/Compare 4 register TIMx_CH4
TI4[1..15] edge control
detector TRC

ETRF

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MSv62393V2

RM0454 Rev 5 435/989

507
General-purpose timers (TIM3/TIM4) RM0454

16.3 TIM3/TIM4 functional description

16.3.1 Time-base unit

The main block of the programmable timer is a 16-bit counter with its related auto-reload
register. The counter can count up, down or both up and down but also down or both up and
down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 116 and Figure 117 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

436/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 116. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 117. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

RM0454 Rev 5 437/989

507
General-purpose timers (TIM3/TIM4) RM0454

16.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 118. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

438/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 119. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 120. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

RM0454 Rev 5 439/989

507
General-purpose timers (TIM3/TIM4) RM0454

Figure 121. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 122. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

440/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 123. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.

RM0454 Rev 5 441/989

507
General-purpose timers (TIM3/TIM4) RM0454

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 124. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 125. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

442/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 126. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31186V1

Figure 127. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

RM0454 Rev 5 443/989

507
General-purpose timers (TIM3/TIM4) RM0454

Figure 128. Counter timing diagram, Update event when repetition counter
is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

444/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31189V3

1. Here, center-aligned mode 1 is used (for more details refer to Section 16.4.1: TIMx control register 1
(TIMx_CR1)(x = 3 to 4) on page 479).

RM0454 Rev 5 445/989

507
General-purpose timers (TIM3/TIM4) RM0454

Figure 130. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

446/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 132. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 133. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

RM0454 Rev 5 447/989

507
General-purpose timers (TIM3/TIM4) RM0454

Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

16.3.3 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin (TIx)
• External clock mode2: external trigger input (ETR)
• Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer X can be configured to act as a prescaler for Timer Y. Refer to : Using
one timer as prescaler for another timer on page 473 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 135 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

448/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Figure 135. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

Figure 136. TI2 external clock connection example

TIMx_SMCR
TS[4:0]

or TI2F or
TI1F or Encoder
ITRx mode
000xx
TIMx_CH2 TI1_ED TRGI External clock
00100
TI1FP1 00101 mode 1 CK_PSC
TI2[0]
TI2F_Rising
TI2 Edge 0 TI2FP2 00110 ETRF External clock
TI2[1..15] Filter
detector 1 ETRF 00111 mode 2
TI2F_Falling
(1) CK_INT Internal clock
ICF[3:0] CC2P (internal clock) mode
TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR
MSv40117V1

1. Codes ranging from 01000 to 11111: ITRy.

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).

RM0454 Rev 5 449/989

507
General-purpose timers (TIM3/TIM4) RM0454

Note: The capture prescaler is not used for triggering, so it does not need to be configured.
4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the
TIMx_CCER register.
5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
6. Select TI2 as the input source by writing TS=00110 in the TIMx_SMCR register.
7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 137. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 138 gives an overview of the external trigger input block.

450/989 RM0454 Rev 5

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Figure 138. External trigger input block

TI2F or
or
TI1F or Encoder
ETR0 input from AF controller mode

TRGI External clock

ETR mode 1 CK_PSC
0
Divider ETRP
ETRF External clock
ETR1..15 inputs from
on-chip sources 1
TBDf
/1, /2, /4, /8
Filter
downcounter mode 2
DTS
CK_INT Internal clock
ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ETRSEL[3:0] ECE SMS[2:0]

TIMx_AF1 TIMx_SMCR
MSv40928V1

For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. Select the proper ETR source (internal or external) with the ETRSEL[3:0] bits in the
TIMx_AF1 register.
2. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
3. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
4. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
5. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency
which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When
the ETRP signal is faster, the user should apply a division of the external signal by a proper
ETPS prescaler setting.

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Figure 139. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_CNT =CK_PSC

Counter register 34 35 36

MSv33111V3

16.3.4 Capture/Compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 140. Capture/Compare channel (example: channel 1 input stage)

TI1F_ED
TI1[0]
TIMx_CH1 To the slave mode controller

TI1[1..15]
Filter TI1F_Rising
downcounter TI1F Edge 0 TI1FP1
fDTS TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10 /1, /2, /4, /8
ICF[3:0] CC1P/CC1NP
TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER
MSv40120V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

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Figure 141. Capture/Compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
(from time TIMx_CCMR1
Comparator
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

Figure 142. Output stage of Capture/Compare channel (channel 1)

TIMx_SMCR
OCCS

OCREF_CLR To the master

0
mode controller
ETRF
1 OC1REFC
ocref_clr_int OC1REF
‘0’ 0 0
CNT > CCR1 Output OC1
Output enable
mode Output 1 1
CNT = CCR1 circuit
controller selector

CC1E CC1P
OC2REF
TIMx_CCER TIMx_CCER CC1E TIMx_CCER

OC1CE OC1M[3:0]
TIMx_CCMR1

MS33145V5

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

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16.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
3. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
4. Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case).
5. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
6. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
7. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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16.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).
4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’ (active on falling edge).
6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register
(TI1FP1 selected).
7. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
8. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.

Figure 143. PWM input mode timing

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.

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16.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high
(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.

16.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).

Procedure
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4. Select the output mode. For example, one must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

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The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 144.

Figure 144. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

16.3.9 PWM mode

Pulse width modulation mode permits to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be

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cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
• When the result of the comparison or
• When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting
mode on page 438.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 145 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.

Figure 145. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting
mode on page 441.
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at 100%. PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Center-aligned mode (up/down counting) on page 444.
Figure 146 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

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Figure 146. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

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16.3.10 Asymmetric PWM mode

Asymmetric mode allows two center-aligned PWM signals to be generated with a
programmable phase shift. While the frequency is determined by the value of the
TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of
TIMx_CCRx registers. One register controls the PWM during up-counting, the second
during down counting, so that PWM is adjusted every half PWM cycle:
• OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
• OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
Asymmetric PWM mode can be selected independently on two channels (one OCx output
per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’
(Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
When a given channel is used as asymmetric PWM channel, its secondary channel can also
be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM
mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC
signal resulting from asymmetric PWM mode 2.
Figure 147 shows an example of signals that can be generated using Asymmetric PWM
mode (channels 1 to 4 are configured in Asymmetric PWM mode 1).

Figure 147. Generation of 2 phase-shifted PWM signals with 50% duty cycle

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OC1REFC
CCR1=0
CCR2=8
OC3REFC
CCR3=3
CCR4=5

MS33117V1

16.3.11 Combined PWM mode

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with
programmable delay and phase shift between respective pulses. While the frequency is
determined by the value of the TIMx_ARR register, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or
AND logical combination of two reference PWMs:
– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
Combined PWM mode can be selected independently on two channels (one OCx output per
pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM
mode 2) in the OCxM bits in the TIMx_CCMRx register.

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When a given channel is used as combined PWM channel, its secondary channel must be
configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the
other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 148 shows an example of signals that can be generated using Asymmetric PWM
mode, obtained with the following configuration:
• Channel 1 is configured in Combined PWM mode 2,
• Channel 2 is configured in PWM mode 1,
• Channel 3 is configured in Combined PWM mode 2,
• Channel 4 is configured in PWM mode 1

Figure 148. Combined PWM mode on channels 1 and 3

OC2’
OC1’

OC2

OC1

OC1REF
OC2REF

OC1REF’
OC2REF’

OC1REFC

OC1REFC’

OC1REFC = OC1REF AND OC2REF

OC1REFC’ = OC1REF’ OR OC2REF’

MS31094V1

16.3.12 Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
OCxREF remains low until the next update event (UEV) occurs. This function can only be
used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.

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The OCxREF signal for a given channel can be reset by applying a high level on the ETRF
input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF
remains low until the next update event (UEV) occurs.
This function can be used only in the output compare and PWM modes. It does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be
used for current handling. In this case, ETR must be configured as follows:
1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is
cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.
Figure 149 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.

Figure 149. Clearing TIMx OCxREF

(CCRx)
Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

ocref_clr_int ocref_clr_int
becomes high still high
MS33105V2

Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the
next counter overflow.

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16.3.13 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• CNT<CCRx ≤ ARR (in particular, 0<CCRx),

Figure 150. Example of one-pulse mode.

TI2

OC1REF
OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY tPULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
1. Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
3. TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.
4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=00110
in the TIMx_SMCR register.
5. TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
• Let’s say one want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.

Particular case: OCx fast enable:

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

16.3.14 Retriggerable one pulse mode

This mode allows the counter to be started in response to a stimulus and to generate a
pulse with a programmable length, but with the following differences with Non-retriggerable
one pulse mode described in Section 16.3.13:
• The pulse starts as soon as the trigger occurs (no programmable delay)
• The pulse is extended if a new trigger occurs before the previous one is completed
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger
mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for
Retriggerable OPM mode 1 or 2.
If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0
(the ARR register sets the pulse length). If the timer is configured in Down-counting mode
CCRx must be above or equal to ARR.
Note: In retriggerable one pulse mode, the CCxIF flag is not significant.
The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit is not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.

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Figure 151. Retriggerable one-pulse mode.

TRGI

Counter

Output

MS33106V1

16.3.15 Encoder interface mode

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be
programmed as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 72. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the quadrature encoder and its content, therefore, always represents the encoder’s position.
The count direction correspond to the rotation direction of the connected sensor. The table
summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same
time.

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Table 72. Counting direction versus encoder signals

Level on opposite TI1FP1 signal TI2FP2 signal
Active edge signal (TI1FP1 for
TI2, TI2FP2 for TI1) Rising Falling Rising Falling

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 152 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
• CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
• CC1P and CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
• CC2P and CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
• SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
• CEN= 1 (TIMx_CR1 register, Counter is enabled)

Figure 152. Example of counter operation in encoder interface mode

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

Figure 153 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).

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Figure 153. Example of encoder interface mode with TI1FP1 polarity inverted

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

16.3.16 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update
interrupt flag (UIF) into bit 31 of the timer counter register’s bit 31 (TIMxCNT[31]). This
permits to atomically read both the counter value and a potential roll-over condition signaled
by the UIFCPY flag. It eases the calculation of angular speed by avoiding race conditions
caused, for instance, by a processing shared between a background task (counter reading)
and an interrupt (update interrupt).
There is no latency between the UIF and UIFCPY flag assertions.
In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is
overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only
accessible in write mode).

16.3.17 Timer input XOR function

The TI1S bit in the TIM1xx_CR2 register, allows the input filter of channel 1 to be connected
to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
An example of this feature used to interface Hall sensors is given in Section 15.3.25:
Interfacing with Hall sensors on page 387.

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16.3.18 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).
2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
3. Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 154. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V2

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:

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1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 155. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.
Note: The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not
have any effect in gated mode because gated mode acts on a level and not on an edge.

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

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CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=00110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 156. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

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A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 157. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

16.3.19 Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 158: Master/Slave timer example and Figure 159: Master/slave connection example
with 1 channel only timers present an overview of the trigger selection and the master mode
selection blocks.

Figure 158. Master/Slave timer example

TIMy TIMz

Clock
TS SMS
MMS
UEV
Master Slave
TRGO ITR2 CK_PSC
Prescaler Counter mode mode Prescaler Counter
control control

Input
trigger
selection
MSv62394V1

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Figure 159. Master/slave connection example with 1 channel only timers

TIM_mstr TIM_slv
Clock
Prescaler Counter TS SMS

Output Slave
tim_oc1 tim_itr CK_PSC
mode
control control
Compare 1 Prescaler Counter

Input
TIM_CH1 trigger
selection
MSv65225V1

Note: The timers with one channel only (see Figure 159) do not feature a master mode. However,
the OC1 output signal can be used to trigger some other timers (including timers described
in other sections of this document). Check the “TIMx internal trigger connection” table of any
TIMx_SMCR register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer will detect the trigger.
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.

Using one timer as prescaler for another timer

For example, TIMy can be configured to act as a prescaler for TIMz. Refer to Figure 158. To
do this:
1. Configure TIMy in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIMy_CR2 register, a rising edge is
output on TRGO each time an update event is generated.
2. To connect the TRGO output of TIMy to TIMz, TIMz must be configured in slave mode
using ITR as internal trigger. This is selected through the TS bits in the TIMz_SMCR
register (writing TS=00).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIMz_SMCR register). This causes TIMz to be clocked by the rising edge of the
periodic TIMy trigger signal (which correspond to the TIMy counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on TIMy as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIMz.

Using one timer to enable another timer

In this example, we control the enable of TIMz with the output compare 1 of Timer y. Refer
to Figure 158 for connections. TIMz counts on the divided internal clock only when OC1REF
of TIMy is high. Both counter clock frequencies are divided by 3 by the prescaler compared
to CK_INT (fCK_CNT = fCK_INT/3).

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1. Configure TIMy master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMy_CR2 register).
2. Configure the TIMy OC1REF waveform (TIMy_CCMR1 register).
3. Configure TIMz to get the input trigger from TIMy (TS=00 in the TIMz_SMCR register).
4. Configure TIMz in gated mode (SMS=101 in TIMz_SMCR register).
5. Enable TIMz by writing ‘1 in the CEN bit (TIMz_CR1 register).
6. Start TIMy by writing ‘1 in the CEN bit (TIMy_CR1 register).
Note: The counter z clock is not synchronized with counter 1, this mode only affects the TIMz
counter enable signal.

Figure 160. Gating TIMz with OC1REF of TIMy

CK_INT

TIMy-OC1REF

TIMy-CNT FC FD FE FF 00 01

TIMz-CNT 3045 3046 3047 3048

TIMz-TIF

Write TIF = 0
MSv37634V1

In the example in Figure 160, the TIMz counter and prescaler are not initialized before being
started. So they start counting from their current value. It is possible to start from a given
value by resetting both timers before starting TIMy. Then any value can be written in the
timer counters. The timers can easily be reset by software using the UG bit in the
TIMx_EGR registers.
In the next example (refer to Figure 161), we synchronize TIMy and TIMz. TIMy is the
master and starts from 0. TIMz is the slave and starts from 0xE7. The prescaler ratio is the
same for both timers. TIMz stops when TIMy is disabled by writing ‘0 to the CEN bit in the
TIMy_CR1 register:
1. Configure TIMy master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMy_CR2 register).
2. Configure the TIMy OC1REF waveform (TIMy_CCMR1 register).
3. Configure TIMz to get the input trigger from TIMy (TS=00 in the TIMz_SMCR register).
4. Configure TIMz in gated mode (SMS=101 in TIMz_SMCR register).
5. Reset TIMy by writing ‘1 in UG bit (TIMy_EGR register).
6. Reset TIMz by writing ‘1 in UG bit (TIMz_EGR register).
7. Initialize TIMz to 0xE7 by writing ‘0xE7’ in the TIMz counter (TIMz_CNTL).
8. Enable TIMz by writing ‘1 in the CEN bit (TIMz_CR1 register).
9. Start TIMy by writing ‘1 in the CEN bit (TIMy_CR1 register).
10. Stop TIMy by writing ‘0 in the CEN bit (TIMy_CR1 register).

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Figure 161. Gating TIMz with Enable of TIMy

CK_INT

TIMy-CEN=CNT_EN

TIMy-CNT_INIT

TIMy-CNT 75 00 01 02

TIMz-CNT AB 00 E7 E8 E9

TIMz-CNT_INIT

TIMz-write CNT

TIMz-TIF

Write TIF = 0
MSv37635V1

Using one timer to start another timer

In this example, we set the enable of Timer z with the update event of Timer y. Refer to
Figure 158 for connections. Timer z starts counting from its current value (which can be non-
zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer z receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIMz_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
1. Configure TIMy master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIMy_CR2 register).
2. Configure the TIMy period (TIMy_ARR registers).
3. Configure TIMz to get the input trigger from TIMy (TS=00 in the TIMz_SMCR register).
4. Configure TIMz in trigger mode (SMS=110 in TIMz_SMCR register).
5. Start TIMy by writing ‘1 in the CEN bit (TIMy_CR1 register).

Figure 162. Triggering TIMz with update of TIMy

CK_INT

TIMy-UEV

TIMy-CNT FD FE FF 00 01 02

TIMz-CNT 45 46 47 48

TIMz-CEN=CNT_EN

TIMz-TIF

Write TIF = 0
MSv37636V1

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As in the previous example, both counters can be initialized before starting counting.
Figure 163 shows the behavior with the same configuration as in Figure 162 but in trigger
mode instead of gated mode (SMS=110 in the TIMz_SMCR register).

Figure 163. Triggering TIMz with Enable of TIMy

CK_INT

TIMy-CEN=CNT_EN

TIMy-CNT_INIT

TIMy-CNT 75 00 01 02

TIMz-CNT CD 00 E7 E8 E9 EA

TIMz-CNT_INIT

TIMz
write CNT

TIMz-TIF

Write TIF = 0

MSv37637V1

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of TIMy when its TI1 input rises, and the enable of TIMz
with the enable of TIMy. Refer to Figure 158 for connections. To ensure the counters are
aligned, TIMy must be configured in Master/Slave mode (slave with respect to TI1, master
with respect to TIMz):
1. Configure TIMy master mode to send its Enable as trigger output (MMS=001 in the
TIMy_CR2 register).
2. Configure TIMy slave mode to get the input trigger from TI1 (TS=00100 in the
TIMy_SMCR register).
3. Configure TIMy in trigger mode (SMS=110 in the TIMy_SMCR register).
4. Configure the TIMy in Master/Slave mode by writing MSM=1 (TIMy_SMCR register).
5. Configure TIMz to get the input trigger from TIMy (TS=00000 in the TIMz_SMCR
register).
6. Configure TIMz in trigger mode (SMS=110 in the TIMz_SMCR register).
When a rising edge occurs on TI1 (TIMy), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but an offset can easily be inserted between them by
writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on TIMy.

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Figure 164. Triggering TIMy and TIMz with TIMy TI1 input

CK_INT

TIMy-TI1

TIMy-CEN=CNT_EN

TIMy-CK_PSC

TIMy-CNT 00 01 02 03 04 05 06 07 08 09

TIMy-TIF
TIMz-CEN=CNT_EN

TIMz-CK_PSC

TIMz-CNT 00 01 02 03 04 05 06 07 08 09

TIMz-TIF

MSv37638V1

Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.

16.3.20 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event.
The main purpose is to be able to re-program part of the timer multiple times without
software overhead, but it can also be used to read several registers in a row, at regular
intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.
On a given timer event, the timer launches a sequence of DMA requests (burst). Each write
into the TIMx_DMAR register is actually redirected to one of the timer registers.
The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the
number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA
transfers (when read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register:
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
As an example, the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the
CCRx registers.
This is done in the following steps:

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1. Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
This example is for the case where every CCRx register has to be updated once. If every
CCRx register is to be updated twice for example, the number of data to transfer should be
6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5
and data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.

16.3.21 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBGMCU module. For more details, refer to Section 29.9.2: Debug support for timers,
watchdog and I2C.

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16.4 TIM3/TIM4 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

16.4.1 TIMx control register 1 (TIMx_CR1)(x = 3 to 4)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
MAP
rw rw rw rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.

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Bit 3 OPM: One-pulse mode

0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

16.4.2 TIMx control register 2 (TIMx_CR2)(x = 3 to 4)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res.
rw rw rw rw rw

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Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also Section 15.3.25: Interfacing with Hall sensors on page 387
Bits 6:4 MMS[2:0]: Master mode selection
These bits permit to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic AND between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REFC signal is used as trigger output (TRGO)
101: Compare - OC2REFC signal is used as trigger output (TRGO)
110: Compare - OC3REFC signal is used as trigger output (TRGO)
111: Compare - OC4REFC signal is used as trigger output (TRGO)
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.

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16.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 3 to 4)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] OCCS SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=00111).
It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 00111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.

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Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.
00000: Internal Trigger 0 (ITR0)
00001: Internal Trigger 1 (ITR1)
00010: Internal Trigger 2 (ITR2)
00011: Internal Trigger 3 (ITR3)
00100: TI1 Edge Detector (TI1F_ED)
00101: Filtered Timer Input 1 (TI1FP1)
00110: Filtered Timer Input 2 (TI2FP2)
00111: External Trigger input (ETRF)
01000: Internal Trigger 4 (ITR4)
01001: Internal Trigger 5 (ITR5)
01010: Internal Trigger 6 (ITR6)
01011: Internal Trigger 7 (ITR7)
01100: Internal Trigger 8 (ITR8)
Others: Reserved
See Table 73: TIM3 internal trigger connection on page 485 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection
This bit is used to select the OCREF clear source
0: OCREF_CLR_INT is unconnected.
1: OCREF_CLR_INT is connected to ETRF

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Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.

Table 73. TIM3 internal trigger connection

Slave TIM ITR0 ITR1 ITR2 ITR3

TIM3 TIM1 - TIM15 TIM14_OC1

TIM4 TIM1 - TIM15 TIM14_OC1

16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 3 to 4)

Address offset: 0x0C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TDE Res. CC4DE CC3DE CC2DE CC1DE UDE Res. TIE Res. CC4IE CC3IE CC2IE CC1IE UIE
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, must be kept at reset value.

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Bit 12 CC4DE: Capture/Compare 4 DMA request enable

0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

16.4.5 TIMx status register (TIMx_SR)(x = 3 to 4)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. Res. TIF Res. CC4IF CC3IF CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

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Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode. It is set when the
counter starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

Refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare mode)
or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred
If channel CC1 is configured as output: this flag is set when the content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to
the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been captured
in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity
defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.

16.4.6 TIMx event generation register (TIMx_EGR)(x = 3 to 4)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. CC4G CC3G CC2G CC1G UG
w w w w w w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
Refer to CC1G description

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Bit 2 CC2G: Capture/compare 2 generation

Refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

16.4.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)

(x = 3 to 4)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode.
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F[3:0] IC2PSC[1:0] CC2S[1:0] IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0]: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler

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Bits 9:8 CC2S[1:0]: Capture/compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is
reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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16.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)

(x = 3 to 4)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M OC1M
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[3] [3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE OC2M[2:0] OC2PE OC2FE CC2S[1:0] OC1CE OC1M[2:0] OC1PE OC1FE CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC2CE: Output compare 2 clear enable
Bits 24, 14:12 OC2M[3:0]: Output compare 2 mode
refer to OC1M description on bits 6:4
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger
event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1
and the channels becomes inactive again at the next update. In down-counting mode, the
channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is
performed as in PWM mode 1 and the channels becomes inactive again at the next update.
1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a
trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM
mode 2 and the channels becomes inactive again at the next update. In down-counting
mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a
comparison is performed as in PWM mode 1 and the channels becomes active again at the
next update.
1010: Reserved,
1011: Reserved,
1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.
OC1REFC is the logical OR between OC1REF and OC2REF.
1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.
OC1REFC is the logical AND between OC1REF and OC2REF.
1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.
OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting
down.
1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.
OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting
down.
Note: In PWM mode, the OCREF level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM”
mode.
Note: The OC1M[3] bit is not contiguous, located in bit 16.

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Bit 3 OC1PE: Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one-pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

16.4.9 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)

(x = 3 to 4)
Address offset: 0x1C
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode.
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F[3:0] IC4PSC[1:0] CC4S[1:0] IC3F[3:0] IC3PSC[1:0] CC3S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC4F[3:0]: Input capture 4 filter
Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler

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Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F[3:0]: Input capture 3 filter
Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

16.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)

(x = 3 to 4)
Address offset: 0x1C
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M OC3M
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[3] [3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE OC4M[2:0] OC4PE OC4FE CC4S[1:0] OC3CE OC3M[2:0] OC3PE OC3FE CC3S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC4CE: Output compare 4 clear enable
Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode
Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable

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Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode
Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

16.4.11 TIMx capture/compare enable register

(TIMx_CCER)(x = 3 to 4)
Address offset: 0x20
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 CC4NP: Capture/Compare 4 output Polarity.

Refer to CC1NP description
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
Refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
Refer to CC1NP description
Bit 10 Reserved, must be kept at reset value.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
Refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
Refer to CC1E description

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Bit 7 CC2NP: Capture/Compare 2 output Polarity.

Refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output: CC1NP must be kept cleared in this case.
CC1 channel configured as input: This bit is used in conjunction with CC1P to define
TI1FP1/TI2FP1 polarity. refer to CC1P description.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active
polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising
and falling edges (capture or trigger operations in reset, external clock
or trigger mode), TIxFP1is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
Bit 0 CC1E: Capture/Compare 1 output enable.
0: Capture mode disabled / OC1 is not active
1: Capture mode enabled / OC1 signal is output on the corresponding output pin

Table 74. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output disabled (not driven by the timer: Hi-Z)
1 Output enabled (tim_ocx = tim_ocxref + Polarity)

Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO and AFIO registers.

16.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4)

Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
• This section is for UIFREMAP = 0
• Next section is for UIFREMAP = 1

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Address offset: 0x24

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 CNT[31:16]: Most significant part counter value

Bits 15:0 CNT[15:0]: Least significant part of counter value

16.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4)

Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
• Previous section is for UIFREMAP = 0
• This section is for UIFREMAP = 1
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY CNT[30:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register
Bits 30:16 CNT[30:16]: Most significant part counter value
Bits 15:0 CNT[15:0]: Least significant part of counter value

16.4.14 TIMx prescaler (TIMx_PSC)(x = 3 to 4)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

16.4.15 TIMx auto-reload register (TIMx_ARR)(x = 3 to 4)

Address offset: 0x2C
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 ARR[31:16]: High auto-reload value

Bits 15:0 ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 436 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

16.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 3 to 4)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value

Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.

16.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 3 to 4)

Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value

Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.

16.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3 to 4)

Address offset: 0x3C
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value

Bits 15:0 CCR3[15:0]: Low Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.

16.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 3 to 4)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value

Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1. if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2
register (bit OC4PE). Else the preload value is copied in the active capture/compare 4
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4). The
TIMx_CCR4 register is read-only and cannot be programmed.

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16.4.20 TIMx DMA control register (TIMx_DCR)(x = 3 to 4)

Address offset: 0x48
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

16.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 3 to 4)

Address offset: 0x4C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

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16.4.22 TIM3 alternate function option register 1 (TIM3_AF1)

Address offset: 0x60
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: ETR legacy mode
Others: Reserved
Bits 13:0 Reserved, must be kept at reset value.

16.4.23 TIM4 alternate function option register 1 (TIM4_AF1)

Address offset: 0x60
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: ETR legacy mode
Others: Reserved
Bits 13:0 Reserved, must be kept at reset value.

16.4.24 TIM3 timer input selection register (TIM3_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI3SEL[3:0]
rw rw rw rw

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection
These bits select the TI3[0] to TI3[15] input source.
0000: TIM3_CH3 input
Others: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection
These bits select the TI2[0] to TI2[15] input source.
0000: TIM3_CH2 input
Others: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection
These bits select the TI1[0] to TI1[15] input source.
0000: TIM3_CH1 input
Others: Reserved

16.4.25 TIM4 timer input selection register (TIM4_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI3SEL[3:0]
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection
These bits select the TI3[0] to TI3[15] input source.
0000: TIM4_CH3 input
Others: Reserved
Bits 15:12 Reserved, must be kept at reset value.

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General-purpose timers (TIM3/TIM4) RM0454

Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection

These bits select the TI2[0] to TI2[15] input source.
0000: TIM4_CH2 input
Others: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection
These bits select the TI1[0] to TI1[15] input source.
0000: TIM4_CH1 input
Others: Reserved

504/989 RM0454 Rev 5

 0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0454

16.4.26

mode
mode

Output
Output
name

TIMx_SR
TIMx_CR2
TIMx_CR1

TIMx_EGR
Register

TIMx_DIER

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIMx_CCER
TIMx_SMCR

Input Capture
Input Capture

TIMx_CCMR2
TIMx_CCMR2
TIMx_CCMR1
TIMx_CCMR1

Compare mode
Compare mode
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
TIMx register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
Res. Res. OC4M[3] Res. OC2M[3] Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
TS
[4:3]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

RM0454 Rev 5
0
0
0

Res. Res. OC3M[3] Res. OC1M[3] Res. Res. Res. SMS[3] Res. Res. 16

0
0
0
0
0
0

CC4NP O24CE OC2CE Res. Res. Res. ETP Res. Res. 15

0
0
0
0
0
0

Res. Res. Res. TDE ECE Res. Res. 14

0
0
0
0
0
0

CC4P Res. Res. Res. Res. Res. 13

[2:0]
[2:0]

IC4F[3:0]
IC2F[3:0]

OC4M
OC2M
[1:0]

0
0
0
0
0
0
0

0
ETPS

CC4E Res. CC4OF CC4DE Res. Res. 12

TIMx registers are mapped as described in the table below:

0
0
0
0
0
0
0

0
0

CC3NP OC4PE OC2PE Res. CC3OF CC3DE Res. UIFREMA 11

IC4
IC2

[1:0]
[1:0]

PSC
PSC

0
0
0
0
0
0
0

Res. OC4FE OC2FE Res. CC2OF CC2DE Res. Res. 10

Table 75. TIM3/TIM4 register map and reset values

0
0
0
0
0
0
0
0
0

CC3P Res. CC1OF CC1DE Res. 9

ETF[3:0]

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
CKD

0
0
0
0
0
0
0
0

CC4S
CC4S
CC2S
CC2S
CC3E Res. Res. UDE Res. 8

0
0
0
0
0
0
0
0

CC2NP OC3CE OC1CE Res. Res. Res. MSM TI1S ARPE 7

0
0
0
0
0
0

0
0
0
0

Res. TG TIF TIE 6

[1:0]
CMS

0
0
0
0
0
0
0
0

CC2P Res. Res. Res. 5

[2:0]
[2:0]

IC3F[3:0]
IC1F[3:0]

OC3M
OC1M
TS[2:0]

0
0
0
0
0
0
0

0
0
0
0

MMS[2:0]

CC2E CC4G CC4IF CC4IE DIR 4

0
0
0
0
0
0

0
0
0
0

CC1NP OC3PE OC1PE CC3G CC3IF CC3IE Res. CCDS OPM 3

IC3
IC1

[1:0]
[1:0]

PSC
PSC

0
0
0
0
0
0

0
0
0

Res. OC3FE OC1FE CC2G CC2IF CC2IE Res. URS 2

0
0
0
0
0
0
0

0
0
0

CC1P CC1G CC1IF CC1IE Res. UDIS 1

[1:0]
[1:0]
[1:0]
[1:0]

0
0
0
0
0
0

0
0
0
0

SMS[2:0]

CC3S
CC3S
CC1S
CC1S

CC1E UG UIF UIE Res. CEN 0

General-purpose timers (TIM3/TIM4)

505/989
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General-purpose timers (TIM3/TIM4) RM0454

Table 75. TIM3/TIM4 register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CNT[31] or UIFCPY CNT[30:16]

TIMx_CNT CNT[15:0]
0x24 ( only, reserved on the other timers)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_PSC PSC[15:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ARR[31:16]
TIMx_ARR ARR[15:0]
0x2C ( only, reserved on the other timers)

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0x30 Reserved

CCR1[31:16]
TIMx_CCR1 CCR1[15:0]
0x34 ( only, reserved on the other timers)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR2[31:16]
TIMx_CCR2 CCR2[15:0]
0x38 ( only, reserved on the other timers)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR3[31:16]
TIMx_CCR3 CCR3[15:0]
0x3C ( only, reserved on the other timers)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR4[31:16]
TIMx_CCR4 CCR4[15:0]
0x40 ( only, reserved on the other timers)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x44 Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

TIMx_DCR DBL[4:0] DBA[4:0]

0x48
Reset value 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIMx_DMAR DMAB[15:0]
0x4C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETRSEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIM3_AF1
[3:0]
0x60
Reset value 0 0 0 0

ETRSEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIM4_AF1
[3:0]
0x60
Reset value 0 0 0 0

506/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM3/TIM4)

Table 75. TIM3/TIM4 register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
TIM3_TISEL TI3SEL[3:0] TI2SEL[3:0] TI1SEL[3:0]
0x68
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
TIM4_TISEL TI3SEL[3:0] TI2SEL[3:0] TI1SEL[3:0]
0x68
Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

RM0454 Rev 5 507/989

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Basic timers (TIM6/TIM7) RM0454

17 Basic timers (TIM6/TIM7)

17.1 TIM6/TIM7 introduction

The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used as generic timers for time base generation.
The timers are completely independent, and do not share any resources.

17.2 TIM6/TIM7 main features

Basic timer (TIM6/TIM7) features include:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Interrupt/DMA generation on the update event: counter overflow

Figure 165. Basic timer block diagram

Trigger TRGO
Internal clock (CK_INT) controller
TIMxCLK from RCC

Reset, enable, Count

Control

Auto-reload register
U UI
Stop, clear or up
U
CK_PSC PSC CK_CNT
+ CNT counter
prescaler

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event

Interrupt & DMA output MSv50981V1

508/989 RM0454 Rev 5

RM0454 Basic timers (TIM6/TIM7)

17.3 TIM6/TIM7 functional description

17.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload
register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an
attempt is made to write or read the auto-reload register. The contents of the preload
register are transferred into the shadow register permanently or at each update event UEV,
depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The
update event is sent when the counter reaches the overflow value and if the UDIS bit equals
0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 166 and Figure 167 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

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Figure 166. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 167. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

510/989 RM0454 Rev 5

RM0454 Basic timers (TIM6/TIM7)

17.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values into the preload
registers. In this way, no update event occurs until the UDIS bit has been written to 0,
however, the counter and the prescaler counter both restart from 0 (but the prescale rate
does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.

Figure 168. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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Basic timers (TIM6/TIM7) RM0454

Figure 169. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 170. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

512/989 RM0454 Rev 5

RM0454 Basic timers (TIM6/TIM7)

Figure 171. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 172. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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Basic timers (TIM6/TIM7) RM0454

Figure 173. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

17.3.3 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to
atomically read both the counter value and a potential roll-over condition signaled by the
UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.

17.3.4 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 174 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

514/989 RM0454 Rev 5

RM0454 Basic timers (TIM6/TIM7)

Figure 174. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

17.3.5 Debug mode

When the microcontroller enters the debug mode (Cortex®-M0+ core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 29.9.2: Debug
support for timers, watchdog and I2C.

17.4 TIM6/TIM7 registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

17.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. Res. Res. ARPE Res. Res. Res. OPM URS UDIS CEN
MAP
rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bits 10:8 Reserved, must be kept at reset value.

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Bit 7 ARPE: Auto-reload preload enable

0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

516/989 RM0454 Rev 5

RM0454 Basic timers (TIM6/TIM7)

17.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res.
rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0]: Master mode selection
These bits are used to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer
is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR
register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bits 3:0 Reserved, must be kept at reset value.

17.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. UDE Res. Res. Res. Res. Res. Res. Res. UIE
rw rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

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17.4.4 TIMx status register (TIMx_SR)(x = 6 to 7)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIF
rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
and UDIS = 0 in the TIMx_CR1 register.

17.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG
w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).

17.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0454 Basic timers (TIM6/TIM7)

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value

17.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

17.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Prescaler value

ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 17.3.1: Time-base unit on page 509 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

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 0x28
0x24
0x20
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C

0x18-
Offset

520/989
17.4.9

name

TIMx_SR
TIMx_CR2
TIMx_CR1

TIMx_PSC
TIMx_CNT

TIMx_ARR
TIMx_EGR
Register

TIMx_DIER

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
0
Res. Res. UIFCPY or Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Basic timers (TIM6/TIM7)

Res. Res. Res. Res. Res. Res. Res. Res. 29

Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
TIMx register map

Res. Res. Res. Res. Res. Res. Res. Res. 25

Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
17

Reserved
Reserved

Res. Res. Res. Res. Res. Res. Res. Res.

Res. Res. Res. Res. Res. Res. Res. Res. 16

1
0
0
Res. Res. Res. Res. Res. 15

1
0
0
Res. Res. Res. Res. Res. 14

1
0
0
Res. Res. Res. Res. Res. 13

1
0
0
Res. Res. Res. Res. Res. 12

1
0
0
0

Res. Res. Res. Res. UIFREMA 11

Table 76. TIMx register map and reset values

1
0
0
Res. Res. Res. Res. Res. 10

1
0
0
Res. Res. Res. Res. Res. 9

Refer to Section 2.2 on page 44 for the register boundary addresses.

1
0
0
0

Res. Res. UDE Res. Res. 8

1
0
0
0

Res. Res. Res. Res. ARPE 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

1
0
0
0

Res. Res. Res. Res. 6

1
0
0
0

Res. Res. Res. Res. 5

[2:0]
MMS

1
0
0
0

Res. Res. Res. Res. 4

1
0
0
0

Res. Res. Res. Res. OPM 3

1
0
0
0

Res. Res. Res. Res. URS 2

1
0
0
0

Res. Res. Res. Res. UDIS 1

1
0
0
0
0
0
0
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
RM0454

UG UIF UIE Res. CEN 0

RM0454 General-purpose timers (TIM14)

18 General-purpose timers (TIM14)

18.1 TIM14 introduction

The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM14 timer is completely independent, and does not share any resources.

18.2 TIM14 main features

18.2.1 TIM14 main features

The features of general-purpose timer TIM14 include:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65536 (can be changed “on the fly”)
• independent channel for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on the following events:
– Update: counter overflow, counter initialization (by software)
– Input capture
– Output compare

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Figure 175. General-purpose timer block diagram (TIM14)

Internal clock (CK_INT)

Trigger Enable
Controller counter
To other
timers for
cross-
trigerring(1)

U Auto-reload register
UI
Stop, clear
U
CK_PSC PSC CK_CNT +/-
CNT counter
prescaler
C1I CC1I
TI1[0] Input U
TIMx_CH1 TI1FP1 IC1 Capture/compare 1
filter & Prescaler IC1PS OC1REF Output OC1
register TIMx_CH1
TI1[1..15] edge control
selector

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event

Interrupt & DMA output MSv40931V2

1. This signal can be used as trigger for some slave timers, see Section 18.3.11: Using timer output as trigger
for other timers (TIM14).

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RM0454 General-purpose timers (TIM14)

18.3 TIM14 functional description

18.3.1 Time-base unit

The main block of the timer is a 16-bit up-counter with its related auto-reload register. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in details for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set.
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 176 and Figure 177 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

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Figure 176. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 177. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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RM0454 General-purpose timers (TIM14)

18.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 178. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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Figure 179. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 180. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

526/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM14)

Figure 181. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 182. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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Figure 183. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

18.3.3 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)

Internal clock source (CK_INT)

The internal clock source is the default clock source for TIM14.
Figure 184 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

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RM0454 General-purpose timers (TIM14)

Figure 184. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

r clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

18.3.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 185 to Figure 187 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as the capture command. It is prescaled before the capture register (ICxPS).

Figure 185. Capture/compare channel (example: channel 1 input stage)

TI1[0]
TIMx_CH1
TI1[1..15]
Filter TI1F_Rising
downcounter TI1F Edge 0 TI1FP1
fDTS TI1F_Falling 01
detector 1
IC1 Divider IC1PS
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP

TIMx_CCMR1 TIMx_CCER

CC1S[1:0] ICPS[1:0] CC1E

TIMx_CCMR1 TIMx_CCER
MSv45749V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

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Figure 186. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
(from time TIMx_CCMR1
Comparator
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

Figure 187. Output stage of capture/compare channel (channel 1)

To the master mode
controller

OC1REF OC1REFC

‘0’ 0 0 Output
CNT > CCR1 Output OC1
Output enable
mode 1 1 circuit
selector
CNT = CCR1 controller

OC2REF(1)
CC1E CC1P CC1E
TIM1_CCER TIM1_CCER TIM1_CCER

OC1M[3:0]
TIMx_CCMR1
MSv45743V3

1. Available on TIM12 only.

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

18.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be

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cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes read-
only.
3. Program the appropriate input filter duration in relation with the signal connected to the
timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of
the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at
must 5 internal clock cycles. We must program a filter duration longer than these 5
clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to
‘0011’ in the TIMx_CCMR1 register.
4. Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).
5. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
6. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
7. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.

18.3.6 Forced output mode

In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
‘0101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is
forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity
bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.

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The OCxREF signal can be forced low by writing the OCxM bits to ‘0100’ in the
TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is
described in the output compare mode section below.

18.3.7 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
1. Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCxM=’0000’), be
set active (OCxM=’0001’), be set inactive (OCxM=’0010’) or can toggle (OCxM=’0011’)
on match.
2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = ‘0011’ to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = ‘0’ to disable preload register
– Write CCxP = ‘0’ to select active high polarity
– Write CCxE = ‘1’ to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 188.

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Figure 188. Output compare mode, toggle on OC1.

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

18.3.8 PWM mode

Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 189 shows some edge-
aligned PWM waveforms in an example where TIMx_ARR=8.

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Figure 189. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

18.3.9 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled using the CEN bit. Generating the waveform can be
done in output compare mode or PWM mode. One-pulse mode is selected by setting the
OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next
update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be as follows:
CNT < CCRx = ARR (in particular, 0 < CCRx)

18.3.10 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to
atomically read both the counter value and a potential roll-over condition signaled by the
UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.

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18.3.11 Using timer output as trigger for other timers (TIM14)

The timers with one channel only do not feature a master mode. However, the OC1 output
signal can be used to trigger some other timers (including timers described in other sections
of this document). Check the “TIMx internal trigger connection” table of any TIMx_SMCR
register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer will detect the trigger.
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.

18.3.12 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 29.9.2: Debug support for timers,
watchdog and I2C.

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18.4 TIM14 registers

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

18.4.1 TIM14 control register 1 (TIM14_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
MAP

rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.

18.4.2 TIM14 Interrupt enable register (TIM14_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE UIE

rw rw

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

18.4.3 TIM14 status register (TIM14_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1OF Res. Res. Res. Res. Res. Res. Res. CC1IF UIF

rc_w0 rc_w0 rc_w0

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Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare mode)
or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred.
If channel CC1 is configured as output: this flag is set when he content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to
the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow and if UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

18.4.4 TIM14 event generation register (TIM14_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1G UG

w w

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Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.

18.4.5 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)

Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode.
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. IC1F[3:0] IC1PSC[1:0] CC1S[1:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

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Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

18.4.6 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)

Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the

540/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM14)

corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[3]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0]
rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bits 15:7 Reserved, must be kept at reset value.
Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])
These bits define the behavior of the output reference signal OC1REF from which OC1 is
derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.
0000: Frozen. The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active
Others: Reserved
Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison
changes or when the output compare mode switches from frozen to PWM mode.
Note: The OC1M[3] bit is not contiguous, located in bit 16.

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Bit 3 OC1PE: Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit decreases the latency between a trigger event and a transition on the timer output. It
must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then
set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only
if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: Reserved.
11: Reserved.
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

18.4.7 TIM14 capture/compare enable register (TIM14_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E

rw rw rw

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
CC1 channel configured as output: CC1NP must be kept cleared.
CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define
TI1FP1 polarity (refer to CC1P description).

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Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P: Capture/Compare 1 output Polarity.
0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active
polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising
and falling edges (capture or trigger operations in reset, external clock
or trigger mode), TIxFP1is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0:This configuration is reserved, it must not be used.
Bit 0 CC1E: Capture/Compare 1 output enable.
0: Capture mode disabled / OC1 is not active
1: Capture mode enabled / OC1 signal is output on the corresponding output pin

Table 77. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output disabled (not driven by the timer: Hi-Z)
1 Output enabled (tim_ocx = tim_ocxref + Polarity)

Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

18.4.8 TIM14 counter (TIM14_CNT)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value

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18.4.9 TIM14 prescaler (TIM14_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

18.4.10 TIM14 auto-reload register (TIM14_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 18.3.1: Time-base unit on page 523 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

18.4.11 TIM14 capture/compare register 1 (TIM14_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0454 General-purpose timers (TIM14)

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

18.4.12 TIM14 timer input selection register (TIM14_TISEL)

Address offset: 0x68
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0]

rw

Bits 15:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM14_CH1 input
0001: RTC CLK
0010: HSE/32
0011: MCO
0100: MCO2(1)
Others: Reserved
1. Available on STM32G0B0xx salestypes only.

18.4.13 TIM14 register map

TIMx registers are mapped as 16-bit addressable registers as described in the tables below:

Table 78. TIM14 register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0

name
UIFREMA

ARPE

UDIS

CKD
OPM
URS

CEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

TIMx_CR1
[1:0]
0x00

Reset value 0 0 0 0 0 0 0 0

0x04 to Reserved Res.

0x08
CC1IE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

UIE

TIMx_DIER
0x0C
Reset value 0 0

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 0x68
0x64
0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10

0x2C
0x1C

0x38 to
Offset

546/989
mode
mode
name

TIMx_SR

Reserved
Reserved
Reserved

TIMx_PSC
TIMx_CNT
TIMx_EGR

TIMx_ARR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIMx_CCR1
TIMx_CCER
Input capture

TIM14_TISEL
TIMx_CCMR1
TIMx_CCMR1
Output compare

0
Res. Res. Res. Res. UIFCPY Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
General-purpose timers (TIM14)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

RM0454 Rev 5
0

Res. Res. Res. Res. Res. Res. Res. OC1M[3] Res. Res. 16

0
0
0
0
Res. Res. Res. Res. Res. Res. 15

Res.
Res.
Res.

0
0
0
0
Res. Res. Res. Res. Res. Res. 14

0
0
0
0
Res. Res. Res. Res. Res. Res. 13

0
0
0
0
Res. Res. Res. Res. Res. Res. 12

0
0
0
0
Res. Res. Res. Res. Res. Res. 11

0
0
0
0
Res. Res. Res. Res. Res. Res. 10

0
0
0
0
0

Res. Res. Res. Res. Res. CC1OF 9

0
0
0
0

Refer to Section 2.2 on page 44 for the register boundary addresses.

Res. Res. Res. Res. Res. Res. 8
Table 78. TIM14 register map and reset values (continued)

0
0
0
0
0

Res. Res. Res. Res. Res. 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

0
0
0
0
0
0

CCR1[15:0]
Res. Res. Res. Res. 6

0
0
0
0
0
0

Res. Res. Res. Res. 5

[2:0]

IC1F[3:0]
OC1M

0
0
0
0
0
0

Res. Res. Res. Res. 4

0
0
0
0

0
0
0
0

CC1NP OC1PE Res. Res. 3

IC1

[1:0]
PSC

0
0
0
0

0
0
0

Res. OC1FE Res. Res. 2

0
0
0
0

0
0
0
0
0
0

CC1P CC1G CC1IF 1

TI1SEL[3:0]
[1:0]
[1:0]

0
0
0
0

0
0
0
0
0
0

CC1S
CC1S

CC1E UG UIF 0
RM0454
RM0454 General-purpose timers (TIM15/TIM16/TIM17)

19 General-purpose timers (TIM15/TIM16/TIM17)

19.1 TIM15/TIM16/TIM17 introduction

The TIM15/TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM15/TIM16/TIM17 timers are completely independent, and do not share any
resources. TIM15 can be synchronized as described in Section 19.4.22: Timer
synchronization (TIM15).

19.2 TIM15 main features

TIM15 includes the following features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Up to 2 independent channels for:
– Input capture
– Output compare
– PWM generation (edge mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time (for channel 1 only)
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together
• Repetition counter to update the timer registers only after a given number of cycles of
the counter
• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow, counter initialization (by software or internal/external
trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
– Break input (interrupt request)

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19.3 TIM16/TIM17 main features

The TIM16/TIM17 timers include the following features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• One channel for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time
• Repetition counter to update the timer registers only after a given number of cycles of
the counter
• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow
– Input capture
– Output compare
– Break input

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Figure 190. TIM15 block diagram

Internal clock (CK_INT) from RCC

Trigger
controller TRGO
to other timers
ITR0 TRG
ITR1 ITR Slave
ITR2 controller Reset, enable, count
TRC TRGI
ITR3 mode
TI1F_ED
TI1FP1
TI2FP2

REP register (1)

U UI
Auto-reload register
Repetition
Stop, clear or up/down U
counter
XOR CK_PSC PSC CK_CNT +/- CNT counter
TI1[0] TI1 prescaler DTG registers
TIMx_CH1 Input CC1I U CC1I
filter & TIMx_CH1
TI1FP1 OC1REF
TI1[1..15] edge IC1 IC1PS Output OC1
TI1FP2 Prescaler Capture/Compare 1 register
detector DTG
control TIMx_CH1N
TRC
CC2I OC1N
TI2[0] U CC2I
TIMx_CH2 Input TI2FP1
TI2 filter & IC2 IC2PS OC2REF Output OC2
TI2FP2 Prescaler Capture/Compare 2 register TIMx_CH2
TI2[1..15] edge control
detector TRC

Internal sources
SBIF

BIF
BRK request
TIMx_BKIN Break circuitry(1)

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output MSv40934V5

1. The internal break event source can be:

- A clock failure event generated by CSS. For further information on the CSS, refer to Section 5.2.8: Clock security system
(CSS)
- SRAM parity error signal
- Cortex®-M0+ LOCKUP (Hardfault) output

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Figure 191. TIM16/TIM17 block diagram

Internal clock (CK_INT)

Counter Enable (CEN)

REP register
To other
Auto-reload register UI timers for
U cross-
Repetition U trigerring(1)
Stop, clear or up/down counter
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler DTG registers
C1I CC1I
TI1[0] Input U TIMx_CH1
TIMx_CH1 TI1FP1 IC1
filter & IC1PS OC1REF Output OC1
Prescaler Capture/compare 1 register
TI1[1..15] edge DTG control TIMx_CH1N
detector
OC1N
Internal sources
SBIF

BIF
BRK request
TIMx_BKIN Break circuitry(2)

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MSv40937V2

1. This signal can be used as trigger for some slave timer, see Section 19.4.23: Using timer output as trigger for other timers
(TIM16/TIM17).
2. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to Section 5.2.8: Clock security system
(CSS)
- SRAM parity error signal
- Cortex®-M0+ LOCKUP (Hardfault) output

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19.4 TIM15/TIM16/TIM17 functional description

19.4.1 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit upcounter with its
related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
• Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in detailed for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 192 and Figure 193 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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Figure 192. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 193. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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19.4.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register,
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

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Figure 194. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

Figure 195. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

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Figure 196. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

Figure 197. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

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Figure 198. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

Figure 199. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

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19.4.3 Repetition counter

Section 19.4.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows. It is actually generated only when the repetition counter
has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows, where N is the
value in the TIMx_RCR repetition counter register.
The repetition counter is decremented at each counter overflow.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 200). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

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Figure 200. Update rate examples depending on mode and TIMx_RCR register
settings

Edge-aligned mode

Upcounting

Counter
TIMx_CNT

TIMx_RCR = 0 UEV

TIMx_RCR = 1 UEV

TIMx_RCR = 2 UEV

TIMx_RCR = 3 UEV

TIMx_RCR = 3
and
re-synchronization UEV

(by SW)

UEV Update Event: preload registers transferred to active registers

and update interrupt generated.

MS31084V2

19.4.4 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin
• Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, TIM1 can be configured to act as a prescaler for TIM15.
Refer to Using one timer as prescaler for another timer on page 473 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed

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only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 201 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 201. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

Figure 202. TI2 external clock connection example

TIMx_SMCR

TS[4:0]

ITRx
000xx
TI1_ED
00100 TRGI External clock
TI1FP1
00101 mode 1 CK_PSC
TI2[0] TI2F_Rising
Edge 0 TI2FP2
Filter 00110
TI2[1..15] detector 1
TI2F_Falling
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER

SMS[2:0]

TIMx_SMCR
MSv40935V1

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:

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1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
4. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
6. Select TI2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register.
7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 203. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

19.4.5 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 204 to Figure 207 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 204. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1[0]
TI1F_Rising
0 TI1FP1
TI1[1..15] Filter Edge
TI1F_Falling 01
fDTS downcounter detector 1

TI2FP1 IC1 Divider IC1PS

10
/1, /2, /4, /8
ICF[3:0] CC1P
TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER
MSv40936V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 205. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
Comparator (from time TIMx_CCMR1
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

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Figure 206. Output stage of capture/compare channel (channel 1)

To the master mode
controller
0 Output OC1
enable
‘0’ 1
x0 circuit
OC1REF OC1REFC
01
OC1_DT CC1P
CNT>CCR1 Output 11
Output Dead-time TIM1_CCER
mode
CNT=CCR1 selector generator
controller OC1N_DT
11
10 0
Output OC1N
OC2REF ‘0’ 0x enable
1 circuit

CC1NE CC1E TIMx_CCER

OC1M[3:0] DTG[7:0] CC1NE CC1E CC1NP MOE OSSI OSSR

TIMx_CCMR1 TIMx_BDTR TIMx_CCER TIMx_CCER TIMx_BDTR
OIS1 OIS1N TIMx_CR2
MSv65226V1

Figure 207. Output stage of capture/compare channel (channel 2 for TIM15)

To the master
mode controller
OC2REFC

OC2REF
‘0’ 0 0
CNT > CCR2 Output OC2
Output enable
Output
mode 1 1 circuit
CNT = CCR2 selector
controller
CC2E CC2P
OC1REF
TIMx_CCER TIMx_CCER CC2E TIMx_CCER
OC2M[3:0]
OIS2 TIMx_CR2
TIMx_CCMR1
MSv65242V1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

19.4.6 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was

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already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
3. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at least 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
4. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIMx_CCER register (rising edge in this case).
5. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
6. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
7. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

19.4.7 PWM input mode (only for TIM15)

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

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For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
1. Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).
4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
and CC2NP bits to ‘10’ (active on falling edge).
6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register
(TI1FP1 selected).
7. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
8. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 208. PWM input mode timing

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.

19.4.8 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.

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Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

19.4.9 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).

Procedure
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 209.

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Figure 209. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

19.4.10 PWM mode

Pulse Width Modulation mode allows a signal to be generated with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The TIM15/TIM16/TIM17 are capable of upcounting only. Refer to Upcounting mode on
page 553.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at

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‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 210 shows some edge-
aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 210. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

19.4.11 Combined PWM mode (TIM15 only)

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with
programmable delay and phase shift between respective pulses. While the frequency is
determined by the value of the TIMx_ARR register, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or
AND logical combination of two reference PWMs:
• OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers
Combined PWM mode can be selected independently on two channels (one OCx output per
pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM
mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as a combined PWM channel, its complementary channel
must be configured in the opposite PWM mode (for instance, one in Combined PWM mode
1 and the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 211 represents an example of signals that can be generated using Asymmetric PWM
mode, obtained with the following configuration:
• Channel 1 is configured in Combined PWM mode 2,
• Channel 2 is configured in PWM mode 1,

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Figure 211. Combined PWM mode on channel 1 and 2

OC2’
OC1’

OC2

OC1

OC1REF
OC2REF

OC1REF’
OC2REF’

OC1REFC

OC1REFC’

OC1REFC = OC1REF AND OC2REF

OC1REFC’ = OC1REF’ OR OC2REF’

MS31094V1

19.4.12 Complementary outputs and dead-time insertion

The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and
manage the switching-off and switching-on of the outputs.
This time is generally known as dead-time and it has to be adjusted depending on the
devices that are connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
The polarity of the outputs (main output OCx or complementary OCxN) can be selected
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 83: Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) on page 622 for more details. In particular, the dead-time is activated when
switching to the idle state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a

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reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
• The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
• The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

Figure 212. Complementary output with dead-time insertion.

OCxREF

OCx
delay
OCxN
delay

MS31095V1

Figure 213. Dead-time waveforms with delay greater than the negative pulse.

OCxREF

OCx

delay
OCxN

MS31096V1

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Figure 214. Dead-time waveforms with delay greater than the positive pulse.

OCxREF

OCx

OCxN

delay

MS31097V1

The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 19.6.14: TIMx break and dead-time
register (TIMx_BDTR)(x = 16 to 17) on page 625 for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows a specific waveform to be sent (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

19.4.13 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals
generated with the TIM15/TIM16/TIM17 timers. The break input is usually connected to fault
outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts
down the PWM outputs and forces them to a predefined safe state.
The break channel gathers both system-level fault (clock failure, parity error,...) and
application fault from input pins. The break circuitry can force the outputs to a predefined
level (either active or inactive) after a deadtime duration.

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The output enable signal and output levels during break are depending on several control
bits:
• the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software
and is reset in case of break or break2 event.
• the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in
inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z
mode)
• the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-
down level, either active or inactive. The OCx and OCxN outputs cannot be set both to
active level at a given time, whatever the OISx and OISxN values. Refer to Table 81:
Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) on page 601 for more details.
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
A programmable filter (BKF[3:0] bits in the TIMx_BDTR register allows to filter out spurious
events.
The break can be generated from multiple sources which can be individually enabled and
with programmable edge sensitivity, using the TIMx_AF1 register.
The sources for break (BRK) channel are:
• An external source connected to one of the BKIN pin (as per selection done in the
AFIO controller), with polarity selection and optional digital filtering
• An internal source:
– A system break:
- the Cortex®-M0+ LOCKUP output
- the SRAM parity error signal
- a Flash ECC error
- a clock failure event generated by the CSS detector

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Figure 215. Break circuitry overview

Lockup LOCK
Core Lockup
System break requests
SBIF flag

Parity LOCK
RAM parity Error

ECC LOCK
ECC Error

CSS

Software break
requests: BG

BKE BIF flag

BKINP BKF[3:0] BKP

BRK request
BKIN inputs BKINE
from AF Filter
controller

BKCMP1P Application break requests

MSv50983V1

Caution: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (example, using the internal PLL and/or the
CSS) must be used to guarantee that break events are handled.
When a break occurs (selected level on the break input):
• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or even releasing the control to the AFIO controller (selected by the OSSI bit). This
feature functions even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control
(taken over by the AFIO controller) else the enable output remains high.
• When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO
controller which forces a Hi-Z state) else the enable outputs remain or become
high as soon as one of the CCxE or CCxNE bits is high.
• The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.

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Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows the configuration
of several parameters to be freezed (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 19.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on
page 625. The LOCK bits can be written only once after an MCU reset.
The Figure 216 shows an example of behavior of the outputs in response to a break.

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Figure 216. Output behavior in response to a break

BREAK (MOE )

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

OCx

OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

MS31098V1

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19.4.14 Bidirectional break inputs

The TIM15/TIM16/TIM17 are featuring bidirectional break I/Os, as represented on
Figure 217.
They allow the following:
• A board-level global break signal available for signaling faults to external MCUs or gate
drivers, with a unique pin being both an input and an output status pin
• Internal break sources and multiple external open drain comparator outputs ORed
together to trigger a unique break event, when multiple internal and external break
sources must be merged
The break input is configured in bidirectional mode using the BKBID bit in the TIMxBDTR
register. The BKBID programming bit can be locked in read-only mode using the LOCK bits
in the TIMxBDTR register (in LOCK level 1 or above).
The bidirectional mode requires the I/O to be configured in open-drain mode with active low
polarity (using BKINP and BKP bits). Any break request coming either from system (e.g.
CSS), from on-chip peripherals or from break inputs forces a low level on the break input to
signal the fault event. The bidirectional mode is inhibited if the polarity bits are not correctly
set (active high polarity), for safety purposes.
The break software event (BG) also causes the break I/O to be forced to '0' to indicate to the
external components that the timer has entered in break state. However, this is valid only if
the break is enabled (BKE = 1). When a software break event is generated with BKE = 0,
the outputs are put in safe state and the break flag is set, but there is no effect on the break
I/O.
A safe disarming mechanism prevents the system to be definitively locked-up (a low level on
the break input triggers a break which enforces a low level on the same input).
When the BKDSRM bit is set to 1, this releases the break output to clear a fault signal and to
give the possibility to re-arm the system.
At no point the break protection circuitry can be disabled:
• The break input path is always active: a break event is active even if the BKDSRM bit is
set and the open drain control is released. This prevents the PWM output to be re-
started as long as the break condition is present.
• The BKDSRM bit cannot disarm the break protection as long as the outputs are
enabled (MOE bit is set) (see Table 79)

Table 79. Break protection disarming conditions

MOE BKDIR BKDSRM Break protection state

0 0 X Armed
0 1 0 Armed
0 1 1 Disarmed
1 X X Armed

Arming and re-arming break circuitry

The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset
configuration).

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The following procedure must be followed to re-arm the protection after a break event:
• The BKDSRM bit must be set to release the output control
• The software must wait until the system break condition disappears (if any) and clear
the SBIF status flag (or clear it systematically before re-arming)
• The software must poll the BKDSRM bit until it is cleared by hardware (when the
application break condition disappears)
From this point, the break circuitry is armed and active, and the MOE bit can be set to re-
enable the PWM outputs.

Figure 217. Output redirection

System break request
SBIF flag
Software break
requests: BG

Peripheral BKE BIF flag

Other break inputs
break sources BKF[3:0] BKP BRK
request
AF input Filter
AF
(active low)
controller
Bidirectional BKIN inputs from Application break requests
Break I/O AF controller

AF output
(open drain)

Bidirectional System break request

mode control logic
Vss
BRK request

MOE BKBID BKBDSRM

MSv42028V2

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19.4.15 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• CNT < CCRx ≤ ARR (in particular, 0 < CCRx)

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Figure 218. Example of one pulse mode

TI2

OC1REF
OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY tPULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the
TIMx_TISEL register.
2. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
3. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’00110’
in the TIMx_SMCR register.
5. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
• Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
Since only 1 pulse is needed, a 1 must be written in the OPM bit in the TIMx_CR1 register to
stop the counter at the next update event (when the counter rolls over from the auto-reload
value back to 0).

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Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

19.4.16 Retriggerable one pulse mode (TIM15 only)

This mode allows the counter to be started in response to a stimulus and to generate a
pulse with a programmable length, but with the following differences with Non-retriggerable
one pulse mode described in Section 19.4.15:
– The pulse starts as soon as the trigger occurs (no programmable delay)
– The pulse is extended if a new trigger occurs before the previous one is completed
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger
mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for
Retrigerrable OPM mode 1 or 2.
If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0
(the ARR register sets the pulse length). If the timer is configured in Down-counting mode,
CCRx must be above or equal to ARR.
Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit are not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.

Figure 219. Retriggerable one pulse mode

TRGI

Counter

Output

MS33106V1

19.4.17 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows both

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the counter value and a potential roll-over condition signaled by the UIFCPY flag, to be
atomically read. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.

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19.4.18 Timer input XOR function (TIM15 only)

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2.
The XOR output can be used with all the timer input functions such as trigger or input
capture. It is useful for measuring the interval between the edges on two input signals, as
shown in Figure 220.

Figure 220. Measuring time interval between edges on 2 signals

TI1
TI2

TI1 XOR TI2

Counter

MS31400V1

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19.4.19 External trigger synchronization (TIM15 only)

The TIM timers are linked together internally for timer synchronization or chaining.
The TIM15 timer can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=’0’ and CC1NP=’0’ in the TIMx_CCER register to validate the polarity (and
detect rising edges only).
2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
3. Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 221. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP = ‘0’ in the TIMx_CCER register to validate the polarity (and
detect low level only).
2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 222. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC2S bits
are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1
register. Write CC2P=’1’ and CC2NP=’0’ in the TIMx_CCER register to validate the
polarity (and detect low level only).
2. Configure the timer in trigger mode by writing SMS=110 in the TIMx_SMCR register.
Select TI2 as the input source by writing TS=00110 in the TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 223. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

19.4.20 Slave mode – combined reset + trigger mode

In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter,
generates an update of the registers, and starts the counter.
This mode is used for one-pulse mode.

19.4.21 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests on a single event.
The main purpose is to be able to re-program several timer registers multiple times without
software overhead, but it can also be used to read several registers in a row, at regular
intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.
On a given timer event, the timer launches a sequence of DMA requests (burst). Each write
into the TIMx_DMAR register is actually redirected to one of the timer registers.

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The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the
number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA
transfers (when read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
For example, the timer DMA burst feature could be used to update the contents of the CCRx
registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the
CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into the CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
This example is for the case where every CCRx register is to be updated once. If every
CCRx register is to be updated twice for example, the number of data to transfer should be
6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5
and data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.

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19.4.22 Timer synchronization (TIM15)

The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 16.3.19: Timer synchronization for details.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.

19.4.23 Using timer output as trigger for other timers (TIM16/TIM17)

The timers with one channel only do not feature a master mode. However, the OC1 output
signal can be used to trigger some other timers (including timers described in other sections
of this document). Check the “TIMx internal trigger connection” table of any TIMx_SMCR
register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer will detect the trigger.
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.

19.4.24 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 29.9.2: Debug support for timers,
watchdog and I2C.
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.

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19.5 TIM15 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

19.5.1 TIM15 control register 1 (TIM15_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
MAP
rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters
(TIx)
00: tDTS = tCK_INT
01: tDTS = 2 * tCK_INT
10: tDTS = 4 * tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.

19.5.2 TIM15 control register 2 (TIM15_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw rw

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 OIS2: Output idle state 2 (OC2 output)
0: OC2=0 when MOE=0
1: OC2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIM15_BDTR register).
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BDTR register).

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Bit 7 TI1S: TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic AND between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the
master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REFC signal is used as trigger output (TRGO).
101: Compare - OC2REFC signal is used as trigger output (TRGO).
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.

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19.5.3 TIM15 slave mode control register (TIM15_SMCR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. MSM TS[2:0] Res. SMS[2:0]
rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if
we want to synchronize several timers on a single external event.
Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
00000: Internal Trigger 0 (ITR0)
00001: Internal Trigger 1 (ITR1)
00010: Internal Trigger 2 (ITR2)
00011: Internal Trigger 3 (ITR3)
00100: TI1 Edge Detector (TI1F_ED)
00101: Filtered Timer Input 1 (TI1FP1)
00110: Filtered Timer Input 2 (TI2FP2)
Other: Reserved
See Table 80: TIMx Internal trigger connection on page 591 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.

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Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the
internal clock.
0001: Reserved
0010: Reserved
0011: Reserved
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and
stop of the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas
the gated mode checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.

Table 80. TIMx Internal trigger connection

Slave TIM ITR0 (TS = 00000) ITR1 (TS = 00001) ITR2 (TS = 00010) ITR3 (TS = 00011)

TIM15 - TIM3 TIM16_OC1 TIM17_OC1

19.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMD
Res. TDE Res. Res. CC2DE CC1DE UDE BIE TIE COMIE Res. Res. CC2IE CC1IE UIE
E
rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled

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Bits 12:11 Reserved, must be kept at reset value.

Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

19.5.5 TIM15 status register (TIM15_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. CC2OF CC1OF Res. BIF TIF COMIF Res. Res. CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

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Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode, both edges in case
gated mode is selected). It is set when the counter starts or stops when gated mode is
selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software.
0: No COM event occurred
1: COM interrupt pending
Bits 4:3 Reserved, must be kept at reset value.

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare
mode) or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred
If channel CC1 is configured as output: this flag is set when the content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer
to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0) and if
the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 19.5.3: TIM15 slave mode
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

19.5.6 TIM15 event generation register (TIM15_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG Res. Res. CC2G CC1G UG
w w rw w w w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled

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Bit 5 COMG: Capture/Compare control update generation

This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected).

19.5.7 TIM15 capture/compare mode register 1 [alternate]

(TIM15_CCMR1)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode.
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F[3:0] IC2PSC[1:0] CC2S[1:0] IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0]: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler

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Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N consecutive events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as
soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.5.8 TIM15 capture/compare mode register 1 [alternate]

(TIM15_CCMR1)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the

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corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M OC1M
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[3] [3]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC1 OC1
Res. OC2M[2:0] CC2S[1:0] Res. OC1M[2:0] CC1S[1:0]
PE FE PE FE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Bits 24, 14:12 OC2M[3:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 Reserved, must be kept at reset value.

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Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive.
0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active.
1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger
event is detected (on TRGI signal). Then, a comparison is performed as in PWM
mode 1 and the channels becomes active again at the next update. In down-counting
mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then,
a comparison is performed as in PWM mode 1 and the channels becomes inactive
again at the next update.
1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a
trigger event is detected (on TRGI signal). Then, a comparison is performed as in
PWM mode 2 and the channels becomes inactive again at the next update. In down-
counting mode, the channel is active until a trigger event is detected (on TRGI
signal). Then, a comparison is performed as in PWM mode 1 and the channels
becomes active again at the next update.
1010: Reserved
1011: Reserved
1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.
OC1REFC is the logical OR between OC1REF and OC2REF.
1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.
OC1REFC is the logical AND between OC1REF and OC2REF.
1110: Reserved,
1111: Reserved,
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
In PWM mode, the OCREF level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM”
mode.
On channels that have a complementary output, this bit field is preloaded. If the CCPC
bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from
the preloaded bits only when a COM event is generated.
The OC1M[3] bit is not contiguous, located in bit 16.

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Bit 3 OC1PE: Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only
if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.5.9 TIM15 capture/compare enable register (TIM15_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP CC1NE CC1P CC1E
rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
Refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output polarity
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description

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Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configured as output:
0: OC1N active high
1: OC1N active low
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to CC1P description.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active
polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising
and falling edges (capture or trigger operations in reset, external clock
or trigger mode), TIxFP1is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0: this configuration is reserved, it must not be used.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Bit 0 CC1E: Capture/Compare 1 output enable
0: Capture mode disabled / OC1 is not active (see below)
1: Capture mode enabled / OC1 signal is output on the corresponding output pin
When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 81
for details.

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Table 81. Output control bits for complementary OCx and OCxN channels with break feature
(TIM15)
Control bits Output states(1)
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state
Output Disabled (not driven by the timer: Hi-Z)
X 0 0 OCx=0
OCxN=0, OCxN_EN=0
Output Disabled (not driven
OCxREF + Polarity
0 0 1 by the timer: Hi-Z)
OCxN=OCxREF XOR CCxNP
OCx=0
Output Disabled (not driven by
OCxREF + Polarity
0 1 0 the timer: Hi-Z)
OCx=OCxREF XOR CCxP
1 X OCxN=0
OCREF + Polarity + dead- Complementary to OCREF (not
X 1 1
time OCREF) + Polarity + dead-time
Off-State (output enabled
OCxREF + Polarity
1 0 1 with inactive state)
OCxN=OCxREF XOR CCxNP
OCx=CCxP
OCxREF + Polarity Off-State (output enabled with
1 1 0 OCx=OCxREF xor CCxP, inactive state)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=1

0 X X
Output disabled (not driven by the timer: Hi-Z)
0 0
0 1 Off-State (output enabled with inactive state)
0 X
1 1 0 Asynchronously: OCx=CCxP, OCxN=CCxNP
Then if the clock is present: OCx=OISx and OCxN=OISxN
1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and AFIO registers.

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19.5.10 TIM15 counter (TIM15_CNT)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UIF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value

19.5.11 TIM15 prescaler (TIM15_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

19.5.12 TIM15 auto-reload register (TIM15_ARR)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 19.4.1: Time-base unit on page 551 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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19.5.13 TIM15 repetition counter register (TIM15_RCR)

Address offset: 0x30
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode.

19.5.14 TIM15 capture/compare register 1 (TIM15_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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19.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

19.5.16 TIM15 break and dead-time register (TIM15_BDTR)

Address offset: 0x44
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK
Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. BKF[3:0]
DSRM
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may
be write-locked depending on the LOCK configuration, it may be necessary to configure all
of them during the first write access to the TIMx_BDTR register.

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 BKBID: Break Bidirectional
0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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Bit 27 Reserved, must be kept at reset value.

Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample the BRK input signal and the length of the
digital filter applied to BRK. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, BRK acts asynchronously
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 19.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 599).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

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Bit 13 BKP: Break polarity

0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 19.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 599).
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
is taken over by the AFIO logic, which forces a Hi-Z state)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 19.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 599).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.

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Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x tdtg with tdtg = tDTS
DTG[7:5] = 10x => DT = (64+DTG[5:0]) x tdtg with tdtg = 2 x tDTS
DTG[7:5] = 110 => DT = (32+DTG[4:0]) x tdtg with tdtg = 8 x tDTS
DTG[7:5] = 111 => DT = (32+DTG[4:0]) x tdtg with tdtg = 16 x tDTS
Example if tDTS = 125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

19.5.17 TIM15 DMA control register (TIM15_DCR)

Address offset: 0x48
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit field defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...

19.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)

Address offset: 0x4C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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General-purpose timers (TIM15/TIM16/TIM17) RM0454

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

19.5.19 TIM15 alternate register 1 (TIM15_AF1)

Address offset: 0x60
Reset value: 0x0000 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. BKINP Res. Res. Res. Res. Res. Res. Res. Res. BKINE
rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active low
1: BKIN input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:1 Reserved, must be kept at reset value.
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is
‘ORed’ with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

19.5.20 TIM15 input selection register (TIM15_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

608/989 RM0454 Rev 5

 0x14
0x10
0x08
0x04
0x00

0x0C
Offset
RM0454

19.5.21

name

TIM15_SR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM15_CR2
TIM15_CR1

TIM15_EGR
TIM15_DIER
TIM15_SMCR
below:
Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. 26
0001: Reserved
0001: Reserved

0010: TIM3_IC1
0010: TIM3_IC2

Others: Reserved
Others: Reserved

TIM15 register map

Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. 24
0000: TIM15_CH1 input
0000: TIM15_CH2 input

Res. Res. Res. Res. Res. Res. 23

Res. Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. 21

TS
[4:3]

0
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. 19
Bits 7:4 Reserved, must be kept at reset value.

Res. Res. Res. Res. Res. Res. 18

Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input

Res. Res. Res. Res. Res. Res. 17

RM0454 Rev 5
0
Res. Res. Res. SMS[3] Res. Res. 16
Res. Res. Res. Res. Res. Res. 15

0
Res. Res. TDE Res. Res. Res. 14

0
Res. Res. COMDE Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. 12

0
Res. Res. Res. Res. Res. UIFREMA 11

0
0
0
Table 82. TIM15 register map and reset values

Res. CC2OF CC2DE Res. OIS2 Res. 10

0
0
0
0
Res. CC1OF CC1DE Res. OIS1N 9
[1:0]
CKD

0
0
0
Res. Res. UDE Res. OIS1 8

0
0
0
0
0
0
BG BIF BIE MSM TI1S ARPE 7

0
0
0
0
0
TG TIF TIE Res. 6

0
0
0
0
0
COMG COMIF COMIE Res. 5

TS[2:0]

0
0
MMS[2:0]
Res. Res. Res. Res. 4
0
0

Res. Res. Res. Res. CCDS OPM 3

0
0
0
0
0
0
TIM15 registers are mapped as 16-bit addressable registers as described in the table

CC2G CC2IF CC2IE CCUS URS 2

0
0
0
0
0

CC1G CC1IF CC1IE Res. UDIS 1

0
0
0
0
0
0

SMS[2:0]
UG UIF UIE CCPC CEN 0
General-purpose timers (TIM15/TIM16/TIM17)

609/989
633
 0x48
0x44
0x38
0x34
0x30
0x28
0x24
0x20
0x18

0x2C
Offset

610/989
mode
Output
name
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM15_PSC
TIM15_CNT

TIM15_DCR
TIM15_RCR
TIM15_ARR
Input Capture

TIM15_CCR2
TIM15_CCR1

TIM15_BDTR
TIM15_CCER
Compare mode

TIM15_CCMR1
TIM15_CCMR1

0
Res. Res. Res. Res. Res. Res. Res. UIFCPY or Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
Res. BKBID Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. BKDSRM Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC2M[3] 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
General-purpose timers (TIM15/TIM16/TIM17)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

BKF[3:0]

RM0454 Rev 5
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[3] 16

0
0
0
1
0
0
0

Res. MOE Res. Res. Res. 15

0
0
0
1
0
0
0
0

Res. AOE Res. Res. 14

0
0
0
1
0
0
0
0

Res. BKP Res. Res. 13

[2:0]

IC2F[3:0]
OC2M

0
0
0
1
0
0
0
0

BKE Res. Res. 12

0
0
0
1
0
0
0
0

OSSR Res. Res. OC2PE 11

IC2

[1:0]
PSC

0
0
0
1
0
0
0
0

OSSI Res. Res. OC2FE 10

0
0
0
1
0
0
0
0

DBL[4:0]
Res. Res. 9

[1:0]
[1:0]
[1:0]

0
0
0
1
0
0
0
0

CC2S
CC2S

LOCK
Res. Res. 8
Table 82. TIM15 register map and reset values (continued)

0
0
0
1
0
0
0

0
0

Res. CC2NP Res. 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

CCR2[15:0]
CCR1[15:0]

0
0
0
1
0
0
0
0

0
Res. Res. 6

0
0
0
1
0
0
0
0

0
0

Res. CC2P 5
[2:0]

IC1F[3:0]
OC1M

0
0
0
1
0
0
0
0

0
0

CC2E 4

0
0
0
1
0
0
0
0

0
0

REP[7:0]
CC1NP OC1PE 3

DTG[7:0]
IC1

[1:0]
PSC

0
0
0
1
0
0
0
0

0
0

CC1NE OC1FE 2

0
0
0
1
0
0

0
0
0

0
0

DBA[4:0]
CC1P 1
[1:0]
[1:0]

0
0
0
0
0

0
1
0
0

0
0
CC1S
CC1S

CC1E 0
RM0454
RM0454 General-purpose timers (TIM15/TIM16/TIM17)

Table 82. TIM15 register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_DMAR DMAB[15:0]
0x4C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKINP

BKINE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_AF1
0x60
Reset value 0 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
TIM15_TISEL TI2SEL[3:0] TI1SEL[3:0]
0x68
Reset value 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

RM0454 Rev 5 611/989

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19.6 TIM16/TIM17 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

19.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFRE
Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
MAP
rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(TIx),
00: tDTS = tCK_INT
01: tDTS = 2 * tCK_INT
10: tDTS = 4 * tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.

612/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM15/TIM16/TIM17)

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit
is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.

19.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. OIS1N OIS1 Res. Res. Res. Res. CCDS CCUS Res. CCPC
rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.

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Bit 0 CCPC: Capture/compare preloaded control

0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

19.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)

Address offset: 0x0C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1DE UDE BIE Res. COMIE Res. Res. Res. CC1IE UIE
rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

614/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM15/TIM16/TIM17)

19.6.4 TIMx status register (TIMx_SR)(x = 16 to 17)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1OF Res. BIF Res. COMIF Res. Res. Res. CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software.
0: No COM event occurred
1: COM interrupt pending
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare
mode) or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred
If channel CC1 is configured as output: this flag is set when the content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer
to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

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Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0)
and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.

19.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. BG Res. COMG Res. Res. Res. CC1G UG
w w w w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected).

616/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM15/TIM16/TIM17)

19.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)

(x = 16 to 17)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode.
Input capture mode:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

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General-purpose timers (TIM15/TIM16/TIM17) RM0454

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input.
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
Others: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.6.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)

(x = 16 to 17)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[3]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0]
rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bits 15:7 Reserved, must be kept at reset value.
Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive.
0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active.
All other values: Reserved
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
The OC1M[3] bit is not contiguous, located in bit 16.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

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Bit 2 OC1FE: Output Compare 1 fast enable

This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
Others: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)

Address offset: 0x20
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP CC1NE CC1P CC1E
rw rw rw rw

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
0: OC1N active high
1: OC1N active low
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to the description of CC1P.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bit only when a commutation event is generated.

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Bit 2 CC1NE: Capture/Compare 1 complementary output enable

0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active
polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge
(capture or trigger operations in reset, external clock or trigger mode),
TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising
and falling edges (capture or trigger operations in reset, external clock
or trigger mode), TIxFP1is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0: this configuration is reserved, it must not be used.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Bit 0 CC1E: Capture/Compare 1 output enable
0: Capture mode disabled / OC1 is not active (see below)
1: Capture mode enabled / OC1 signal is output on the corresponding output pin
When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 83
for details.

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Table 83. Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17)
Control bits Output states(1)

MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state

Output Disabled (not driven by the timer: Hi-Z)

X 0 0 OCx=0
OCxN=0, OCxN_EN=0
Output Disabled (not driven
OCxREF + Polarity
0 0 1 by the timer: Hi-Z)
OCxN=OCxREF XOR CCxNP
OCx=0
Output Disabled (not driven by
OCxREF + Polarity
0 1 0 the timer: Hi-Z)
OCx=OCxREF XOR CCxP
1 X OCxN=0
OCREF + Polarity + dead- Complementary to OCREF (not
X 1 1
time OCREF) + Polarity + dead-time
Off-State (output enabled
OCxREF + Polarity
1 0 1 with inactive state)
OCxN=OCxREF XOR CCxNP
OCx=CCxP
OCxREF + Polarity Off-State (output enabled with
1 1 0 OCx=OCxREF XOR CCxP, inactive state)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=1
0 X X
Output disabled (not driven by the timer: Hi-Z).
0 0
0 1 Off-State (output enabled with inactive state)
0 X
1 1 0 Asynchronously: OCx=CCxP, OCxN=CCxNP
Then if the clock is present: OCx=OISx and OCxN=OISxN
1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and AFIO registers.

19.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value

19.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

19.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 19.4.1: Time-base unit on page 551 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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19.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)

Address offset: 0x30
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode.

19.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)

Address offset: 0x34
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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19.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)

Address offset: 0x44
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK
Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. BKF[3:0]
DSRM
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may
be write-locked depending on the LOCK configuration, it may be necessary to configure all
of them during the first write access to the TIMx_BDTR register.

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 BKBID: Break Bidirectional
0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 27 Reserved, must be kept at reset value.
Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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Bits 25:20 Reserved, must be kept at reset value.

Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample BRK input and the length of the digital
filter applied to BRK. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: No filter, BRK acts asynchronously
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 19.6.8: TIMx capture/compare
enable register (TIMx_CCER)(x = 16 to 17) on page 620).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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Bit 11 OSSR: Off-state selection for Run mode

This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 19.6.8: TIMx capture/compare
enable register (TIMx_CCER)(x = 16 to 17) on page 620).
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
is taken over by the AFIO logic, which forces a Hi-Z state)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 19.6.8: TIMx capture/compare
enable register (TIMx_CCER)(x = 16 to 17) on page 620).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x tdtg with tdtg = tDTS
DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x tdtg with tdtg = 2 x tDTS
DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x tdtg with tdtg = 8 x tDTS
DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x tdtg with tdtg = 16 x tDTS
Example if tDTS = 125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

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19.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)

Address offset: 0x48
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit field defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

19.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)

Address offset: 0x4C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

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RM0454 General-purpose timers (TIM15/TIM16/TIM17)

19.6.17 TIM16 alternate function register 1 (TIM16_AF1)

Address offset: 0x60
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. BKINP Res. Res. Res. Res. Res. Res. Res. Res. BKINE
rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active low
1: BKIN input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:1 Reserved, must be kept at reset value.
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is
‘ORed’ with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

19.6.18 TIM16 input selection register (TIM16_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM16_CH1 input
0001: LSI
0010: LSE
0011: RTC wakeup
0100: MCO2(1)
Others: Reserved

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1. Available on STM32G0B0xx salestypes only, reserved otherwise.

19.6.19 TIM17 alternate function register 1 (TIM17_AF1)

Address offset: 0x60
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. BKINP Res. Res. Res. Res. Res. Res. Res. Res. BKINE
rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active low
1: BKIN input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:1 Reserved, must be kept at reset value.
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is
‘ORed’ with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

19.6.20 TIM17 input selection register (TIM17_TISEL)

Address offset: 0x68
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

630/989 RM0454 Rev 5

RM0454 General-purpose timers (TIM15/TIM16/TIM17)

Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input

0000: TIM17_CH1 input
0001: reserved
0010: HSE/32
0011: MCO
0100: MCO2(1)
Others: Reserved
1. Available on STM32G0B0xx salestypes only, reserved otherwise.

RM0454 Rev 5 631/989

633
 0x28
0x24
0x20
0x18
0x14
0x10
0x04
0x00

0x2C
0x0C
Offset

632/989
19.6.21

mode
Output
name

TIMx_SR
TIMx_CR2
TIMx_CR1

TIMx_PSC
TIMx_CNT

TIMx_ARR
TIMx_EGR
Register

TIMx_DIER

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIMx_CCER
Input Capture
TIMx_CCMR1
TIMx_CCMR1

Compare mode
below:

0
Res. Res. UIFCPY or Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
TIM16/TIM17 register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
General-purpose timers (TIM15/TIM16/TIM17)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

0
Res. Res. Res. Res. Res. OC1M[3] Res. Res. Res. Res. Res. 16

1
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 15

1
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 14

1
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 13

1
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 12

1
0
0
0

Res. Res. Res. Res. Res. Res. Res. UIFREMA 11

1
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 10

1
0
0
0
0
0
0
Table 84. TIM16/TIM17 register map and reset values

Res. Res. Res. Res. CC1OF CC1DE OIS1N 9

[1:0]
CKD

1
0
0
0
0
0

Res. Res. Res. Res. Res. UDE OIS1 8

1
0
0
0
0
0
0
0

Res. Res. BG BIF BIE Res. ARPE 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

1
0
0
0
0
Res. Res. Res. Res. Res. Res. 6

1
0
0
0
0
0
0
0

Res. COMG COMIF COMIE Res. Res. 5

[2:0]

IC1F[3:0]
OC1M

1
0
0
0
0

Res. Res. Res. Res. Res. Res. 4

1
0
0
0
0
0
0
0

CC1NP OC1PE Res. Res. Res. CCDS OPM 3

IC1

[1:0]
PSC

1
0
0
0
0
0
0
0

CC1NE OC1FE Res. Res. Res. CCUS URS 2

1
0
0
0
0
0
0
0
0
0

CC1P CC1G CC1IF CC1IE Res. UDIS 1

S
S

[1:0]
[1:0]

CC1
CC1

1
0
0
0
0
0
0
0
0
0
0
TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table
RM0454

CC1E UG UIF UIE CCPC CEN 0

 0x68
0x68
0x60
0x60
0x48
0x44
0x34
0x30

0x4C
Offset
RM0454

name

TIMx_DCR
TIMx_RCR
Register

TIM17_AF1
TIM16_AF1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIMx_CCR1

TIMx_BDTR

TIMx_DMAR

TIM17_TISEL
TIM16_TISEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
Res. Res. Res. Res. Res. Res. BKBID Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. BKDSRM Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0

Res. Res. Res. Res. Res. Res. Res. Res. 18

0

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. 17
BKF[3:0]

Res. Res. Res. Res. 0 Res. Res. Res. Res. 16

0
0

Res. Res. Res. Res. Res. MOE Res. 15

0
0
0

Res. Res. Res. Res. Res. AOE Res. 14

0
0
0

Res. Res. Res. Res. Res. BKP Res. 13

0
0

0
0

Res. Res. Res. Res. BKE Res. 12

0
0

0
0

Res. Res. Res. Res. OSSR Res. 11

0
0

0
0

Res. Res. Res. Res. OSSI Res. 10

0
0

0
0
0
0

DBL[4:0]

Res. Res. BKINP BKINP Res. 9

K

Refer to Section 2.2 on page 44 for the register boundary addresses.

[1:0]
LOC

0
0

0
0

Res. Res. Res. Res. Res. 8

0
0
0
0

Res. Res. Res. Res. Res. 7

Table 84. TIM16/TIM17 register map and reset values (continued)

CCR1[15:0]

DMAB[15:0]

0
0
0
0

Res. Res. Res. Res. Res. 6

0
0
0
0

Res. Res. Res. Res. Res. 5

0
0

0
0
0

Res. Res. Res. Res. 4

0
0

0
0

0
0
0

Res. Res. 3
REP[7:0]

DTG[7:0]

0
0

0
0

0
0
0

Res. Res. 2
0
0
0

0
0
0
0

DBA[4:0]

Res. Res. 1
TI1SEL[3:0]
TI1SEL[3:0]
0
0
0

0
0
1
1
0
0

BKINE BKINE
General-purpose timers (TIM15/TIM16/TIM17)

633/989
0

633
Infrared interface (IRTIM) RM0454

20 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions.
It uses internal connections with USART1, USART4 (on STM32G070/B0xx) or USART2
(STM32G030/50xx), TIM16 and TIM17 as shown in Figure 224.
To generate the infrared remote control signals, the IR interface must be enabled and TIM16
channel 1 (TIM16_OC1) and TIM17 channel 1 (TIM17_OC1) must be properly configured to
generate correct waveforms.
The infrared receiver can be implemented easily through a basic input capture mode.

Figure 224. IRTIM internal hardware connections

TIM17_CH1

IRTIM
IR_OUT
TIM16_CH1

USART1

USART4(1)

IR_MOD[1:0] IR_POL
MS44790V2

2. USART4 (on STM32G070/B0xx) or USART2 (STM32G030/50xx).

All standard IR pulse modulation modes can be obtained by programming the two timer
output compare channels.
TIM17 is used to generate the high frequency carrier signal, while TIM16 or alternatively
USART1 or USART4(a) generates the modulation envelope according to the setting of the
IR_MOD[1:0] bits in the SYSCFG_CFGR1 register.
The polarity of the output signal from IRTIM is controlled by the IR_POL bit in the
SYSCFG_CFGR1 register and could be inverted by setting of this bit.
The infrared function is output on the IR_OUT pin. The activation of this function is done
through the GPIOx_AFRx register by enabling the related alternate function bit.
The high sink LED driver capability (only available on the PB9 pin) can be activated through
the I2C_PB9_FMP bit in the SYSCFG_CFGR1 register and used to sink the high current
needed to directly control an infrared LED.

a. USART4 (on STM32G070/B0xx) or USART2 (STM32G030/50xx).

634/989 RM0454 Rev 5

RM0454 Independent watchdog (IWDG)

21 Independent watchdog (IWDG)

21.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 22 on page
644.

21.2 IWDG main features

• Free-running downcounter
• Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
• Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
– Reset (if watchdog activated) if the downcounter is reloaded outside the window

21.3 IWDG functional description

21.3.1 IWDG block diagram

Figure 225 shows the functional blocks of the independent watchdog module.

Figure 225. Independent watchdog block diagram

VDD
Prescaler register Status register Reload register Key register
IWDG_PR IWDG_SR IWDG_RLR IWDG_KR

12-bit reload value

LSI 8-bit
(32 kHz) prescaler
12-bit downcounter IWDG reset
VDD voltage domain

MSv37838V1

1. The register interface is located in the VDD voltage domain. The watchdog function is located in the VDD
voltage domain, still functional in Stop and Standby modes.

RM0454 Rev 5 635/989

643
Independent watchdog (IWDG) RM0454

When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG
key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF.
When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
Once running, the IWDG cannot be stopped.

21.3.2 Window option

The IWDG can also work as a window watchdog by setting the appropriate window in the
IWDG window register (IWDG_WINR).
If the reload operation is performed while the counter is greater than the value stored in the
IWDG window register (IWDG_WINR), then a reset is provided.
The default value of the IWDG window register (IWDG_WINR) is 0x0000 0FFF, so if it is not
updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset
the downcounter to the IWDG reload register (IWDG_RLR) value and ease the cycle
number calculation to generate the next reload.

Configuring the IWDG when the window option is enabled

1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the IWDG prescaler by programming IWDG prescaler register (IWDG_PR) from
0 to 7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Write to the IWDG window register (IWDG_WINR). This automatically refreshes the
counter value in the IWDG reload register (IWDG_RLR).
Note: Writing the window value allows the counter value to be refreshed by the RLR when IWDG
status register (IWDG_SR) is set to 0x0000 0000.

Configuring the IWDG when the window option is disabled

When the window option it is not used, the IWDG can be configured as follows:
1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the prescaler by programming the IWDG prescaler register (IWDG_PR) from 0 to
7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA).

636/989 RM0454 Rev 5

RM0454 Independent watchdog (IWDG)

21.3.3 Hardware watchdog

If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the IWDG key register
(IWDG_KR) is written by the software before the counter reaches end of count or if the
downcounter is reloaded inside the window.

21.3.4 Register access protection

Write access to IWDG prescaler register (IWDG_PR), IWDG reload register (IWDG_RLR)
and IWDG window register (IWDG_WINR) is protected. To modify them, the user must first
write the code 0x0000 5555 in the IWDG key register (IWDG_KR). A write access to this
register with a different value breaks the sequence and register access is protected again.
This is the case of the reload operation (writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or of the
downcounter reload value or of the window value is ongoing.

21.3.5 Debug mode

When the device enters Debug mode (core halted), the IWDG counter either continues to
work normally or stops, depending on the configuration of the corresponding bit in
DBGMCU freeze register.

RM0454 Rev 5 637/989

643
Independent watchdog (IWDG) RM0454

21.4 IWDG registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

21.4.1 IWDG key register (IWDG_KR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see Section 21.3.4: Register access protection)
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option
is selected)

638/989 RM0454 Rev 5

RM0454 Independent watchdog (IWDG)

21.4.2 IWDG prescaler register (IWDG_PR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0]

rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see Section 21.3.4: Register access protection. They
are written by software to select the prescaler divider feeding the counter clock. PVU bit of
the IWDG status register (IWDG_SR) must be reset in order to be able to change the
prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG
status register (IWDG_SR) is reset.

RM0454 Rev 5 639/989

643
Independent watchdog (IWDG) RM0454

21.4.3 IWDG reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. RL[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Register access protection. They are written by
software to define the value to be loaded in the watchdog counter each time the value
0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts
down from this value. The timeout period is a function of this value and the clock prescaler.
Refer to the datasheet for the timeout information.
The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the
reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on it. For this
reason the value read from this register is valid only when the RVU bit in the IWDG
status register (IWDG_SR) is reset.

640/989 RM0454 Rev 5

RM0454 Independent watchdog (IWDG)

21.4.4 IWDG status register (IWDG_SR)

Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU

r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 WVU: Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is ongoing. It is
reset by hardware when the reload value update operation is completed in the VDD voltage
domain (takes up to five LSI cycles).
Window value can be updated only when WVU bit is reset.
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to five LSI cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to five LSI cycles).
Prescaler value can be updated only when PVU bit is reset.

Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.

RM0454 Rev 5 641/989

643
Independent watchdog (IWDG) RM0454

21.4.5 IWDG window register (IWDG_WINR)

Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. WIN[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected, see Section 21.3.4, they contain the high limit of the
window value to be compared with the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to
change the reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG status register
(IWDG_SR) is reset.

642/989 RM0454 Rev 5

 0x10
0x08
0x04
0x00

0x0C
Offset
21.4.6
RM0454

name

IWDG_SR
IWDG_PR
IWDG_KR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

IWDG_RLR

IWDG_WINR
Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res.
IWDG register map

25
Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res.

RM0454 Rev 5
17
Res. Res. Res. Res. Res. 16
0

Res. Res. Res. Res. 15

0

Res. Res. Res. Res. 14

0

Res. Res. Res. Res. 13

0

Res. Res. Res. Res. 12

1
1
0

Res. Res. 11
Table 85. IWDG register map and reset values

1
1
0

Res. Res. 10
The following table gives the IWDG register map and reset values.

1
1
0

Res. Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.
1
1
0

Res. Res. 8
1
1
0

Res. Res. 7
KEY[15:0]

1
1
0

Res. Res. 6
1
1
0

Res. Res. 5
RL[11:0]

WIN[11:0]

1
1
0

Res. Res. 4
1
1
0

Res. Res. 3
1
1
0

0
0

WVU 2
1
1
0

0
0

RVU 1
PR[2:0]

1
1
0

0
0

PVU
Independent watchdog (IWDG)

643/989
0

643
System window watchdog (WWDG) RM0454

22 System window watchdog (WWDG)

22.1 Introduction
The system window watchdog (WWDG) is used to detect the occurrence of a software fault,
usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its normal sequence. The watchdog circuit
generates an MCU reset on expiry of a programmed time period, unless the program
refreshes the contents of the down-counter before the T6 bit becomes cleared. An MCU
reset is also generated if the 7-bit down-counter value (in the control register) is refreshed
before the down-counter has reached the window register value. This implies that the
counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that
can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an
accurate timing window.

22.2 WWDG main features

• Programmable free-running down-counter
• Conditional reset
– Reset (if watchdog activated) when the down-counter value becomes lower than
0x40
– Reset (if watchdog activated) if the down-counter is reloaded outside the window
(see Figure 227)
• Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when
the down-counter is equal to 0x40.

22.3 WWDG functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit down-counter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it
initiates a reset. If the software reloads the counter while the counter is greater than the
value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value and higher than 0x3F. The value to be stored
in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 226 for the WWDG block diagram.

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22.3.1 WWDG block diagram

Figure 226. Watchdog block diagram

WWDG
Register interface CMP = 1 when
W[6:0] T[6:0] > W[6:0]
APB bus

WWDG_CFR

CMP
wwdg_out_rst

WWDG_SR WDGA
Write to WWDG_CR
T[6:0] T6

= 0x40 ?
readback

Logic
WWDG_CR T[6:0] EWI wwdg_it
cnt_out EWIF
preload
7-bit DownCounter (CNT)

pclk ÷ 4096 ÷ 2WDGTB

MS47214V1

22.3.2 Enabling the watchdog

When the user option WWDG_SW selects “Software window watchdog”, the watchdog is
always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR
register, then it cannot be disabled again except by a reset.
When the user option WWDG_SW selects “Hardware window watchdog”, the watchdog is
always enabled after a reset, it cannot be disabled.

22.3.3 Controlling the down-counter

This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 227). The WWDG configuration register (WWDG_CFR) contains the high limit of the
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
the window register value and greater than 0x3F. Figure 227 describes the window
watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

22.3.4 How to program the watchdog timeout

Use the formula in Figure 227 to calculate the WWDG timeout.

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Warning: When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

Figure 227. Window watchdog timing diagram

CNT DownCounter
Refresh not allowed Refresh allowed

T[6:0]

W[6:0]

0x3F
Time
Tpclk x 4096 x 2WDGTB
0x41
0x40
0x3F

wwdg_ewit

EWIF = 0
wwdg_rst

T6 bit

MS47266V1

The formula to calculate the timeout value is given by:

WDGTB[1:0]
t WWDG = t PCLK × 4096 × 2 × ( T [ 5:0 ] + 1 ) ( ms )

where:
tWWDG: WWDG timeout
tPCLK: APB clock period measured in ms
4096: value corresponding to internal divider

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As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[1:0] is set to 3 and
T[5:0] is set to 63:
3
t WWDG = ( 1 ⁄ 48000 ) × 4096 × 2 × ( 63 + 1 ) = 43.69ms

Refer to the datasheet for the minimum and maximum values of the tWWDG.

22.3.5 Debug mode

When the device enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details refer to Section 29: Debug support (DBG).

22.4 WWDG interrupts

The early wakeup interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the actual reset is generated. The EWI interrupt is enabled by
setting the EWI bit in the WWDG_CFR register. When the down-counter reaches the value
0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)
can be used to trigger specific actions (such as communications or data logging), before
resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case, the corresponding interrupt service routine (ISR) has to reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset is eventually generated.

22.5 WWDG registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).

22.5.1 WWDG control register (WWDG_CR)

Address offset: 0x000
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]

rs rw rw rw rw rw rw rw

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Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter, decremented every
(4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).

22.5.2 WWDG configuration register (WWDG_CFR)

Address offset: 0x004
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. WDGTB[2:0] Res. EWI Res. Res. W[6:0]
rw rw rw rs rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 13:11 WDGTB[2:0]: Timer base
The timebase of the prescaler can be modified as follows:
000: CK Counter Clock (PCLK div 4096) div 1
001: CK Counter Clock (PCLK div 4096) div 2
010: CK Counter Clock (PCLK div 4096) div 4
011: CK Counter Clock (PCLK div 4096) div 8
100: CK Counter Clock (PCLK div 4096) div 16
101: CK Counter Clock (PCLK div 4096) div 32
110: CK Counter Clock (PCLK div 4096) div 64
111: CK Counter Clock (PCLK div 4096) div 128
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared with the down-counter.

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22.5.3 WWDG status register (WWDG_SR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF
rc_w0

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing ‘0’. Writing ‘1’ has no effect. This bit is also set if the interrupt is not
enabled.

22.5.4 WWDG register map

The following table gives the WWDG register map and reset values.

Table 86. WWDG register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
WDGA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDG_CR Res. T[6:0]
0x000

Reset value 0 1 1 1 1 1 1 1

WDGTB
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
EWI

WWDG_CFR W[6:0]
0x004 [2:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1

EWIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDG_SR
0x008

Reset value 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

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23 Real-time clock (RTC)

23.1 Introduction
The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupts.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).
The RTC is functional in VBAT mode.

23.2 RTC main features

The RTC supports the following features (see Figure 228: RTC block diagram):
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.

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23.3 RTC functional description

23.3.1 RTC block diagram

Figure 228. RTC block diagram

rtc_tamp_evt
rtc_its TSF
Time stamp detection
RTC_TS
Time stamp registers

RTC_TSTR
RTC_TSDR
RTC_TSSR

RTC_REFIN

RTC_CALR RTC_PRER RTC_PRER ck_spre

rtc_ker_ck (default 1 Hz)
Asynchronous Synchronous
Smooth prescaler prescaler rtc_calovf
calibration (default = 128) (default = 256) Calendar
Shadow register Shadow registers
ck_apre RTC_SSR RTC_TR,
WUCKSEL[1:0] (default 256 Hz) RTC_DR
ck_apre clock domain
Prescaler
2, 4, 8, 16

CALIB
RTC_OUT1
TAMP Output
TAMPALARM
TAMPOE control
RTC_OUT2
ALARM
ck_wut RTC_WUTR
WUTF OSEL[1:0]
rtc_wut_trg
16-bit wakeup =0
auto reload timer
ck_wut clock domain

Alarm A ALRAF
rtc_alra_trg
RTC_ALRMAR =
RTC_ALRMASSR

Alarm B ALRBF
rtc_alrb_trg
RTC_ALRMBR =
RTC_ALRMBSSR

rtc_ker_ck clock domain

rtc_it
IRQ interface

rtc_pclk
Registers interface
rtc_pclk clock domain
MSv47411V2

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23.3.2 RTC pins and internal signals

Table 87. RTC input/output pins

Pin name Signal type Description

RTC_TS Input RTC timestamp input

RTC_REFIN Input RTC 50 or 60 Hz reference clock input
RTC_OUT1 Output RTC output 1
RTC_OUT2 Output RTC output 2

• RTC_OUT1 and RTC_OUT2 which selects one of the following two outputs:
– CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz). This
output is enabled by setting the COE bit in the RTC_CR register.
– TAMPALRM: This output is the OR between TAMP and ALARM outputs.
ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select
the alarm A, alarm B or wakeup outputs. TAMP is enabled by setting the TAMPOE bit in the
RTC_CR register which selects the tamper event outputs.

Table 88. RTC internal input/output signals

Internal signal name Signal type Description

RTC kernel clock, also named RTCCLK in

rtc_ker_ck Input
this document
rtc_pclk Input RTC APB clock
rtc_its Input RTC internal timestamp event
Tamper event (internal or external) detected
rtc_tamp_evt Input
in TAMP peripheral
RTC interrupts (refer to Section 23.5: RTC
rtc_it Output
interrupts for details)
rtc_alra_trg Output RTC alarm A event detection trigger
rtc_alrb_trg Output RTC alarm B event detection trigger
rtc_wut_trg Output RTC wakeup timer event detection trigger
rtc_calovf Output RTC calendar overflow

The RTC kernel clock is usually the LSE at 32.768 kHz although it is possible to select other
clock sources in the RCC (refer to RCC for more details). Some functions are not available
in some low-power modes or VBAT when the selected clock is not LSE. Refer to
Section 23.4: RTC low-power modes for more details.

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Table 89. RTC interconnection

Signal name Source/destination

From power controller (PWR): main power loss/switch to VBAT detection

rtc_its
output
rtc_tamp_evt From TAMP peripheral: tamp_evt
rtc_calovf To TAMP peripheral: tamp_itamp5

The triggers outputs can be used as triggers for other peripherals.

23.3.3 GPIOs controlled by the RTC and TAMP

The GPIOs included in the Battery Backup Domain (VBAT) are directly controlled by the
peripherals providing functions on these I/Os, whatever the GPIO configuration.
Both RTC and TAMP peripherals provide functions on these I/Os (refer to Section 24:
Tamper and backup registers (TAMP)).
RTC_OUT1, RTC_TS and TAMP_IN1 are mapped on the same pin (PC13). The RTC and
TAMP functions mapped on PC13 are available in all low-power modes and in VBAT mode.
The output mechanism follows the priority order shown in Table 90.

Table 90. PC13 configuration(1)

(TAMP_IN1 input enable)

(TAMPER output enable)
(ALARM output enable)

(RTC_TS input enable)

(CALIB output enable)

TAMPALRM_TYPE

TAMPALRM_PU
OSEL[1:0]

TAMPOE

OUT2EN

TAMP1E
COE

TSE
PC13 Pin function

01 or
10 or 0
11
TAMPALRM output Don’t Don’t Don’t Don’t
00 1 0 0
Push-Pull care care care care
01 or
10 or 1
11

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Table 90. PC13 configuration(1) (continued)

(TAMP_IN1 input enable)

(TAMPER output enable)
(ALARM output enable)

(RTC_TS input enable)

(CALIB output enable)

TAMPALRM_TYPE

TAMPALRM_PU
OSEL[1:0]

TAMPOE

OUT2EN

TAMP1E
COE

TSE
PC13 Pin function

01 or
10 or 0
11
Don’t Don’t Don’t Don’t
No pull 00 1 1 0
care care care care
01 or
10 or 1
TAMPALRM 11
output
Open-Drain(2) 01 or
10 or 0
11
Internal Don’t Don’t Don’t Don’t
00 1 1 1
pull-up care care care care
01 or
10 or 1
11
Don’t Don’t Don’t Don’t
CALIB output PP 00 0 1 0
care care care care
Don’t
00 0 0
care
Don’t Don’t
TAMP_IN1 input floating 00 0 1 1 0
care care
Don’t Don’t 1
0
care care
Don’t
00 0 0
care
RTC_TS and TAMP_IN1 Don’t Don’t
00 0 1 1 1
input floating care care
Don’t Don’t 1
0
care care
Don’t
00 0 0
care
Don’t Don’t
RTC_TS input floating 00 0 1 0 1
care care
Don’t Don’t 1
0
care care

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Table 90. PC13 configuration(1) (continued)

(TAMP_IN1 input enable)

(TAMPER output enable)
(ALARM output enable)

(RTC_TS input enable)

(CALIB output enable)

TAMPALRM_TYPE

TAMPALRM_PU
OSEL[1:0]

TAMPOE

OUT2EN

TAMP1E
COE

TSE
PC13 Pin function

Don’t
00 0 0
care
Wakeup pin or Standard Don’t Don’t
00 0 1 0 0
GPIO care care
Don’t Don’t 1
0
care care
1. OD: open drain; PP: push-pull.
2. In this configuration the GPIO must be configured in input.

In addition, it is possible to output RTC_OUT2 on PA4 pin thanks to OUT2EN bit. This
output is not available in VBAT mode. The different functions are mapped on RTC_OUT1 or
on RTC_OUT2 depending on OSEL, COE and OUT2EN configuration, as show in table
Table 91.
For PA4, the GPIO should be configured as an alternate function.

Table 91. RTC_OUT mapping

OSEL[1:0] bits
COE bit (CALIB OUT2EN RTC_OUT1 on RTC_OUT2 on
ALARM
output enable) bit PC13 PA4
output enable)

00 0 - -
00 1 0 CALIB -
01 or 10 or 11 Don’t care TAMPALRM -
00 0 - -
00 1 - CALIB
1
01 or 10 or 11 0 - TAMPALRM
01 or 10 or 11 1 TAMPALRM CALIB

23.3.4 Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to Section 5: Reset and clock control (RCC).

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A programmable prescaler stage generates a 1 Hz clock which is used to update the

calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 228: RTC block diagram):
• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.
fck_apre is given by the following formula:
f RTCCLK
f CK_APRE = --------------------------------------
-
PREDIV_A + 1

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
f RTCCLK
f CK_SPRE = ----------------------------------------------------------------------------------------------
( PREDIV_S + 1 ) × ( PREDIV_A + 1 )

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 23.3.7: Periodic auto-wakeup for details).

23.3.5 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.
• RTC_SSR for the subseconds
• RTC_TR for the time
• RTC_DR for the date
Every RTCCLK periods, the current calendar value is copied into the shadow registers, and
the RSF bit of RTC_ICSR register is set (see Section 23.6.10: RTC shift control register
(RTC_SHIFTR)). The copy is not performed in Stop and Standby mode. When exiting these
modes, the shadow registers are updated after up to 4 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the

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BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD = 0 mode, the
frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock
(fRTCCLK).
The shadow registers are reset by system reset.

23.3.6 Programmable alarms

The RTC unit provides programmable alarm: alarm A and alarm B. The description below is
given for alarm A, but can be translated in the same way for alarm B.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR
register.
The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day
match the values programmed in the alarm registers RTC_ALRMASSR and
RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits
of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR
register.
The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.
Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous
prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct
behavior.
Alarm A and alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
TAMPALRM output. TAMPALRM output polarity can be configured through bit POL the
RTC_CR register.

23.3.7 Periodic auto-wakeup

The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input ck_wut can be:
• RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE (32.768 kHz), this allows to configure the wakeup interrupt
period from 122 µs to 32 s, with a resolution down to 61 µs.
• ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1 Hz, this allows to achieve a wakeup time from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
– from 1 s to 18 hours when WUCKSEL [2:1] = 10
– and from around 18 h to 36 h when WUCKSEL[2:1] = 11. In this last case 216 is
added to the 16-bit counter current value. When the initialization sequence is
complete (see Programming the wakeup timer on page 659), the timer starts
counting down. When the wakeup function is enabled, the down-counting remains
active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in

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the RTC_SR register, and the wakeup counter is automatically reloaded with its
reload value (RTC_WUTR register value).
The WUTF flag must then be cleared by software.
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR
register, it can exit the device from low-power modes.
The periodic wakeup flag can be routed to the TAMPALRM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. TAMPALRM output polarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on
the wakeup timer.

23.3.8 RTC initialization and configuration

RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when BYPSHAD
= 0.

RTC register write protection

After system reset, the RTC registers are protected against parasitic write access by the
DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit
must be set in order to enable RTC registers write access.
After Backup domain reset, some of the RTC registers are write-protected.
Writing to the protected RTC registers is enabled by writing a key into the Write Protection
register, RTC_WPR.
The following steps are required to unlock the write protection on the protected RTC
registers.
1. Write 0xCA into the RTC_WPR register.
2. Write 0x53 into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:

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1. Set INIT bit to 1 in the RTC_ICSR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ICSR register. The initialization phase mode is entered
when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock
synchronization).
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors
in RTC_PRER register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.
Note: After a system reset, the application can read the INITS flag in the RTC_ICSR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its Backup domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ICSR register.

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP
of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one
single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

A similar procedure must be followed to program or update the programmable alarms. The
procedure below is given for alarm A but can be translated in the same way for alarm B.
1. Clear ALRAE in RTC_CR to disable alarm A.
2. Program the alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).
3. Set ALRAE in the RTC_CR register to enable alarm A again.
Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock
cycles due to clock synchronization.

Programming the wakeup timer

The following sequence is required to configure or change the wakeup timer auto-reload
value (WUT[15:0] in RTC_WUTR):
1. Clear WUTE in RTC_CR to disable the wakeup timer.
2. Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup auto-
reload counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
calendar initialization mode. It takes around 2 RTCCLK clock cycles (due to clock
synchronization).
3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection
(WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again.

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The wakeup timer restarts down-counting.The WUTWF bit is cleared up to 2 RTCCLK

clocks cycles after WUTE is cleared, due to clock synchronization.

23.3.9 Reading the calendar

When BYPSHAD control bit is cleared in the RTC_CR register
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1
clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock
frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.
If the APB1 clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB1 clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ICSR register each time the calendar registers are copied into
the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every
RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or
RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is
read. In case the software makes read accesses to the calendar in a time interval smaller
than 1 RTCCLK periods: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR
and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and
RTC_DR registers.
The RSF bit must be cleared after wakeup and not before entering low-power mode.
After a system reset, the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to
their default values.
After an initialization (refer to Calendar initialization and configuration on page 658): the
software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR
registers.
After synchronization (refer to Section 23.3.11: RTC synchronization): the software must
wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus
eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting
from low-power modes (Stop or Standby), since the shadow registers are not updated
during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be
coherent with each other if an RTCCLK edge occurs between two read accesses to the
registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge
occurs during the read operation. The software must read all the registers twice, and then
compare the results to confirm that the data is coherent and correct. Alternatively, the
software can just compare the two results of the least-significant calendar register.

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Note: While BYPSHAD = 1, instructions which read the calendar registers require one extra APB
cycle to complete.

23.3.10 Resetting the RTC

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the
RTC status register (RTC_ICSR) are reset to their default values by all available system
reset sources.
On the contrary, the following registers are reset to their default values by a Backup domain
reset and are not affected by a system reset: the RTC current calendar registers, the RTC
control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register
(RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers
(RTC_TSSSR, RTC_TSTR and RTC_TSDR), the wakeup timer register (RTC_WUTR), and
the alarm A and alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and
RTC_ALRMBSSR/RTC_ALRMBR).
In addition, when clocked by LSE, the RTC keeps on running under system reset if the reset
source is different from the Backup domain reset one (refer to RCC for details about RTC
clock sources not affected by system reset). When a Backup domain reset occurs, the RTC
is stopped and all the RTC registers are set to their reset values.

23.3.11 RTC synchronization

The RTC can be synchronized to a remote clock with a high degree of precision. After
reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the
precise offset between the times being maintained by the remote clock and the RTC. The
RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a
second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to
calculate the exact time being maintained by the RTC down to a resolution of
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution
allowed (30.52 µs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to
maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the
asynchronous prescaler output increases, which may increase the RTC dynamic
consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing
to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a
resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the
SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.
If at the same time the ADD1S bit is set, this results in adding one second and at the same
time subtracting a fraction of second, so this will advance the clock.
Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that
no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF
flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by
hardware as soon as the shift operation has completed.

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Caution: This synchronization feature is not compatible with the reference clock detection feature:
firmware must not write to RTC_SHIFTR when REFCKON = 1.

23.3.12 RTC reference clock detection

The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN,
which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN
reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN
detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the
LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update
frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found
within a given time window). In most cases, the two clock edges are properly aligned. When
the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts
the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism,
the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock
(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the asynchronous prescaler which
outputs the ck_spre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same
moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their
default values:
• PREDIV_A = 0x007F
• PREVID_S = 0x00FF
Note: RTC_REFIN clock detection is not available in Standby mode.

23.3.13 RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a
range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using
series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.

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The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-
second cycle.
• Setting CALM[1] to 1 causes two additional cycles to be masked
• Setting CALM[2] to 1 causes four additional cycles to be masked
• and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.
Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during
the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1] = 1 causes two
other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2] = 1 causes
four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on
up to CALM[8] = 1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to 1 effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that
512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency
(FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]

Calibration when PREDIV_A < 3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct
setting if RTCCLK is exactly 32768.00 Hz.

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Verifying the RTC calibration

RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating
the correct CALM value and CALP values. An optional 1 Hz output is provided to allow
applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a
measurement error of up to 2 RTCCLK clock cycles over the measurement period,
depending on how the digital calibration cycle is aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same
length as the calibration cycle period. In this case, the only error observed is the error due to
the resolution of the digital calibration.
• By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds
guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds,
due to the limitation of the calibration resolution).
• CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration
cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum error
of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0]
bit is stuck at 0 when CALW16 is set to 1.
• CALW8 bit of the RTC_CALR register can be set to 1 to force a 8-second calibration
cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of
1.907 ppm (0.5 RTCCLK cycles over 8 s). The long term RTC precision is also reduced to
1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ICSR/INITF = 0,
by using the follow process:
1. Poll the RTC_ICSR/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1
3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.

23.3.14 Timestamp function

Timestamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1.
When TSE is set:
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a timestamp event is detected on the RTC_TS pin.
When TAMPTS is set:
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a tamper event is detected on the TAMP_INx pinx.
When ITSE is set:

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The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)

when an internal timestamp event is detected. The internal timestamp event is generated by
the switch to the VBAT supply.
When a timestamp event occurs, due to internal or external event, the timestamp flag bit
(TSF) in RTC_SR register is set. In case the event is internal, the ITSF flag is also set in
RTC_SR register.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp
event occurs.
If a new timestamp event is detected while the timestamp flag (TSF) is already set, the
timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.
Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two timestamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.
Caution: If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then
both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the
same moment, the application must not write 0 into TSF bit unless it has already read it to 1.
Optionally, a tamper event can cause a timestamp to be recorded. See the description of the
TAMPTS control bit in the RTC control register (RTC_CR).

23.3.15 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
CALIB device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the CALIB
frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK
frequency at 32.768 kHz. The CALIB duty cycle is irregular: there is a light jitter on falling
edges. It is therefore recommended to use rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz.
Note: When the CALIB output is selected, the RTC_OUT1 pin is automatically configured but the
RTC_OUT2 pin must be set as alternate function.
When COSEL is cleared, the CALIB output is the output of the 6th stage of the
asynchronous prescaler.
When COSEL is set, the CALIB output is the output of the 8th stage of the synchronous
prescaler.

23.3.16 Tamper and alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output
TAMPALRM, and to select the function which is output. These functions reflect the contents
of the corresponding flags in the RTC_SR register.

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When the TAMPOE control bit is set is the RTC_CR, all external and internal tamper flags
are ORed and routed to the TAMPALRM output. If OSEL = 00 the TAMPALRM output
reflects only the tampers flags. If OSEL ≠ 00, the signal on TAMPALRM provides both
tamper flags and alarm A, B, or wakeup flag.
The polarity of the TAMPALRM output is determined by the POL control bit in RTC_CR so
that the opposite of the selected flags bit is output when POL is set to 1.

TAMPALRM output
The TAMPALRM pin can be configured in output open drain or output push-pull using the
control bit TAMPALRM_TYPE in the RTC_CR register. It is possible to apply the internal
pull-up in output mode thanks to TAMPALRM_PU in the RTC_CR.
Note: Once the TAMPALRM output is enabled, it has priority over CALIB on RTC_OUT1.
When TAMPALRM output is selected, the RTC_OUT1 pin is automatically configured but
the RTC_OUT2 pin must be set as alternate function. In case the TAMPALRM is configured
open-drain in the RTC, the RTC_OUT1 GPIO must be configured as input.

23.4 RTC low-power modes

Table 92. Effect of low-power modes on RTC
Mode Description

No effect
Sleep
RTC interrupts cause the device to exit the Sleep mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC interrupts
Stop
cause the device to exit the Stop mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC interrupts
Standby
cause the device to exit the Standby mode.

The table below summarizes the RTC pins and functions capability in all modes.

Table 93. RTC pins functionality over modes

Functional in all low-
Functional in Standby Functional in VBAT
Functions power modes except
mode mode
Standby modes

RTC_TS Yes Yes Yes

RTC_REFIN Yes No No
RTC_OUT1 Yes Yes Yes
RTC_OUT2 Yes Yes No

23.5 RTC interrupts

The interrupt channel is set in the masked interrupt status register. The interrupt output is
also activated.

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Table 94. Interrupt requests

Exit from
Interrupt Exit from
Interrupt Event Enable Stop and
Interrupt event clear Sleep
acronym flag(1) control bit(2) Standby
method mode
mode

write 1 in
Alarm A ALRAF ALRAIE Yes Yes(3)
CALRAF
write 1 in
Alarm B ALRBF ALRBIE Yes Yes(3)
CALRBF
RTC
write 1 in
Timestamp TSF TSIE Yes Yes(3)
CTSF
Wakeup timer write 1 in
WUTF WUTIE Yes Yes(3)
interrupt CWUTF
1. The event flags are in the RTC_SR register.
2. The interrupt masked flags (resulting from event flags AND enable control bits) are in the RTC_MISR
register.
3. Wakeup from Stop and Standby modes is possible only when the RTC clock source is LSE or LSI.

23.6 RTC registers

Refer to Section 1.2 on page 39 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).

23.6.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 658 and
Reading the calendar on page 660.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x00
Backup domain reset value: 0x0000 0000
System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

23.6.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 658 and
Reading the calendar on page 660.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x04
Backup domain reset value: 0x0000 2101
System reset value: 0x0000 2101 (when BYPSHAD = 0, not affected when BYPSHAD = 1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. YT[3:0] YU[3:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format

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Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

Note: The calendar is frozen when reaching the maximum value, and can’t roll over.

23.6.3 RTC sub second register (RTC_SSR)

Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given
by the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.

23.6.4 RTC initialization control and status register (RTC_ICSR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: 0bxxxx xxxx xxxx xxxx xxxx xxxx 000x xxxx (not affected, except INIT,
INITF, and RSF bits which are cleared to 0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECAL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUTW ALRB ALRAW
Res. Res. Res. Res. Res. Res. Res. Res. INIT INITF RSF INITS SHPF
F WF F
rw r rc_w0 r r r r r

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Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration settings
are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 INIT: Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER). Counters are stopped and start counting from the new
value when INIT is reset.
Bit 6 INITF: Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed
Bit 5 RSF: Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in
initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow
register mode (BYPSHAD = 1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
Bit 4 INITS: Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (Backup domain
reset state).
0: Calendar has not been initialized
1: Calendar has been initialized
Bit 3 SHPF: Shift operation pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has
been executed. Writing to the SHPF bit has no effect.
0: No shift operation is pending
1: A shift operation is pending

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RM0454 Real-time clock (RTC)

Bit 2 WUTWF: Wakeup timer write flag

This bit is set by hardware when WUT value can be changed, after the WUTE bit has been
set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Wakeup timer configuration update not allowed except in initialization mode
1: Wakeup timer configuration update allowed
Bit 1 ALRBWF: Alarm B write flag
This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm B update not allowed
1: Alarm B update allowed
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed

23.6.5 RTC prescaler register (RTC_PRER)

This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to Calendar initialization and configuration on
page 658.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV_A[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PREDIV_S[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)

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23.6.6 RTC wakeup timer register (RTC_WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ICSR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every
(WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits
of the RTC_CR register.
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE
is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.

23.6.7 RTC control register (RTC_CR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x18
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP TAMP
OUT2 TAMP TAMP
ALRM_ ALRM_ Res. Res. ITSE COE OSEL[1:0] POL COSEL BKP SUB1H ADD1H
EN OE TS
TYPE PU
rw rw rw rw rw rw rw rw rw rw rw rw w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRB ALRA BYP REFCK TS
TSIE WUTIE TSE WUTE ALRBE ALRAE Res. FMT WUCKSEL[2:0]
IE IE SHAD ON EDGE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0454 Real-time clock (RTC)

Bit 31 OUT2EN: RTC_OUT2 output enable

Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows:
OUT2EN = 0: RTC output 2 disable
If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1
If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1
OUT2EN = 1: RTC output 2 enable
If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2
If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2
If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and
TAMPALRM is output on RTC_OUT1.
Bit 30 TAMPALRM_TYPE: TAMPALRM output type
0: TAMPALRM is push-pull output
1: TAMPALRM is open-drain output
Bit 29 TAMPALRM_PU: TAMPALRM pull-up enable
0: No pull-up is applied on TAMPALRM output
1: A pull-up is applied on TAMPALRM output
Bits 28:27 Reserved, must be kept at reset value.
Bit 26 TAMPOE: Tamper detection output enable on TAMPALRM
0: The tamper flag is not routed on TAMPALRM
1: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and
with the polarity provided by POL.
Bit 25 TAMPTS: Activate timestamp on tamper detection event
0: Tamper detection event does not cause a RTC timestamp to be saved
1: Save RTC timestamp on tamper detection event
TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the
tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the
tamper interrupts in order to avoid servicing 2 interrupts.
Bit 24 ITSE: timestamp on internal event enable
0: internal event timestamp disabled
1: internal event timestamp enabled
Bit 23 COE: Calibration output enable
This bit enables the CALIB output
0: Calibration output disabled
1: Calibration output enabled
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to TAMPALRM output.
00: Output disabled
01: Alarm A output enabled
10: Alarm B output enabled
11: Wakeup output enabled
Bit 20 POL: Output polarity
This bit is used to configure the polarity of TAMPALRM output.
0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or
when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).
1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or
when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).

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Bit 19 COSEL: Calibration output selection

When COE = 1, this bit selects which signal is output on CALIB.
0: Calibration output is 512 Hz
1: Calibration output is 1 Hz
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values
(PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 23.3.15: Calibration clock output.
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the
current hour is not 0. This bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change.
Bit 16 ADD1H: Add 1 hour (summer time change)
When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit
is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change
Bit 15 TSIE: Timestamp interrupt enable
0: Timestamp interrupt disable
1: Timestamp interrupt enable
Bit 14 WUTIE: Wakeup timer interrupt enable
0: Wakeup timer interrupt disabled
1: Wakeup timer interrupt enabled
Bit 13 ALRBIE: Alarm B interrupt enable
0: Alarm B interrupt disable
1: Alarm B interrupt enable
Bit 12 ALRAIE: Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
Bit 11 TSE: timestamp enable
0: timestamp disable
1: timestamp enable
Bit 10 WUTE: Wakeup timer enable
0: Wakeup timer disabled
1: Wakeup timer enabled
Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
Bit 9 ALRBE: Alarm B enable
0: Alarm B disabled
1: Alarm B enabled
Bit 8 ALRAE: Alarm A enable
0: Alarm A disabled
1: Alarm A enabled
Bit 7 Reserved, must be kept at reset value.

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RM0454 Real-time clock (RTC)

Bit 6 FMT: Hour format

0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to 1.
Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
0: RTC_TS input rising edge generates a timestamp event
1: RTC_TS input falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Bits 2:0 WUCKSEL[2:0]: ck_wut wakeup clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value

Note: Bits 6 and 4 of this register can be written in initialization mode only (RTC_ICSR/INITF = 1).
WUT = wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.

23.6.8 RTC write protection register (RTC_WPR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]
w w w w w w w w

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Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write
protection.

23.6.9 RTC calibration register (RTC_CALR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x28
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALW
CALP CALW8 Res. Res. Res. Res. CALM[8:0]
16
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of
RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) -
CALM.
Refer to Section 23.3.13: RTC smooth digital calibration.
Bit 14 CALW8: Use an 8-second calibration cycle period
When CALW8 is set to 1, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 23.3.13: RTC smooth
digital calibration.

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RM0454 Real-time clock (RTC)

Bit 13 CALW16: Use a 16-second calibration cycle period

When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must
not be set to 1 if CALW8 = 1.
Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 23.3.13: RTC smooth digital
calibration.
Bits 12:9 Reserved, must be kept at reset value.
Bits 8:0 CALM[8:0]: Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See Section 23.3.13: RTC smooth digital calibration on page 662.

23.6.10 RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SUBFS[14:0]
w w w w w w w w w w w w w w w

Bit 31 ADD1S: Add one second

0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF = 1, in RTC_ICSR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF = 1, in RTC_ICSR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be
sure that the shadow registers have been updated with the shifted time.

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23.6.11 RTC timestamp time register (RTC_TSTR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
TSF bit is reset.
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]
r r r r r r r r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

23.6.12 RTC timestamp date register (RTC_TSDR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
TSF bit is reset.
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]
r r r r r r r r r r r r r r

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RM0454 Real-time clock (RTC)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[2:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

23.6.13 RTC timestamp sub second register (RTC_TSSSR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
the TSF bit is reset.
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.

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23.6.14 RTC alarm A register (RTC_ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x40
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDSE
MSK4 DT[1:0] DU[3:0] MSK3 PM HT[1:0] HU[3:0]
L
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2 MNT[2:0] MNU[3:0] MSK1 ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 MSK4: Alarm A date mask

0: Alarm A set if the date/day match
1: Date/day don’t care in alarm A comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format
Bits 27:24 DU[3:0]: Date units or day in BCD format
Bit 23 MSK3: Alarm A hours mask
0: Alarm A set if the hours match
1: Hours don’t care in alarm A comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 MSK2: Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in alarm A comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 MSK1: Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in alarm A comparison
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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RM0454 Real-time clock (RTC)

23.6.15 RTC alarm A sub second register (RTC_ALRMASSR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x44
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SS[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don’t care in alarm A comparison. Only SS[2:0] are compared.
...
12:SS[14:12] are don’t care in alarm A comparison. SS[11:0] are compared.
13:SS[14:13] are don’t care in alarm A comparison. SS[12:0] are compared.
14:SS[14] is don’t care in alarm A comparison. SS[13:0] are compared.
15:All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can
be different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine
if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.

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23.6.16 RTC alarm B register (RTC_ALRMBR)

This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 658.
Address offset: 0x48
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WD
MSK4 DT[1:0] DU[3:0] MSK3 PM HT[1:0] HU[3:0]
SEL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2 MNT[2:0] MNU[3:0] MSK1 ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 MSK4: Alarm B date mask

0: Alarm B set if the date and day match
1: Date and day don’t care in alarm B comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format
Bits 27:24 DU[3:0]: Date units or day in BCD format
Bit 23 MSK3: Alarm B hours mask
0: Alarm B set if the hours match
1: Hours don’t care in alarm B comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 MSK2: Alarm B minutes mask
0: Alarm B set if the minutes match
1: Minutes don’t care in alarm B comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 MSK1: Alarm B seconds mask
0: Alarm B set if the seconds match
1: Seconds don’t care in alarm B comparison
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

682/989 RM0454 Rev 5

RM0454 Real-time clock (RTC)

23.6.17 RTC alarm B sub second register (RTC_ALRMBSSR)

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization
mode.
This register is write protected.The write access procedure is described in Section : RTC
register write protection.
Address offset: 0x4C
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SS[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0x0: No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don’t care in alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don’t care in alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don’t care in alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don’t care in alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don’t care in alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don’t care in alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine
if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.

23.6.18 RTC status register (RTC_SR)

Address offset: 0x50
Backup domain reset value: 0x0000 0000
System reset: not affected

RM0454 Rev 5 683/989

703
Real-time clock (RTC) RM0454

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ITSF TSOVF TSF WUTF ALRBF ALRAF
r r r r r r

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ITSF: Internal timestamp flag
This flag is set by hardware when a timestamp on the internal event occurs.
Bit 4 TSOVF: Timestamp overflow flag
This flag is set by hardware when a timestamp event occurs while TSF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Bit 3 TSF: Timestamp flag
This flag is set by hardware when a timestamp event occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
Bit 2 WUTF: Wakeup timer flag
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 1 ALRBF: Alarm B flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm B register (RTC_ALRMBR).
Bit 0 ALRAF: Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm A register (RTC_ALRMAR).

Note: The bits of this register are cleared 2 APB clock cycles after setting their corresponding
clear bit in the RTC_SCR register.

23.6.19 RTC masked interrupt status register (RTC_MISR)

Address offset: 0x54
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITS TSOV TS WUT ALRB ALRA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MF MF MF MF MF MF
r r r r r r

684/989 RM0454 Rev 5

RM0454 Real-time clock (RTC)

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ITSMF: Internal timestamp masked flag
This flag is set by hardware when a timestamp on the internal event occurs and
timestampinterrupt is raised.
Bit 4 TSOVMF: Timestamp overflow masked flag
This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Bit 3 TSMF: Timestamp masked flag
This flag is set by hardware when a timestamp interrupt occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
Bit 2 WUTMF: Wakeup timer masked flag
This flag is set by hardware when the wakeup timer interrupt occurs.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 1 ALRBMF: Alarm B masked flag
This flag is set by hardware when the alarm B interrupt occurs.
Bit 0 ALRAMF: Alarm A masked flag
This flag is set by hardware when the alarm A interrupt occurs.

23.6.20 RTC status clear register (RTC_SCR)

Address offset: 0x5C
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITS CTSOV CTS CWUT CALRB CALRA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
F F F F F F
w w w w w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CITSF: Clear internal timestamp flag
Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
Bit 4 CTSOVF: Clear timestamp overflow flag
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Bit 3 CTSF: Clear timestamp flag
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.

RM0454 Rev 5 685/989

703
Real-time clock (RTC) RM0454

Bit 2 CWUTF: Clear wakeup timer flag

Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
Bit 1 CALRBF: Clear alarm B flag
Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
Bit 0 CALRAF: Clear alarm A flag
Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.

686/989 RM0454 Rev 5

 0x38
0x34
0x30
0x28
0x24
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C
Offset
RM0454

23.6.21

RTC_TR

RTC_CR
RTC_DR

RTC_SSR

RTC_WPR
RTC_ICSR
Register

RTC_TSTR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RTC_TSDR
RTC_PRER

RTC_WUTR

RTC_ CALR

RTC_TSSSR
RTC_SHIFTR

0
0
Res. Res. Res. ADD1S Res. Res. OUT2EN Res. Res. Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. TAMPALRM_TYPE Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. TAMPALRM_PU Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. TAMPOE Res. Res. Res. Res. Res. Res.
RTC register map

26

0
Res. Res. Res. Res. Res. Res. TAMPTS Res. Res. Res. Res. Res. Res. 25

0
Res. Res. Res. Res. Res. Res. ITSE Res. Res. Res. Res. Res. Res. 24

0
0

Res. Res. Res. Res. Res. Res. COE Res. Res. Res. Res. Res. 23

0
0
1
0
0

Res. Res. PM Res. Res. Res. Res. Res. Res. PM 22

O
SEL
[1:0]

0
0
1
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 21

YT[3:0]

HT[1:0]
HT
[1:0]

0
0
1
0
0

Res. Res. Res. Res. Res. POL Res. Res. Res. 20

0
0
1
0
0

Res. Res. Res. Res. Res. COSEL Res. Res. Res. 19

0
0
1
0
0

Res. Res. Res. Res. Res. BKP Res. Res. Res. 18

PREDIV_A[6:0]

0
0
1
0
0

Res. Res. Res. Res. Res. SUB1H Res. Res. Res.

RM0454 Rev 5
17
YU[3:0]

HU[3:0]
HU[3:0]

0
0
1
0
0
0

Res. Res. Res. Res. Res. ADD1H Res. RECALPF Res. 16

0
0
0
1
0
0
0

Res. Res. CALP Res. TSIE Res. Res. 15

0
0
0

0
0
0
0
1
0
0

CALW8 Res. WUTIE Res. 14

0
0
0
0
0
1
0
0
1
0

WDU[1:0]
WDU[2:0]

MNT[2:0] CALW16 Res. ALRBIE Res. 13

0
0
0
0
1
0
0
0
0
MNT[2:0]

MT Res. Res. ALRAIE Res. MT 12

0
0
0
0
1
0
0
0
0

Res. Res. TSE Res. 11

Table 95. RTC register map and reset values

0
0
0
0
1
0
0
0
0

Res. Res. WUTE Res. 10

0
0
0
0
1
0
0
0
0

Res. Res. ALRBE Res. 9

MU[3:0]
MU[3:0]

MNU[3:0]
MNU[3:0]

0
0

0
1

0
0
0

0
1
0
0

Res. ALRAE Res. 8

0
0
0
1
1

0
0
0

Res. Res. Res. INIT Res. Res. 7

SS[15:0]
SS[15:0]

WUT[15:0]

0
0
0
0

0
1
1

0
0
0

Res. FMT INITF Res. 6

PREDIV_S[14:0]

SUBFS[14:0]
0

0
0
0
0
1
1
0
0

0
0
0
0

BYPSHAD RSF 5

DT
DT

ST[2:0]
ST[2:0]

[1:0]
[1:0]

0
0
0
0
1
1
0
0

0
0
0
0

REFCKON INITS 4
0

0
0
0
0
1
1
0
0

0
0
0
0

TSEDGE SHPF

CALM[8:0]
3
KEY[7:0]

0
0
0
0

0
1
1
0
0

0
0
1
0

WUT WF 2

0
0
0
0

0
1
1
0
0

0
0
1
0

ALRBWF 1

SU[3:0]
SU[3:0]

DU[3:0]
DU[3:0]

WUCK
SEL[2:0]

0
1
1
1

0
0
0
0

0
0
1
0

ALRAWF 0
Real-time clock (RTC)

687/989
703
Real-time clock (RTC) RM0454

Table 95. RTC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
WDSEL
MSK4

MSK3

MSK2

MSK1
DT HT

PM
RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]
0x40 [1:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_ MASKSS
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SS[14:0]
0x44 ALRMASSR [3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDSEL
MSK4

MSK3

MSK2

MSK1
DT HT

PM
RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]
0x48 [1:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_ MASKSS
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SS[14:0]
0x4C ALRMBSSR [3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSOVF

ALRBF
ALRAF
WUTF
ITSF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TSF
RTC_SR
0x50

Reset value 0 0 0 0 0 0

TSOVMF

ALRBMF
ALRAMF
WUTMF
ITSMF

TSMF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RTC_MISR
0x54

Reset value 0 0 0 0 0 0

CTSOVF

CALRBF
CALRAF
CWUTF
CITSF

CTSF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RTC_SCR
0x5C

Reset value 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

688/989 RM0454 Rev 5

RM0454 Tamper and backup registers (TAMP)

24 Tamper and backup registers (TAMP)

24.1 Introduction
5 32-bit backup registers are retained in all low-power modes and also in VBAT mode. They
can be used to store sensitive data as their content is protected by an tamper detection
circuit. Up to 3 tamper pins and 4 internal tampers are available for anti-tamper detection.
The external tamper pins can be configured for edge detection, or level detection with or
without filtering.

24.2 TAMP main features

• 5 backup registers:
– the backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to 3 external tamper detection events.
– External passive tampers with configurable filter and internal pull-up.
• 4 internal tamper events.
• Any tamper detection can generate a RTC timestamp event.
• Any tamper detection can erase the backup registers.

RM0454 Rev 5 689/989

703
Tamper and backup registers (TAMP) RM0454

24.3 TAMP functional description

24.3.1 TAMP block diagram

Figure 229. TAMP block diagram

tamp_ker_ck clock domain

TAMP1F
Tamper detection
TAMP_IN1
EDGE detection

tamp_trg1
LEVEL detection

TAMP2F
Tamper detection
TAMP_IN2
EDGE detection

tamp_trg2
LEVEL detection

...
...

TAMP1F when TAMP1NOER=0

TAMPxF when TAMPxNOER=0

TAMPxF(1)
Tamper detection
TAMP_INx
EDGE detection

LEVEL detection
ITAMP1F

ITAMP1F
ITAMPyF

ITAMPyF
TAMP1F

TAMPxF

... ... ... ...

tamp_ker_ck

tamp_evt

tamp_erase

tamp_it
IRQ interface
Backup registers
Registers interface
tamp_pclk
tamp_pclk clock domain

MSv43847V4

1. The number of external and internal tampers depends on products.

690/989 RM0454 Rev 5

RM0454 Tamper and backup registers (TAMP)

24.3.2 TAMP pins and internal signals

Table 96. TAMP input/output pins

Pin name Signal type Description

TAMP_INx (x = pin index) Input Tamper input pin

Table 97. TAMP internal input/output signals

Internal signal name Signal type Description

TAMP kernel clock, connected to rtc_ker_ck

tamp_ker_ck Input
and also named RTCCLK in this document
tamp_pclk Input TAMP APB clock, connected to rtc_pclk
tamp_itamp[y]
Inputs Internal tamper event sources
(y = signal index)
Tamper event detection (internal or external)
tamp_evt Output The tamp_evt is used to generate a RTC
timestamp event
Device secrets erase request following tamper
tamp_erase Output
event detection (internal or external)
TAMP interrupt (refer to Section 24.5: TAMP
tamp_it Output
interrupts for details)
tamp_trg[x]
Output Tamper detection trigger
(x = signal index)

The TAMP kernel clock is usually the LSE at 32.768 kHz although it is possible to select
other clock sources in the RCC (refer to RCC for more details). Some detections modes are
not available in some low-power modes or VBAT when the selected clock is not LSE (refer to
Section 24.4: TAMP low-power modes for more details.

Table 98. TAMP interconnection

Signal name Source/Destination

tamp_evt rtc_tamp_evt used to generate a timestamp event

The tamp_erase signal is used to erase the device secrets listed
tamp_erase
hereafter: backup registers
tamp_itamp3 LSE monitoring
tamp_itamp4 HSE monitoring
tamp_itamp5 RTC calendar overflow (rtc_calovf)
tamp_itamp6 ST manufacturer readout

24.3.3 TAMP register write protection

After system reset, the TAMP registers (including backup registers) are protected against
parasitic write access by the DBP bit in the power control peripheral (refer to the PWR
power control section). DBP bit must be set in order to enable TAMP registers write access.

RM0454 Rev 5 691/989

703
Tamper and backup registers (TAMP) RM0454

24.3.4 Tamper detection

The tamper detection can be configured for the following purposes:
• erase the backup registers (default configuration)
• generate an interrupt, capable to wakeup from Stop and Standby mode
• generate a hardware trigger for the low-power timers

TAMP backup registers

The backup registers (TAMP_BKPxR) are not reset by system reset or when the device
wakes up from Standby mode.
The backup registers are reset when a tamper detection event occurs except if the
TAMPxNOER bit is set, or if the TAMPxMSK is set in the TAMP_CR2 register.
Note: The backup registers are also erased when the readout protection of the flash is changed
from level 1 to level 0.

Tamper detection initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the TAMP_CR
register.
Each TAMP_INx tamper detection input is associated with a flag TAMPxF in the TAMP_SR
register.
When TAMPxMSK is cleared:
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided
below:
• 3 ck_apre cycles when TAMPFLT differs from 0x0 (level detection with filtering)
• 3 ck_apre cycles when TAMPTS = 1 (timestamp on tamper event)
• No latency when TAMPFLT = 0x0 (edge detection) and TAMPTS = 0
A new tamper occurring on the same pin during this period and as long as TAMPxF is set
cannot be detected.
When TAMPxMSK is set:
A new tamper occurring on the same pin cannot be detected during the latency described
above and 2.5 ck_rtc additional cycles.
By setting the TAMPxIE bit in the TAMP_IER register, an interrupt is generated when a
tamper detection event occurs (when TAMPxF is set). Setting TAMPxIE is not allowed when
the corresponding TAMPxMSK is set.

Trigger output generation on tamper event

The tamper event detection can be used as trigger input by the low-power timers.
When TAMPxMSK bit in cleared in TAMP_CR register, the TAMPxF flag must be cleared by
software in order to allow a new tamper detection on the same pin.
When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR
register. This configuration allows to trig automatically the low-power timers in Stop mode,
without requiring the system wakeup to perform the TAMPxF clearing. In this case, the
backup registers are not cleared.

692/989 RM0454 Rev 5

RM0454 Tamper and backup registers (TAMP)

This feature is available only when the tamper is configured in the Level detection with
filtering on tamper inputs (passive mode) mode (TAMPFLT ≠ 00 and active mode is not
selected).

Timestamp on tamper event

With TAMPTS set to 1 in the RTC_CR, any tamper event causes a timestamp to occur. In
this case, either the TSF bit or the TSOVF bit is set in RTC_SR, in the same manner as if a
normal timestamp event occurs. The affected tamper flag register TAMPxF is set in the
TAMP_SR at the same time that TSF or TSOVF is set in the RTC_SR.

Edge detection on tamper inputs (passive mode)

If the TAMPFLT bits are 00, the TAMP_INx pins generate tamper detection events when
either a rising edge/high level or a falling edge/low level is observed depending on the
corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMP_INx inputs are
deactivated when edge detection is selected.
Caution: When using the edge detection, it is recommended to check by software the tamper pin
level just after enabling the tamper detection (by reading the GPIO registers), and before
writing sensitive values in the backup registers, to ensure that an active edge did not occur
before enabling the tamper event detection.
When TAMPFLT = 00 and TAMPxTRG = 0 (rising edge detection), a tamper event may be
detected by hardware if the tamper input is already at high level before enabling the tamper
detection.
After a tamper event has been detected and cleared, the TAMP_INx should be disabled and
then re-enabled (TAMPxE set to 1) before re-programming the backup registers
(TAMP_BKPxR). This prevents the application from writing to the backup registers while the
TAMP_INx input value still indicates a tamper detection. This is equivalent to a level
detection on the TAMP_INx input.
Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting
of the backup registers, the pin to which the TAMPx is mapped should be externally tied to
the correct level.

Level detection with filtering on tamper inputs (passive mode)

Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits.
The TAMP_INx inputs are precharged through the I/O internal pull-up resistance before its
state is sampled, unless disabled by setting TAMPPUDIS to 1. The duration of the
precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the
TAMP_INx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note: Refer to the datasheet for the electrical characteristics of the pull-up resistors.

RM0454 Rev 5 693/989

703
Tamper and backup registers (TAMP) RM0454

24.4 TAMP low-power modes

Table 99. Effect of low-power modes on TAMP
Mode Description

No effect.
Sleep
TAMP interrupts cause the device to exit the Sleep mode.
No effect on all features, except for level detection with filtering mode which remain
Stop active only when the clock source is LSE or LSI.
Tamper events cause the device to exit the Stop mode.
No effect on all features, except for level detection with filtering mode which remain
Standby active only when the clock source is LSE or LSI.Tamper events cause the device to exit
the Standby mode.

24.5 TAMP interrupts

The interrupt channel is set in the interrupt status register. The interrupt output is also
activated.

Table 100. Interrupt requests

Exit from
Interrupt Exit from
Interrupt Interrupt Enable Stop and
Event flag(1) clear Sleep
acronym event control bit(2) Standby
method mode
modes

Write 1 in
Tamper x(3) TAMPxF TAMPxIE Yes Yes(4)
CTAMPxF
TAMP
Internal Write 1 in
ITAMPyF ITAMPyIE Yes Yes(4)
tamper y(3) CITAMPxF
1. The event flags are in the TAMP_SR register.
2. The interrupt masked flags (resulting from event flags AND enable control bits) are in the TAMP_MISR
register.
3. The number of tampers and internal tampers events depend on products.
4. In case of level detection with filtering passive tamper mode, wakeup from Stop and Standby modes is
possible only when the TAMP clock source is LSE or LSI.

24.6 TAMP registers

Refer to Section 1.2 on page 39 of the reference manual for a list of abbreviations used in
register descriptions. The peripheral registers can be accessed by words (32-bit).

694/989 RM0454 Rev 5

RM0454 Tamper and backup registers (TAMP)

24.6.1 TAMP control register 1 (TAMP_CR1)

Address offset: 0x00
Backup domain reset value: 0xFFFF 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP6 ITAMP5 ITAMP4 ITAMP3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
E E E E

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3 TAMP2 TAMP1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
E E E

rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 ITAMP6E: Internal tamper 6 enable: ST manufacturer readout
0: Internal tamper 6 disabled.
1: Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout.
Bit 20 ITAMP5E: Internal tamper 5 enable: RTC calendar overflow
0: Internal tamper 5 disabled.
1: Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its
maximum value, on the 31st of December 99, at 23:59:59. The calendar is then frozen and
cannot overflow.
Bit 19 ITAMP4E: Internal tamper 4 enable: HSE monitoring
0: Internal tamper 4 disabled.
1: Internal tamper 4 enabled. a tamper is generated when the HSE frequency is below or
above thresholds.
Bit 18 ITAMP3E: Internal tamper 3 enable: LSE monitoring
0: Internal tamper 3 disabled.
1: Internal tamper 3 enabled: a tamper is generated when the LSE frequency is below or
above thresholds.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.

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Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable

0: Tamper detection on TAMP_IN3 is disabled.
1: Tamper detection on TAMP_IN3 is enabled.
Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable
0: Tamper detection on TAMP_IN2 is disabled.
1: Tamper detection on TAMP_IN2 is enabled.
Bit 0 TAMP1E: Tamper detection on TAMP_IN1 enable
0: Tamper detection on TAMP_IN1 is disabled.
1: Tamper detection on TAMP_IN1 is enabled.

24.6.2 TAMP control register 2 (TAMP_CR2)

Address offset: 0x04
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3 TAMP2 TAMP1 TAMP3 TAMP2 TAMP1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TRG TRG TRG MSK MSK MSK

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3 TAMP2 TAMP1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NOER NOER NOER

rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 TAMP3TRG: Active level for tamper 3 input (active mode disabled)
0: If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection
event.
Bit 25 TAMP2TRG: Active level for tamper 2 input (active mode disabled)
0: If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection
event.
Bit 24 TAMP1TRG: Active level for tamper 1 input (active mode disabled)
0: If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection
event.
Bit 23 Reserved, must be kept at reset value.

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RM0454 Tamper and backup registers (TAMP)

Bits 22:19 Reserved, must be kept at reset value.

Bit 18 TAMP3MSK: Tamper 3 mask
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers are not erased.
The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
Bit 17 TAMP2MSK: Tamper 2 mask
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to
allow next tamper event detection.
1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by
hardware. The backup registers are not erased.
The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
Bit 16 TAMP1MSK: Tamper 1 mask
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to
allow next tamper event detection.
1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by
hardware. The backup registers are not erased.
The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3NOER: Tamper 3 no erase
0: Tamper 3 event erases the backup registers.
1: Tamper 3 event does not erase the backup registers.
Bit 1 TAMP2NOER: Tamper 2 no erase
0: Tamper 2 event erases the backup registers.
1: Tamper 2 event does not erase the backup registers.
Bit 0 TAMP1NOER: Tamper 1 no erase
0: Tamper 1 event erases the backup registers.
1: Tamper 1 event does not erase the backup registers.

24.6.3 TAMP filter control register (TAMP_FLTCR)

Address offset: 0x0C
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP TAMPPRCH TAMPFLT TAMPFREQ
Res. Res. Res. Res. Res. Res. Res. Res.
PUDIS [1:0] [1:0] [2:0]
rw rw rw rw rw rw rw rw

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Bits 31:8 Reserved, must be kept at reset value.

Bit 7 TAMPPUDIS: TAMP_INx pull-up disable
This bit determines if each of the TAMPx pins are precharged before each sample.
0: Precharge TAMP_INx pins before sampling (enable internal pull-up)
1: Disable precharge of TAMP_INx pins.
Bits 6:5 TAMPPRCH[1:0]: TAMP_INx precharge duration
These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the TAMP_INx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
Bits 4:3 TAMPFLT[1:0]: TAMP_INx filter count
These bits determines the number of consecutive samples at the specified level
(TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the
TAMP_INx inputs.
0x0: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no
internal pull-up on TAMP_INx input).
0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: Tamper event is activated after 8 consecutive samples at the active level.
Bits 2:0 TAMPFREQ[2:0]: Tamper sampling frequency
Determines the frequency at which each of the TAMP_INx inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

Note: This register concerns only the tamper inputs in passive mode.

24.6.4 TAMP interrupt enable register (TAMP_IER)

Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP6 ITAMP5 ITAMP4 ITAMP3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
IE IE IE IE

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP TAMP TAMP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
3IE 2IE 1IE

rw rw rw

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RM0454 Tamper and backup registers (TAMP)

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable: ST manufacturer readout
0: Internal tamper 6 interrupt disabled.
1: Internal tamper 6 interrupt enabled.
Bit 20 ITAMP5IE: Internal tamper 5 interrupt enable: RTC calendar overflow
0: Internal tamper 5 interrupt disabled.
1: Internal tamper 5 interrupt enabled.
Bit 19 ITAMP4IE: Internal tamper 4 interrupt enable: HSE monitoring
0: Internal tamper 4 interrupt disabled.
1: Internal tamper 4 interrupt enabled.
Bit 18 ITAMP3IE: Internal tamper 3 interrupt enable: LSE monitoring
0: Internal tamper 3 interrupt disabled.
1: Internal tamper 3 interrupt enabled.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3IE: Tamper 3 interrupt enable
0: Tamper 3 interrupt disabled.
1: Tamper 3 interrupt enabled..
Bit 1 TAMP2IE: Tamper 2 interrupt enable
0: Tamper 2 interrupt disabled.
1: Tamper 2 interrupt enabled.
Bit 0 TAMP1IE: Tamper 1 interrupt enable
0: Tamper 1 interrupt disabled.
1: Tamper 1 interrupt enabled.

24.6.5 TAMP status register (TAMP_SR)

Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP6 ITAMP5 ITAMP4 ITAMP3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
F F F F

r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP TAMP TAMP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
3F 2F 1F

r r r

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Tamper and backup registers (TAMP) RM0454

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 ITAMP6F: ST manufacturer readout tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 6.
Bit 20 ITAMP5F: RTC calendar overflow tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 5.
Bit 19 ITAMP4F: HSE monitoring tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 4.
Bit 18 ITAMP3F: LSE monitoring tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 3.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3F: TAMP3 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.
Bit 1 TAMP2F: TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.
Bit 0 TAMP1F: TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.

24.6.6 TAMP masked interrupt status register (TAMP_MISR)

Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP6 ITAMP5 ITAMP4 ITAMP3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MF MF MF MF

r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP TAMP TAMP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
3MF 2MF 1MF

r r r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.

700/989 RM0454 Rev 5

RM0454 Tamper and backup registers (TAMP)

Bit 21 ITAMP6MF: ST manufacturer readout tamper interrupt masked flag

This flag is set by hardware when the internal tamper 6 interrupt is raised.
Bit 20 ITAMP5MF: RTC calendar overflow tamper interrupt masked flag
This flag is set by hardware when the internal tamper 5 interrupt is raised.
Bit 19 ITAMP4MF: HSE monitoring tamper interrupt masked flag
This flag is set by hardware when the internal tamper 4 interrupt is raised.
Bit 18 ITAMP3MF: LSE monitoring tamper interrupt masked flag
This flag is set by hardware when the internal tamper 3 interrupt is raised.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3MF: TAMP3 interrupt masked flag
This flag is set by hardware when the tamper 3 interrupt is raised.
Bit 1 TAMP2MF: TAMP2 interrupt masked flag
This flag is set by hardware when the tamper 2 interrupt is raised.
Bit 0 TAMP1MF: TAMP1 interrupt masked flag
This flag is set by hardware when the tamper 1 interrupt is raised.

24.6.7 TAMP status clear register (TAMP_SCR)

Address offset: 0x3C
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C C C C
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ITAMP ITAMP ITAMP ITAMP Res. Res.
6F 5F 4F 3F

w w w w

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP CTAMP CTAMP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
3F 2F 1F
w w w

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 CITAMP6F: Clear ITAMP6 detection flag
Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
Bit 20 CITAMP5F: Clear ITAMP5 detection flag
Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
Bit 19 CITAMP4F: Clear ITAMP4 detection flag
Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.
Bit 18 CITAMP3F: Clear ITAMP3 detection flag
Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.

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Tamper and backup registers (TAMP) RM0454

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 CTAMP3F: Clear TAMP3 detection flag
Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
Bit 1 CTAMP2F: Clear TAMP2 detection flag
Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
Bit 0 CTAMP1F: Clear TAMP1 detection flag
Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.

24.6.8 TAMP backup x register (TAMP_BKPxR)

Address offset: 0x100 + 0x04 * x, (x = 0 to 4)
Backup domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:0 BKP[31:0]

The application can write or read data to and from these registers.
They are powered-on by VBAT when VDD is switched off, so that they are not reset by System
reset, and their contents remain valid when the device operates in low-power mode.
In the default configuration this register is reset on a tamper detection event. It is forced to
reset value as long as there is at least one internal or external tamper flag being set. This
register is also reset when the readout protection (RDP) is disabled.

702/989 RM0454 Rev 5

 (x =
0x34
0x30
0x04
0x00

0x3C
0x2C
0x0C

0 to 4)
0x04*x,
0x100 +
Offset
24.6.9
RM0454

TAMP_SR
TAMP_IER
Register

Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TAMP_CR2
TAMP_CR1

TAMP_SCR
TAMP_MISR
TAMP_FLTCR

TAMP_BKPxR

0
Res. Res. Res. Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. 29

0
Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. TAMP3TRG Res. 26
TAMP register map

0
0
Res. Res. Res. Res. Res. TAMP2TRG Res. 25

0
0
Res. Res. Res. Res. Res. TAMP1TRG Res. 24

0
Res. Res. Res. Res. Res. Res. Res. 23

0
Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
1

CITAMP6F ITAMP6MF ITAMP6F ITAMP6IE Res. Res. ITAMP6E 21

0
0
0
0
0
1

CITAMP5F ITAMP5MF ITAMP5F ITAMP5IE Res. Res. ITAMP5E 20

0
0
0
0
0
1

CITAMP4F ITAMP4MF ITAMP4F ITAMP4IE Res. Res. ITAMP4E 19

0
0
0
0
0
0
1

CITAMP3F ITAMP3MF ITAMP3F ITAMP3IE Res. TAMP3MSK ITAMP3E 18

0
0

Res.

RM0454 Rev 5
Res. Res. Res. Res. TAMP2MSK Res. 17

0
0

Res. Res. Res. Res. Res. TAMP1MSK Res. 16

0
Res. Res. Res. Res. Res. Res. Res. 15

BKP[31:0]

0
Res. Res. Res. Res. Res. Res. Res. 14

0
Res. Res. Res. Res. Res. Res. Res. 13

0
Res. Res. Res. Res. Res. Res. Res. 12

0
Res. Res. Res. Res. Res. Res. Res. 11
Table 101. TAMP register map and reset values

0
Res. Res. Res. Res. Res. Res. Res. 10

0
Res. Res. Res. Res. Res. Res. Res. 9

Refer to Section 2.2 on page 44 for the register boundary addresses.

0
Res. Res. Res. Res. Res. Res. Res. 8

0
0

Res. Res. Res. Res. TAMPPUDIS Res. Res. 7

0
0

Res. Res. Res. Res. Res. Res. 6

.TAMPPRCH[1:0]

0
0

Res. Res. Res. Res. Res. Res. 5

0
0

Res. Res. Res. Res. Res. Res. 4

.TAMPFLT[1:0]

0
0

Res. Res. Res. Res. Res. Res. 3

0
0
0
0
0
0
0
0

CTAMP3F TAMP3MF TAMP3F TAMP3IE TAMP3NOER TAMP3E 2

0
0
0
0
0
0
0
0

CTAMP2F TAMP2MF TAMP2F TAMP2IE TAMPFREQ[2:0] TAMP2NOER TAMP2E 1

0
0
0
0
0
0
0
0

CTAMP1F TAMP1MF TAMP1F TAMP1IE TAMP1NOER TAMP1E 0

703/989
Tamper and backup registers (TAMP)

703
Inter-integrated circuit (I2C) interface RM0454

25 Inter-integrated circuit (I2C) interface

25.1 Introduction
The I2C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C
bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm),
Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus (power management bus)
compatible.
DMA can be used to reduce CPU overload.

25.2 I2C main features

• I2C bus specification rev03 compatibility:
– Slave and master modes
– Multimaster capability
– Standard-mode (up to 100 kHz)
– Fast-mode (up to 400 kHz)
– Fast-mode Plus (up to 1 MHz)
– 7-bit and 10-bit addressing mode
– Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
– All 7-bit addresses acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• 1-byte buffer with DMA capability
• Programmable analog and digital noise filters

704/989 RM0454 Rev 5

RM0454 Inter-integrated circuit (I2C) interface

The following additional features are also available depending on the product
implementation (see Section 25.3: I2C implementation):
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and Device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop mode on address match.

25.3 I2C implementation

The devices incorporate up to three I²C-bus controllers, I2C1, I2C2, and I2C3, with full or
limited feature sets as shown in the following table.

Table 102. STM32G0x0 I2C implementation

I2C features(1) I2C1 I2C2 I2C3(2)

7-bit addressing mode X X X

10-bit addressing mode X X X
Standard mode (up to 100 kbit/s) X X X
Fast mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up
X X X
to 1 Mbit/s)
Independent clock X X(2) / - -
(2)
Wakeup from Stop mode X X /- -
SMBus/PMbus X X(2) /- -
1. X = supported.
2. STM32G0B0xx devices only.

25.4 I2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I2C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).

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Inter-integrated circuit (I2C) interface RM0454

If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.

25.4.1 I2C1 block diagram

The block diagram of the I2C1 interface is shown in Figure 230.

Figure 230. I2C1 block diagram

I2CCLK
I2c_ker_ck

Data control
Digital Analog
Shift register noise noise GPIO
filter I2C_SDA
filter logic
SMBUS
PEC
generation/
check
Wakeup
on
address
match Clock control
Master clock
generation Digital Analog
noise noise
Slave clock GPIO I2C_SCL
filter filter
stretching logic

SMBus
Timeout
check

SMBus Alert
control & I2C_SMBA
status

PCLK
I2c_pclk Registers

APB bus

MSv46198V2

The I2C1 is clocked by an independent clock source which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 25.3: I2C implementation.

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RM0454 Inter-integrated circuit (I2C) interface

25.4.2 I2C2 block diagram

The block diagram of the I2C2 interface is shown in Figure 231.

Figure 231. I2C2 block diagram

I2CCLK
PCLK

Data control
Digital Analog
Shift register noise noise GPIO
filter I2C1_SDA
filter logic
SMBUS
PEC
generation/
check
Wakeup
on
address
match Clock control
Master clock
generation Digital Analog
noise noise
Slave clock GPIO I2C1_SCL
filter filter
stretching logic

SMBus
Timeout
check

SMBus Alert
control & I2C1_SMBA
status

Registers

APB bus

MSv46199V2

For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 25.3: I2C implementation.

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25.4.3 I2C pins and internal signals

Table 103. I2C input/output pins
Pin name Signal type Description

I2C_SDA Bidirectional I2C data

I2C_SCL Bidirectional I2C clock
I2C_SMBA Bidirectional SMBus Alert

Table 104. I2C internal input/output signals

Internal signal name Signal type Description

I2C kernel clock, also named I2CCLK in this

i2c_ker_ck Input
document
i2c_pclk Input I2C APB clock
I2C interrupts, refer to Table 118: I2C Interrupt
i2c_it Output
requests for the full list of interrupt sources
i2c_rx_dma Output I2C Receive Data DMA request (I2C_RX)
i2c_tx_dma Output I2C Transmit Data DMA request (I2C_TX)

25.4.4 I2C clock requirements

The I2C kernel is clocked by I2CCLK.
The I2CCLK period tI2CCLK must respect the following conditions:
tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH
with:
tLOW: SCL low time and tHIGH: SCL high time
tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK.
The PCLK clock period tPCLK must respect the following condition:
tPCLK < 4/3 tSCL
with tSCL: SCL period
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for tI2CCLK.

25.4.5 Mode selection

The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver

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By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.

Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection can be enabled or disabled
by software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.

Figure 232. I2C bus protocol

SDA
MSB ACK

SCL
1 2 8 9

Start Stop
condition condition

MS19854V1

Acknowledge can be enabled or disabled by software. The I2C interface addresses can be
selected by software.

25.4.6 I2C initialization

Enabling and disabling the peripheral
The I2C peripheral clock must be configured and enabled in the clock controller.
Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register.
When the I2C is disabled (PE=0), the I2C performs a software reset. Refer to
Section 25.4.7: Software reset for more details.

Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must
configure the noise filters, if needed. By default, an analog noise filter is present on the SDA
and SCL inputs. This analog filter is compliant with the I2C specification which requires the

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suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows spikes with a
programmable length of 1 to 15 I2CCLK periods to be suppressed.

Table 105. Comparison of analog vs. digital filters

- Analog filter Digital filter

Pulse width of Programmable length from 1 to 15 I2C peripheral

≥ 50 ns
suppressed spikes clocks
– Programmable length: extra filtering capability
Benefits Available in Stop mode vs. standard requirements
– Stable length
Variation vs. temperature, Wakeup from Stop mode on address match is not
Drawbacks
voltage, process available when digital filter is enabled

Caution: Changing the filter configuration is not allowed when the I2C is enabled.

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I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window

Figure 233. Setup and hold timings

DATA HOLD TIME
SCL falling edge internal
detection

tSYNC1 SDADEL: SCL stretched low by the I2C

SDA output delay

SCL

SDA

tHD;DAT
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.

DATA SETUP TIME

SCLDEL
SCL stretched low by the I2C

SCL

SDA

tSU;DAT
SU;STA
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output. MSv40108V1
MS49608V1

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• When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1)
x tI2CCLK.
TSDADEL impacts the hold time tHD;DAT.

The total SDA output delay is:

tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK }
tSYNC1 duration depends on these parameters:
– SCL falling slope
– When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max)
– When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK
– Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
In order to bridge the undefined region of the SCL falling edge, the user must program
SDADEL in such a way that:
{tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL
SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }
Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to
device datasheet for tAF values.
The maximum tHD;DAT can be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode
and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time.
This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before
it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation
becomes:
SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }.
Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to Table 106: I2C-SMBus specification data setup and hold times for tf, tr, tHD;DAT and
tVD;DAT standard values.
• After tSDADEL delay, or after sending SDA output in case the slave had to stretch the
clock because the data was not yet written in I2C_TXDR register, SCL line is kept at
low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where
tPRESC = (PRESC+1) x tI2CCLK.
tSCLDEL impacts the setup time tSU;DAT .

In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), the user must program SCLDEL in such a way that:
{[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL
Refer to Table 106: I2C-SMBus specification data setup and hold times for tr and tSU;DAT
standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using
the maximum values from the standard increases the constraints for the SDADEL and
SCLDEL calculation, but ensures the feature whatever the application.

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Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK, in both transmission
and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR
when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data
is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH=1 in slave mode, the SCL is not stretched. Consequently the SDADEL
must be programmed in such a way to guarantee also a sufficient setup time.

Table 106. I2C-SMBus specification data setup and hold times

Standard-mode Fast-mode Fast-mode Plus
SMBus
(Sm) (Fm) (Fm+)
Symbol Parameter Unit
Min. Max Min. Max Min. Max Min. Max

tHD;DAT Data hold time 0 - 0 - 0 - 0.3 -

µs
tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 - -
tSU;DAT Data setup time 250 - 100 - 50 - 250 -
Rise time of both SDA
tr - 1000 - 300 - 120 - 1000
and SCL signals ns
Fall time of both SDA
tf - 300 - 300 - 120 - 300
and SCL signals

Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.
• When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x
tI2CCLK.
tSCLL impacts the SCL low time tLOW .
• When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is tSCLH = (SCLH+1) x tPRESC where tPRESC =
(PRESC+1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH .

Refer to I2C master initialization for more details.

Caution: Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to I2C slave initialization for more details.
Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.

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Figure 234. I2C initialization flowchart

Initial settings

Clear PE bit in I2C_CR1

Configure ANFOFF and DNF[3:0] in I2C_CR1

Configure PRESC[3:0],

SDADEL[3:0], SCLDEL[3:0], SCLH[7:0],

SCLL[7:0] in I2C_TIMINGR

Configure NOSTRETCH in I2C_CR1

Set PE bit in I2C_CR1

End

MS19847V2

25.4.7 Software reset

A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that
case I2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. I2C_CR2 register: START, STOP, NACK
2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR
and in addition when the SMBus feature is supported:
1. I2C_CR2 register: PECBYTE
2. I2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least 3 APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence: - Write PE=0 - Check
PE=0 - Write PE=1.

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25.4.8 Data transfer

The data transfer is managed through transmit and receive data registers and a shift
register.

Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th
SCL pulse (before the Acknowledge pulse).

Figure 235. Data reception

ACK pulse ACK pulse

legend:
SCL SCL
stretch
Shift register xx data1 xx data2 xx

RXNE

rd data0 rd data1

I2C_RXDR data0 data1 data2

MS19848V1

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Transmission
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register
after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is
stretched low until I2C_TXDR is written. The stretch is done after the 9th SCL pulse.

Figure 236. Data transmission

ACK pulse ACK pulse

legend:
SCL
SCL
stretch

data1

data2
Shift register xx xx xx

TXE

wr data1 wr data2

I2C_TXDR data0 data1 data2

MS19849V1

Hardware transfer management

The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
– NACK, STOP and ReSTART generation in master mode
– ACK control in slave receiver mode
– PEC generation/checking when SMBus feature is supported
The byte counter is always used in master mode. By default it is disabled in slave mode, but
it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or
if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode,
TCR flag is set when the number of bytes programmed in NBYTES has been transferred,
and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR
is cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.

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When RELOAD=0 in master mode, the counter can be used in 2 modes:

• Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the
master automatically sends a STOP condition once the number of bytes programmed
in the NBYTES[7:0] bit field has been transferred.
• Software end mode (AUTOEND = ‘0’ in the I2C_CR2 register). In this mode, software
action is expected once the number of bytes programmed in the NBYTES[7:0] bit field
has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is
set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by
software when the START or STOP bit is set in the I2C_CR2 register. This mode must
be used when the master wants to send a RESTART condition.
Caution: The AUTOEND bit has no effect when the RELOAD bit is set.

Table 107. I2C configuration

Function SBC bit RELOAD bit AUTOEND bit

Master Tx/Rx NBYTES + STOP x 0 1

Master Tx/Rx + NBYTES + RESTART x 0 0
Slave Tx/Rx
0 x x
all received bytes ACKed
Slave Rx with ACK control 1 1 x

25.4.9 I2C slave mode

I2C slave initialization
In order to work in slave mode, the user must enable at least one slave address. Two
registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own
addresses OA1 and OA2.
• OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by
setting the OA1MODE bit in the I2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.
• If additional slave addresses are required, the 2nd slave address OA2 can be
configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in
the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2],
OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received
address. As soon as OA2MSK is not equal to 0, the address comparator for OA2
excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not
acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except
reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific
enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with
OA2MSK=0.
OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.
• The General Call address is enabled by setting the GCEN bit in the I2C_CR1 register.
When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is
set, and an interrupt is generated if the ADDRIE bit is set.

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By default, the slave uses its clock stretching capability, which means that it stretches the
SCL signal at low level when needed, in order to perform software actions. If the master
does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the
I2C_CR1 register.
After receiving an ADDR interrupt, if several addresses are enabled the user must read the
ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR
flag must also be checked in order to know the transfer direction.

Slave clock stretching (NOSTRETCH = 0)

In default mode, the I2C slave stretches the SCL clock in the following situations:
• When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.
• In transmission, if the previous data transmission is completed and no new data is
written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag
is cleared (TXE=1). This stretch is released when the data is written to the I2C_TXDR
register.
• In reception when the I2C_RXDR register is not read yet and a new data reception is
completed. This stretch is released when I2C_RXDR is read.
• When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.
• After SCL falling edge detection, the I2C stretches SCL low during
[(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK.

Slave without clock stretching (NOSTRETCH = 1)

When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL
signal.
• The SCL clock is not stretched while the ADDR flag is set.
• In transmission, the data must be written in the I2C_TXDR register before the first SCL
pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is
set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register. The OVR flag is also set when the first data transmission starts and
the STOPF bit is still set (has not been cleared). Therefore, if the user clears the
STOPF flag of the previous transfer only after writing the first data to be transmitted in
the next transfer, he ensures that the OVR status is provided, even for the first data to
be transmitted.
• In reception, the data must be read from the I2C_RXDR register before the 9th SCL
pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag
is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register.

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Slave Byte Control mode

In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must
be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant
with SMBus standards.
Reload mode must be selected in order to allow byte ACK control in slave reception mode
(RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR
interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is
received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL
pulses. The user can read the data from the I2C_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is
released by programming NBYTES to a non-zero value: the acknowledge or not-
acknowledge is sent and next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is
continuous during NBYTES data reception.
Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not
addressed, or when ADDR=1.
The RELOAD bit value can be changed when ADDR=1, or when TCR=1.
Caution: Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when
NOSTRETCH=1 is not allowed.

Figure 237. Slave initialization flowchart

Slave
initialization

Initial settings

Clear {OA1EN, OA2EN} in I2C_OAR1 and I2C_OAR2

Configure {OA1[9:0], OA1MODE, OA1EN,

OA2[6:0], OA2MSK[2:0], OA2EN, GCEN}

Configure SBC in I2C_CR1*

Enable interrupts and/or

DMA in I2C_CR1

End

*SBC must be set to support SMBus features

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Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.
The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be
transmitted.
When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is
generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases
the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition.
The TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF
flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the
SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is
received (ADDR=1), the user can choose either to send the content of the I2C_TXDR
register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in
order to program a new data byte.
In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be
programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case,
the number of TXIS events during the transfer corresponds to the value programmed in
NBYTES.
Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to
program the first data byte. The first data byte to be sent must be previously programmed in
the I2C_TXDR register:
• This data can be the data written in the last TXIS event of the previous transmission
message.
• If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error is
generated (the OVR flag is set).
If a TXIS event is needed, (Transmit Interrupt or Transmit DMA request), the user must
set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.

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Figure 238. Transfer sequence flowchart for I2C slave transmitter,

NOSTRETCH= 0

Slave
transmission

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Optional: Set I2C_ISR.TXE = 1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

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Figure 239. Transfer sequence flowchart for I2C slave transmitter,

NOSTRETCH= 1

Slave
transmission

Slave initialization

No
No
I2C_ISR.TXIS I2C_ISR.STOPF
=1? =1?

Yes Yes

Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1

and I2C_ISR.TXIS=1

Set I2C_ICR.STOPCF

MS19852V2

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Figure 240. Transfer bus diagrams for I2C slave transmitter

legend:
Example I2C slave transmitter 3 bytes with 1st data flushed,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS TXIS reception

S Address A A A data3 NA P
SCL stretch
data1 data2

EV1 EV2 EV3 EV4 EV5

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)

legend :
Example I2C slave transmitter 3 bytes without 1st data flush,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS reception

SCL stretch
S Address A data1 A data2 A data3 NA P

EV1 EV2 EV3 EV4

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)

legend:
Example I2C slave transmitter 3 bytes, NOSTRETCH=1:
transmission
TXIS TXIS TXIS STOPF
reception

S Address A data1 A data2 A data3 NA P SCL stretch

EV1 EV2 EV3 EV4 EV5

TXE

EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF

MS19853V2

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Slave receiver
RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is
set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.
When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an
interrupt is generated.

Figure 241. Transfer sequence flowchart for slave receiver with NOSTRETCH=0

Slave reception

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE
=1?

Yes

Write I2C_RXDR.RXDATA

MS19855V2

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Figure 242. Transfer sequence flowchart for slave receiver with NOSTRETCH=1

Slave reception

Slave initialization

No
No
I2C_ISR.RXNE I2C_ISR.STOPF
=1? =1?

Yes Yes

Read I2C_RXDR.RXDATA Set I2C_ICR.STOPCF

MS19856V2

Figure 243. Transfer bus diagrams for I2C slave receiver

legend:
Example I2C slave receiver 3 bytes, NOSTRETCH=0:
transmission
ADDR RXNE RXNE RXNE reception

SCL stretch
S Address A data1 A data2 A data3 A

EV1 EV2 EV3 EV4

RXNE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: RXNE ISR: rd data1
EV3 : RXNE ISR: rd data2
EV4: RXNE ISR: rd data3

Example I2C slave receiver 3 bytes, NOSTRETCH=1: legend:

transmission
RXNE RXNE RXNE reception

S Address A data 1 A data 2 A data 3 A P SCL stretch

EV1 EV2 EV3

RXNE

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF
MS19857V2

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25.4.10 I2C master mode

I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the
SCLH and SCLL bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
• The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
• The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK
clock. The I2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.
The I2C detects its own SCL high level after a tSYNC2 delay depending on the SCL rising
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The I2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the I2C_TIMINGR register.
Consequently the master clock period is:
tSCL = tSYNC1 + tSYNC2 + {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x tI2CCLK}
The duration of tSYNC1 depends on these parameters:
– SCL falling slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
The duration of tSYNC2 depends on these parameters:
– SCL rising slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)

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Figure 244. Master clock generation

SCL master clock generation

SCL high level detected

SCLH counter starts

tSYNC2 SCLH
SCLL
tSYNC1
SCL

SCL low level detected

SCL released
SCLL counter starts

SCL driven low

SCL master clock synchronization

SCL high level detected SCL high level detected SCL high level detected
SCLH counter starts SCLH counter starts SCLH counter starts

SCLH SCLH SCLH

SCLL SCLL

SCL driven low by SCL driven low by

another device another device
SCL low level detected
SCLL counter starts

SCL low level detected

SCLL counter starts SCL released

MS19858V1

Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given the
table below.

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Table 108. I2C-SMBus specification clock timings

Standard- Fast-mode Fast-mode
SMBus
mode (Sm) (Fm) Plus (Fm+)
Symbol Parameter Unit
Min Max Min Max Min Max Min Max

fSCL SCL clock frequency - 100 - 400 - 1000 - 100 kHz

tHD:STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - 4.0 - µs
Set-up time for a repeated START
tSU:STA 4.7 - 0.6 - 0.26 - 4.7 - µs
condition
tSU:STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - 4.0 - µs
Bus free time between a STOP and
tBUF 4.7 - 1.3 - 0.5 - 4.7 - µs
START condition
tLOW Low period of the SCL clock 4.7 - 1.3 - 0.5 - 4.7 - µs
tHIGH Period of the SCL clock 4.0 - 0.6 - 0.26 - 4.0 50 µs
tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 - 1000 ns
tf Fall time of both SDA and SCL signals - 300 - 300 - 120 - 300 ns

Note: SCLL is also used to generate the tBUF and tSU:STA timings.
SCLH is also used to generate the tHD:STA and tSU:STO timings.
Refer to Section 25.4.11: I2C_TIMINGR register configuration examples for examples of
I2C_TIMINGR settings vs. I2CCLK frequency.

Master communication initialization (address phase)

In order to initiate the communication, the user must program the following parameters for
the addressed slave in the I2C_CR2 register:
• Addressing mode (7-bit or 10-bit): ADD10
• Slave address to be sent: SADD[9:0]
• Transfer direction: RD_WRN
• In case of 10-bit address read: HEAD10R bit. HEAD10R must be configure to indicate
if the complete address sequence must be sent, or only the header in case of a
direction change.
• The number of bytes to be transferred: NBYTES[7:0]. If the number of bytes is equal to
or greater than 255 bytes, NBYTES[7:0] must initially be filled with 0xFF.
The user must then set the START bit in I2C_CR2 register. Changing all the above bits is
not allowed when START bit is set.
Then the master automatically sends the START condition followed by the slave address as
soon as it detects that the bus is free (BUSY = 0) and after a delay of tBUF.
In case of an arbitration loss, the master automatically switches back to slave mode and can
acknowledge its own address if it is addressed as a slave.
Note: The START bit is reset by hardware when the slave address has been sent on the bus,
whatever the received acknowledge value. The START bit is also reset by hardware if an
arbitration loss occurs.
In 10-bit addressing mode, when the Slave Address first 7 bits is NACKed by the slave, the

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master re-launches automatically the slave address transmission until ACK is received. In
this case ADDRCF must be set if a NACK is received from the slave, in order to stop
sending the slave address.
If the I2C is addressed as a slave (ADDR=1) while the START bit is set, the I2C switches to
slave mode and the START bit is cleared, when the ADDRCF bit is set.
Note: The same procedure is applied for a Repeated Start condition. In this case BUSY=1.

Figure 245. Master initialization flowchart

Master
initialization

Initial settings

Enable interrupts and/or DMA in I2C_CR1

End

MS19859V2

Initialization of a master receiver addressing a 10-bit address slave

• If the slave address is in 10-bit format, the user can choose to send the complete read
sequence by clearing the HEAD10R bit in the I2C_CR2 register. In this case the master
automatically sends the following complete sequence after the START bit is set:
(Re)Start + Slave address 10-bit header Write + Slave address 2nd byte + REStart +
Slave address 10-bit header Read

Figure 246. 10-bit address read access with HEAD10R=0

11110XX 0 11110XX 1

Slave address Slave address Slave address

S R/W A1 A2 Sr R/W A3 DATA A DATA A P
1st 7 bits 2nd byte 1st 7 bits

Write Read

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• If the master addresses a 10-bit address slave, transmits data to this slave and then
reads data from the same slave, a master transmission flow must be done first. Then a
repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this
case the master sends this sequence: ReStart + Slave address 10-bit header Read.

Figure 247. 10-bit address read access with HEAD10R=1

11110XX 0

Slave address Slave address

S R/W A A DATA A DATA A/A
1st 7 bits 2nd byte

Write

11110XX 1
Slave address
Sr R/W A DATA A DATA A P
1st 7 bits

Read

MS19823V1

Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th
SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the I2C_CR1 register. The flag is
cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode
must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low
until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
• When RELOAD=0 and NBYTES data have been transferred:
– In automatic end mode (AUTOEND=1), a STOP is automatically sent.
– In software end mode (AUTOEND=0), the TC flag is set and the SCL line is
stretched low in order to perform software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition is
sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
• If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically
sent after the NACK reception. the NACKF flag is set in the I2C_ISR register, and an
interrupt is generated if the NACKIE bit is set.

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Figure 248. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes

Master
transmission

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF = I2C_ISR.TXIS
1? =1?

Yes Yes

Write I2C_TXDR
End

NBYTES No
transmitted?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

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Figure 249. Transfer sequence flowchart for I2C master transmitter for N>255 bytes

Master
transmission

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD = 1
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF I2C_ISR.TXIS
= 1? = 1?

Yes Yes

Write I2C_TXDR
End

No
NBYTES
transmitted ?

Yes

Yes
I2C_ISR.TC
= 1?

Set I2C_CR2.START
with slave addess No
NBYTES ...

I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES = N; N = 0; RELOAD = 0
AUTOEND = 0 for RESTART; 1 for STOP
End
ELSE
NBYTES = 0xFF; N = N-255
RELOAD = 1

MS19861V3

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Figure 250. Transfer bus diagrams for I2C master transmitter

Example I2C master transmitter 2 bytes, automatic end mode (STOP)

legend:

TXIS TXIS transmission

reception
S Address A data1 A data2 A P
SCL stretch
INIT EV1 EV2

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example I2C master transmitter 2 bytes, software end mode (RESTART)

TXIS TXIS TC legend:

transmission
S Address A data1 A data2 A ReS Address
reception

INIT EV1 EV2 EV3 SCL stretch

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

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Master receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th
SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1
register. The flag is cleared when I2C_RXDR is read.
If the total number of data bytes to be received is greater than 255, reload mode must be
selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched
low until NBYTES[7:0] is written to a non-zero value.
• When RELOAD=0 and NBYTES[7:0] data have been transferred:
– In automatic end mode (AUTOEND=1), a NACK and a STOP are automatically
sent after the last received byte.
– In software end mode (AUTOEND=0), a NACK is automatically sent after the last
received byte, the TC flag is set and the SCL line is stretched low in order to allow
software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition,
followed by slave address, are sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.

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Figure 251. Transfer sequence flowchart for I2C master receiver for N≤255 bytes

Master reception

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

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Figure 252. Transfer sequence flowchart for I2C master receiver for N >255 bytes

Master reception

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD =1
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

Set I2C_CR2.START with

No
slave addess NBYTES ...
No
I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES =N; N=0;RELOAD=0
AUTOEND=0 for RESTART; 1 for STOP
ELSE
NBYTES =0xFF;N=N-255
RELOAD=1

End

MS19864V2

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Figure 253. Transfer bus diagrams for I2C master receiver

Example I2C master receiver 2 bytes, automatic end mode (STOP)

RXNE RXNE
legend:

S Address A data1 A data2 NA P transmission

reception
INIT EV1 EV2
SCL stretch
NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2

Example I2C master receiver 2 bytes, software end mode (RESTART)

RXNE RXNE TC legend:

transmission
S Address A data1 A data2 NA ReS Address
reception

INIT EV1 EV2 SCL stretch

NBYTES

xx 2 N

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: read data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

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25.4.11 I2C_TIMINGR register configuration examples

The tables below provide examples of how to program the I2C_TIMINGR to obtain timings
compliant with the I2C specification. In order to get more accurate configuration values, the
STM32CubeMX tool (I2C Configuration window) must be used.

Table 109. Examples of timing settings for fI2CCLK = 8 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 500 kHz

PRESC 1 1 0 0
SCLL 0xC7 0x13 0x9 0x6
tSCLL 200x250 ns = 50 µs 20x250 ns = 5.0 µs 10x125 ns = 1250 ns 7x125 ns = 875 ns
SCLH 0xC3 0xF 0x3 0x3
tSCLH 196x250 ns = 49 µs 16x250 ns = 4.0µs 4x125 ns = 500 ns 4x125 ns = 500 ns
(1)
tSCL ~100 µs(2) ~10 µs(2) ~2500 ns(3) ~2000 ns(4)
SDADEL 0x2 0x2 0x1 0x0
tSDADEL 2x250 ns = 500 ns 2x250 ns = 500 ns 1x125 ns = 125 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
tSCLDEL 5x250 ns = 1250 ns 5x250 ns = 1250 ns 4x125 ns = 500 ns 2x125 ns = 250 ns
1. SCL period tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples
only.
2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 655 ns.

Table 110. Examples of timings settings for fI2CCLK = 16 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 1000 kHz

PRESC 3 3 1 0
SCLL 0xC7 0x13 0x9 0x4
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 5 x 62.5 ns = 312.5 ns
SCLH 0xC3 0xF 0x3 0x2
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
(1)
tSCL ~100 µs(2) ~10 µs(2) ~2500 ns(3) ~1000 ns(4)
SDADEL 0x2 0x2 0x2 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 2 x 125 ns = 250 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x2
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
1. SCL period tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples
only.

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2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 500 ns.

Table 111. Examples of timings settings for fI2CCLK = 48 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 1000 kHz

PRESC 0xB 0xB 5 5

SCLL 0xC7 0x13 0x9 0x3
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 4 x 125 ns = 500 ns
SCLH 0xC3 0xF 0x3 0x1
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
tSCL(1) ~100 µs(2) ~10 µs(2) ~2500 ns(3) ~875 ns(4)
SDADEL 0x2 0x2 0x3 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 3 x 125 ns = 375 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
1. The SCL period tSCL is greater than tSCLL + tSCLH due to the SCL internal detection delay. Values provided for tSCL are only
examples.
2. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 1000 ns
3. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 750 ns
4. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 250 ns

25.4.12 SMBus specific features

This section is relevant only when SMBus feature is supported. Refer to Section 25.3: I2C
implementation.

Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. SMBus provides a control bus for system and power management
related tasks.
This peripheral is compatible with the SMBus specification (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
• A slave is a device that receives or responds to a command.
• A master is a device that issues commands, generates the clocks and terminates the
transfer.
• A host is a specialized master that provides the main interface to the system’s CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.

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Bus protocols
There are eleven possible command protocols for any given device. A device may use any
or all of the eleven protocols to communicate. The protocols are Quick Command, Send
Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block
Read, Block Write and Block Write-Block Read Process Call. These protocols should be
implemented by the user software.
For more details of these protocols, refer to SMBus specification (http://smbus.org).

Address resolution protocol (ARP)

SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. In order to provide a mechanism to isolate each device for the
purpose of address assignment each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit in I2C_CR1 register. The
ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus Address Resolution Protocol, refer to SMBus specification
(http://smbus.org).

Received Command and Data acknowledge control

A SMBus receiver must be able to NACK each received command or data. In order to allow
the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting
SBC bit in I2C_CR1 register. Refer to Slave Byte Control mode on page 719 for more
details.

Host Notify protocol

This peripheral supports the Host Notify protocol by setting the SMBHEN bit in the I2C_CR1
register. In this case the host acknowledges the SMBus Host Address (0b0001 000).
When this protocol is used, the device acts as a master and the host as a slave.

SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host
through the SMBALERT# pin that it wants to talk. The host processes the interrupt and
simultaneously accesses all SMBALERT# devices through the Alert Response Address
(0b0001 100). Only the device(s) which pulled SMBALERT# low acknowledges the Alert
Response Address.
When configured as a slave device(SMBHEN=0), the SMBA pin is pulled low by setting the
ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same
time.
When configured as a host (SMBHEN=1), the ALERT flag is set in the I2C_ISR register
when a falling edge is detected on the SMBA pin and ALERTEN=1. An interrupt is
generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN=0, the ALERT
line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN=0.

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Packet error checking

A packet error checking mechanism has been introduced in the SMBus specification to
improve reliability and communication robustness. Packet Error Checking is implemented
by appending a Packet Error Code (PEC) at the end of each message transfer. The PEC is
calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial on all the message bytes
(including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows a Not Acknowledge to be
sent automatically when the received byte does not match with the hardware calculated
PEC.

Timeouts
This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined
in SMBus specification.

Table 112. SMBus timeout specifications

Limits
Symbol Parameter Unit
Min Max

tTIMEOUT Detect clock low timeout 25 35 ms

tLOW:SEXT(1) Cumulative clock low extend time (slave device) - 25 ms
tLOW:MEXT(2) Cumulative clock low extend time (master device) - 10 ms
1. tLOW:SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that, another slave device or the master also extends the
clock causing the combined clock low extend time to be greater than tLOW:SEXT. Therefore, this parameter is
measured with the slave device as the sole target of a full-speed master.
2. tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master also extends the clock causing the combined clock low time to be greater than tLOW:MEXT
on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of
the master.

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Figure 254. Timeout intervals for tLOW:SEXT, tLOW:MEXT.

Start Stop
tLOW:SEXT

ClkAck ClkAck
tLOW:MEXT tLOW:MEXT tLOW:MEXT

SMBCLK

SMBDAT

MS19866V1

Bus idle detection

A master can assume that the bus is free if it detects that the clock and data signals have
been high for tIDLE greater than tHIGH,MAX. (refer to Table 106: I2C-SMBus specification data
setup and hold times)
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.

25.4.13 SMBus initialization

This section is relevant only when SMBus feature is supported. Refer to Section 25.3: I2C
implementation.
In addition to I2C initialization, some other specific initialization must be done in order to
perform SMBus communication:

Received Command and Data Acknowledge control (Slave mode)

A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave Byte Control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to Slave Byte Control mode on page 719 for more
details.

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Specific address (Slave mode)

The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection on
page 742 for more details.
• The SMBus Device Default Address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus Host Address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
• The Alert Response Address (0b0001100) is enabled by setting the ALERTEN bit in the
I2C_CR1 register.

Packet error checking

PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC
transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the I2C_CR2
register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.

Table 113. SMBus with PEC configuration

Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit

Master Tx/Rx NBYTES + PEC+ STOP x 0 1 1

Master Tx/Rx NBYTES + PEC + ReSTART x 0 0 1
Slave Tx/Rx with PEC 1 0 x 1

Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification.
• tTIMEOUT check
In order to enable the tTIMEOUT check, the 12-bit TIMEOUTA[11:0] bits must be
programmed with the timer reload value in order to check the tTIMEOUT parameter. The
TIDLE bit must be configured to ‘0’ in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x tI2CCLK, the TIMEOUT
flag is set in the I2C_ISR register.
Refer to Table 114: Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms).
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
• tLOW:SEXT and tLOW:MEXT check
Depending on if the peripheral is configured as a master or as a slave, The 12-bit
TIMEOUTB timer must be configured in order to check tLOW:SEXT for a slave and

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tLOW:MEXT for a master. As the standard specifies only a maximum, the user can choose
the same value for the both.
Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than
(TIMEOUTB+1) x 2048 x tI2CCLK, and in the timeout interval described in Bus idle
detection on page 742 section, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 115: Examples of TIMEOUTB settings for various I2CCLK frequencies
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.

Bus Idle detection

In order to enable the tIDLE check, the 12-bit TIMEOUTA[11:0] field must be programmed
with the timer reload value in order to obtain the tIDLE parameter. The TIDLE bit must be
configured to ‘1 in order to detect both SCL and SDA high level timeout.
Then the timer is enabled by setting the TIMOUTEN bit in the I2C_TIMEOUTR register.
If both the SCL and SDA lines remain high for a time greater than (TIMEOUTA+1) x 4 x
tI2CCLK, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 116: Examples of TIMEOUTA settings for various I2CCLK frequencies (max
tIDLE = 50 µs)
Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is
set.

25.4.14 SMBus: I2C_TIMEOUTR register configuration examples

This section is relevant only when SMBus feature is supported. Refer to Section 25.3: I2C
implementation.
• Configuring the maximum duration of tTIMEOUT to 25 ms:

Table 114. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max tTIMEOUT = 25 ms)
fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIMEOUT
8 MHz 0x61 0 1 98 x 2048 x 125 ns = 25 ms
16 MHz 0xC3 0 1 196 x 2048 x 62.5 ns = 25 ms
48 MHz 0x249 0 1 586 x 2048 x 20.08 ns = 25 ms

• Configuring the maximum duration of tLOW:SEXT and tLOW:MEXT to 8 ms:

Table 115. Examples of TIMEOUTB settings for various I2CCLK frequencies

fI2CCLK TIMEOUTB[11:0] bits TEXTEN bit tLOW:EXT
8 MHz 0x1F 1 32 x 2048 x 125 ns = 8 ms
16 MHz 0x3F 1 64 x 2048 x 62.5 ns = 8 ms
48 MHz 0xBB 1 188 x 2048 x 20.08 ns = 8 ms

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• Configuring the maximum duration of tIDLE to 50 µs

Table 116. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max tIDLE = 50 µs)
fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIDLE
8 MHz 0x63 1 1 100 x 4 x 125 ns = 50 µs
16 MHz 0xC7 1 1 200 x 4 x 62.5 ns = 50 µs
48 MHz 0x257 1 1 600 x 4 x 20.08 ns = 50 µs

25.4.15 SMBus slave mode

This section is relevant only when SMBus feature is supported. Refer to Section 25.3: I2C
implementation.
In addition to I2C slave transfer management (refer to Section 25.4.9: I2C slave mode)
some additional software flowcharts are provided to support SMBus.

SMBus Slave transmitter

When the IP is used in SMBus, SBC must be programmed to ‘1’ in order to allow the PEC
transmission at the end of the programmed number of data bytes. When the PECBYTE bit
is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In
that case the total number of TXIS interrupts is NBYTES-1 and the content of the
I2C_PECR register is automatically transmitted if the master requests an extra byte after the
NBYTES-1 data transfer.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 255. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC

SMBus slave
transmission

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = N + 1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

MS19867V2

Figure 256. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
legend:
Example SMBus slave transmitter 2 bytes + PEC,
transmission
ADDR TXIS TXIS reception

S Address A data1 A A PEC NA P

SCL stretch
data2

EV1 EV2 EV3

NBYTES 3

EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2

MS19869V2

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SMBus Slave receiver

When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the
PEC checking at the end of the programmed number of data bytes. In order to allow the
ACK control of each byte, the reload mode must be selected (RELOAD=1). Refer to Slave
Byte Control mode on page 719 for more details.
In order to check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit
must be set. In this case, after NBYTES-1 data have been received, the next received byte
is compared with the internal I2C_PECR register content. A NACK is automatically
generated if the comparison does not match, and an ACK is automatically generated if the
comparison matches, whatever the ACK bit value. Once the PEC byte is received, it is
copied into the I2C_RXDR register like any other data, and the RXNE flag is set.
In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the
ERRIE bit is set in the I2C_CR1 register.
If no ACK software control is needed, the user can program PECBYTE=1 and, in the same
write operation, program NBYTES with the number of bytes to be received in a continuous
flow. After NBYTES-1 are received, the next received byte is checked as being the PEC.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 257. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC

SMBus slave
reception

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = 1, RELOAD =1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE =1?
I2C_ISR.TCR = 1?

Yes
Read I2C_RXDR.RXDATA
Program I2C_CR2.NACK = 0
I2C_CR2.NBYTES = 1
N=N-1

No
N = 1?

Yes
Read I2C_RXDR.RXDATA
Program RELOAD = 0
NACK = 0 and NBYTES = 1

No
I2C_ISR.RXNE =1?

Yes
Read I2C_RXDR.RXDATA

End
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Figure 258. Bus transfer diagrams for SMBus slave receiver (SBC=1)
legend:
Example SMBus slave receiver 2 bytes + PEC
transmission
ADDR RXNE RXNE RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 3

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC

Example SMBus slave receiver 2 bytes + PEC, with ACK control legend :

(RELOAD=1/0) transmission
ADDR RXNE,TCR RXNE,TCR RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 1

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYTES = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYTES = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC

MS19870V2

This section is relevant only when SMBus feature is supported. Refer to Section 25.3: I2C
implementation.
In addition to I2C master transfer management (refer to Section 25.4.10: I2C master mode)
some additional software flowcharts are provided to support SMBus.

SMBus Master transmitter

When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts is NBYTES-1. So if the PECBYTE bit is
set when NBYTES=0x1, the content of the I2C_PECR register is automatically transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
must be selected (AUTOEND=1). In this case, the STOP condition automatically follows the
PEC transmission.

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When the SMBus master wants to send a RESTART condition after the PEC, software
mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been
transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the
PEC transmission, stretching the SCL line low. The RESTART condition must be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 259. Bus transfer diagrams for SMBus master transmitter

Example SMBus master transmitter 2 bytes + PEC, automatic end mode (STOP)

TXIS TXIS
legend:

S Address A data1 A data2 A PEC A P transmission

reception
INIT EV1 EV2
SCL stretch
TXE

NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example SMBus master transmitter 2 bytes + PEC, software end mode (RESTART)

TC legend:
TXIS TXIS
transmission
S Address A data1 A data2 A PEC A Rstart Address
reception

INIT EV1 EV2 EV3 SCL stretch

xx 3 N

NBYTES

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19871V2

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SMBus Master receiver

When the SMBus master wants to receive the PEC followed by a STOP at the end of the
transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be
set and the slave address must be programmed, before setting the START bit. In this case,
after NBYTES-1 data have been received, the next received byte is automatically checked
versus the I2C_PECR register content. A NACK response is given to the PEC byte, followed
by a STOP condition.
When the SMBus master receiver wants to receive the PEC byte followed by a RESTART
condition at the end of the transfer, software mode must be selected (AUTOEND=0). The
PECBYTE bit must be set and the slave address must be programmed, before setting the
START bit. In this case, after NBYTES-1 data have been received, the next received byte is
automatically checked versus the I2C_PECR register content. The TC flag is set after the
PEC byte reception, stretching the SCL line low. The RESTART condition can be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 260. Bus transfer diagrams for SMBus master receiver

Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)

RXNE RXNE RXNE

legend:

S Address A data1 A data2 A PEC NA P transmission

reception
INIT EV1 EV2 EV3
SCL stretch
NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC

Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)

RXNE RXNE RXNE TC legend:

transmission
S Address A data1 A data2 A PEC NA Restart Address
reception

INIT EV1 EV2 EV3 EV4 SCL stretch

NBYTES

xx 3 N

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START

MS19872V2

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25.4.16 Wakeup from Stop mode on address match

This section is relevant only when Wakeup from Stop mode feature is supported. Refer to
Section 25.3: I2C implementation.
The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is
addressed. All addressing modes are supported.
Wakeup from Stop mode is enabled by setting the WUPEN bit in the I2C_CR1 register. The
HSI16 oscillator must be selected as the clock source for I2CCLK in order to allow wakeup
from Stop mode.
During Stop mode, the HSI16 is switched off. When a START is detected, the I2C interface
switches the HSI16 on, and stretches SCL low until HSI16 is woken up.
HSI16 is then used for the address reception.
In case of an address match, the I2C stretches SCL low during MCU wakeup time. The
stretch is released when ADDR flag is cleared by software, and the transfer goes on
normally.
If the address does not match, the HSI16 is switched off again and the MCU is not woken
up.
Note: If the I2C clock is the system clock, or if WUPEN = 0, the HSI16 is not switched on after a
START is received.
Only an ADDR interrupt can wakeup the MCU. Therefore do not enter Stop mode when the
I2C is performing a transfer as a master, or as an addressed slave after the ADDR flag is
set. This can be managed by clearing SLEEPDEEP bit in the ADDR interrupt routine and
setting it again only after the STOPF flag is set.
Caution: The digital filter is not compatible with the wakeup from Stop mode feature. If the DNF bit is
not equal to 0, setting the WUPEN bit has no effect.
Caution: This feature is available only when the I2C clock source is the HSI16 oscillator.
Caution: Clock stretching must be enabled (NOSTRETCH=0) to ensure proper operation of the
wakeup from Stop mode feature.
Caution: If wakeup from Stop mode is disabled (WUPEN=0), the I2C peripheral must be disabled
before entering Stop mode (PE=0).

25.4.17 Error conditions

The following errors are the error conditions which may cause communication to fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a
SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C is involved in the transfer as master or addressed
slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the I2C enters
address recognition state like for a correct START condition.
When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt
is generated if the ERRIE bit is set in the I2C_CR1 register.

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Arbitration lost (ARLO)

An arbitration loss is detected when a high level is sent on the SDA line, but a low level is
sampled on the SCL rising edge.
• In master mode, arbitration loss is detected during the address phase, data phase and
data acknowledge phase. In this case, the SDA and SCL lines are released, the
START control bit is cleared by hardware and the master switches automatically to
slave mode.
• In slave mode, arbitration loss is detected during data phase and data acknowledge
phase. In this case, the transfer is stopped, and the SCL and SDA lines are released.
When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Overrun/underrun error (OVR)

An overrun or underrun error is detected in slave mode when NOSTRETCH=1 and:
• In reception when a new byte is received and the RXDR register has not been read yet.
The new received byte is lost, and a NACK is automatically sent as a response to the
new byte.
• In transmission:
– When STOPF=1 and the first data byte should be sent. The content of the
I2C_TXDR register is sent if TXE=0, 0xFF if not.
– When a new byte must be sent and the I2C_TXDR register has not been written
yet, 0xFF is sent.
When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register,
and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Packet Error Checking Error (PECERR)

This section is relevant only when the SMBus feature is supported. Refer to Section 25.3:
I2C implementation.
A PEC error is detected when the received PEC byte does not match with the I2C_PECR
register content. A NACK is automatically sent after the wrong PEC reception.
When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Timeout Error (TIMEOUT)

This section is relevant only when the SMBus feature is supported. Refer to Section 25.3:
I2C implementation.
A timeout error occurs for any of these conditions:
• TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is
used to detect a SMBus timeout.
• TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA
[11:0] bits: this is used to detect a bus idle condition.
• Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus tLOW:MEXT parameter)
• Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus tLOW:SEXT parameter)

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When a timeout violation is detected in master mode, a STOP condition is automatically

sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Refer to Section 25.3:
I2C implementation.
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the
alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin.
An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

25.4.18 DMA requests

Transmission using DMA
DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit
in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see Section 9: Direct memory access controller (DMA)) to the I2C_TXDR
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
• In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to Master transmitter on page 730.
• In slave mode:
– With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
– With NOSTRETCH=1, the DMA must be initialized before the address match
event.
• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to SMBus Slave transmitter on page 745 and SMBus Master transmitter on
page 749.
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

Reception using DMA

DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured using the DMA peripheral (refer to Section 9: Direct memory access controller
(DMA) on page 213) whenever the RXNE bit is set. Only the data (including PEC) are
transferred with DMA.
• In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the

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DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
• In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
• If SMBus is supported (see Section 25.3: I2C implementation): the PEC transfer is
managed with the NBYTES counter. Refer to SMBus Slave receiver on page 747 and
SMBus Master receiver on page 751.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.

25.4.19 Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module.

25.5 I2C low-power modes

Table 117. Effect of low-power modes on the I2C
Mode Description

Sleep No effect. I2C interrupts cause the device to exit the Sleep mode.
The I2C registers content is kept. If WUPEN = 1 and I2C is clocked by an internal
oscillator (HSI16): the address recognition is functional. The I2C address match
Stop(1)
condition causes the device to exit the Stop mode. If WUPEN=0: the I2C must be
disabled before entering Stop mode
The I2C peripheral is powered down and must be reinitialized after exiting
Standby
Standby mode.
1. Refer to Section 25.3: I2C implementation for information about the Stop modes supported by each
instance. If wakeup from a specific Stop mode is not supported, the instance must be disabled before
entering this Stop mode.

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25.6 I2C interrupts

The table below gives the list of I2C interrupt requests.

Table 118. I2C Interrupt requests

Exit the Exit the Exit the
Interrupt Interrupt Event Enable Interrupt clear
Sleep Stop Standby
acronym event flag control bit method
mode mode modes

Receive buffer Read I2C_RXDR

RXNE RXIE
not empty register
Transmit buffer Write I2C_TXDR
TXIS TXIE
interrupt status register
Stop detection Write
STOPF STOPIE
interrupt flag STOPCF=1
Transfer Write I2C_CR2
Complete TCR with No
Reload TCIE NBYTES[7:0] ≠ 0
Yes
I2C_EV Transfer Write START=1 No
TC
complete or STOP=1
Address Write
ADDR ADDRIE Yes(1)
matched ADDRCF=1
NACK Write
NACKF NACKIE No
reception NACKCF=1
I2C Write
Bus error BERR
BERRCF=1
Write
Arbitration loss ARLO
ARLOCF=1
Overrun/Under
OVR Write OVRCF=1
run Yes
I2C_ER ERRIE No No
Write
PEC error PECERR
PECERRCF=1
Timeout/tLOW Write
TIMEOUT
error TIMEOUTCF=1
Write
SMBus Alert ALERT
ALERTCF=1
1. The ADDR match event can wake up the device from Stop mode only if the I2C instance supports the Wakeup from Stop
mode feature. Refer to Section 25.3: I2C implementation.

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25.7 I2C registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers are accessed by words (32-bit).

25.7.1 I2C control register 1 (I2C_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to
2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALERT SMBD SMBH WUPE NOSTR
Res. Res. Res. Res. Res. Res. Res. Res. PECEN GCEN SBC
EN EN EN N ETCH

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMA TXDMA ANF STOP NACK ADDR
Res. DNF[3:0] ERRIE TCIE RXIE TXIE PE
EN EN OFF IE IE IE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PECEN: PEC enable
0: PEC calculation disabled
1: PEC calculation enabled
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 22 ALERTEN: SMBus alert enable
0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled
(0001100x followed by NACK).
1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is
enabled (0001100x followed by ACK).
Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 21 SMBDEN: SMBus Device Default Address enable
0: Device Default Address disabled. Address 0b1100001x is NACKed.
1: Device Default Address enabled. Address 0b1100001x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 20 SMBHEN: SMBus Host Address enable
0: Host Address disabled. Address 0b0001000x is NACKed.
1: Host Address enabled. Address 0b0001000x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.

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Bit 19 GCEN: General call enable

0: General call disabled. Address 0b00000000 is NACKed.
1: General call enabled. Address 0b00000000 is ACKed.
Bit 18 WUPEN: Wakeup from Stop mode enable
0: Wakeup from Stop mode disable.
1: Wakeup from Stop mode enable.
Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced
by hardware to ‘0’. Refer to Section 25.3: I2C implementation.
Note: WUPEN can be set only when DNF = ‘0000’
Bit 17 NOSTRETCH: Clock stretching disable
This bit is used to disable clock stretching in slave mode. It must be kept cleared in master
mode.
0: Clock stretching enabled
1: Clock stretching disabled
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bit 16 SBC: Slave byte control
This bit is used to enable hardware byte control in slave mode.
0: Slave byte control disabled
1: Slave byte control enabled
Bit 15 RXDMAEN: DMA reception requests enable
0: DMA mode disabled for reception
1: DMA mode enabled for reception
Bit 14 TXDMAEN: DMA transmission requests enable
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
Bit 13 Reserved, must be kept at reset value.
Bit 12 ANFOFF: Analog noise filter OFF
0: Analog noise filter enabled
1: Analog noise filter disabled
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bits 11:8 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL input. The digital
filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to 1 tI2CCLK
...
1111: digital filter enabled and filtering capability up to15 tI2CCLK
Note: If the analog filter is also enabled, the digital filter is added to the analog filter.
This filter can only be programmed when the I2C is disabled (PE = 0).

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Bit 7 ERRIE: Error interrupts enable

0: Error detection interrupts disabled
1: Error detection interrupts enabled
Note: Any of these errors generate an interrupt:
Arbitration Loss (ARLO)
Bus Error detection (BERR)
Overrun/Underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)
Bit 6 TCIE: Transfer Complete interrupt enable
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
Note: Any of these events generate an interrupt:
Transfer Complete (TC)
Transfer Complete Reload (TCR)
Bit 5 STOPIE: Stop detection Interrupt enable
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
Bit 4 NACKIE: Not acknowledge received Interrupt enable
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
Bit 3 ADDRIE: Address match Interrupt enable (slave only)
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
Bit 2 RXIE: RX Interrupt enable
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
Bit 1 TXIE: TX Interrupt enable
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable
Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and
status bits are put back to their reset value. When cleared, PE must be kept low for at
least 3 APB clock cycles.

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25.7.2 I2C control register 2 (I2C_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEC AUTOE RE
Res. Res. Res. Res. Res. NBYTES[7:0]
BYTE ND LOAD

rs rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEAD1 RD_
NACK STOP START ADD10 SADD[9:0]
0R WRN
rs rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 PECBYTE: Packet error checking byte
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a
STOP condition or an Address matched is received, also when PE=0.
0: No PEC transfer.
1: PEC transmission/reception is requested
Note: Writing ‘0’ to this bit has no effect.
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 25 AUTOEND: Automatic end mode (master mode)
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR
flag is set when NBYTES data are transferred, stretching SCL low.
Bits 23:16 NBYTES[7:0]: Number of bytes
The number of bytes to be transmitted/received is programmed there. This field is don’t care
in slave mode with SBC=0.
Note: Changing these bits when the START bit is set is not allowed.

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Bit 15 NACK: NACK generation (slave mode)

The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP
condition or an Address matched is received, or when PE=0.
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
Note: Writing ‘0’ to this bit has no effect.
This bit is used in slave mode only: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART condition, whatever the NACK
bit value.
When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is
automatically generated whatever the NACK bit value.
When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value
does not depend on the NACK value.
Bit 14 STOP: Stop generation (master mode)
The bit is set by software, cleared by hardware when a STOP condition is detected, or when
PE = 0.
In Master Mode:
0: No Stop generation.
1: Stop generation after current byte transfer.
Note: Writing ‘0’ to this bit has no effect.
Bit 13 START: Start generation
This bit is set by software, and cleared by hardware after the Start followed by the address
sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can
also be cleared by software by writing ‘1’ to the ADDRCF bit in the I2C_ICR register.
0: No Start generation.
1: Restart/Start generation:
If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a
Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer.
Otherwise setting this bit generates a START condition once the bus is free.
Note: Writing ‘0’ to this bit has no effect.
The START bit can be set even if the bus is BUSY or I2C is in slave mode.
This bit has no effect when RELOAD is set.
Bit 12 HEAD10R: 10-bit address header only read direction (master receiver mode)
0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit
address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Note: Changing this bit when the START bit is set is not allowed.

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Bit 11 ADD10: 10-bit addressing mode (master mode)

0: The master operates in 7-bit addressing mode,
1: The master operates in 10-bit addressing mode
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (master mode)
0: Master requests a write transfer.
1: Master requests a read transfer.
Note: Changing this bit when the START bit is set is not allowed.
Bits 9:0 SADD[9:0]: Slave address (master mode)
In 7-bit addressing mode (ADD10 = 0):
SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9],
SADD[8] and SADD[0] are don't care.
In 10-bit addressing mode (ADD10 = 1):
SADD[9:0] should be written with the 10-bit slave address to be sent.
Note: Changing these bits when the START bit is set is not allowed.

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25.7.3 I2C own address 1 register (I2C_OAR1)

Address offset: 0x08
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1
OA1EN Res. Res. Res. Res. OA1[9:0]
MODE

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA1EN: Own Address 1 enable
0: Own address 1 disabled. The received slave address OA1 is NACKed.
1: Own address 1 enabled. The received slave address OA1 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 OA1MODE: Own Address 1 10-bit mode
0: Own address 1 is a 7-bit address.
1: Own address 1 is a 10-bit address.
Note: This bit can be written only when OA1EN=0.
Bits 9:0 OA1[9:0]: Interface own slave address
7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9],
OA1[8] and OA1[0] are don't care.
10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address.
Note: These bits can be written only when OA1EN=0.

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25.7.4 I2C own address 2 register (I2C_OAR2)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN Res. Res. Res. Res. OA2MSK[2:0] OA2[7:1] Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA2EN: Own Address 2 enable
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:8 OA2MSK[2:0]: Own Address 2 masks
000: No mask
001: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
Note: These bits can be written only when OA2EN=0.
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and
0b1111xxx) are not acknowledged even if the comparison matches.
Bits 7:1 OA2[7:1]: Interface address
7-bit addressing mode: 7-bit address
Note: These bits can be written only when OA2EN=0.
Bit 0 Reserved, must be kept at reset value.

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25.7.5 I2C timing register (I2C_TIMINGR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH[7:0] SCLL[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 PRESC[3:0]: Timing prescaler

This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for
data setup and hold counters (refer to I2C timings on page 711) and for SCL high and low
level counters (refer to I2C master initialization on page 726).
tPRESC = (PRESC+1) x tI2CCLK
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
tSCLDEL.
tSCLDEL = (SCLDEL+1) x tPRESC
Note: tSCLDEL is used to generate tSU:DAT timing.
Bits 19:16 SDADEL[3:0]: Data hold time
This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
tSDADEL.
tSDADEL= SDADEL x tPRESC
Note: SDADEL is used to generate tHD:DAT timing.
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
This field is used to generate the SCL high period in master mode.
tSCLH = (SCLH+1) x tPRESC
Note: SCLH is also used to generate tSU:STO and tHD:STA timing.
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
This field is used to generate the SCL low period in master mode.
tSCLL = (SCLL+1) x tPRESC
Note: SCLL is also used to generate tBUF and tSU:STA timings.

Note: This register must be configured when the I2C is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.

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25.7.6 I2C timeout register (I2C_TIMEOUTR)

Address offset: 0x14
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN Res. Res. Res. TIMEOUTB[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN Res. Res. TIDLE TIMEOUTA[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 TEXTEN: Extended clock timeout enable

0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected
In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected
tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
Note: These bits can be written only when TEXTEN=0.
Bit 15 TIMOUTEN: Clock timeout enable
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or
high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Note: This bit can be written only when TIMOUTEN=0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
This field is used to configure:
The SCL low timeout condition tTIMEOUT when TIDLE=0
tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
The bus idle condition (both SCL and SDA high) when TIDLE=1
tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK
Note: These bits can be written only when TIMOUTEN=0.

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 25.3: I2C implementation.

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25.7.7 I2C interrupt and status register (I2C_ISR)

Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] DIR

r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME PEC
BUSY Res. ALERT OVR ARLO BERR TCR TC STOPF NACKF ADDR RXNE TXIS TXE
OUT ERR

r r r r r r r r r r r r r rs rs

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:17 ADDCODE[6:0]: Address match code (Slave mode)
These bits are updated with the received address when an address match event occurs
(ADDR = 1).
In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2
MSBs of the address.
Bit 16 DIR: Transfer direction (Slave mode)
This flag is updated when an address match event occurs (ADDR=1).
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode.
Bit 15 BUSY: Bus busy
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected. It is cleared by hardware when a STOP condition is
detected, or when PE=0.
Bit 14 Reserved, must be kept at reset value.
Bit 13 ALERT: SMBus alert
This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1
and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by
setting the ALERTCF bit.
Note: This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 12 TIMEOUT: Timeout or tLOW detection flag
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
Note: This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.

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Bit 11 PECERR: PEC Error in reception

This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
Note: This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 10 OVR: Overrun/Underrun (slave mode)
This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun
error occurs. It is cleared by software by setting the OVRCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 9 ARLO: Arbitration lost
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the
ARLOCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 8 BERR: Bus error
This flag is set by hardware when a misplaced Start or STOP condition is detected whereas
the peripheral is involved in the transfer. The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 7 TCR: Transfer Complete Reload
This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is
cleared by software when NBYTES is written to a non-zero value.
Note: This bit is cleared by hardware when PE=0.
This flag is only for master mode, or for slave mode when the SBC bit is set.
Bit 6 TC: Transfer Complete (master mode)
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been
transferred. It is cleared by software when START bit or STOP bit is set.
Note: This bit is cleared by hardware when PE=0.
Bit 5 STOPF: Stop detection flag
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer:
– either as a master, provided that the STOP condition is generated by the peripheral.
– or as a slave, provided that the peripheral has been addressed previously during
this transfer.
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 4 NACKF: Not Acknowledge received flag
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 3 ADDR: Address matched (slave mode)
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
Note: This bit is cleared by hardware when PE=0.

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Bit 2 RXNE: Receive data register not empty (receivers)

This bit is set by hardware when the received data is copied into the I2C_RXDR register, and
is ready to be read. It is cleared when I2C_RXDR is read.
Note: This bit is cleared by hardware when PE=0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
Note: This bit is cleared by hardware when PE=0.
Bit 0 TXE: Transmit data register empty (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software in order to flush the transmit data register
I2C_TXDR.
Note: This bit is set by hardware when PE=0.

25.7.8 I2C interrupt clear register (I2C_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERT TIMOU ARLOC BERRC STOPC NACKC ADDR
Res. Res. PECCF OVRCF Res. Res. Res. Res. Res.
CF TCF F F F F CF

w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ALERTCF: Alert flag clear
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 12 TIMOUTCF: Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.
Bit 11 PECCF: PEC Error flag clear
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 25.3: I2C implementation.

770/989 RM0454 Rev 5

RM0454 Inter-integrated circuit (I2C) interface

Bit 10 OVRCF: Overrun/Underrun flag clear

Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Bit 9 ARLOCF: Arbitration lost flag clear
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Bit 8 BERRCF: Bus error flag clear
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Bit 4 NACKCF: Not Acknowledge flag clear
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Bit 3 ADDRCF: Address matched flag clear
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
Bits 2:0 Reserved, must be kept at reset value.

25.7.9 I2C PEC register (I2C_PECR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PEC[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0] Packet error checking register
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE=0.

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 25.3: I2C implementation.

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25.7.10 I2C receive data register (I2C_RXDR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. RXDATA[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 RXDATA[7:0] 8-bit receive data
Data byte received from the I2C bus

25.7.11 I2C transmit data register (I2C_TXDR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TXDATA[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 TXDATA[7:0] 8-bit transmit data
Data byte to be transmitted to the I2C bus
Note: These bits can be written only when TXE=1.

772/989 RM0454 Rev 5

 0x8
0x4
0x0

0xC

0x24
0x20
0x18
0x14
0x10

0x1C
Offset
RM0454

25.7.12

I2C_
I2C_
name

I2C_ISR

I2C_ICR
I2C_CR2
I2C_CR1

TIMINGR

I2C_PECR
I2C_OAR2
I2C_OAR1

I2C_RXDR
Register

TIMEOUTR

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0
0
Res. Res. Res. Res. TEXTEN Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
PRESC[3:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
I2C register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res. Res. PECBYTE Res. 26

0
0
Res. Res. Res. Res. Res. Res. Res. AUTOEND Res. 25

0
0
Res. Res. Res. Res. Res. Res. Res. RELOAD Res. 24

0
0
0
0
0

Res. Res. Res. Res. Res. PECEN 23

0
0
0
0
0

Res. Res. Res. Res. Res. ALERTEN 22

[3:0]

0
0
0
0
0

Res. Res. Res. Res. Res. SMBDEN 21

SCLDEL

0
0
0
0
0

Res. Res. Res. Res. Res. SMBHEN 20

TIMEOUTB[11:0]

0
0
0
0
0

Res. Res. Res. Res. Res. GCEN 19

ADDCODE[6:0]

0
0
0
0
0

NBYTES[7:0]

Res. Res. Res. Res. Res. WUPEN 18

RM0454 Rev 5
[3:0]

0
0
0
0
0

Res. Res. Res. Res. Res. NOSTRETCH 17

SDADEL

0
0
0
0
0

Res. Res. Res. DIR Res. Res. SBC 16

0
0

0
0
0
0
0

Res. Res. Res. BUSY TIMOUTEN OA2EN OA1EN NACK RXDMAEN 15

0
0
0

Res. Res. Res. Res. Res. Res. Res. STOP TXDMAEN 14

0
0
0

0
Res. Res. ALERTCF ALERT Res. Res. Res. START Res. 13

0
0
0
0
0

0
Res. Res. TIMOUTCF TIMEOUT TIDLE Res. Res. HEAD10R ANFOFF 12

0
0
0
0
0

0
Res. Res. PECCF PECERR Res. Res. ADD10 11
Table 119. I2C register map and reset values

SCLH[7:0]

0
0
0
0
0
0
0

0
The table below provides the I2C register map and reset values.

Res. Res. OVRCF OVR OA1MODE RD_WRN 10

0
0
0
0
0
0
0

0
Res. Res. ARLOCF ARLO 9
DNF[3:0]

K [2:0]
OA2MS

0
0
0
0
0
0
0

0
Res. Res. BERRCF BERR 8

0
0
0
0
0
0
0

0
0
Res. TCR ERRIE 7

0
0
0
0
0
0
0

0
0
Res. TC TCIE 6

0
0
0
0
0
0
0

0
0
0
STOPCF STOPF STOPIE 5

0
0
0
0
0
0
0

0
0
0
NACKCF NACKF NACKIE 4
OA1[9:0]

TIMEOUTA[11:0]
SADD[9:0]

OA2[7:1]

0
0
0
0
0
0
0

0
0
0
ADDRCF ADDR ADDRIE 3

PEC[7:0]
SCLL[7:0]

0
0
0
0
0
0
0

0
0

RXDATA[7:0]
Res. RXNE RXIE 2

0
0
0
0
0
0
0

0
0
Res. TXIS TXIE 1

1
0
0
0
0
0

0
0
0

773/989
Inter-integrated circuit (I2C) interface

Res. TXE Res. PE

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Inter-integrated circuit (I2C) interface RM0454

Table 119. I2C register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C_TXDR TXDATA[7:0]
0x28

Reset value 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

774/989 RM0454 Rev 5

RM0454 Universal synchonous receiver transmitter (USART)

26 Universal synchonous receiver transmitter (USART)

This section describes the universal synchronous asynchronous receiver transmitter

(USART).

26.1 USART introduction

The USART offers a flexible means to perform Full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and Half-duplex Single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and Modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications are possible by using the DMA (direct memory access)
for multibuffer configuration.

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26.2 USART main features

• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous master/slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
• Wakeup from Stop mode

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RM0454 Universal synchonous receiver transmitter (USART)

26.3 USART extended features

• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
• Smartcard mode
– Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition

26.4 USART implementation

The table below describes USART implementation on STM32G0x0 devices..

Table 120. STM32G0x0 features

STM32G030xx
USART instances STM32G070xx STM32G0B0xx
STM32G050xx

USART1 FULL FULL FULL

USART2 BASIC FULL FULL
USART3 - BASIC FULL
USART4 - BASIC BASIC
USART5 - - BASIC
USART6 - - BASIC

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Table 121. USART features

Low-power
USART modes/features(1) Full feature set Basic feature set
feature set

Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (Master/Slave) X X -
Smartcard mode X - -
Single-wire Half-duplex communication X X X
IrDA SIR ENDEC block X - -
LIN mode X - -
Dual clock domain and wakeup from low-power mode X - X
Receiver timeout interrupt X - -
Modbus communication X - -
Auto baud rate detection X - -
Driver Enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X - X
Tx/Rx FIFO size 8 - 8
Prescaler X - X
1. X = supported.

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RM0454 Universal synchonous receiver transmitter (USART)

26.5 USART functional description

26.5.1 USART block diagram

Figure 261. USART block diagram

USART
usart_ker_ck clock domain
usart_wkup
IRQ Interface
usart_it usart_pclk
usart_tx_dma clock domain
DMA Interface
usart_rx_dma
COM Controller
CK
USART_CR1
USART_ISR
USART_CR2 CTS/NSS
Hardware
USART_CR3 flow control
RTS/DE
USART_RQR
32-bit APB bus

USART_ICR TX Shift Reg

... TX

TxFIFO
USART_TDR

RX Shift Reg RX
...
RxFIFO

USART_RDR
USART_
RTOR Baudrate
USART_GTPR generator &
USART_BRR orversampling
usart_pclk
USART_ usart_ker_ck_pres
usart_ker_ck PRESC

MSv40854V3

The simplified block diagram given in Figure 261 shows two fully-independent clock
domains:
• The usart_pclk clock domain
The usart_pclk clock signal feeds the peripheral bus interface. It must be active when
accesses to the USART registers are required.
• The usart_ker_ck kernel clock domain.
The usart_ker_ck is the USART clock source. It is independent from usart_pclk and
delivered by the RCC. The USART registers can consequently be written/read even
when the usart_ker_ck clock is stopped.
When the dual clock domain feature is disabled, the usart_ker_ck clock is the same as
the usart_pclk clock.
There is no constraint between usart_pclk and usart_ker_ck: usart_ker_ck can be faster
or slower than usart_pclk. The only limitation is the software ability to manage the
communication fast enough.
When the USART operates in SPI slave mode, it handles data flow using the serial interface
clock derived from the external SCLK signal provided by the external master SPI device.
The usart_ker_ck clock must be at least 3 times faster than the clock on the CK input.

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26.5.2 USART signals

USART bidirectional communications
USART bidirectional communications require a minimum of two pins: Receive Data In (RX)
and Transmit Data Out (TX):
• RX (Receive Data Input)
RX is the serial data input. Oversampling techniques are used for data recovery. They
discriminate between valid incoming data and noise.
• TX (Transmit Data Output)
When the transmitter is disabled, the output pin returns to its I/O port configuration.
When the transmitter is enabled and no data needs to be transmitted, the TX pin is
High. In Single-wire and Smartcard modes, this I/O is used to transmit and receive
data.

RS232 Hardware flow control mode

The following pins are required in RS232 Hardware flow control mode:
• CTS (Clear To Send)
When driven high, this signal blocks the data transmission at the end of the current
transfer.
• RTS (Request To Send)
When it is low, this signal indicates that the USART is ready to receive data.

RS485 Hardware control mode

The following pin is required in RS485 Hardware control mode:
• DE (Driver Enable)
This signal activates the transmission mode of the external transceiver.
Note: DE and RTS share the same pin.

Synchronous master/slave mode and Smartcard mode

The following pin is required in synchronous master/slave mode and Smartcard mode:
• CK
This pin acts as Clock output in Synchronous master and Smartcard modes.
It acts as Clock input is Synchronous slave mode.
In Synchronous Master mode, this pin outputs the transmitter data clock for
synchronous transmission corresponding to SPI master mode (no clock pulses on start
bit and stop bit, and a software option to send a clock pulse on the last data bit). In
parallel, data can be received synchronously on RX pin. This mechanism can be used
to control peripherals featuring shift registers (e.g. LCD drivers). The clock phase and
polarity are software programmable.
In Smartcard mode, CK output provides the clock to the smartcard.
• NSS
This pin acts as Slave Select input in Synchronous slave mode.
Note: NSS and CTS share the same pin.

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RM0454 Universal synchonous receiver transmitter (USART)

26.5.3 USART character description

The word length can be set to 7, 8 or 9 bits, by programming the M bits (M0: bit 12 and M1:
bit 28) in the USART_CR1 register (see Figure 262):
• 7-bit character length: M[1:0] = ‘10’
• 8-bit character length: M[1:0] = ‘00’
• 9-bit character length: M[1:0] = ‘01’
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F
and 0x55 frames detection) are not supported.
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.
An Idle character is interpreted as an entire frame of “1”s (the number of “1”s includes the
number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator. The transmission
and reception clock are generated when the enable bit is set for the transmitter and receiver,
respectively.
A detailed description of each block is given below.

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Figure 262. Word length programming

9-bit word length (M = 01 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

8-bit word length (M = 00 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

7-bit word length (M = 10 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

** LBCL bit controls last data clock pulse

MS33194V2

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RM0454 Universal synchonous receiver transmitter (USART)

26.5.4 USART FIFOs and thresholds

The USART can operate in FIFO mode.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The
FIFO mode is enabled by setting FIFOEN in USART_CR1 register (bit 29). This mode is
supported only in UART, SPI and Smartcard modes.
Since the maximum data word length is 9 bits, the TXFIFO is 9-bit wide. However the
RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store
the data in the FIFO, but also the error flags associated to each character (Parity error,
Noise error and Framing error flags).
Note: The received data is stored in the RXFIFO together with the corresponding flags. However,
only the data are read when reading the RDR.
The status flags are available in the USART_ISR register.
It is possible to configure the TXFIFO and RXFIFO levels at which the Tx and RX interrupts
are triggered. These thresholds are programmed through RXFTCFG and TXFTCFG
bitfields in USART_CR3 control register.
In this case:
• The RXFT flag is set in the USART_ISR register and the corresponding interrupt (if
enabled) is generated, when the number of received data in the RXFIFO reaches the
threshold programmed in the RXFTCFG bits fields.
This means that the RXFIFO is filled until the number of data in the RXFIFO is equal to
the programmed threshold.
RXFTCFG data have been received: one data in USART_RDR and (RXFTCFG - 1)
data in the RXFIFO. As an example, when the RXFTCFG is programmed to ‘101’, the
RXFT flag is set when a number of data corresponding to the FIFO size has been
received (FIFO size -1 data in the RXFIFO and 1 data in the USART_RDR). As a
result, the next received data is not set the overrun flag.
• The TXFT flag is set in the USART_ISR register and the corresponding interrupt (if
enabled) is generated when the number of empty locations in the TXFIFO reaches the
threshold programmed in the TXFTCFG bits fields.
This means that the TXFIFO is emptied until the number of empty locations in the
TXFIFO is equal to the programmed threshold.

26.5.5 USART transmitter

The transmitter can send data words of either 7 or 8 or 9 bits, depending on the M bit status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin while the corresponding clock
pulses are output on the SCLK pin.

Character transmission
During an USART transmission, data shifts out the least significant bit first (default
configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register.
When FIFO mode is enabled, the data written to the transmit data register (USART_TDR)
are queued in the TXFIFO.

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Every character is preceded by a start bit which corresponds to a low logic level for one bit
period. The character is terminated by a configurable number of stop bits.
The number of stop bits can be configured to 0.5, 1, 1.5 or 2.
Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during data transmission. Resetting the TE bit during the
transmission corrupts the data on the TX pin as the baud rate counters get frozen. The
current data being transmitted are then lost.
An idle frame is sent when the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
USART_CR2, bits 13,12.
• 1 stop bit: This is the default value of number of stop bits.
• 2 stop bits: This is supported by normal USART, Single-wire and Modem modes.
• 1.5 stop bits: To be used in Smartcard mode.
An idle frame transmission includes the stop bits.
A break transmission features 10 low bits (when M[1:0] = ‘00’) or 11 low bits (when
M[1:0] = ‘01’) or 9 low bits (when M[1:0] = ‘10’) followed by 2 stop bits (see Figure 263). It is
not possible to transmit long breaks (break of length greater than 9/10/11 low bits).

Figure 263. Configurable stop bits

8-bit data, 1 Stop bit

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop
bit
bit
CLOCK **

** LBCL bit controls last data clock pulse

8-bit data, 1 1/2 Stop bits
Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 1.5
bit
Stop
bits

8-bit data, 2 Stop bits

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 2
bit
Stop
bits
MSv31887V1

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Character transmission procedure

To transmit a character, follow the sequence below:
1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the USART_BRR register.
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAT) in USART_CR3 if multibuffer communication must take
place. Configure the DMA register as explained in Section 26.5.10: USART
multiprocessor communication.
6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USART_TDR register. Repeat this for each data to be
transmitted in case of single buffer.
– When FIFO mode is disabled, writing a data to the USART_TDR clears the TXE
flag.
– When FIFO mode is enabled, writing a data to the USART_TDR adds one data to
the TXFIFO. Write operations to the USART_TDR are performed when TXFNF
flag is set. This flag remains set until the TXFIFO is full.
8. When the last data is written to the USART_TDR register, wait until TC = 1.
– When FIFO mode is disabled, this indicates that the transmission of the last frame
is complete.
– When FIFO mode is enabled, this indicates that both TXFIFO and shift register are
empty.
This check is required to avoid corrupting the last transmission when the USART is
disabled or enters Halt mode.

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Single byte communication

• When FIFO mode is disabled
Writing to the transmit data register always clears the TXE bit. The TXE flag is set by
hardware. It indicates that:
– the data have been moved from the USART_TDR register to the shift register and
the data transmission has started;
– the USART_TDR register is empty;
– the next data can be written to the USART_TDR register without overwriting the
previous data.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is ongoing, a write instruction to the USART_TDR register stores
the data in the TDR buffer. It is then copied in the shift register at the end of the current
transmission.
When no transmission is ongoing, a write instruction to the USART_TDR register
places the data in the shift register, the data transmission starts, and the TXE bit is set.
• When FIFO mode is enabled, the TXFNF (TXFIFO not full) flag is set by hardware to
indicate that:
– the TXFIFO is not full;
– the USART_TDR register is empty;
– the next data can be written to the USART_TDR register without overwriting the
previous data. When a transmission is ongoing, a write operation to the
USART_TDR register stores the data in the TXFIFO. Data are copied from the
TXFIFO to the shift register at the end of the current transmission.
When the TXFIFO is not full, the TXFNF flag stays at ‘1’ even after a write operation to
USART_TDR register. It is cleared when the TXFIFO is full. This flag generates an
interrupt if the TXFNFIE bit is set.
Alternatively, interrupts can be generated and data can be written to the FIFO when the
TXFIFO threshold is reached. In this case, the CPU can write a block of data defined by
the programmed trigger level.
If a frame is transmitted (after the stop bit) and the TXE flag (TXFE in case of FIFO
mode) is set, the TC flag goes high. An interrupt is generated if the TCIE bit is set in the
USART_CR1 register.
After writing the last data to the USART_TDR register, it is mandatory to wait until TC is set
before disabling the USART or causing the device to enter the low-power mode (see
Figure 264: TC/TXE behavior when transmitting).

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Figure 264. TC/TXE behavior when transmitting

Note: When FIFO management is enabled, the TXFNF flag is used for data transmission.

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bit (see Figure 262).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (stop) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
When the SBKRQ bit is set, the break character is sent at the end of the current
transmission.
When FIFO mode is enabled, sending the break character has priority on sending data even
if the TXFIFO is full.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

26.5.6 USART receiver

The USART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the
USART_CR1 register.

Start bit detection

The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.

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Figure 265. Start bit detection when oversampling by 16 or 8

RX state
Idle Start bit

RX line

Ideal
sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
clock
Sampled values

Real
sample X X X X X X X X 9 10 11 12 13 14 15 16
clock
6/16

7/16 7/16

One-bit time

Conditions
to validate 1 1 1 0 X 0 X 0 X 0 0 0 0 X X X X X X
the start bit
Falling edge At least 2 bits At least 2 bits
detection out of 3 at 0 out of 3 at 0
ai15471b

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set and interrupt generated if RXNEIE = 1, or RXFNE
flag set and interrupt generated if RXFNEIE = 1 if FIFO mode enabled) if the 3 sampled bits
are at ‘0’ (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at ‘0’ and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at ‘0’).
The start bit is validated but the NE noise flag is set if,
a) for both samplings, 2 out of the 3 sampled bits are at ‘0’ (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)
or
b) for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at ‘0’.
If neither of the above conditions are met, the start detection aborts and the receiver returns
to the idle state (no flag is set).

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Character reception
During an USART reception, data are shifted out least significant bit first (default
configuration) through the RX pin.
Character reception procedure
To receive a character, follow the sequence below:
1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register USART_BRR
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to ‘1’.
5. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in Section 26.5.10: USART
multiprocessor communication.
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received:
• When FIFO mode is disabled, the RXNE bit is set to indicate that the content of the
shift register is transferred to the RDR. In other words, data have been received and
can be read (as well as their associated error flags).
• When FIFO mode is enabled, the RXFNE bit is set to indicate that the RXFIFO is not
empty. Reading the USART_RDR returns the oldest data entered in the RXFIFO.
When a data is received, it is stored in the RXFIFO together with the corresponding
error bits.
• An interrupt is generated if the RXNEIE (RXFNEIE when FIFO mode is enabled) bit is
set.
• The error flags can be set if a frame error, noise, parity or an overrun error was
detected during reception.
• In multibuffer communication mode:
– When FIFO mode is disabled, the RXNE flag is set after every byte reception. It is
cleared when the DMA reads the Receive data Register.
– When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not
empty. After every DMA request, a data is retrieved from the RXFIFO. A DMA
request is triggered when the RXFIFO is not empty i.e. when there are data to be
read from the RXFIFO.
• In single buffer mode:
– When FIFO mode is disabled, clearing the RXNE flag is done by performing a
software read from the USART_RDR register. The RXNE flag can also be cleared
by programming RXFRQ bit to ‘1’ in the USART_RQR register. The RXNE flag
must be cleared before the end of the reception of the next character to avoid an
overrun error.
– When FIFO mode is enabled, the RXFNE is set when the RXFIFO is not empty.
After every read operation from USART_RDR, a data is retrieved from the
RXFIFO. When the RXFIFO is empty, the RXFNE flag is cleared. The RXFNE flag
can also be cleared by programming RXFRQ bit to ‘1’ in USART_RQR. When the
RXFIFO is full, the first entry in the RXFIFO must be read before the end of the
reception of the next character, to avoid an overrun error. The RXFNE flag
generates an interrupt if the RXFNEIE bit is set. Alternatively, interrupts can be

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generated and data can be read from RXFIFO when the RXFIFO threshold is
reached. In this case, the CPU can read a block of data defined by the
programmed threshold.

Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, it is handled in the same way as a data character reception
except that an interrupt is generated if the IDLEIE bit is set.

Overrun error
• FIFO mode disabled
An overrun error occurs if a character is received and RXNE has not been reset.
Data can not be transferred from the shift register to the RDR register until the RXNE
bit is cleared. The RXN E flag is set after every byte reception.
An overrun error occurs if RXNE flag is set when the next data is received or the
previous DMA request has not been serviced. When an overrun error occurs:
– the ORE bit is set;
– the RDR content is not lost. The previous data is available by reading the
USART_RDR register.
– the shift register is overwritten. After that, any data received during overrun is lost.
– an interrupt is generated if either the RXNEIE or the EIE bit is set.
• FIFO mode enabled
An overrun error occurs when the shift register is ready to be transferred and the
receive FIFO is full.
Data can not be transferred from the shift register to the USART_RDR register until
there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is
not empty.
An overrun error occurs if the RXFIFO is full and the shift register is ready to be
transferred. When an overrun error occurs:
– The ORE bit is set.
– The first entry in the RXFIFO is not lost. It is available by reading the
USART_RDR register.
– The shift register is overwritten. After that point, any data received during overrun
is lost.
– An interrupt is generated if either the RXFNEIE or EIE bit is set.
The ORE bit is reset by setting the ORECF bit in the USART_ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost.
When the FIFO mode is disabled, there are two possibilities
• if RXNE = 1, then the last valid data is stored in the receive register (RDR) and can be
read,
• if RXNE = 0, the last valid data has already been read and there is nothing left to be
read in the RDR register. This case can occur when the last valid data is read in the
RDR register at the same time as the new (and lost) data is received.

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Selecting the clock source and the appropriate oversampling method

The choice of the clock source is done through the Clock Control system (see Section Reset
and clock control (RCC)). The clock source must be selected through the UE bit before
enabling the USART.
The clock source must be selected according to two criteria:
• Possible use of the USART in low-power mode
• Communication speed.
The clock source frequency is usart_ker_ck.
When the dual clock domain and the wakeup from low-power mode features are supported,
the usart_ker_ck clock source can be configurable in the RCC (see Section Reset and clock
control (RCC)). Otherwise the usart_ker_ck clock is the same as usart_pclk.
The usart_ker_ck clock can be divided by a programmable factor, defined in the
USART_PRESC register.

Figure 266. usart_ker_ck clock divider block diagram

usart_ker_ck_pres
USARTx_BRR register
usart_ker_ck USARTx_PRESC[3:0] and oversampling

MSv40855V1

Some usart_ker_ck sources enable the USART to receive data while the MCU is in low-
power mode. Depending on the received data and wakeup mode selected, the USART
wakes up the MCU, when needed, in order to transfer the received data, by performing a
software read to the USART_RDR register or by DMA.
For the other clock sources, the system must be active to enable USART communications.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise. This enables obtaining the best a trade-off between the maximum communication
speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register either to 16 or 8 times the baud rate clock (see Figure 267 and
Figure 268).
Depending on your application:
• select oversampling by 8 (OVER8 = 1) to achieve higher speed (up to
usart_ker_ck_pres/8). In this case the maximum receiver tolerance to clock deviation is
reduced (refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on
page 795)
• select oversampling by 16 (OVER8 = 0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum

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usart_ker_ck_pres/16 (where usart_ker_ck_pres is the USART input clock divided by a

prescaler).
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. Two options are available:
• The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NE bit is set.
• A single sample in the center of the received bit
Depending on your application:
– select the three sample majority vote method (ONEBIT = 0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 122) because this indicates that a glitch occurred during the sampling.
– select the single sample method (ONEBIT = 1) when the line is noise-free to
increase the receiver tolerance to clock deviations (see Section 26.5.8: Tolerance
of the USART receiver to clock deviation on page 795). In this case the NE bit is
never set.
When noise is detected in a frame:
• The NE bit is set at the rising edge of the RXNE bit (RXFNE in case of FIFO mode
enabled).
• The invalid data is transferred from the Shift register to the USART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit (RXFNE in case of FIFO mode enabled) which itself
generates an interrupt. In case of multibuffer communication an interrupt is issued if the
EIE bit is set in the USART_CR3 register.
The NE bit is reset by setting NECF bit in USART_ICR register.
Note: Noise error is not supported in SPI mode.
Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes,
the OVER8 bit is forced to ‘0 ’ by hardware.

Figure 267. Data sampling when oversampling by 16

RX line

sampled values
Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16
7/16 7/16
One bit time

MSv31152V1

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Figure 268. Data sampling when oversampling by 8

RX line

sampled values
Sample
clock (x8) 1 2 3 4 5 6 7 8

2/8
3/8 3/8
One bit time

MSv31153V1

Table 122. Noise detection from sampled data

Sampled value NE status Received bit value

000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 1 1
110 1 1
111 0 1

Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
• the FE bit is set by hardware;
• the invalid data is transferred from the Shift register to the USART_RDR register
(RXFIFO in case FIFO mode is enabled).
• no interrupt is generated in case of single byte communication. However this bit rises at
the same time as the RXNE bit (RXFNE in case FIFO mode is enabled) which itself
generates an interrupt. In case of multibuffer communication an interrupt is issued if the
EIE bit is set in the USART_CR3 register.
The FE bit is reset by writing ‘1’ to the FECF in the USART_ICR register.
Note: Framing error is not supported in SPI mode.

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Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of
USART_CR: it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
• 0.5 stop bit (reception in Smartcard mode): no sampling is done for 0.5 stop bit. As a
consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
• 1 stop bit: sampling for 1 stop bit is done on the 8th, 9th and 10th samples.
• 1.5 stop bits (Smartcard mode)
When transmitting in Smartcard mode, the device must check that the data are
correctly sent. The receiver block must consequently be enabled (RE = 1 in
USART_CR1) and the stop bit is checked to test if the Smartcard has detected a parity
error.
In the event of a parity error, the Smartcard forces the data signal low during the
sampling (NACK signal), which is flagged as a framing error. The FE flag is then set
through RXNE flag (RXFNE if the FIFO mode is enabled) at the end of the 1.5 stop bit.
Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock
period after the beginning of the stop bit). The 1.5 stop bit can be broken into 2 parts:
one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit
period during which sampling occurs halfway through (refer to Section 26.5.16: USART
receiver timeout on page 809 for more details).
• 2 stop bits
Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit.
The framing error flag is set if a framing error is detected during the first stop bit.
The second stop bit is not checked for framing error. The RXNE flag (RXFNE if the
FIFO mode is enabled) is set at the end of the first stop bit.

26.5.7 USART baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the value
programmed in the USART_BRR register.
Equation 1: baud rate for standard USART (SPI mode included) (OVER8 = ‘0’ or ‘1’)
In case of oversampling by 16, the baud rate is given by the following formula:

Tx/Rx baud = usart_ker_ckpres

-----------------------------------------------
USARTDIV

In case of oversampling by 8, the baud rate is given by the following formula:

× usart_ker_ckpres-
Tx/Rx baud = 2
--------------------------------------------------------
USARTDIV

Equation 2: baud rate in Smartcard, LIN and IrDA modes (OVER8 = 0)

The baud rate is given by the following formula:

Tx/Rx baud = usart_ker_ckpres

-----------------------------------------------
USARTDIV

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USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
• When OVER8 = 0, BRR = USARTDIV.
• When OVER8 = 1
– BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
– BRR[3] must be kept cleared.
– BRR[15:4] = USARTDIV[15:4]
Note: The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
In case of oversampling by 16 and 8, USARTDIV must be greater than or equal to 16.

How to derive USARTDIV from USART_BRR register values

Example 1
To obtain 9600 baud with usart_ker_ck_pres = 8 MHz:
• In case of oversampling by 16:
USARTDIV = 8 000 000/9600
BRR = USARTDIV = 0d833 = 0x0341
• In case of oversampling by 8:
USARTDIV = 2 * 8 000 000/9600
USARTDIV = 1666,66 (0d1667 = 0x683)
BRR[3:0] = 0x3 >> 1 = 0x1
BRR = 0x681
Example 2
To obtain 921.6 Kbaud with usart_ker_ck_pres = 48 MHz:
• In case of oversampling by 16:
USARTDIV = 48 000 000/921 600
BRR = USARTDIV = 0d52 = 0x34
• In case of oversampling by 8:
USARTDIV = 2 * 48 000 000/921 600
USARTDIV = 104 (0d104 = 0x68)
BRR[3:0] = USARTDIV[3:0] >> 1 = 0x8 >> 1 = 0x4
BRR = 0x64

26.5.8 Tolerance of the USART receiver to clock deviation

The USART asynchronous receiver operates correctly only if the total clock system
deviation is less than the tolerance of the USART receiver.

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The causes which contribute to the total deviation are:

• DTRA: deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: error due to the baud rate quantization of the receiver
• DREC: deviation of the receiver local oscillator
• DTCL: deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)

DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance

where
DWU is the error due to sampling point deviation when the wakeup from low-
power mode is used.
when M[1:0] = 01:
t WUUSART
DWU = --------------------------
-
11 × Tbit

when M[1:0] = 00:

t WUUSART
DWU = --------------------------
-
10 × Tbit

when M[1:0] = 10:

t WUUSART
DWU = --------------------------
-
9 × Tbit

tWUUSART is the time between the detection of the start bit falling edge and the
instant when the clock (requested by the peripheral) is ready and reaching the
peripheral, and the regulator is ready.
The USART receiver can receive data correctly at up to the maximum tolerated deviation
specified in Table 123, Table 124, depending on the following settings:
• 9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register
• Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
• Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
• Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.

Table 123. Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8 bit = 0 OVER8 bit = 1
M bits
ONEBIT = 0 ONEBIT = 1 ONEBIT = 0 ONEBIT = 1

00 3.75% 4.375% 2.50% 3.75%

01 3.41% 3.97% 2.27% 3.41%
10 4.16% 4.86% 2.77% 4.16%

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Table 124. Tolerance of the USART receiver when BRR[3:0] is different from 0000
OVER8 bit = 0 OVER8 bit = 1
M bits
ONEBIT = 0 ONEBIT = 1 ONEBIT = 0 ONEBIT = 1

00 3.33% 3.88% 2% 3%
01 3.03% 3.53% 1.82% 2.73%
10 3.7% 4.31% 2.22% 3.33%

Note: The data specified in Table 123 and Table 124 may slightly differ in the special case when
the received frames contain some Idle frames of exactly 10-bit times when M bits = 00 (11-
bit times when M = 01 or 9- bit times when M = 10).

26.5.9 USART Auto baud rate detection

The USART can detect and automatically set the USART_BRR register value based on the
reception of one character. Automatic baud rate detection is useful under two
circumstances:
• The communication speed of the system is not known in advance.
• The system is using a relatively low accuracy clock source and this mechanism
enables the correct baud rate to be obtained without measuring the clock deviation.
The clock source frequency must be compatible with the expected communication speed.
• When oversampling by 16, the baud rate ranges from usart_ker_ck_pres/65535 and
usart_ker_ck_pres/16.
• When oversampling by 8, the baud rate ranges from usart_ker_ck_pres/65535 and
usart_ker_ck_pres/8.
Before activating the auto baud rate detection, the auto baud rate detection mode must be
selected through the ABRMOD[1:0] field in the USART_CR2 register. There are four modes
based on different character patterns. In these auto baud rate modes, the baud rate is
measured several times during the synchronization data reception and each measurement
is compared to the previous one.

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These modes are the following:

• Mode 0: Any character starting with a bit at ‘1’.
In this case the USART measures the duration of the start bit (falling edge to rising
edge).
• Mode 1: Any character starting with a 10xx bit pattern.
In this case, the USART measures the duration of the Start and of the 1st data bit. The
measurement is done falling edge to falling edge, to ensure a better accuracy in the
case of slow signal slopes.
• Mode 2: A 0x7F character frame (it may be a 0x7F character in LSB first mode or a
0xFE in MSB first mode).
In this case, the baud rate is updated first at the end of the start bit (BRs), then at the
end of bit 6 (based on the measurement done from falling edge to falling edge: BR6).
Bit0 to bit6 are sampled at BRs while further bits of the character are sampled at BR6.
• Mode 3: A 0x55 character frame.
In this case, the baud rate is updated first at the end of the start bit (BRs), then at the
end of bit0 (based on the measurement done from falling edge to falling edge: BR0),
and finally at the end of bit6 (BR6). Bit 0 is sampled at BRs, bit 1 to bit 6 are sampled at
BR0, and further bits of the character are sampled at BR6. In parallel, another check is
performed for each intermediate RX line transition. An error is generated if the
transitions on RX are not sufficiently synchronized with the receiver (the receiver being
based on the baud rate calculated on bit 0).
Prior to activating the auto baud rate detection, the USART_BRR register must be initialized
by writing a non-zero baud rate value.
The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2
register. The USART then waits for the first character on the RX line. The auto baud rate
operation completion is indicated by the setting of the ABRF flag in the USART_ISR
register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this
case the BRR value may be corrupted and the ABRE error flag is set. This also happens if
the communication speed is not compatible with the automatic baud rate detection range
(bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between
8 and 65536 clock periods (oversampling by 8)).
The auto baud rate detection can be re-launched later by resetting the ABRF flag (by writing
a ‘0’).
When FIFO management is disabled and an auto baud rate error occurs, the ABRE flag is
set through RXNE and FE bits.
When FIFO management is enabled and an auto baud rate error occurs, the ABRE flag is
set through RXFNE and FE bits.
If the FIFO mode is enabled, the auto baud rate detection should be made using the data on
the first RXFIFO location. So, prior to launching the auto baud rate detection, make sure
that the RXFIFO is empty by checking the RXFNE flag in USART_ISR register.
Note: The BRR value might be corrupted if the USART is disabled (UE = 0) during an auto baud
rate operation.

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26.5.10 USART multiprocessor communication

It is possible to perform USART multiprocessor communications (with several USARTs
connected in a network). For instance one of the USARTs can be the master with its TX
output connected to the RX inputs of the other USARTs, while the others are slaves with
their respective TX outputs logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations, it is often desirable that only the intended message
recipient actively receives the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non-addressed devices can be placed in Mute mode by means of the muting function.
To use the Mute mode feature, the MME bit must be set in the USART_CR1 register.
Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared
and then set again quickly (within two usart_ker_ck cycles), otherwise Mute mode might
remain active.
When the Mute mode is enabled:
• none of the reception status bits can be set;
• all the receive interrupts are inhibited;
• the RWU bit in USART_ISR register is set to ‘1’. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the USART_RQR register, under
certain conditions.
The USART can enter or exit from Mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
• Idle Line detection if the WAKE bit is reset,
• Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE = 0)

The USART enters Mute mode when the MMRQ bit is written to ‘1’ and the RWU is
automatically set.
The USART wakes up when an Idle frame is detected. The RWU bit is then cleared by
hardware but the IDLE bit is not set in the USART_ISR register. An example of Mute mode
behavior using Idle line detection is given in Figure 269.

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Figure 269. Mute mode using Idle line detection

RXNE RXNE

RX Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6

RWU Mute mode Normal mode

MMRQ written to 1 Idle frame detected

MSv31154V1

Note: If the MMRQ is set while the IDLE character has already elapsed, Mute mode is not entered
(RWU is not set).
If the USART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE = 1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’, otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the USART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The USART enters Mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
USART enters Mute mode. When FIFO management is enabled, the software should
ensure that there is at least one empty location in the RXFIFO before entering Mute mode.
The USART also enters Mute mode when the MMRQ bit is written to 1. The RWU bit is also
automatically set in this case.
The USART exits from Mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been
cleared.
Note: When FIFO management is enabled, when MMRQ is set while the receiver is sampling last
bit of a data, this data may be received before effectively entering in Mute mode
An example of Mute mode behavior using address mark detection is given in Figure 270.

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Figure 270. Mute mode using address mark detection

In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RXNE RXNE RXNE

RX IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5

RWU Mute mode Normal mode Mute mode

MMRQ written to 1 Matching address Non-matching address

(RXNE was cleared)

Non-matching address
MSv31155V1

26.5.11 USART Modbus communication

The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII
protocols. Modbus/RTU is a Half-duplex, block-transfer protocol. The control part of the
protocol (address recognition, block integrity control and command interpretation) must be
implemented in software.
The USART offers basic support for the end of the block detection, without software
overhead or other resources.

Modbus/RTU
In this mode, the end of one block is recognized by a “silence” (idle line) for more than 2
character times. This function is implemented through the programmable timeout function.
The timeout function and interrupt must be activated, through the RTOEN bit in the
USART_CR2 register and the RTOIE in the USART_CR1 register. The value corresponding
to a timeout of 2 character times (for example 22 x bit time) must be programmed in the
RTO register. When the receive line is idle for this duration, after the last stop bit is received,
an interrupt is generated, informing the software that the current block reception is
completed.

Modbus/ASCII
In this mode, the end of a block is recognized by a specific (CR/LF) character sequence.
The USART manages this mechanism using the character match function.
By programming the LF ASCII code in the ADD[7:0] field and by activating the character
match interrupt (CMIE = 1), the software is informed when a LF has been received and can
check the CR/LF in the DMA buffer.

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26.5.12 USART parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bits, the possible USART frame formats are as listed in Table 125.

Table 125. USART frame formats

M bits PCE bit USART frame(1)

00 0 | SB | 8 bit data | STB |

00 1 | SB | 7-bit data | PB | STB |
01 0 | SB | 9-bit data | STB |
01 1 | SB | 8-bit data PB | STB |
10 0 | SB | 7bit data | STB |
10 1 | SB | 6-bit data | PB | STB |
1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB
position (8th or 7th, depending on the M bit value).

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 6, 7 or 8
LSB bits (depending on M bit values) and the parity bit.
As an example, if data = 00110101 and 4 bits are set, the parity bit is equal to 0 if even parity
is selected (PS bit in USART_CR1 = 0).

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7
or 8 LSB bits (depending on M bit values) and the parity bit.
As an example, if data = 00110101 and 4 bits set, then the parity bit is equal to 1 if odd parity
is selected (PS bit in USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the USART_ICR register.

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is selected (PS=1).

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26.5.13 USART LIN (local interconnection network) mode

This section is relevant only when LIN mode is supported. Refer to Section 26.4: USART
implementation on page 777.
The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN
mode, the following bits must be kept cleared:
• CLKEN in the USART_CR2 register,
• STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.

LIN transmission
The procedure described in Section 26.5.4 has to be applied for LIN Master transmission. It
must be the same as for normal USART transmission with the following differences:
• Clear the M bit to configure 8-bit word length.
• Set the LINEN bit to enter LIN mode. In this case, setting the SBKRQ bit sends 13 ‘0
bits as a break character. Then two bits of value ‘1 are sent to enable the next start
detection.

LIN reception
When LIN mode is enabled, the break detection circuit is activated. The detection is totally
independent from the normal USART receiver. A break can be detected whenever it occurs,
during Idle state or during a frame.
When the receiver is enabled (RE = 1 in USART_CR1), the circuit looks at the RX input for
a start signal. The method for detecting start bits is the same when searching break
characters or data. After a start bit has been detected, the circuit samples the next bits
exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in
USART_CR2) or 11 (when LBDL = 1 in USART_CR2) consecutive bits are detected as ‘0,
and are followed by a delimiter character, the LBDF flag is set in USART_ISR. If the LBDIE
bit = 1, an interrupt is generated. Before validating the break, the delimiter is checked for as
it signifies that the RX line has returned to a high level.
If a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the
current detection and searches for a start bit again.
If the LIN mode is disabled (LINEN = 0), the receiver continues working as normal USART,
without taking into account the break detection.
If the LIN mode is enabled (LINEN = 1), as soon as a framing error occurs (i.e. stop bit
detected at ‘0, which is the case for any break frame), the receiver stops until the break
detection circuit receives either a ‘1, if the break word was not complete, or a delimiter
character if a break has been detected.
The behavior of the break detector state machine and the break flag is shown on the
Figure 271: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 804.
Examples of break frames are given on Figure 272: Break detection in LIN mode vs.
Framing error detection on page 805.

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Figure 271. Break detection in LIN mode (11-bit break length - LBDL bit is set)

Case 1: break signal not long enough => break discarded, LBDF is not set

Break frame
RX line

Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 1

Case 2: break signal just long enough => break detected, LBDF is set

Break frame
RX line
Delimiter is immediate
Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 B10 Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 0

LBDF

Case 3: break signal long enough => break detected, LBDF is set

Break frame
RX line

Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 wait delimiter Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 0

LBDF

MSv31156V1

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Figure 272. Break detection in LIN mode vs. Framing error detection

Case 1: break occurring after an Idle

RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header)

1 data time 1 data time

RXNE /FE

LBDF

Case 2: break occurring while data is being received

RX line data 1 data2 BREAK data 2 (0x55) data 3 (header)

1 data time 1 data time

RXNE /FE

LBDF

MSv31157V1

26.5.14 USART synchronous mode

Master mode
The synchronous master mode is selected by programming the CLKEN bit in the
USART_CR2 register to ‘1’. In synchronous mode, the following bits must be kept cleared:
• LINEN bit in the USART_CR2 register,
• SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The SCLK pin is the output of the USART transmitter
clock. No clock pulses are sent to the SCLK pin during start bit and stop bit. Depending on
the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated
during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is
used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to
select the phase of the external clock (see Figure 273, Figure 274 and Figure 275).
During the Idle state, preamble and send break, the external SCLK clock is not activated.
In synchronous master mode, the USART transmitter operates exactly like in asynchronous
mode. However, since SCLK is synchronized with TX (according to CPOL and CPHA), the
data on TX is synchronous.
In synchronous master mode, the USART receiver operates in a different way compared to
asynchronous mode. If RE is set to 1, the data are sampled on SCLK (rising or falling edge,
depending on CPOL and CPHA), without any oversampling. A given setup and a hold time
must be respected (which depends on the baud rate: 1/16 bit time).

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Note: In master mode, the SCLK pin operates in conjunction with the TX pin. Thus, the clock is
provided only if the transmitter is enabled (TE = 1) and data are being transmitted
(USART_TDR data register written). This means that it is not possible to receive
synchronous data without transmitting data.

Figure 273. USART example of synchronous master transmission

RX Data out
TX Data in
Synchronous device
USART
(e.g. slave SPI)

SCLK Clock

MSv31158V1

Figure 274. USART data clock timing diagram in synchronous master mode
(M bits = 00)

Idle or preceding M bits = 00 (8 data bits) Idle or next

transmission Start Stop transmission

Clock (CPOL=0, CPHA=0) *

Clock (CPOL=0, CPHA=1)

*

Clock (CPOL=1, CPHA=0) *

Clock (CPOL=1, CPHA=1) *

Data on TX
0 1 2 3 4 5 6 7
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7
(from slave)
LSB MSB
*
Capture strobe
*LBCL bit controls last data pulse

MSv34709V2

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Figure 275. USART data clock timing diagram in synchronous master mode
(M bits = 01)
Idle or
Idle or next
preceding Start M bits =01 (9 data bits) Stop
transmission
transmission

Clock (CPOL=0,
CPHA=0) *
Clock (CPOL=0,
CPHA=1) *

Clock (CPOL=1, *
CPHA=0)
Clock (CPOL=1, *
CPHA=1)

Data on TX
0 1 2 3 4 5 6 7 8
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7 8
(from slave)
LSB MSB
Capture *
strobe
*LBCL bit controls last data pulse

MSv34710V1

Slave mode
The synchronous slave mode is selected by programming the SLVEN bit in the
USART_CR2 register to ‘1’. In synchronous slave mode, the following bits must be kept
cleared:
• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in slave mode. The SCLK pin is the input of the USART in slave mode.
Note: When the peripheral is used in SPI slave mode, the frequency of peripheral clock source
(usart_ker_ck_pres) must be greater than 3 times the CK input frequency.
The CPOL bit and the CPHA bit in the USART_CR2 register are used to select the clock
polarity and the phase of the external clock, respectively (see Figure 276).
An underrun error flag is available in slave transmission mode. This flag is set when the first
clock pulse for data transmission appears while the software has not yet loaded any value to
USART_TDR.
The slave supports the hardware and software NSS management.

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Figure 276. USART data clock timing diagram in synchronous slave mode
(M bits = 00)
M bits = 00 (8 data bits)

NSS (from Master)

Clock (CPOL=0, CPHA=0)

Clock (CPOL=0, CPHA=1)

Clock (CPOL=1, CPHA=0)

Clock (CPOL=1, CPHA=1)

Data on TX
0 1 2 3 4 5 6 7
(from slave)
LSB MSB
Data on RX
0 1 2 3 4 5 6 7
(from master)
LSB MSB

Capture strobe

MSv45359V1

Slave Select (NSS) pin management

The hardware or software slave select management can be set through the DIS_NSS bit in
the USART_CR2 register:
• Software NSS management (DIS_NSS = 1)
The SPI slave is always selected and NSS input pin is ignored.
The external NSS pin remains free for other application uses.
• Hardware NSS management (DIS_NSS = 0)
The SPI slave selection depends on NSS input pin. The slave is selected when NSS is
low and deselected when NSS is high.
Note: The LBCL (used only on SPI master mode), CPOL and CPHA bits have to be selected when
the USART is disabled (UE = 0) to ensure that the clock pulses function correctly.
In SPI slave mode, the USART must be enabled before starting the master communications
(or between frames while the clock is stable). Otherwise, if the USART slave is enabled
while the master is in the middle of a frame, it becomes desynchronized with the master.
The data register of the slave needs to be ready before the first edge of the communication
clock or before the end of the ongoing communication, otherwise the SPI slave transmits
zeros.
SPI Slave underrun error
When an underrun error occurs, the UDR flag is set in the USART_ISR register, and the SPI
slave goes on sending the last data until the underrrun error flag is cleared by software.
The underrun flag is set at the beginning of the frame. An underrun error interrupt is
triggered if EIE bit is set in the USART_CR3 register.
The underrun error flag is cleared by setting bit UDRCF in the USART_ICR register.

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In case of underrun error, it is still possible to write to the TDR register. Clearing the
underrun error enables sending new data.
If an underrun error occurred and there is no new data written in TDR, then the TC flag is set
at the end of the frame.
Note: An underrun error may occur if the moment the data is written to the USART_TDR is too
close to the first SCLK transmission edge. To avoid this underrun error, the USART_TDR
should be written 3 usart_ker_ck cycles before the first SCLK edge.

26.5.15 USART single-wire Half-duplex communication

Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to ‘1’:
• The TX and RX lines are internally connected.
• The RX pin is no longer used.
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Apart from this, the communication protocol is similar to normal USART mode. Any conflict
on the line must be managed by software (for instance by using a centralized arbiter). In
particular, the transmission is never blocked by hardware and continues as soon as data are
written in the data register while the TE bit is set.

26.5.16 USART receiver timeout

The receiver timeout feature is enabled by setting the RTOEN bit in the USART_CR2
control register.
The timeout duration is programmed using the RTO bitfields in the USART_RTOR register.
The receiver timeout counter starts counting:
• from the end of the stop bit if STOP = ‘00’ or STOP = ‘11’
• from the end of the second stop bit if STOP = ‘10’.
• from the beginning of the stop bit if STOP = ‘01’.
When the timeout duration has elapsed, the RTOF flag in the USART_ISR register is set. A
timeout is generated if RTOIE bit in USART_CR1 register is set.

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26.5.17 USART Smartcard mode

This section is relevant only when Smartcard mode is supported. Refer to Section 26.4:
USART implementation on page 777.
Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
Smartcard mode, the following bits must be kept cleared:
• LINEN bit in the USART_CR2 register,
• HDSEL and IREN bits in the USART_CR3 register.
The CLKEN bit can also be set to provide a clock to the Smartcard.
The Smartcard interface is designed to support asynchronous Smartcard protocol as
defined in the ISO 7816-3 standard. Both T = 0 (character mode) and T = 1 (block mode)
are supported.
The USART should be configured as:
• 8 bits plus parity: M = 1 and PCE = 1 in the USART_CR1 register
• 1.5 stop bits when transmitting and receiving data: STOP = ’11’ in the USART_CR2
register. It is also possible to choose 0.5 stop bit for reception.
In T = 0 (character) mode, the parity error is indicated at the end of each character during
the guard time period.
Figure 277 shows examples of what can be seen on the data line with and without parity
error.

Figure 277. ISO 7816-3 asynchronous protocol

Without Parity error

Guard time
S 0 1 2 3 4 5 6 7 p
Start bit

WithParity error
Guard time
S 0 1 2 3 4 5 6 7 p

Start bit
Line pulled low by receiver
during stop in case of parity error

MSv31162V1

When connected to a Smartcard, the TX output of the USART drives a bidirectional line that
is also driven by the Smartcard. The TX pin must be configured as open drain.
Smartcard mode implements a single wire half duplex communication protocol.
• Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register starts
shifting on the next baud clock edge. In Smartcard mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
• In transmission, if the Smartcard detects a parity error, it signals this condition to the
USART by driving the line low (NACK). This NACK signal (pulling transmit line low for 1
baud clock) causes a framing error on the transmitter side (configured with 1.5 stop
bits). The USART can handle automatic re-sending of data according to the protocol.

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The number of retries is programmed in the SCARCNT bitfield. If the USART continues
receiving the NACK after the programmed number of retries, it stops transmitting and
signals the error as a framing error. The TXE bit (TXFNF bit in case FIFO mode is
enabled) may be set using the TXFRQ bit in the USART_RQR register.
• Smartcard auto-retry in transmission: A delay of 2.5 baud periods is inserted between
the NACK detection by the USART and the start bit of the repeated character. The TC
bit is set immediately at the end of reception of the last repeated character (no
guardtime). If the software wants to repeat it again, it must insure the minimum 2 baud
periods required by the standard.
• If a parity error is detected during reception of a frame programmed with a 1.5 stop bit
period, the transmit line is pulled low for a baud clock period after the completion of the
receive frame. This is to indicate to the Smartcard that the data transmitted to the
USART has not been correctly received. A parity error is NACKed by the receiver if the
NACK control bit is set, otherwise a NACK is not transmitted (to be used in T = 1
mode). If the received character is erroneous, the RXNE (RXFNE in case FIFO mode
is enabled)/receive DMA request is not activated. According to the protocol
specification, the Smartcard must resend the same character. If the received character
is still erroneous after the maximum number of retries specified in the SCARCNT
bitfield, the USART stops transmitting the NACK and signals the error as a parity error.
• Smartcard auto-retry in reception: the BUSY flag remains set if the USART NACKs the
card but the card doesn’t repeat the character.
• In transmission, the USART inserts the Guard Time (as programmed in the Guard Time
register) between two successive characters. As the Guard Time is measured after the
stop bit of the previous character, the GT[7:0] register must be programmed to the
desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12
(the duration of one character).
• The assertion of the TC flag can be delayed by programming the Guard Time register.
In normal operation, TC is asserted when the transmit shift register is empty and no
further transmit requests are outstanding. In Smartcard mode an empty transmit shift
register triggers the Guard Time counter to count up to the programmed value in the
Guard Time register. TC is forced low during this time. When the Guard Time counter
reaches the programmed value TC is asserted high. The TCBGT flag can be used to
detect the end of data transfer without waiting for guard time completion. This flag is set
just after the end of frame transmission and if no NACK has been received from the
card.
• The deassertion of TC flag is unaffected by Smartcard mode.
• If a framing error is detected on the transmitter end (due to a NACK from the receiver),
the NACK is not detected as a start bit by the receive block of the transmitter.
According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud
clock periods.
• On the receiver side, if a parity error is detected and a NACK is transmitted the receiver
does not detect the NACK as a start bit.
Note: Break characters are not significant in Smartcard mode. A 0x00 data with a framing error is
treated as data and not as a break.
No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the
other configurations) is not defined by the ISO protocol.
Figure 278 shows how the NACK signal is sampled by the USART. In this example the
USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the
USART is enabled in order to check the integrity of the data and the NACK signal.

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Figure 278. Parity error detection using the 1.5 stop bits

Bit 7 Parity bit 1.5 Stop bit

1 bit time 1.5 bit time

Sampling at Sampling at
8th, 9th, 10th 8th, 9th, 10th

0.5 bit time

Sampling at Sampling at
8th, 9th, 10th 8th, 9th, 10th
MSv31163V1

The USART can provide a clock to the Smartcard through the SCLK output. In Smartcard
mode, SCLK is not associated to the communication but is simply derived from the internal
peripheral input clock through a 5-bit prescaler. The division ratio is configured in the
USART_GTPR register. SCLK frequency can be programmed from usart_ker_ck_pres/2 to
usart_ker_ck_pres/62, where usart_ker_ck_pres is the peripheral input clock divided by a
programmed prescaler.

Block mode (T = 1)
In T = 1 (block) mode, the parity error transmission can be deactivated by clearing the
NACK bit in the USART_CR3 register.
When requesting a read from the Smartcard, in block mode, the software must program the
RTOR register to the BWT (block wait time) - 11 value. If no answer is received from the
card before the expiration of this period, a timeout interrupt is generated. If the first
character is received before the expiration of the period, it is signaled by the RXNE/RXFNE
interrupt.
Note: The RXNE/RXFNE interrupt must be enabled even when using the USART in DMA mode to
read from the Smartcard in block mode. In parallel, the DMA must be enabled only after the
first received byte.
After the reception of the first character (RXNE/RXFNE interrupt), the RTO register must be
programmed to the CWT (character wait time -11 value), in order to enable the automatic
check of the maximum wait time between two consecutive characters. This time is
expressed in baud time units. If the Smartcard does not send a new character in less than
the CWT period after the end of the previous character, the USART signals it to the software
through the RTOF flag and interrupt (when RTOIE bit is set).
Note: As in the Smartcard protocol definition, the BWT/CWT values should be defined from the
beginning (start bit) of the last character. The RTO register must be programmed to BWT -
11 or CWT -11, respectively, taking into account the length of the last character itself.
A block length counter is used to count all the characters received by the USART. This
counter is reset when the USART is transmitting. The length of the block is communicated
by the Smartcard in the third byte of the block (prologue field). This value must be
programmed to the BLEN field in the USART_RTOR register. When using DMA mode,
before the start of the block, this register field must be programmed to the minimum value

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(0x0). With this value, an interrupt is generated after the 4th received character. The
software must read the LEN field (third byte), its value must be read from the receive buffer.
In interrupt driven receive mode, the length of the block may be checked by software or by
programming the BLEN value. However, before the start of the block, the maximum value of
BLEN (0xFF) may be programmed. The real value is programmed after the reception of the
third character.
If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the
BLEN = LEN. If the block is using the CRC mechanism (2 epilog bytes), BLEN = LEN+1
must be programmed. The total block length (including prologue, epilogue and information
fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF
flag and interrupt (when EOBIE bit is set).
In case of an error in the block length, the end of the block is signaled by the RTO interrupt
(Character Wait Time overflow).
Note: The error checking code (LRC/CRC) must be computed/verified by software.

Direct and inverse convention

The Smartcard protocol defines two conventions: direct and inverse.
The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state
of the line and parity is even. In order to use this convention, the following control bits must
be programmed: MSBFIRST = 0, DATAINV = 0 (default values).
The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state
on the signal line and parity is even. In order to use this convention, the following control bits
must be programmed: MSBFIRST = 1, DATAINV = 1.
Note: When logical data values are inverted (0 = H, 1 = L), the parity bit is also inverted in the
same way.
In order to recognize the card convention, the card sends the initial character, TS, as the
first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS
are: LHHL LLL LLH and LHHL HHH LLH.
• (H) LHHL LLL LLH sets up the inverse convention: state L encodes value 1 and
moment 2 conveys the most significant bit (MSB first). When decoded by inverse
convention, the conveyed byte is equal to '3F'.
• (H) LHHL HHH LLH sets up the direct convention: state H encodes value 1 and
moment 2 conveys the least significant bit (LSB first). When decoded by direct
convention, the conveyed byte is equal to '3B'.
Character parity is correct when there is an even number of bits set to 1 in the nine
moments 2 to 10.
As the USART does not know which convention is used by the card, it needs to be able to
recognize either pattern and act accordingly. The pattern recognition is not done in
hardware, but through a software sequence. Moreover, assuming that the USART is
configured in direct convention (default) and the card answers with the inverse convention,
TS = LHHL LLL LLH results in a USART received character of 03 and an odd parity.

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Therefore, two methods are available for TS pattern recognition:

Method 1
The USART is programmed in standard Smartcard mode/direct convention. In this case, the
TS pattern reception generates a parity error interrupt and error signal to the card.
• The parity error interrupt informs the software that the card did not answer correctly in
direct convention. Software then reprograms the USART for inverse convention
• In response to the error signal, the card retries the same TS character, and it is
correctly received this time, by the reprogrammed USART.
Alternatively, in answer to the parity error interrupt, the software may decide to reprogram
the USART and to also generate a new reset command to the card, then wait again for the
TS.
Method 2
The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives
any of the two TS patterns as:
(H) LHHL LLL LLH = 0x103: inverse convention to be chosen
(H) LHHL HHH LLH = 0x13B: direct convention to be chosen
The software checks the received character against these two patterns and, if any of them
match, then programs the USART accordingly for the next character reception.
If none of the two is recognized, a card reset may be generated in order to restart the
negotiation.

26.5.18 USART IrDA SIR ENDEC block

This section is relevant only when IrDA mode is supported. Refer to Section 26.4: USART
implementation on page 777.
IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode,
the following bits must be kept cleared:
• LINEN, STOP and CLKEN bits in the USART_CR2 register,
• SCEN and HDSEL bits in the USART_CR3 register.
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation
scheme that represents logic 0 as an infrared light pulse (see Figure 279).
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream
output from USART. The output pulse stream is transmitted to an external output driver and
infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In
normal mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to the USART. The decoder input is
normally high (marking state) in the Idle state. The transmit encoder output has the opposite
polarity to the decoder input. A start bit is detected when the decoder input is low.
• IrDA is a half duplex communication protocol. If the Transmitter is busy (when the
USART is sending data to the IrDA encoder), any data on the IrDA receive line is
ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving
decoded data from the USART), data on the TX from the USART to IrDA is not

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encoded. While receiving data, transmission should be avoided as the data to be

transmitted could be corrupted.
• A ‘0‘ is transmitted as a high pulse and a ‘1’ is transmitted as a ‘0’. The width of the
pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 280).
• The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
• The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
• The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.
• The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the USART_GTPR). Pulses of width less than 1 PSC period are always
rejected, but those of width greater than one and less than two periods may be
accepted or rejected, those greater than two periods are accepted as a pulse. The IrDA
encoder/decoder doesn’t work when PSC = 0.
• The receiver can communicate with a low-power transmitter.
• In IrDA mode, the stop bits in the USART_CR2 register must be configured to ‘1 stop
bit’.

IrDA low-power mode

• Transmitter
In low-power mode, the pulse width is not maintained at 3/16 of the bit period. Instead,
the width of the pulse is 3 times the low-power baud rate which can be a minimum of
1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz < PSC < 2.12 MHz). A low-
power mode programmable divisor divides the system clock to achieve this value.
• Receiver
Receiving in low-power mode is similar to receiving in normal mode. For glitch
detection the USART should discard pulses of duration shorter than 1/PSC. A valid low
is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud
clock (PSC value in the USART_GTPR).
Note: A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).

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Figure 279. IrDA SIR ENDEC block diagram

TX
OR USART_TX

SIR
SIREN Transmit IrDA_OUT
Encoder
USART

SIR
RX
Receive IrDA_IN
DEcoder

USART_RX

MSv31164V1

Figure 280. IrDA data modulation (3/16) - Normal mode

Start Stop
bit bit
0 1 0 1 0 0 1 1 0 1
TX

IrDA_OUT
Bit period 3/16
IrDA_IN

RX 0 1 0 1 0 0 1 1 0 1

MSv31165V1

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26.5.19 Continuous communication using USART and DMA

The USART is capable of performing continuous communications using the DMA. The DMA
requests for Rx buffer and Tx buffer are generated independently.
Note: Refer to Section 26.4: USART implementation on page 777 to determine if the DMA mode is
supported. If DMA is not supported, use the USART as explained in Section 26.5.6. To
perform continuous communications when the FIFO is disabled, clear the TXE/ RXNE flags
in the USART_ISR register.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data are loaded from an SRAM area configured using the DMA peripheral (refer to
the corresponding Direct memory access controller section) to the USART_TDR register
whenever the TXE flag (TXFNF flag if FIFO mode is enabled) is set. To map a DMA channel
for USART transmission, use the following procedure (x denotes the channel number):
1. Write the USART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE (or TXFNF if FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the USART_TDR register from this memory area
after each TXE (or TXFNF if FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Clear the TC flag in the USART_ISR register by setting the TCCF bit in the
USART_ICR register.
7. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART
communication is complete. This is required to avoid corrupting the last transmission before
disabling the USART or before the system enters a low-power mode when the peripheral
clock is disabled. Software must wait until TC = 1. The TC flag remains cleared during all
data transfers and it is set by hardware at the end of transmission of the last frame.

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Figure 281. Transmission using DMA

Idle preamble Frame 1 Frame 2 Frame 3
TX line

Set by hardware Set by hardware

TXE flag cleared by DMA read cleared by DMA read Set by hardware

DMA request Ignored by the DMA because

the transfer is complete

USART_TDR F1 F2 F3

TC flag Set by
hardware
DMA writes
USART_TDR
Cleared
DMA TCIF flag by
Set by hardware software
(transfer
complete)

Software The DMA

configures DMA DMA writes DMA writes DMA writes transfer is
to send 3 data F1 into F2 into F3 into complete Software waits until TC=1
blocks and USART_TDR USART_TDR USART_TDR (TCIF=1 in
enables USART DMA_ISR)

ai17192b

Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full
(i.e. TXFNF = 1).

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data are loaded from the USART_RDR register to an SRAM area configured using the DMA
peripheral (refer to the corresponding Direct memory access controller section) whenever a
data byte is received. To map a DMA channel for USART reception, use the following
procedure:
1. Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE (RXFNE in case FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE (RXFNE in case FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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Figure 282. Reception using DMA

Frame 1 Frame 2 Frame 3
TX line

Set by hardware
RXNE flag cleared by DMA read

DMA request

USART_RDR F1 F2 F3

DMA reads
USART_RDR
Cleared
DMA TCIF flag Set by hardware by
(transfer complete) software

Software configures the The DMA transfer

DMA to receive 3 data DMA reads F1 DMA reads F2 DMA reads F3 is complete
blocks and enables from USART_RDR from USART_RDR from USART_RDR (TCIF=1 in
the USART DMA_ISR)
ai17193c

Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not
empty (i.e. RXFNE = 1).

Error flagging and interrupt generation in multibuffer communication

If any error occurs during a transaction in multibuffer communication mode, the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in
case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt
enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the
current byte if any of these errors occur.

26.5.20 RS232 Hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The Figure 283 shows how to connect 2 devices in this mode:

Figure 283. Hardware flow control between 2 USARTs

USART 1 USART 2

TX RX
TX circuit RX circuit
CTS RTS

RX TX
RX circuit TX circuit
RTS CTS

MSv31169V2

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RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits to ‘1’ in the USART_CR3 register.

RS232 RTS flow control

If the RTS flow control is enabled (RTSE = 1), then nRTS is asserted (tied low) as long as
the USART receiver is ready to receive a new data. When the receive register is full, nRTS
is deasserted, indicating that the transmission is expected to stop at the end of the current
frame. Figure 284 shows an example of communication with RTS flow control enabled.

Figure 284. RS232 RTS flow control

Start Stop Start Stop

RX Data 1 Idle Data 2
bit bit bit bit

nRTS

RXNE Data 1 read RXNE

Data 2 can now be transmitted

MSv31168V1

Note: When FIFO mode is enabled, nRTS is deasserted only when RXFIFO is full.

RS232 CTS flow control

If the CTS flow control is enabled (CTSE = 1), then the transmitter checks the nCTS input
before transmitting the next frame. If nCTS is asserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE = 0), else
the transmission does not occur. When nCTS is deasserted during a transmission, the
current transmission is completed before the transmitter stops.
When CTSE = 1, the CTSIF status bit is automatically set by hardware as soon as the nCTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 285
shows an example of communication with CTS flow control enabled.

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Figure 285. RS232 CTS flow control

CTS CTS

nCTS

Transmit data register

TDR Data 2 empty Data 3 empty

Stop Start Stop Start

TX Data 1 Data 2 Idle Data 3
bit bit bit bit

Writing data 3 in TDR Transmission of Data 3 is

delayed until nCTS = 0
MSv31167V1

Note: For correct behavior, nCTS must be asserted at least 3 USART clock source periods before
the end of the current character. In addition it should be noted that the CTSCF flag may not
be set for pulses shorter than 2 x PCLK periods.

RS485 driver enable

The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register.
This enables the user to activate the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the
USART_CR1 control register. The deassertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bitfields in the USART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit time,
depending on the oversampling rate).

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26.5.21 USART low-power management

The USART has advanced low-power mode functions, that enables transferring properly
data even when the usart_pclk clock is disabled.
The USART is able to wake up the MCU from low-power mode when the UESM bit is set.
When the usart_pclk is gated, the USART provides a wakeup interrupt (usart_wkup) if a
specific action requiring the activation of the usart_pclk clock is needed:
• If FIFO mode is disabled
usart_pclk clock has to be activated to empty the USART data register.
In this case, the usart_wkup interrupt source is RXNE set to ‘1’. The RXNEIE bit must
be set before entering low-power mode.
• If FIFO mode is enabled
usart_pclk clock has to be activated to:
– to fill the TXFIFO
– or to empty the RXFIFO
In this case, the usart_wkup interrupt source can be:
– RXFIFO not empty. In this case, the RXFNEIE bit must be set before entering low-
power mode.
– RXFIFO full. In this case, the RXFFIE bit must be set before entering low-power
mode, the number of received data corresponds to the RXFIFO size, and the
RXFF flag is not set.
– TXFIFO empty. In this case, the TXFEIE bit must be set before entering low-power
mode.
This enables sending/receiving the data in the TXFIFO/RXFIFO during low-power
mode.
To avoid overrun/underrun errors and transmit/receive data in low-power mode, the
usart_wkup interrupt source can be one of the following events:
– TXFIFO threshold reached. In this case, the TXFTIE bit must be set before
entering low-power mode.
– RXFIFO threshold reached. In this case, the RXFTIE bit must be set before
entering low-power mode.
For example, the application can set the threshold to the maximum RXFIFO size if the
wakeup time is less than the time required to receive a single byte across the line.
Using the RXFIFO full, TXFIFO empty, RXFIFO not empty and RXFIFO/TXFIFO
threshold interrupts to wakeup the MCU from low-power mode enables doing as many
USART transfers as possible during low-power mode with the benefit of optimizing
consumption.
Alternatively, a specific usart_wkup interrupt can be selected through the WUS bitfields.
When the wakeup event is detected, the WUF flag is set by hardware and a usart_wkup
interrupt is generated if the WUFIE bit is set. In this case the usart_wkup interrupt is not
mandatory and setting the WUF being is sufficient to wake up the MCU from low-power
mode.

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Note: Before entering low-power mode, make sure that no USART transfers are ongoing.
Checking the BUSY flag cannot ensure that low-power mode is never entered when data
reception is ongoing.
The WUF flag is set when a wakeup event is detected, independently of whether the MCU is
in low-power or active mode.
When entering low-power mode just after having initialized and enabled the receiver, the
REACK bit must be checked to make sure the USART is enabled.
When DMA is used for reception, it must be disabled before entering low-power mode and
re-enabled when exiting from low-power mode.
When the FIFO is enabled, waking up from low-power mode on address match is only
possible when Mute mode is enabled.

Using Mute mode with low-power mode

If the USART is put into Mute mode before entering low-power mode:
• Wakeup from Mute mode on idle detection must not be used, because idle detection
cannot work in low-power mode.
• If the wakeup from Mute mode on address match is used, then the low-power mode
wakeup source must also be the address match. If the RXNE flag was set when
entering the low-power mode, the interface remains in Mute mode upon address match
and wake up from low-power mode.
Note: When FIFO management is enabled, Mute mode can be used with wakeup from low-power
mode without any constraints (i.e.the two points mentioned above about Mute and low-
power mode are valid only when FIFO management is disabled).

Wakeup from low-power mode when USART kernel clock (usart_ker_ck) is

OFF in low-power mode
If during low-power mode, the usart_ker_ck clock is switched OFF when a falling edge on
the USART receive line is detected, the USART interface requests the usart_ker_ck clock to
be switched ON thanks to the usart_ker_ck_req signal. usart_ker_ck is then used for the
frame reception.
If the wakeup event is verified, the MCU wakes up from low-power mode and data reception
goes on normally.
If the wakeup event is not verified, usart_ker_ck is switched OFF again, the MCU is not
woken up and remains in low-power mode, and the kernel clock request is released.
The example below shows the case of a wakeup event programmed to “address match
detection” and FIFO management disabled.

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Figure 286 shows the USART behavior when the wakeup event is verified.

Figure 286. Wakeup event verified (wakeup event = address match, FIFO disabled)

Address match event WUF =’1'

USART sends a wakeup event to the MCU

Data reception goes on

Start bit

Start bit
Idle

Stop bit
Stop bit
RX line Rx data 1 Rx data 2

Startup time

Usart_ker_ck
ON
OFF

Low-power mode Run mode

MSv40856V2

Figure 287 shows the USART behavior when the wakeup event is not verified.

Figure 287. Wakeup event not verified (wakeup event = address match,
FIFO disabled)

Address does not match

Start bit

Idle Idle
Stop bit

RX line Rx data 1

Startup time

Usart_ker_ck
ON OFF
OFF

Low-power mode

MSv40857V2

Note: The figures above are valid when address match or any received frame is used as wakeup
event. If the wakeup event is the start bit detection, the USART sends the wakeup event to
the MCU at the end of the start bit.

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Determining the maximum USART baud rate that enables to correctly wake
up the device from low-power mode
The maximum baud rate that enables to correctly wake up the device from low-power mode
depends on the wakeup time parameter (refer to the device datasheet) and on the USART
receiver tolerance (see Section 26.5.8: Tolerance of the USART receiver to clock deviation).
Let us take the example of OVER8 = 0, M bits = ‘01’, ONEBIT = 0 and BRR [3:0] = 0000.
In these conditions, according to Table 123: Tolerance of the USART receiver when BRR
[3:0] = 0000, the USART receiver tolerance equals 3.41%.
DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance
DWUmax = tWUUSART/ (11 x Tbit Min)
Tbit Min = tWUUSART/ (11 x DWUmax)
where tWUUSART is the wakeup time from low-power mode.
If we consider the ideal case where DTRA, DQUANT, DREC and DTCL parameters are at
0%, the maximum value of DWU is 3.41%. In reality, we need to consider at least the
usart_ker_ck inaccuracy.
For example, if HSI is used as usart_ker_ck, and the HSI inaccuracy is of 1%, then we
obtain:
tWUUSART = 3 µs (values provided only as examples; for correct values, refer to the
device datasheet).
DWUmax = 3.41% - 1% = 2.41%
Tbit min = 3 µs/ (11 x 2.41%) = 11.32 µs.
As a result, the maximum baud rate that enables to wakeup correctly from low-power
mode is: 1/11.32 µs = 88.36 Kbaud.

26.6 USART in low-power modes

Table 126. Effect of low-power modes on the USART
Mode Description

Sleep No effect. USART interrupts cause the device to exit Sleep mode.
The content of the USART registers is kept.
Stop(1) The USART is able to wake up the microcontroller from Stop mode when
the USART is clocked by an oscillator available in Stop mode.
The USART peripheral is powered down and must be reinitialized after
Standby
exiting Standby mode.
1. Refer to Section 26.4: USART implementation to know if the wakeup from Stop mode is supported for a
given peripheral instance. If an instance is not functional in a given Stop mode, it must be disabled before
entering this Stop mode.

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26.7 USART interrupts

Refer to Table 127 for a detailed description of all USART interrupt requests.

Table 127. USART interrupt requests

Exit from Exit from Exit from
Interrupt Event Enable Interrupt clear
Interrupt event Sleep Stop(1) Standby
vector flag Control bit method
mode modes mode

Transmit data register empty TXE TXEIE Write TDR NO

Transmit FIFO not Full TXFNF TXFNFIE TXFIFO full NO

Write TDR or write 1 in

Transmit FIFO Empty TXFE TXFEIE YES
TXFRQ

Transmit FIFO threshold

USART TXFT TXFTIE Write TDR YES
reached YES NO
or UART
CTS interrupt CTSIF CTSIE Write 1 in CTSCF NO

Write TDR or write 1 in

Transmission Complete TC TCIE NO
TCCF

Transmission Complete Before Write TDR or write 1 in

TCBGT TCBGTIE NO
Guard Time TCBGT

Receive data register not Read RDR or write 1

RXNE RXNEIE YES
empty (data ready to be read) in RXFRQ

Read RDR until

Receive FIFO Not Empty RXFNE RXFNEIE RXFIFO empty or YES
write 1 in RXFRQ

Receive FIFO Full RXFF(2) RXFFIE Read RDR YES

Receive FIFO threshold

RXFT RXFTIE Read RDR YES
reached

RXNEIE/
Overrun error detected ORE RXFNEIE Write 1 in ORECF NO

Idle line detected IDLE IDLEIE Write 1 in IDLECF NO

Parity error PE PEIE Write 1 in PECF NO

USART
LIN break LBDF LBDIE Write 1 in LBDCF YES NO NO
or UART
Noise error in multibuffer
NE Write 1 in NFCF NO
communication

Overrun error in multibuffer

ORE(3) EIE Write 1 in ORECF NO
communication

Framing Error in multibuffer

FE Write 1 in FECF NO
communication
Character match CMF CMIE Write 1 in CMCF NO

Receiver timeout RTOF RTOFIE Write 1 in RTOCCF NO

End of Block EOBF EOBIE Write 1 in EOBCF NO

Wakeup from low-power mode WUF WUFIE Write 1 in WUC YES

SPI slave underrun error UDR EIE Write 1 in UDRCF NO

1. The USART can wake up the device from Stop mode only if the peripheral instance supports the Wakeup from Stop mode
feature. Refer to Section 26.4: USART implementation for the list of supported Stop modes.

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2. RXFF flag is asserted if the USART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in
USART_RDR. In Stop mode, USART_RDR is not clocked. As a result, this register is not written and once n data are
received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).
3. When OVRDIS = 0.

26.8 USART registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).

26.8.1 USART control register 1 [alternate] (USART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXF FIFO
TXFEIE M1 EOBIE RTOIE DEAT[4:0] DEDT[4:0]
FIE EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8 CMIE MME M0 WAKE PCE PS PEIE TXFNFIE TCIE RXFNEIE IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 RXFFIE: RXFIFO Full interrupt enable

This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when RXFF = 1 in the USART_ISR register
Bit 30 TXFEIE: TXFIFO empty interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 29 FIFOEN: FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.

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Bit 28 M1: Word length

This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit
M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit
M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit
This bit can only be written when the USART is disabled (UE = 0).
Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate
(0x7F and 0x55 frames detection) are not supported.
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Section 26.4: USART implementation on page 777.
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time,
depending on the oversampling rate).
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bits 20:16 DEDT[4:0]: Driver Enable deassertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample
time units (1/8 or 1/16 bit time, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 15 OVER8: Oversampling mode
0: Oversampling by 16
1: Oversampling by 8
This bit can only be written when the USART is disabled (UE = 0).
Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

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Bit 13 MME: Mute mode enable

This bit enables the USART Mute mode function. When set, the USART can switch between
active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0: Receiver in active mode permanently
1: Receiver can switch between Mute mode and active mode.
Bit 12 M0: Word length
This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or
cleared by software (refer to bit 28 (M1)description).
This bit can only be written when the USART is disabled (UE = 0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the USART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit
if M = 0) and the parity is checked on the received data. This bit is set and cleared by
software. Once it is set, PCE is active after the current byte (in reception and in
transmission).
0: Parity control disabled
1: Parity control enabled
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever PE = 1 in the USART_ISR register
Bit 7 TXFNFIE: TXFIFO not full interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TXFNF =1 in the USART_ISR register
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TC = 1 in the USART_ISR register
Bit 5 RXFNEIE: RXFIFO not empty interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register

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Bit 4 IDLEIE: IDLE interrupt enable

This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word, except in Smartcard mode. In order to generate an idle
character, the TE must not be immediately written to ‘1’. To ensure the required duration,
the software can poll the TEACK bit in the USART_ISR register.
In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission
starts.
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: USART enable in low-power mode
When this bit is cleared, the USART cannot wake up the MCU from low-power mode.
When this bit is set, the USART can wake up the MCU from low-power mode.
This bit is set and cleared by software.
0: USART not able to wake up the MCU from low-power mode.
1: USART able to wake up the MCU from low-power mode.
Note: It is recommended to set the UESM bit just before entering low-power mode and clear it
when exit from low-power mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all
current operations are discarded. The USART configuration is kept, but all the USART_ISR
status flags are reset. This bit is set and cleared by software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: To enter low-power mode without generating errors on the line, the TE bit must be
previously reset and the software must wait for the TC bit in the USART_ISR to be set
before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.
In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1,
regardless of the UE bit value.

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26.8.2 USART control register 1 [alternate] (USART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFO
Res. Res. M1 EOBIE RTOIE DEAT[4:0] DEDT[4:0]
EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 FIFOEN: FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit
M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit
M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit
This bit can only be written when the USART is disabled (UE = 0).
Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate
(0x7F and 0x55 frames detection) are not supported.
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Section 26.4: USART implementation on page 777.

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Bits 25:21 DEAT[4:0]: Driver Enable assertion time

This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time,
depending on the oversampling rate).
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bits 20:16 DEDT[4:0]: Driver Enable deassertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample
time units (1/8 or 1/16 bit time, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 15 OVER8: Oversampling mode
0: Oversampling by 16
1: Oversampling by 8
This bit can only be written when the USART is disabled (UE = 0).
Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the CMF bit is set in the USART_ISR register.
Bit 13 MME: Mute mode enable
This bit enables the USART Mute mode function. When set, the USART can switch between
active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0: Receiver in active mode permanently
1: Receiver can switch between Mute mode and active mode.
Bit 12 M0: Word length
This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or
cleared by software (refer to bit 28 (M1)description).
This bit can only be written when the USART is disabled (UE = 0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the USART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit
if M = 0) and the parity is checked on the received data. This bit is set and cleared by
software. Once it is set, PCE is active after the current byte (in reception and in
transmission).
0: Parity control disabled
1: Parity control enabled
This bitfield can only be written when the USART is disabled (UE = 0).

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Bit 9 PS: Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever PE = 1 in the USART_ISR register
Bit 7 TXEIE: Transmit data register empty
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TXE =1 in the USART_ISR register
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TC = 1 in the USART_ISR register
Bit 5 RXNEIE: Receive data register not empty
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register
Bit 4 IDLEIE: IDLE interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word, except in Smartcard mode. In order to generate an idle
character, the TE must not be immediately written to ‘1’. To ensure the required duration,
the software can poll the TEACK bit in the USART_ISR register.
In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission
starts.

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Bit 2 RE: Receiver enable

This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: USART enable in low-power mode
When this bit is cleared, the USART cannot wake up the MCU from low-power mode.
When this bit is set, the USART can wake up the MCU from low-power mode.
This bit is set and cleared by software.
0: USART not able to wake up the MCU from low-power mode.
1: USART able to wake up the MCU from low-power mode.
Note: It is recommended to set the UESM bit just before entering low-power mode and clear it
when exit from low-power mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all
current operations are discarded. The USART configuration is kept, but all the USART_ISR
status flags are reset. This bit is set and cleared by software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: To enter low-power mode without generating errors on the line, the TE bit must be
previously reset and the software must wait for the TC bit in the USART_ISR to be set
before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.
In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1,
regardless of the UE bit value.

26.8.3 USART control register 2 (USART_CR2)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSBFI
ADD[7:0] RTOEN ABRMOD[1:0] ABREN DATAINV TXINV RXINV
RST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS_
SWAP LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res. LBDIE LBDL ADDM7 Res. Res. SLVEN
NSS
rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 ADD[7:0]: Address of the USART node

ADD[7:4]:
These bits give the address of the USART node or a character code to be recognized.
They are used to wake up the MCU with 7-bit address mark detection in multiprocessor
communication during Mute mode or low-power mode. The MSB of the character sent by the
transmitter should be equal to 1. They can also be used for character detection during normal
reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this
case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on
match.
These bits can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE = 0).
ADD[3:0]:
These bits give the address of the USART node or a character code to be recognized.
They are used for wakeup with address mark detection, in multiprocessor communication during
Mute mode or low-power mode.
These bits can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE = 0).
Bit 23 RTOEN: Receiver timeout enable
This bit is set and cleared by software.
0: Receiver timeout feature disabled.
1: Receiver timeout feature enabled.
When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle
(no reception) for the duration programmed in the RTOR (receiver timeout register).
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bits 22:21 ABRMOD[1:0]: Auto baud rate mode
These bits are set and cleared by software.
00: Measurement of the start bit is used to detect the baud rate.
01: Falling edge to falling edge measurement (the received frame must start with a single bit = 1
and Frame = Start10xxxxxx)
10: 0x7F frame detection.
11: 0x55 frame detection
This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0).
Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example
0xAA for MSBFIRST)
If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 20 ABREN: Auto baud rate enable
This bit is set and cleared by software.
0: Auto baud rate detection is disabled.
1: Auto baud rate detection is enabled.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
This bitfield can only be written when the USART is disabled (UE = 0).

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Bit 18 DATAINV: Binary data inversion

This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H).
The parity bit is also inverted.
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
This enables the use of an external inverter on the TX line.
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 16 RXINV: RX pin active level inversion
This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
This enables the use of an external inverter on the RX line.
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired
connection to another UART.
This bitfield can only be written when the USART is disabled (UE = 0).
Bit 14 LINEN: LIN mode enable
This bit is set and cleared by software.
0: LIN mode disabled
1: LIN mode enabled
The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the
SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bits 13:12 STOP[1:0]: stop bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: 0.5 stop bit.
10: 2 stop bits
11: 1.5 stop bits
This bitfield can only be written when the USART is disabled (UE = 0).

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Bit 11 CLKEN: Clock enable

This bit enables the user to enable the SCLK pin.
0: SCLK pin disabled
1: SCLK pin enabled
This bit can only be written when the USART is disabled (UE = 0).
Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must
be kept at reset value. Refer to Section 26.4: USART implementation on page 777.
In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps
below must be respected:
UE = 0
SCEN = 1
GTPR configuration
CLKEN= 1
UE = 1
Bit 10 CPOL: Clock polarity
This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous
mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship
0: Steady low value on SCLK pin outside transmission window
1: Steady high value on SCLK pin outside transmission window
This bit can only be written when the USART is disabled (UE = 0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 9 CPHA: Clock phase
This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It
works in conjunction with the CPOL bit to produce the desired clock/data relationship (see
Figure 267 and Figure 268)
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
This bit can only be written when the USART is disabled (UE = 0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 8 LBCL: Last bit clock pulse
This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB)
has to be output on the SCLK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the SCLK pin
1: The clock pulse of the last data bit is output to the SCLK pin
Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit
format selected by the M bit in the USART_CR1 register.
This bit can only be written when the USART is disabled (UE = 0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 7 Reserved, must be kept at reset value.
Bit 6 LBDIE: LIN break detection interrupt enable
Break interrupt mask (break detection using break delimiter).
0: Interrupt is inhibited
1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to
Section 26.4: USART implementation on page 777.

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Bit 5 LBDL: LIN break detection length

This bit is for selection between 11 bit or 10 bit break detection.
0: 10-bit break detection
1: 11-bit break detection
This bit can only be written when the USART is disabled (UE = 0).
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to
Section 26.4: USART implementation on page 777.
Bit 4 ADDM7: 7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the USART is disabled (UE = 0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bit 3 DIS_NSS:
When the DIS_NSS bit is set, the NSS pin input is ignored.
0: SPI slave selection depends on NSS input pin.
1: SPI slave is always selected and NSS input pin is ignored.
Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 SLVEN: Synchronous Slave mode enable
When the SLVEN bit is set, the synchronous slave mode is enabled.
0: Slave mode disabled.
1: Slave mode enabled.
Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.

Note: The CPOL, CPHA and LBCL bits should not be written while the transmitter is enabled.

26.8.4 USART control register 3 (USART_CR3)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXF TCBG
TXFTCFG[2:0] RXFTCFG[2:0] TXFTIE WUFIE WUS[1:0] SCARCNT[2:0] Res.
TIE TIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR ONE HD
DEP DEM DDRE CTSIE CTSE RTSE DMAT DMAR SCEN NACK IRLP IREN EIE
DIS BIT SEL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:29 TXFTCFG[2:0]: TXFIFO threshold configuration

000:TXFIFO reaches 1/8 of its depth
001:TXFIFO reaches 1/4 of its depth
010:TXFIFO reaches 1/2 of its depth
011:TXFIFO reaches 3/4 of its depth
100:TXFIFO reaches 7/8 of its depth
101:TXFIFO becomes empty
Remaining combinations: Reserved
Bit 28 RXFTIE: RXFIFO threshold interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when Receive FIFO reaches the threshold programmed in
RXFTCFG.
Bits 27:25 RXFTCFG[2:0]: Receive FIFO threshold configuration
000:Receive FIFO reaches 1/8 of its depth
001:Receive FIFO reaches 1/4 of its depth
010:Receive FIFO reaches 1/2 of its depth
011:Receive FIFO reaches 3/4 of its depth
100:Receive FIFO reaches 7/8 of its depth
101:Receive FIFO becomes full
Remaining combinations: Reserved
Bit 24 TCBGTIE: Transmission Complete before guard time, interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Note: If the USART does not support the Smartcard mode, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 23 TXFTIE: TXFIFO threshold interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when TXFIFO reaches the threshold programmed in
TXFTCFG.
Bit 22 WUFIE: Wakeup from low-power mode interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Note: WUFIE must be set before entering in low-power mode.

If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on
page 777.

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Bits 21:20 WUS[1:0]: Wakeup from low-power mode interrupt flag selection
This bitfield specifies the event which activates the WUF (Wakeup from low-power mode
flag).
00: WUF active on address match (as defined by ADD[7:0] and ADDM7)
01: Reserved.
10: WUF active on start bit detection
11: WUF active on RXNE/RXFNE.
This bitfield can only be written when the USART is disabled (UE = 0).
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on
page 777.
Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count
This bitfield specifies the number of retries for transmission and reception in Smartcard
mode.
In transmission mode, it specifies the number of automatic retransmission retries, before
generating a transmission error (FE bit set).
In reception mode, it specifies the number or erroneous reception trials, before generating a
reception error (RXNE/RXFNE and PE bits set).
This bitfield must be programmed only when the USART is disabled (UE = 0).
When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to
stop retransmission.
0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1 to 0x7: number of automatic retransmission attempts (before signaling error)
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset
value. Refer to Section 26.4: USART implementation on page 777.
Bit 16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 14 DEM: Driver enable mode
This bit enables the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the USART is disabled (UE = 0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Section 26.4: USART implementation on page 777.
Bit 13 DDRE: DMA Disable on Reception Error
0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data is transferred (used for Smartcard mode).
1: DMA is disabled following a reception error. The corresponding error flag is set, as well
as RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case
FIFO mode is enabled) before clearing the error flag.
This bit can only be written when the USART is disabled (UE=0).
Note: The reception errors are: parity error, framing error or noise error.

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Bit 12 OVRDIS: Overrun Disable

This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new
data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is
written directly in USART_RDR register. Even when FIFO management is enabled, the
RXNE flag is to be used.
This bit can only be written when the USART is disabled (UE = 0).
Note: This control bit enables checking the communication flow w/o reading the data
Bit 11 ONEBIT: One sample bit method enable
This bit enables the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NE) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE = 0).
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0).
If the nCTS input is deasserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while nCTS is asserted,
the transmission is postponed until nCTS is asserted.
This bit can only be written when the USART is disabled (UE = 0)
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The nRTS output is asserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE = 0).
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception

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Bit 5 SCEN: Smartcard mode enable

This bit is used for enabling Smartcard mode.
0: Smartcard Mode disabled
1: Smartcard Mode enabled
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 4 NACK: Smartcard NACK enable
0: NACK transmission in case of parity error is disabled
1: NACK transmission during parity error is enabled
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 3 HDSEL: Half-duplex selection
Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the USART is disabled (UE = 0).
Bit 2 IRLP: IrDA low-power
This bit is used for selecting between normal and low-power IrDA modes
0: Normal mode
1: Low-power mode
This bit can only be written when the USART is disabled (UE = 0).
Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 1 IREN: IrDA mode enable
This bit is set and cleared by software.
0: IrDA disabled
1: IrDA enabled
This bit can only be written when the USART is disabled (UE = 0).
Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 0 EIE: Error interrupt enable
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or
UDR = 1 in the USART_ISR register).
0: Interrupt inhibited
1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in
the USART_ISR register.

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26.8.5 USART baud rate register (USART_BRR)

This register can only be written when the USART is disabled (UE = 0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BRR[15:0]: USART baud rate
BRR[15:4]
BRR[15:4] = USARTDIV[15:4]
BRR[3:0]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.

26.8.6 USART guard time and prescaler register (USART_GTPR)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT[7:0] PSC[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 GT[7:0]: Guard time value
This bitfield is used to program the Guard time value in terms of number of baud clock
periods.
This is used in Smartcard mode. The Transmission Complete flag is set after this guard time
value.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bits 7:0 PSC[7:0]: Prescaler value
In IrDA low-power and normal IrDA mode:
PSC[7:0] = IrDA Normal and Low-Power baud rate
PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve
the low-power frequency: the source clock is divided by the value given in the register (8
significant bits):
In Smartcard mode:
PSC[4:0] = Prescaler value
PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide
the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to
give the division factor of the source clock frequency:

00000: Reserved - do not program this value

00001: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
00010: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
00011: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
...
11111: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
0010 0000: Divides the source clock by 32 (IrDA mode)
...
1111 1111: Divides the source clock by 255 (IrDA mode)

This bitfield can only be written when the USART is disabled (UE = 0).
Note: Bits [7:5] must be kept cleared if Smartcard mode is used.
This bitfield is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA
modes are not supported. Refer to Section 26.4: USART implementation on page 777.

26.8.7 USART receiver timeout register (USART_RTOR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN[7:0] RTO[23:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 BLEN[7:0]: Block Length

This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the
number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1.
Examples:
BLEN = 0: 0 information characters + LEC
BLEN = 1: 0 information characters + CRC
BLEN = 255: 254 information characters + CRC (total 256 characters))
In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO
mode is enabled).
This bitfield can be used also in other modes. In this case, the Block length counter is reset
when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1.
Note: This value can be programmed after the start of the block reception (using the data
from the LEN character in the Prologue Field). It must be programmed only once per
received block.
Bits 23:0 RTO[23:0]: Receiver timeout value
This bitfield gives the Receiver timeout value in terms of number of bits during which there is
no activity on the RX line.
In standard mode, the RTOF flag is set if, after the last received character, no new start bit is
detected for more than the RTO value.
In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard
chapter for more details. In the standard, the CWT/BWT measurement is done starting from
the start bit of the last received character.
Note: This value must only be programmed once per received character.

Note: RTOR can be written on-the-fly. If the new value is lower than or equal to the counter, the
RTOF flag is set.
This register is reserved and forced by hardware to “0x00000000” when the Receiver
timeout feature is not supported. Refer to Section 26.4: USART implementation on page 777.

26.8.8 USART request register (USART_RQR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ ABRRQ
w w w w w

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Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TXFRQ: Transmit data flush request
When FIFO mode is disabled, writing ‘1’ to this bit sets the TXE flag. This enables to discard
the transmit data. This bit must be used only in Smartcard mode, when data have not been
sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the
USART does not support Smartcard mode, this bit is reserved and must be kept at reset
value.
When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag
(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is
supported in both UART and Smartcard modes.
Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in
order to ensure that no data are written in the data register.
Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE.
This enables to discard the received data without reading them, and avoid an overrun
condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: When the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
Bit 0 ABRRQ: Auto baud rate request
Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an
automatic baud rate measurement on the next received data frame.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must
be kept at reset value. Refer to Section 26.4: USART implementation on page 777.

26.8.9 USART interrupt and status register [alternate] (USART_ISR)

Address offset: 0x1C
Reset value: 0x0X80 00C0
X = 2 if FIFO/Smartcard mode is enabled
X = 0 if FIFO is enabled and Smartcard mode is disabled
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RE TE
Res. Res. Res. Res. TXFT RXFT TCBGT RXFF TXFE WUF RWU SBKF CMF BUSY
ACK ACK
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF ABRE UDR EOBF RTOF CTS CTSIF LBDF TXFNF TC RXFNE IDLE ORE NE FE PE
r r r r r r r r r r r r r r r r

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Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TXFT: TXFIFO threshold flag
This bit is set by hardware when the TXFIFO reaches the threshold programmed in
TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An
interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register.
0: TXFIFO does not reach the programmed threshold.
1: TXFIFO reached the programmed threshold.
Bit 26 RXFT: RXFIFO threshold flag
This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3
register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and
one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit
27) in the USART_CR3 register.
0: Receive FIFO does not reach the programmed threshold.
1: Receive FIFO reached the programmed threshold.
Note: When the RXFTCFG threshold is configured to ‘101’, RXFT flag is set if 16 data are
available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the
17th received data does not cause an overrun error. The overrun error occurs after
receiving the 18th data.
Bit 25 TCBGT: Transmission complete before guard time flag
This bit is set when the last data written in the USART_TDR has been transmitted correctly
out of the shift register.
It is set by hardware in Smartcard mode, if the transmission of a frame containing data is
complete and if the smartcard did not send back any NACK. An interrupt is generated if
TCBGTIE = 1 in the USART_CR3 register.
This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or
by a write to the USART_TDR register.
0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is
received from the card)
1: Transmission is complete successfully (before Guard time completion and there is no
NACK from the smart card).
Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at
reset value. If the USART supports the Smartcard mode and the Smartcard mode is
enabled, the TCBGT reset value is ‘1’. Refer to Section 26.4: USART implementation
on page 777.
Bit 24 RXFF: RXFIFO full
This bit is set by hardware when the number of received data corresponds to
RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register.
An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register.
0: RXFIFO not full.
1: RXFIFO Full.
Bit 23 TXFE: TXFIFO empty
This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one
data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4)
in the USART_RQR register.
An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register.
0: TXFIFO not empty.
1: TXFIFO empty.

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Bit 22 REACK: Receive enable acknowledge flag

This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the USART.
It can be used to verify that the USART is ready for reception before entering low-power
mode.
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the USART.
It can be used when an idle frame request is generated by writing TE = 0, followed by
TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
Bit 20 WUF: Wakeup from low-power mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE = 1 in the USART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 19 RWU: Receiver wakeup from Mute mode
This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 18 SBKF: Send break flag
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during
the stop bit of break transmission.
0: Break character transmitted
1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 17 CMF: Character match flag
This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is
cleared by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE = 1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going

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Bit 15 ABRF: Auto baud rate flag

This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set,
generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 13 UDR: SPI slave underrun error flag
In slave transmission mode, this flag is set when the first clock pulse for data transmission
appears while the software has not yet loaded any value into USART_TDR. This flag is
reset by setting UDRCF bit in the USART_ICR register.
0: No underrun error
1: underrun error
Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 12 EOBF: End of block flag
This bit is set by hardware when a complete block has been received (for example T = 1
Smartcard mode). The detection is done when the number of received bytes (from the start
of the block, including the prologue) is equal or greater than BLEN + 4.
An interrupt is generated if the EOBIE = 1 in the USART_CR1 register.
It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.
0: End of Block not reached
1: End of Block (number of characters) reached
Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer
to Section 26.4: USART implementation on page 777.
Bit 11 RTOF: Receiver timeout
This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE = 1 in the USART_CR2 register.
In Smartcard mode, the timeout corresponds to the CWT or BWT timings.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF is set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
kept at reset value.

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Bit 10 CTS: CTS flag

This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin.
0: nCTS line set
1: nCTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE = 1 in the USART_CR3 register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 LBDF: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software, by
writing 1 to the LBDCF in the USART_ICR.
An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 7 TXFNF: TXFIFO not full
TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the
USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO.
This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared
indicating that data can not be written into the USART_TDR.
An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register.
0: Transmit FIFO is full
1: Transmit FIFO is not full
Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending
the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to
writing in TXFIFO (TXFNF and TXFE are set at the same time).
This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit indicates that the last data written in the USART_TDR has been transmitted out of
the shift register.
It is set by hardware when the transmission of a frame containing data is complete and
when TXFE is set.
An interrupt is generated if TCIE = 1 in the USART_CR1 register.
TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a
write to the USART_TDR register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.

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Bit 5 RXFNE: RXFIFO not empty

RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be
read from the USART_RDR register. Every read operation from the USART_RDR frees a
location in the RXFIFO.
RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by
writing 1 to the RXFRQ in the USART_RQR register.
An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register.
0: Data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line
occurs).
If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0),
whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a
software, writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the USART_RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multi buffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in
the USART_CR3 register.

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Bit 2 NE: Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NECF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit
which itself generates an interrupt. An interrupt is generated when the NE flag is set
during multi buffer communication if the EIE bit is set.
When the line is noise-free, the NE flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8:
Tolerance of the USART receiver to clock deviation on page 795).
This error is associated with the character in the USART_RDR.
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
When transmitting data in Smartcard mode, this bit is set when the maximum number of
transmit attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the USART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Note: This error is associated with the character in the USART_RDR.
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error
Note: This error is associated with the character in the USART_RDR.

26.8.10 USART interrupt and status register [alternate] (USART_ISR)

Address offset: 0x1C
Reset value: 0x0000 00C0
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RE TE
Res. Res. Res. Res. Res. Res. TCBGT Res. Res. WUF RWU SBKF CMF BUSY
ACK ACK
r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF ABRE UDR EOBF RTOF CTS CTSIF LBDF TXE TC RXNE IDLE ORE NE FE PE
r r r r r r r r r r r r r r r r

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Bits 31:26 Reserved, must be kept at reset value.

Bit 25 TCBGT: Transmission complete before guard time flag
This bit is set when the last data written in the USART_TDR has been transmitted correctly
out of the shift register.
It is set by hardware in Smartcard mode, if the transmission of a frame containing data is
complete and if the smartcard did not send back any NACK. An interrupt is generated if
TCBGTIE = 1 in the USART_CR3 register.
This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or
by a write to the USART_TDR register.
0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is
received from the card)
1: Transmission is complete successfully (before Guard time completion and there is no
NACK from the smart card).
Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at
reset value. If the USART supports the Smartcard mode and the Smartcard mode is
enabled, the TCBGT reset value is ‘1’. Refer to Section 26.4: USART implementation
on page 777.
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the USART.
It can be used to verify that the USART is ready for reception before entering low-power
mode.
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the USART.
It can be used when an idle frame request is generated by writing TE = 0, followed by
TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
Bit 20 WUF: Wakeup from low-power mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE = 1 in the USART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 19 RWU: Receiver wakeup from Mute mode
This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to Section 26.4: USART implementation on page 777.

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Bit 18 SBKF: Send break flag

This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during
the stop bit of break transmission.
0: Break character transmitted
1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 17 CMF: Character match flag
This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is
cleared by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE = 1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going
Bit 15 ABRF: Auto baud rate flag
This bit is set by hardware when the automatic baud rate has been set (RXNE is also set,
generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed
without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 13 UDR: SPI slave underrun error flag
In slave transmission mode, this flag is set when the first clock pulse for data transmission
appears while the software has not yet loaded any value into USART_TDR. This flag is
reset by setting UDRCF bit in the USART_ICR register.
0: No underrun error
1: underrun error
Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at
reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 12 EOBF: End of block flag
This bit is set by hardware when a complete block has been received (for example T = 1
Smartcard mode). The detection is done when the number of received bytes (from the start
of the block, including the prologue) is equal or greater than BLEN + 4.
An interrupt is generated if the EOBIE = 1 in the USART_CR1 register.
It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.
0: End of Block not reached
1: End of Block (number of characters) reached
Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer
to Section 26.4: USART implementation on page 777.

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Bit 11 RTOF: Receiver timeout

This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE = 1 in the USART_CR2 register.
In Smartcard mode, the timeout corresponds to the CWT or BWT timings.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF is set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
kept at reset value.
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin.
0: nCTS line set
1: nCTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE = 1 in the USART_CR3 register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 LBDF: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software, by
writing 1 to the LBDCF in the USART_ICR.
An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value.
Refer to Section 26.4: USART implementation on page 777.
Bit 7 TXE: Transmit data register empty
TXE is set by hardware when the content of the USART_TDR register has been transferred
into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can
also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the
data (only in Smartcard T = 0 mode, in case of transmission failure).
An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register.
0: Data register full
1: Data register not full

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Bit 6 TC: Transmission complete

This bit indicates that the last data written in the USART_TDR has been transmitted out of
the shift register.
It is set by hardware when the transmission of a frame containing data is complete and
when TXE is set.
An interrupt is generated if TCIE = 1 in the USART_CR1 register.
TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a
write to the USART_TDR register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
Bit 5 RXNE: Read data register not empty
RXNE bit is set by hardware when the content of the USART_RDR shift register has been
transferred to the USART_RDR register. It is cleared by reading from the USART_RDR
register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR
register.
An interrupt is generated if RXNEIE = 1 in the USART_CR1 register.
0: Data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0),
whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a
software, writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXNEIE = 1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the USART_RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multi buffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in
the USART_CR3 register.

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Bit 2 NE: Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NECF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NE flag is set
during multi buffer communication if the EIE bit is set.
When the line is noise-free, the NE flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8:
Tolerance of the USART receiver to clock deviation on page 795).
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
When transmitting data in Smartcard mode, this bit is set when the maximum number of
transmit attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the USART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error

26.8.11 USART interrupt flag clear register (USART_ICR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res.
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCBGT TXFEC
Res. Res. UDRCF EOBCF RTOCF Res. CTSCF LBDCF TCCF IDLECF ORECF NECF FECF PECF
CF F

w w w w w w w w w w w w w

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 WUCF: Wakeup from low-power mode clear flag
Writing 1 to this bit clears the WUF flag in the USART_ISR register.
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on
page 777.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the USART_ISR register.

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Bits 16:14 Reserved, must be kept at reset value.

Bit 13 UDRCF:SPI slave underrun clear flag
Writing 1 to this bit clears the UDRF flag in the USART_ISR register.
Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at
reset value. Refer to Section 26.4: USART implementation on page 777
Bit 12 EOBCF: End of block clear flag
Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 11 RTOCF: Receiver timeout clear flag
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Refer to Section 26.4: USART implementation on
page 777.
Bit 10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 26.4: USART implementation on page 777.
Bit 8 LBDCF: LIN break detection clear flag
Writing 1 to this bit clears the LBDF flag in the USART_ISR register.
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer
to Section 26.4: USART implementation on page 777.
Bit 7 TCBGTCF: Transmission complete before Guard time clear flag
Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
Bit 6 TCCF: Transmission complete clear flag
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Bit 5 TXFECF: TXFIFO empty clear flag
Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Bit 2 NECF: Noise detected clear flag
Writing 1 to this bit clears the NE flag in the USART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USART_ISR register.

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26.8.12 USART receive data register (USART_RDR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. RDR[8:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 261).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

26.8.13 USART transmit data register (USART_TDR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. TDR[8:0]
rw rw rw rw rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The USART_TDR register provides the parallel interface between the internal bus and the
output shift register (see Figure 261).
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE/TXFNF = 1.

RM0454 Rev 5 859/989

862
Universal synchonous receiver transmitter (USART) RM0454

26.8.14 USART prescaler register (USART_PRESC)

This register can only be written when the USART is disabled (UE = 0).
Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRESCALER[3:0]
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 PRESCALER[3:0]: Clock prescaler
The USART input clock can be divided by a prescaler factor:
0000: input clock not divided
0001: input clock divided by 2
0010: input clock divided by 4
0011: input clock divided by 6
0100: input clock divided by 8
0101: input clock divided by 10
0110: input clock divided by 12
0111: input clock divided by 16
1000: input clock divided by 32
1001: input clock divided by 64
1010: input clock divided by 128
1011: input clock divided by 256
Remaining combinations: Reserved
Note: When PRESCALER is programmed with a value different of the allowed ones,
programmed prescaler value is 1011 i.e. input clock divided by 256.

860/989 RM0454 Rev 5

 0x20
0x18
0x14
0x10
0x08
0x04
0x00
0x00

0x1C
0x1C
0x0C
Offset
RM0454

26.8.15

name

enabled

disabled
Register

FIFO mode
FIFO mode

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

USART_ISR
USART_ISR

USART_ICR
USART_CR3
USART_CR2
USART_CR1
USART_CR1

USART_BRR
FIFO enabled

USART_RQR
FIFO disabled

USART_GTPR

USART_RTOR
31

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. RXFFIE
30

0
0
0
0
Res. Res. Res. Res. Res. Res. TXFTCFG[2:0] Res. TXFEIE
29

0
0
0
0
0
Res. Res. Res. Res. Res. Res. FIFOEN FIFOEN
28

0
0
0
0
0
Res. Res. Res. Res. Res. Res. RXFTIE M1 M1
27

0
0
0
0
0
Res. Res. TXFT Res. Res. Res. EOBIE EOBIE

ADD[7:0]

BLEN[7:0]
26

0
0
0
0
0
Res. Res. RXFT Res. Res. Res. RXFTCFG[2:0] RTOIE RTOIE
25

0
0
0
0
0
0
Res. TCBGT TCBGT Res. Res. Res.
USART register map

24

0
0
0
0
0

X X X X
Res. Res. RXFF Res. Res. Res. TCBGTIE
23

0
0
0
0
0

1
Res. Res. TXFE Res. Res. Res. TXFTIE RTOEN
22

0
0
0

0
0
0

0
Res. REACK REACK Res. Res. Res. WUFIE

DEAT[4:0]
DEAT[4:0]

ABRMOD[1:0]
21

0
0
0

0
0
0

0
Res. TEACK TEACK Res. Res. Res.

[1:0]
20

0
0
0
0
0

0
0
0
WUS
WUCF WUF WUF Res. Res. Res. ABREN
19

0
0
0
0

0
0

0
Res. RWU RWU Res. Res. Res. MSBFIRST
18

0
0
0
0

0
0

0
Res. SBKF SBKF Res. Res. Res. DATAINV

SCAR
17

CNT2:0]

0
0
0
0

0
0

0
0
CMCF CMF CMF Res. Res. Res. TXINV
DEDT[4:0]
DEDT[4:0]

RM0454 Rev 5
16

0
0
0

0
0

0
Res. BUSY BUSY Res. Res. Res. Res. RXINV
15

0
0

0
0
0
0

0
0
0
Res. ABRF ABRF Res. DEP SWAP OVER8 OVER8
14

0
0

0
0
0
0

0
0
0
Res. ABRE ABRE Res. DEM LINEN CMIE CMIE
13

0
0

0
0
0
0

0
0
0
0
UDRCF UDR UDR Res. DDRE MME MME
[1:0]

12

0
0

0
0
0
0

0
0
0
0
EOBCF EOBF EOBF Res. OVRDIS M0 M0
STOP

11

0
0

0
0
0
0

0
0
0
0
RTOCF RTOF RTOF Res. ONEBIT CLKEN WAKE WAKE

GT[7:0]

RTO[23:0]
10

0
0

0
0
0
0

0
0
0
Res. CTS CTS Res. CTSIE CPOL PCE PCE
Table 128. USART register map and reset values
The table below gives the USART register map and reset values.

0
0

0
0
0
0

0
0
0
0
CTSCF CTSIF CTSIF Res. CTSE CPHA PS PS
8

0
0

0
0
0
0

0
0
0
0
LBDCF LBDF LBDF Res. RTSE LBCL PEIE PEIE
7

0
0
0

1
1
0
0
0
0

TCBGTCF TXE TXFNF Res. DMAT Res. TXEIE TXFNFIE

BRR[15:0] 6

0
0
0

1
1
0
0
0
0
0

TCCF TC TC Res. DMAR LBDIE TCIE TCIE

5

0
0
0

0
0
0
0
0
0
0

TXFECF RXNE RXFNE Res. SCEN LBDL RXNEIE RXFNEIE

4

0
0
0

0
0
0
0
0
0
0
0

IDLECF IDLE IDLE TXFRQ NACK ADDM7 IDLEIE IDLEIE

3

0
0
0

0
0
0
0
0
0
0
0

ORECF ORE ORE RXFRQ HDSEL DIS_NSS TE TE

PSC[7:0]

0
0
0

0
0
0
0
0
0
0

NECF NE NE MMRQ IRLP Res. RE RE

1

0
0
0

0
0
0
0
0
0
0

FECF FE FE SBKRQ IREN Res. UESM UESM

0

0
0
0

0
0
0
0
0
0
0
0

PECF PE PE ABRRQ EIE SLVEN UE UE

861/989
Universal synchonous receiver transmitter (USART)

862
Universal synchonous receiver transmitter (USART) RM0454

Table 128. USART register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11
name

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
USART_RDR RDR[8:0]
0x24
Reset value 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
USART_TDR TDR[8:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0
USART_ PRESCALE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x2C PRESC R[3:0]
Reset value 0 0 0 0

Refer to Section 2.2: Memory organization for the register boundary addresses.

862/989 RM0454 Rev 5

RM0454 Serial peripheral interface / integrated interchip sound (SPI/I2S)

27 Serial peripheral interface / integrated interchip

sound (SPI/I2S)

27.1 Introduction
The SPI/I²S interface can be used to communicate with external devices using the SPI
protocol or the I2S audio protocol. SPI or I2S mode is selectable by software. SPI Motorola
mode is selected by default after a device reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.
The integrated interchip sound (I2S) protocol is also a synchronous serial communication
interface.It can operate in slave or master mode with half-duplex communication. It can
address four different audio standards including the Philips I2S standard, the MSB- and
LSB-justified standards and the PCM standard.

27.2 SPI main features

• Master or slave operation
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4 to 16-bit data size selection
• Multimaster mode capability
• 8 master mode baud rate prescalers up to fPCLK/2
• Slave mode frequency up to fPCLK/2.
• NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• SPI Motorola support
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte
• Master mode fault, overrun flags with interrupt capability
• CRC Error flag
• Two 32-bit embedded Rx and Tx FIFOs with DMA capability
• Enhanced TI and NSS pulse modes support

RM0454 Rev 5 863/989

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Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0454

27.3 I2S main features

• Half-duplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
• Data format may be 16-bit, 24-bit or 32-bit
• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
• Programmable clock polarity (steady state)
• Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel
sides
• Supported I2S protocols:
– I2S Philips standard
– MSB-justified standard (left-justified)
– LSB-justified standard (right-justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
• Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
• Master clock can be output to drive an external audio component. Ratio is fixed at
256 × FS (where FS is the audio sampling frequency)

27.4 SPI/I2S implementation

The following table describes all the SPI instances and their features embedded in the
devices.

Table 129. STM32G0x0 SPI and SPI/I2S implementation

SPI Features SPI1 / I2S1 SPI2 / I2S2(1) SPI3(1)

Enhanced NSSP & TI modes Yes Yes Yes

I2S support Yes Yes(1) / No No
Hardware CRC calculation Yes Yes Yes
Data size configuration from 4 to 16-bit from 4 to 16-bit from 4 to 16-bit
Rx/Tx FIFO size 32-bit 32-bit 32-bit
Wakeup capability from Low-power Sleep Yes Yes Yes
1. Applies to STM32G0B0xx only.

864/989 RM0454 Rev 5

RM0454 Serial peripheral interface / integrated interchip sound (SPI/I2S)

27.5 SPI functional description

27.5.1 General description

The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram Figure 288.

Figure 288. SPI block diagram

Address and data bus

Read

Rx
FIFO
CRC controller
MOSI
MISO Shift register
RXONLY
CRCEN
CPOL CRCNEXT
CPHA CRCL
Tx DS[0:3]
FIFO
Write Communication
BIDIOE
controller

Baud rate BR[2:0]

SCK Internal NSS
generator

NSS
NSS logic
MS30117V1

Four I/O pins are dedicated to SPI communication with external devices.
• MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.
• MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.
• SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
• NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
– select an individual slave device for communication
– synchronize the data frame or
– detect a conflict between multiple masters
See Section 27.5.5: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.

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27.5.2 Communications between one master and one slave

The SPI allows the MCU to communicate using different configurations, depending on the
device targeted and the application requirements. These configurations use 2 or 3 wires
(with software NSS management) or 3 or 4 wires (with hardware NSS management).
Communication is always initiated by the master.

Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the
shift registers of the master and slave are linked using two unidirectional lines between the
MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the
SCK clock edges provided by the master. The master transmits the data to be sent to the
slave via the MOSI line and receives data from the slave via the MISO line. When the data
frame transfer is complete (all the bits are shifted) the information between the master and
slave is exchanged.

Figure 289. Full-duplex single master/ single slave application

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS (1)
Master Slave

MSv39623V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 27.5.5: Slave select (NSS) pin management.

Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the
SPIx_CR1 register. In this configuration, one single cross connection line is used to link the
shift registers of the master and slave together. During this communication, the data is
synchronously shifted between the shift registers on the SCK clock edge in the transfer
direction selected reciprocally by both master and slave with the BDIOE bit in their
SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin
are free for other application uses and act as GPIOs.

866/989 RM0454 Rev 5

RM0454 Serial peripheral interface / integrated interchip sound (SPI/I2S)

Figure 290. Half-duplex single master/ single slave application

(2)
MISO MISO
Rx shift register Tx shift register
(3)
MOSI 1kΩ (2)
Tx shift register MOSI Rx shift register

SPI clock SCK SCK

generator
NSS (1) NSS(1)
Master Slave

MSv39624V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 27.5.5: Slave select (NSS) pin management.
2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs.
3. A critical situation can happen when communication direction is changed not synchronously between two
nodes working at bidirectionnal mode and new transmitter accesses the common data line while former
transmitter still keeps an opposite value on the line (the value depends on SPI configuration and
communication data). Both nodes then fight while providing opposite output levels on the common line
temporary till next node changes its direction settings correspondingly, too. It is suggested to insert a serial
resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing
between them at this situation.

Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive-
only using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is
used for the transfer between the shift registers of the master and slave. The remaining
MISO and MOSI pins pair is not used for communication and can be used as standard
GPIOs.
• Transmit-only mode (RXONLY=0): The configuration settings are the same as for full-
duplex. The application has to ignore the information captured on the unused input pin.
This pin can be used as a standard GPIO.
• Receive-only mode (RXONLY=1): The application can disable the SPI output function
by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the
pin can be used as a GPIO. The slave continues to receive data from the MOSI pin
while its slave select signal is active (see 27.5.5: Slave select (NSS) pin management).
Received data events appear depending on the data buffer configuration. In the master
configuration, the MOSI output is disabled and the pin can be used as a GPIO. The
clock signal is generated continuously as long as the SPI is enabled. The only way to
stop the clock is to clear the RXONLY bit or the SPE bit and wait until the incoming
pattern from the MISO pin is finished and fills the data buffer structure, depending on its
configuration.

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Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0454

Figure 291. Simplex single master/single slave application (master in transmit-only/

slave in receive-only mode)

(2) MISO MISO

Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS(1)
Master Slave

MSv39625V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 27.5.5: Slave select (NSS) pin management.
2. An accidental input information is captured at the input of transmitter Rx shift register. All the events
associated with the transmitter receive flow must be ignored in standard transmit only mode (e.g. OVF
flag).
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).

27.5.3 Standard multi-slave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to
manage the chip select lines for each slave (see Figure 292.). The master must select one
of the slaves individually by pulling low the GPIO connected to the slave NSS input. When
this is done, a standard master and dedicated slave communication is established.

868/989 RM0454 Rev 5

RM0454 Serial peripheral interface / integrated interchip sound (SPI/I2S)

Figure 292. Master and three independent slaves

NSS (1)

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
IO1 NSS
Master Slave 1
IO2
IO3

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 2

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 3
MSv39626V1

1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see I/O alternate function input/output section (GPIO)).

27.5.4 Multi-master communication

Unless SPI bus is not designed for a multi-master capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.

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Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0454

If potentially both nodes raised their mastering request at the same time a bus conflict event
appears (see mode fault MODF event). Then the user can apply some simple arbitration
process (e.g. to postpone next attempt by predefined different time-outs applied at both
nodes).

Figure 293. Multi-master application

MISO MISO
Rx (Tx) shift register Rx (Tx) shift register
MOSI MOSI
Tx (Rx) shift register Tx (Rx) shift register

SPI clock SCK SCK SPI clock

generator generator
(1)
GPIO NSS

Master NSS(1) GPIO Master

(Slave) (Slave)

MSv39628V1

1. The NSS pin is configured at hardware input mode at both nodes. Its active level enables the MISO line
output control as the passive node is configured as a slave.

27.5.5 Slave select (NSS) pin management

In slave mode, the NSS works as a standard “chip select” input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
• Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.
• Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).
– NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the
MCU is set as master. The NSS pin is managed by the hardware. The NSS signal
is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept
low until the SPI is disabled (SPE =0). A pulse can be generated between
continuous communications if NSS pulse mode is activated (NSSP=1). The SPI
cannot work in multimaster configuration with this NSS setting.
– NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the
master on the bus, this configuration allows multimaster capability. If the NSS pin
is pulled low in this mode, the SPI enters master mode fault state and the device is
automatically reconfigured in slave mode. In slave mode, the NSS pin works as a
standard “chip select” input and the slave is selected while NSS line is at low level.

870/989 RM0454 Rev 5

RM0454 Serial peripheral interface / integrated interchip sound (SPI/I2S)

Figure 294. Hardware/software slave select management

SSI control bit

SSM control bit

NSS Master
Slave mode
Inp. mode
Vdd OK Non active

1 Vss Conflict Active

NSS Input
0
NSS GPIO
pin logic

NSS NSS Output

Output
Control (used in Master mode and NSS
HW management only)

SSOE control bit

NSS external logic NSS internal logic

MSv35526V6

27.5.6 Communication formats

During SPI communication, receive and transmit operations are performed simultaneously.
The serial clock (SCK) synchronizes the shifting and sampling of the information on the data
lines. The communication format depends on the clock phase, the clock polarity and the
data frame format. To be able to communicate together, the master and slaves devices must
follow the same communication format.

Clock phase and polarity controls

Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a
high-level idle state.
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on
each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the
SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge
if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data
capture clock edge.

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Figure 295, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

Figure 295. Data clock timing diagram

CPHA =1
CPOL = 1

CPOL = 0

MOSI(1) MSBit LSBit

MISO(1) MSBit LSBit

NSS (to slave)

Capture strobe

CPHA =0
CPOL = 1

CPOL = 0

MOSI(1) MSBit LSBit

MISO(1) MSBit LSBit

NSS (to slave)

Capture strobe
ai17154e

1. The order of data bits depends on LSBFIRST bit setting.

Data frame format

The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set
from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Whatever the selected data frame size, read access to the FIFO must be aligned with the
FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see Figure 296). During
communication, only bits within the data frame are clocked and transferred.

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Figure 296. Data alignment when data length is not equal to 8-bit or 16-bit
DS <= 8 bits: data is right-aligned on byte DS > 8 bits: data is right-aligned on 16 bit
Example: DS = 5 bit Example: DS = 14 bit

7 5 4 0 15 14 13 0
XXX Data frame TX XX Data frame TX

7 5 4 0 15 14 13 0
000 Data frame RX 00 Data frame RX

MS19589V2

Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.

27.5.7 Configuration of SPI

The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated sections. When a standard communication is to be initialized,
perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a) Configure the serial clock baud rate using the BR[2:0] bits (Note: 4).
b) Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock (CPHA must be
cleared in NSSP mode). (Note: 2 - except the case when CRC is enabled at TI
mode).
c) Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE can't be set at the same time).
d) Configure the LSBFIRST bit to define the frame format (Note: 2).
e) Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is
at idle state).
f) Configure SSM and SSI (Notes: 2 & 3).
g) Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on
NSS if master is configured to prevent MODF error).
3. Write to SPI_CR2 register:
a) Configure the DS[3:0] bits to select the data length for the transfer.
b) Configure SSOE (Notes: 1 & 2 & 3).
c) Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode).
d) Set the NSSP bit if the NSS pulse mode between two data units is required (keep
CHPA and TI bits cleared in NSSP mode).
e) Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read
access size for the SPIx_DR register.
f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode.
4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed.
5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in
DMA registers if the DMA streams are used.

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Note: (1) Step is not required in slave mode.

(2) Step is not required in TI mode.
(3) Step is not required in NSSP mode.
(4) The step is not required in slave mode except slave working at TI mode

27.5.8 Procedure for enabling SPI

It is recommended to enable the SPI slave before the master sends the clock. If not,
undesired data transmission might occur. The data register of the slave must already
contain data to be sent before starting communication with the master (either on the first
edge of the communication clock, or before the end of the ongoing communication if the
clock signal is continuous). The SCK signal must be settled at an idle state level
corresponding to the selected polarity before the SPI slave is enabled.
The master at full-duplex (or in any transmit-only mode) starts to communicate when the
SPI is enabled and TXFIFO is not empty, or with the next write to TXFIFO.
In any master receive only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), master starts
to communicate and the clock starts running immediately after SPI is enabled.
For handling DMA, follow the dedicated section.

27.5.9 Data transmission and reception procedures

RXFIFO and TXFIFO
All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to
work in a continuous flow, and prevents overruns when the data frame size is short. Each
direction has its own FIFO called TXFIFO and RXFIFO. These FIFOs are used in all SPI
modes except for receiver-only mode (slave or master) with CRC calculation enabled (see
Section 27.5.14: CRC calculation).
The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame
format (number of bits in the frame), access size performed on the FIFO data registers (8-bit
or 16-bit), and whether or not data packing is used when accessing the FIFOs (see
Section 27.5.13: TI mode).
A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has
not been read yet. A write access to the SPIx_DR stores the written data in the TXFIFO at
the end of a send queue. The read access must be always aligned with the RXFIFO
threshold configured by the FRXTH bit in SPIx_CR2 register. FTLVL[1:0] and FRLVL[1:0]
bits indicate the current occupancy level of both FIFOs.
A read access to the SPIx_DR register must be managed by the RXNE event. This event is
triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is
reached. When RXNE is cleared, RXFIFO is considered to be empty. In a similar way, write
access of a data frame to be transmitted is managed by the TXE event. This event is
triggered when the TXFIFO level is less than or equal to half of its capacity. Otherwise TXE
is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up to four
data frames, whereas TXFIFO can only store up to three when the data frame format is not
greater than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames
already stored in the TXFIFO when software tries to write more data in 16-bit mode into
TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See
Figure 298 through Figure 301.

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Another way to manage the data exchange is to use DMA (see Communication using DMA
(direct memory addressing)).
If the next data is received when the RXFIFO is full, an overrun event occurs (see
description of OVR flag at Section 27.5.10: SPI status flags). An overrun event can be
polled or handled by an interrupt.
The BSY bit being set indicates ongoing transaction of a current data frame. When the clock
signal runs continuously, the BSY flag stays set between data frames at master but
becomes low for a minimum duration of one SPI clock at slave between each data frame
transfer.

Sequence handling
A few data frames can be passed at single sequence to complete a message. When
transmission is enabled, a sequence begins and continues while any data is present in the
TXFIFO of the master. The clock signal is provided continuously by the master until TXFIFO
becomes empty, then it stops waiting for additional data.
In receive-only modes, half-duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0,
RXONLY=1) the master starts the sequence immediately when both SPI is enabled and
receive-only mode is activated. The clock signal is provided by the master and it does not
stop until either SPI or receive-only mode is disabled by the master. The master receives
data frames continuously up to this moment.
While the master can provide all the transactions in continuous mode (SCK signal is
continuous) it has to respect slave capability to handle data flow and its content at anytime.
When necessary, the master must slow down the communication and provide either a
slower clock or separate frames or data sessions with sufficient delays. Be aware there is no
underflow error signal for master or slave in SPI mode, and data from the slave is always
transacted and processed by the master even if the slave could not prepare it correctly in
time. It is preferable for the slave to use DMA, especially when data frames are shorter and
bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to
select just one of the slaves for communication. In a single slave system it is not necessary
to control the slave with NSS, but it is often better to provide the pulse here too, to
synchronize the slave with the beginning of each data sequence. NSS can be managed by
both software and hardware (see Section 27.5.5: Slave select (NSS) pin management).
When the BSY bit is set it signifies an ongoing data frame transaction. When the dedicated
frame transaction is finished, the RXNE flag is raised. The last bit is just sampled and the
complete data frame is stored in the RXFIFO.

Procedure for disabling the SPI

When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Special care must be taken in packing mode when an odd number of data frames are
transacted to prevent some dummy byte exchange (refer to Data packing section). Before
the SPI is disabled in these modes, the user must follow standard disable procedure. When

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the SPI is disabled at the master transmitter while a frame transaction is ongoing or next
data frame is stored in TXFIFO, the SPI behavior is not guaranteed.
When the master is in any receive only mode, the only way to stop the continuous clock is to
disable the peripheral by SPE=0. This must occur in specific time window within last data
frame transaction just between the sampling time of its first bit and before its last bit transfer
starts (in order to receive a complete number of expected data frames and to prevent any
additional “dummy” data reading after the last valid data frame). Specific procedure must be
followed when disabling SPI in this mode.
Data received but not read remains stored in RXFIFO when the SPI is disabled, and must
be processed the next time the SPI is enabled, before starting a new sequence. To prevent
having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the
correct disabling procedure, or by initializing all the SPI registers with a software reset via
the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the
RCC_APBiRSTR registers).
Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to
check if a transmission session is fully completed. This check can be done in specific cases,
too, when it is necessary to identify the end of ongoing transactions, for example:
• When NSS signal is managed by software and master has to provide proper end of
NSS pulse for slave, or
• When transactions’ streams from DMA or FIFO are completed while the last data frame
or CRC frame transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive only mode is used):
1. Wait until FTLVL[1:0] = 00 (no more data to transmit).
2. Wait until BSY=0 (the last data frame is processed).
3. Disable the SPI (SPE=0).
4. Read data until FRLVL[1:0] = 00 (read all the received data).
The correct disable procedure for certain receive only modes is:
1. Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while
the last data frame is ongoing.
2. Wait until BSY=0 (the last data frame is processed).
3. Read data until FRLVL[1:0] = 00 (read all the received data).
Note: If packing mode is used and an odd number of data frames with a format less than or equal
to 8 bits (fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] =
01, in order to generate the RXNE event to read the last odd data frame and to keep good
FIFO pointer alignment.

Data packing
When the data frame size fits into one byte (less than or equal to 8 bits), data packing is
used automatically when any read or write 16-bit access is performed on the SPIx_DR
register. The double data frame pattern is handled in parallel in this case. At first, the SPI
operates using the pattern stored in the LSB of the accessed word, then with the other half
stored in the MSB. Figure 297 provides an example of data packing mode sequence
handling. Two data frames are sent after the single 16-bit access the SPIx_DR register of
the transmitter. This sequence can generate just one RXNE event in the receiver if the
RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data
frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The

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RxFIFO threshold setting and the following read access must be always kept aligned at the
receiver side, as data can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be
handled. On the transmitter side, writing the last data frame of any odd sequence with an 8-
bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level
for the last data frame received in the odd sequence of frames in order to generate the
RXNE event.

Figure 297. Packing data in FIFO for transmission and reception

NSS

SCK

TXFIFO MOSI RXFIFO

SPIx_DR
SPIx_DR 0x0A 0x0A 0x04 0x0A
0x04 0x0A 0x04 SPI fsm SPI fsm 0x04
& shift & shift 0x04 0x0A

16-bit access when write to data register 16-bit access when read from data register
SPI_DR= 0x040A when TxE=1 SPI_DR= 0x040A when RxNE=1

MS19590V1

1. In this example: Data size DS[3:0] is 4-bit configured, CPOL=0, CPHA=1 and LSBFIRST =0. The Data
storage is always right aligned while the valid bits are performed on the bus only, the content of LSB byte
goes first on the bus, the unused bits are not taken into account on the transmitter side and padded by
zeros at the receiver side.

Communication using DMA (direct memory addressing)

To operate at its maximum speed and to facilitate the data register read/write process
required to avoid overrun, the SPI features a DMA capability, which implements a simple
request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is
set. Separate requests must be issued to the Tx and Rx buffers.
• In transmission, a DMA request is issued each time TXE is set to 1. The DMA then
writes to the SPIx_DR register.
• In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads
the SPIx_DR register.
See Figure 298 through Figure 301.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA
channel. In this case, the OVR flag is set because the data received is not read. When the
SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF
flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI
communication is complete. This is required to avoid corrupting the last transmission before
disabling the SPI or entering the Stop mode. The software must first wait until
FTLVL[1:0]=00 and then until BSY=0.

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When starting communication using DMA, to prevent DMA channel management raising
error events, these steps must be followed in order:
1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is
used.
2. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used.
3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.
4. Enable the SPI by setting the SPE bit.
To close communication it is mandatory to follow these steps in order:
1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.
2. Disable the SPI by following the SPI disable procedure.
3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the
SPI_CR2 register, if DMA Tx and/or DMA Rx are used.

Packing with DMA

If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2
register) packing mode is enabled/disabled automatically depending on the PSIZE value
configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is
equal to 16-bit and SPI data size is less than or equal to 8-bit, then packing mode is
enabled. The DMA then automatically manages the write operations to the SPIx_DR
register.
If data packing mode is used and the number of data to transfer is not a multiple of two, the
LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the
transmission or reception to serve the last DMA transfer (for more details refer to Data
packing on page 876.)

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Communication diagrams
Some typical timing schemes are explained in this section. These schemes are valid no
matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the
LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No
complete configuration of DMA streams is provided.
The following numbered notes are common for Figure 298 on page 880 through Figure 301
on page 883:
1. The slave starts to control MISO line as NSS is active and SPI is enabled, and is
disconnected from the line when one of them is released. Sufficient time must be
provided for the slave to prepare data dedicated to the master in advance before its
transaction starts.
At the master, the SPI peripheral takes control at MOSI and SCK signals (occasionally
at NSS signal as well) only if SPI is enabled. If SPI is disabled the SPI peripheral is
disconnected from GPIO logic, so the levels at these lines depends on GPIO setting
exclusively.
2. At the master, BSY stays active between frames if the communication (clock signal) is
continuous. At the slave, BSY signal always goes down for at least one clock cycle
between data frames.
3. The TXE signal is cleared only if TXFIFO is full.
4. The DMA arbitration process starts just after the TXDMAEN bit is set. The TXE
interrupt is generated just after the TXEIE is set. As the TXE signal is at an active level,
data transfers to TxFIFO start, until TxFIFO becomes full or the DMA transfer
completes.
5. If all the data to be sent can fit into TxFIFO, the DMA Tx TCIF flag can be raised even
before communication on the SPI bus starts. This flag always rises before the SPI
transaction is completed.
6. The CRC value for a package is calculated continuously frame by frame in the
SPIx_TXCRCR and SPIx_RXCRCR registers. The CRC information is processed after
the entire data package has completed, either automatically by DMA (Tx channel must
be set to the number of data frames to be processed) or by SW (the user must handle
CRCNEXT bit during the last data frame processing).
While the CRC value calculated in SPIx_TXCRCR is simply sent out by transmitter,
received CRC information is loaded into RxFIFO and then compared with the
SPIx_RXCRCR register content (CRC error flag can be raised here if any difference).
This is why the user must take care to flush this information from the FIFO, either by
software reading out all the stored content of RxFIFO, or by DMA when the proper
number of data frames is preset for Rx channel (number of data frames + number of
CRC frames) (see the settings at the example assumption).
7. In data packed mode, TxE and RxNE events are paired and each read/write access to
the FIFO is 16 bits wide until the number of data frames are even. If the TxFIFO is ¾
full FTLVL status stays at FIFO full level. That is why the last odd data frame cannot be
stored before the TxFIFO becomes ½ full. This frame is stored into TxFIFO with an 8-
bit access either by software or automatically by DMA when LDMA_TX control is set.
8. To receive the last odd data frame in packed mode, the Rx threshold must be changed
to 8-bit when the last data frame is processed, either by software setting FRXTH=1 or
automatically by a DMA internal signal when LDMA_RX is set.

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Figure 298. Master full-duplex communication

NSS

SCK

BSY 2 2

MOSI MSB DTx1 MSB DTx2 MSB DTx3

SPE

3 3
TXE

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 00 10 11 10 11 10 00

4
MISO DRx1 LSB DRx2 LSB DRx3 LSB

1 1
RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF

MSv19266V2

Assumptions for master full-duplex communication example:

• Data size > 8 bit
If DMA is used:
• Number of Tx frames transacted by DMA is set to 3
• Number of Rx frames transacted by DMA is set to 3
See also : Communication diagrams on page 879 for details about common assumptions
and notes.

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Figure 299. Slave full-duplex communication

NSS

SCK

BSY 2

MISO MSB DTx1 MSB DTx2 MSB DTx3

1

SPE 1

3 3
TXE

4 Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 00 10 11 10 11 10 00

MOSI DRx1 LSB DRx2 LSB DRx3 LSB

RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF

MSv32123V2

Assumptions for slave full-duplex communication example:

• Data size > 8 bit
If DMA is used:
• Number of Tx frames transacted by DMA is set to 3
• Number of Rx frames transacted by DMA is set to 3
See also : Communication diagrams on page 879 for details about common assumptions
and notes.

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Figure 300. Master full-duplex communication with CRC

NSS

SCK

BSY 2

MOSI MSB DTx1 MSB DTx2 MSB CRC

SPE

TXE 3

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DMA or software control at Tx events

FTLVL 00 10 11 10 00

4
MISO DRx1 LSB DRx2 LSB CRC LSB

1 1
RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF 6

MSv32124V2

Assumptions for master full-duplex communication with CRC example:

• Data size = 16 bit
• CRC enabled
If DMA is used:
• Number of Tx frames transacted by DMA is set to 2
• Number of Rx frames transacted by DMA is set to 3
See also : Communication diagrams on page 879 for details about common assumptions
and notes.

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Figure 301. Master full-duplex communication in packed mode

NSS

SCK

BSY 2
DTx1-2 DTx3-4 DTx5

MOSI 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

SPE

3 3
TXE

Enable Tx/Rx DMA or interrupts

DTx1-2 DTx3-4 DTx5 DMA or software control at Tx events

7

FTLVL 00 10 11 10 11 10 01 00

4
MISO 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

1 DRx1-2 DRx3-4 DRx5 1

RXNE

DMA or software control at Rx events DRx1-2 DRx3-4 FRTHX=1 DRx5

8
FRLVL 00 01 10 00 01 10 00 01 00

DMA Tx TICF 5 DMA Rx TICF

MSv32125V2

Assumptions for master full-duplex communication in packed mode example:

• Data size = 5 bit
• Read/write FIFO is performed mostly by 16-bit access
• FRXTH=0
If DMA is used:
• Number of Tx frames to be transacted by DMA is set to 3
• Number of Rx frames to be transacted by DMA is set to 3
• PSIZE for both Tx and Rx DMA channel is set to 16-bit
• LDMA_TX=1 and LDMA_RX=1
See also : Communication diagrams on page 879 for details about common assumptions
and notes.

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27.5.10 SPI status flags

Three status flags are provided for the application to completely monitor the state of the SPI
bus.

Tx buffer empty flag (TXE)

The TXE flag is set when transmission TXFIFO has enough space to store data to send.
TXE flag is linked to the TXFIFO level. The flag goes high and stays high until the TXFIFO
level is lower or equal to 1/2 of the FIFO depth. An interrupt can be generated if the TXEIE
bit in the SPIx_CR2 register is set. The bit is cleared automatically when the TXFIFO level
becomes greater than 1/2.

Rx buffer not empty (RXNE)

The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
• If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or
equal to 1/4 (8-bit).
• If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater
than or equal to 1/2 (16-bit).
An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.
The RXNE is cleared by hardware automatically when the above conditions are no longer
true.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is
busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the
software can disable the SPI or its peripheral clock before entering a low-power mode which
does not provide a clock for the peripheral. This avoids corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions:
• When the SPI is correctly disabled
• When a fault is detected in Master mode (MODF bit set to 1)
• In Master mode, when it finishes a data transmission and no new data is ready to be
sent
• In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
each data transfer.
Note: When the next transmission can be handled immediately by the master (e.g. if the master is
in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and
the BSY flag remains set to '1' between transfers on the master side. Although this is not the
case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the
BSY flags) to handle data transmission or reception operations.

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27.5.11 SPI error flags

An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled
by setting the ERRIE bit.

Overrun flag (OVR)

An overrun condition occurs when data is received by a master or slave and the RXFIFO
has not enough space to store this received data. This can happen if the software or the
DMA did not have enough time to read the previously received data (stored in the RXFIFO)
or when space for data storage is limited e.g. the RXFIFO is not available when CRC is
enabled in receive only mode so in this case the reception buffer is limited into a single data
frame buffer (see Section 27.5.14: CRC calculation).
When an overrun condition occurs, the newly received value does not overwrite the
previous one in the RXFIFO. The newly received value is discarded and all data transmitted
subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register
followed by a read access to the SPI_SR register.

Mode fault (MODF)

Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS
hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the
MODF bit. Master mode fault affects the SPI interface in the following ways:
• The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
• The SPE bit is cleared. This blocks all output from the device and disables the SPI
interface.
• The MSTR bit is cleared, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPIx_SR register while the MODF bit is set.
2. Then write to the SPIx_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state after this clearing sequence. As a security, hardware does
not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the
MODF bit cannot be set except as the result of a previous multimaster conflict.

CRC error (CRCERR)

This flag is used to verify the validity of the value received when the CRCEN bit in the
SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value
received in the shift register does not match the receiver SPIx_RXCRCR value. The flag is
cleared by the software.

TI mode frame format error (FRE)

A TI mode frame format error is detected when an NSS pulse occurs during an ongoing
communication when the SPI is operating in slave mode and configured to conform to the TI
mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI
is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the
next NSS pulse before starting a new transfer. The data may be corrupted since the error
detection may result in the loss of two data bytes.

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The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt
is generated on the NSS error detection. In this case, the SPI should be disabled because
data consistency is no longer guaranteed and communications should be reinitiated by the
master when the slave SPI is enabled again.

27.5.12 NSS pulse mode

This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if
the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first
edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is
generated between two consecutive data frame transfers when NSS stays at high level for
the duration of one clock period at least. This mode allows the slave to latch data. NSSP
pulse mode is designed for applications with a single master-slave pair.
Figure 302 illustrates NSS pin management when NSSP pulse mode is enabled.

Figure 302. NSSP pulse generation in Motorola SPI master mode

Master continuous transfer (CPOL = 1; CPHA = 0; NSSP= 1)

sampling sampling sampling sampling sampling sampling

NSS
output

SCK
output

MOSI
output MSB LSB MSB LSB

MISO
input Do not care MSB LSB Do not care MSB LSB Do not care

tSCK tSCK tSCK tSCK tSCK

4-bits to 16-bits 4-bits to 16-bits

MS19838V1

Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.

27.5.13 TI mode
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ when the current transaction finishes (see Figure 303). Any baud
rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for
the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the

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baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the
formula:

t baud_rate t baud_rate
---------------------- + 4 × t pclk < t release < ---------------------
- + 6 × t pclk
2 2
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is
set.
If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only
mode uses a protocol with one more dummy data bit added after LSB. TI NSS pulse is
generated above this dummy bit clock cycle instead of the LSB in each period.
This feature is not available for Motorola SPI communications (FRF bit set to 0).
Figure 303: TI mode transfer shows the SPI communication waveforms when TI mode is
selected.

Figure 303. TI mode transfer

NSS
g

t RELEASE
in

in

in
er

er

er
pl

pl

pl
gg

gg

gg
m

m
sa

sa

sa
tri

tri

tr i

SCK

MOSI Do not care MSB LSB MSB LSB

MISO 1 or 0 MSB LSB MSB LSB

FRAME 1 FRAME 2

MS19835V2

27.5.14 CRC calculation

Two separate CRC calculators are implemented in order to check the reliability of
transmitted and received data. The SPI offers CRC8 or CRC16 calculation independently of
the frame data length, which can be fixed to 8-bit or 16-bit. For all the other data frame
lengths, no CRC is available.

CRC principle
CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the
SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable
polynomial on each bit. The calculation is processed on the sampling clock edge defined by
the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked
automatically at the end of the data block as well as for transfer managed by CPU or by the
DMA. When a mismatch is detected between the CRC calculated internally on the received
data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption
error. The right procedure for handling the CRC calculation depends on the SPI
configuration and the chosen transfer management.

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Note: The polynomial value should only be odd. No even values are supported.

CRC transfer managed by CPU

Communication starts and continues normally until the last data frame has to be sent or
received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1
register to indicate that the CRC frame transaction follows after the transaction of the
currently processed data frame. The CRCNEXT bit must be set before the end of the last
data frame transaction. CRC calculation is frozen during CRC transaction.
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC
mode only, the reception buffer has to be considered as a single 16-bit buffer used to
receive only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of
data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two
more frames are necessary to send the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the
received value and the value in the SPIx_RXCRC register. Software has to check the
CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or
not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the
SPIx_DR register in order to clear the RXNE flag.

CRC transfer managed by DMA

When SPI communication is enabled with CRC communication and DMA mode, the
transmission and reception of the CRC at the end of communication is automatic (with the
exception of reading CRC data in receive only mode). The CRCNEXT bit does not have to
be handled by the software. The counter for the SPI transmission DMA channel has to be
set to the number of data frames to transmit excluding the CRC frame. On the receiver side,
the received CRC value is handled automatically by DMA at the end of the transaction but
user must take care to flush out received CRC information from RXFIFO as it is always
loaded into it. In full-duplex mode, the counter of the reception DMA channel can be set to
the number of data frames to receive including the CRC, which means, for example, in the
specific case of an 8-bit data frame checked by 16-bit CRC:
DMA_RX = Numb_of_data + 2
In receive only mode, the DMA reception channel counter should contain only the amount of
data transferred, excluding the CRC calculation. Then based on the complete transfer from
DMA, all the CRC values must be read back by software from FIFO as it works as a single
buffer in this mode.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if
corruption occurred during the transfer.
If packing mode is used, the LDMA_RX bit needs managing if the number of data is odd.

Resetting the SPIx_TXCRC and SPIx_RXCRC values

The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is
sampled after a CRC phase. This allows the use of DMA circular mode (not available in
receive-only mode) in order to transfer data without any interruption, (several data blocks
covered by intermediate CRC checking phases).

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If the SPI is disabled during a communication the following sequence must be followed:
1. Disable the SPI
2. Clear the CRCEN bit
3. Enable the CRCEN bit
4. Enable the SPI
Note: When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released. That is why
the CRC calculation cannot be used at NSS Pulse mode when NSS hardware mode should
be applied at slave normally.
At TI mode, despite the fact that clock phase and clock polarity setting is fixed and
independent on SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to be
kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by SPI disable sequence with re-enable the CRCEN bit
described above at both master and slave side, else CRC calculation can be corrupted at
this specific mode.

27.6 SPI interrupts

During SPI communication an interrupt can be generated by the following events:
• Transmit TXFIFO ready to be loaded
• Data received in Receive RXFIFO
• Master mode fault
• Overrun error
• TI frame format error
• CRC protocol error

Interrupts can be enabled and disabled separately.

Table 130. SPI interrupt requests

Interrupt event Event flag Enable Control bit

Transmit TXFIFO ready to be loaded TXE TXEIE

Data received in RXFIFO RXNE RXNEIE
Master Mode fault event MODF
Overrun error OVR
ERRIE
TI frame format error FRE
CRC protocol error CRCERR

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27.7 I2S functional description

27.7.1 I2S general description

The block diagram of the I2S is shown in Figure 304.

Figure 304. I2S block diagram

Address and data bus

Tx buffer

CRC CH
16-bit BSY OVR MODF UDR TxE RxNE FRE
ERR SIDE

MOSI/SD

Shift register
MISO LSB first Communication
16-bit control
Rx buffer

NSS/WS

I2SCFG I2SSTD CK DATLEN CH

[1:0] [1:0] POL [1:0] LEN

I2S
I2SE
MOD

Master control logic

Bidi Bidi CRC CRC Rx

SSM SSI
mode OE EN Next DFF only

SPI LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
baud rate generator First

CK

I2S clock generator

I2S_CK

I2SMOD

MCK I2SxCLK
MCKOE ODD I2SDIV[7:0]

MS32126V1

1. MCK is mapped on the MISO pin.

The SPI can function as an audio I2S interface when the I2S capability is enabled (by
setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same
pins, flags and interrupts as the SPI.

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The I2S shares three common pins with the SPI:

• SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
• WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
• CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
• MCK: Master Clock (mapped separately) is used, when the I2S is configured in master
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × fS, where
fS is the audio sampling frequency.
The I2S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I2S mode. One is linked to the clock generator
configuration SPIx_I2SPR and the other one is a generic I2S configuration register
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I2S mode. Likewise, the
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
The I2S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.

27.7.2 Supported audio protocols

The three-line bus has to handle only audio data generally time-multiplexed on two
channels: the right channel and the left channel. However there is only one 16-bit register
for transmission or reception. So, it is up to the software to write into the data register the
appropriate value corresponding to each channel side, or to read the data from the data
register and to identify the corresponding channel by checking the CHSIDE bit in the
SPIx_SR register. Channel left is always sent first followed by the channel right (CHSIDE
has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
• 16-bit data packed in a 16-bit frame
• 16-bit data packed in a 32-bit frame
• 24-bit data packed in a 32-bit frame
• 32-bit data packed in a 32-bit frame
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant
bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only
one read/write operation).
The 24-bit and 32-bit data frames need two CPU read or write operations to/from the
SPIx_DR register or two DMA operations if the DMA is preferred for the application. For 24-
bit data frame specifically, the 8 non-significant bits are extended to 32 bits with 0-bits (by
hardware).

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For all data formats and communication standards, the most significant bit is always sent
first (MSB first).
The I2S interface supports four audio standards, configurable using the I2SSTD[1:0] and
PCMSYNC bits in the SPIx_I2SCFGR register.

I2S Philips standard

For this standard, the WS signal is used to indicate which channel is being transmitted. It is
activated one CK clock cycle before the first bit (MSB) is available.

Figure 305. I2S Philips protocol waveforms (16/32-bit full accuracy)

CK

WS transmission reception

Can be 16-bit or 32-bit

SD MSB LSB MSB

Channel left
Channel
right
MS19591V1

Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.

Figure 306. I2S Philips standard waveforms (24-bit frame)

CK

WS Transmission Reception

24-bit data 8-bit remaining 0 forced

SD
MSB LSB

Channel left 32-bit

Channel right

MS19592V1

This mode needs two write or read operations to/from the SPIx_DR register.
• In transmission mode:
If 0x8EAA33 has to be sent (24-bit):

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Figure 307. Transmitting 0x8EAA33

First write to Data register Second write to Data register

0x8EAA 0x33XX

Only the 8 MSB are sent

to compare the 24 bits
8 LSBs have no meaning
and can be anything

MS19593V2

• In reception mode:
If data 0x8EAA33 is received:

Figure 308. Receiving 0x8EAA33

First read to Data register Second read to Data register

0x8EAA 0x33XX

Only the 8 MSB are sent

to compare the 24 bits
8 LSBs have no meaning
and can be anything

MS19594V1

Figure 309. I2S Philips standard (16-bit extended to 32-bit packet frame)

CK

WS Transmission Reception

16-bit data 16-bit remaining 0 forced

SD
MSB LSB

Channel left 32-bit

Channel right

MS19599V1

When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in Figure 310 is required.

Figure 310. Example of 16-bit data frame extended to 32-bit channel frame
Only one access to SPIx_DR

0x76A3

MS19595V1

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For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send.
This takes place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).

MSB justified standard

For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.

Figure 311. MSB Justified 16-bit or 32-bit full-accuracy length

CK

WS Transmission Reception

16- or 32 bit data

SD
MSB LSB MSB

Channel left
Channel right

MS30100 V1

Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).

Figure 312. MSB justified 24-bit frame length

CK

WS Transmission Reception

24 bit data 8-bit remaining

SD 0 forced
MSB LSB
Channel left 32-bit

Channel right

MS30101V1

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Figure 313. MSB justified 16-bit extended to 32-bit packet frame

CK

WS Transmission Reception

16-bit data 16-bit remaining

SD 0 forced
MSB LSB
Channel left 32-bit

Channel right

MS30102V1

LSB justified standard

This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).
The sampling of the input and output signals is the same as for the I2S Philips standard.

Figure 314. LSB justified 16-bit or 32-bit full-accuracy

CK

WS
Transmission Reception
16- or 32-bit data
SD
MSB LSB MSB
Channel left

Channel right
MS30103V1

Figure 315. LSB justified 24-bit frame length

CK

WS Reception
Transmission
8-bit data 24-bit remaining
SD 0 forced
MSB LSB

Channel left 32-bit

Channel right

MS30104V1

• In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register
are required by software or by DMA. The operations are shown below.

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Figure 316. Operations required to transmit 0x3478AE

First write to Data register Second write to Data register

conditioned by TXE=1 conditioned by TXE=1

0xXX34 0x78AE

Only the 8 LSB of the

half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs. MS19596V1

• In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.

Figure 317. Operations required to receive 0x3478AE

First read from Data register Second read from Data register
conditioned by RXNE=1 conditioned by RXNE=1

0xXX34 0x78AE

Only the 8 LSB of the

half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.

MS19597V1

Figure 318. LSB justified 16-bit extended to 32-bit packet frame

CK

Reception
WS
Transmission
16-bit data 16-bit remaining
SD 0 forced
MSB LSB

Channel left 32-bit

Channel right
MS30105V1

When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 319 is required.

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Figure 319. Example of 16-bit data frame extended to 32-bit channel frame

Only one access to the SPIx-DR register

0x76A3

MS19598V1

In transmission mode, when a TXE event occurs, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.

PCM standard
For the PCM standard, there is no need to use channel-side information. The two PCM
modes (short and long frame) are available and configurable using the PCMSYNC bit in
SPIx_I2SCFGR register.
In PCM mode, the output signals (WS, SD) are sampled on the rising edge of CK signal.
The input signals (WS, SD) are captured on the falling edge of CK.
Note that CK and WS are configured as output in MASTER mode.

Figure 320. PCM standard waveforms (16-bit)

CK

WS
short frame
13-bits
WS
long frame

SD MSB LSB MSB

MS30106V1

For long frame synchronization, the WS signal assertion time is fixed to 13 bits in master
mode.
For short frame synchronization, the WS synchronization signal is only one cycle long.

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Figure 321. PCM standard waveforms (16-bit extended to 32-bit packet frame)

CK

WS
short frame
Up to 13-bits
WS
long frame
16 bits

SD MSB LSB

MS30107V1

Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.

27.7.3 Start-up description

TheFigure 322 shows how the serial interface is handled in MASTER mode, when the
SPI/I2S is enabled (via I2SE bit). It shows as well the effect of CKPOL on the generated
signals.

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Figure 322. Start sequence in master mode

Master I2S Philips Standard

WS (O)

CK (O), CKPOL = 0

CK (O), CKPOL = 1

dum Left sample Right sample

SD (O)
I2SE

Master I2S MSB or LSB justified

WS (O)

CK (O), CKPOL = 0

CK (O), CKPOL = 1
dum Left sample Right sample
SD (O)

I2SE

Master PCM short frame

WS (O)

CK (O), CKPOL = 0

CK (O), CKPOL = 1
dum Sample1 Sample 2
SD (O)
I2SE
Master PCM long frame
WS (O)

CK (O), CKPOL = 0

CK (O), CKPOL = 1
dum Sample1 Sample 2
SD (O)
I2SE
dum: not significant data
MSv37520V2

In slave mode, the way the frame synchronization is detected, depends on the value of
ASTRTEN bit.
If ASTRTEN = 0, when the audio interface is enabled (I2SE = 1), then the hardware waits for
the appropriate transition on the incoming WS signal, using the CK signal.

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The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used,
or a rising edge for other standards. The falling edge is detected by sampling first WS to 1
and then to 0, and vice-versa for the rising edge detection.
If ASTRTEN = 1, the user has to enable the audio interface before the WS becomes active.
This means that the I2SE bit must be set to 1 when WS = 1 for I2S Philips standard, or when
WS = 0 for other standards.

27.7.4 Clock generator

The I2S bit rate determines the data flow on the I2S data line and the I2S clock signal
frequency.
I2S bit rate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I2S bit rate is calculated as follows:
I2S bit rate = 16 × 2 × fS
It is: I2S bit rate = 32 x 2 x fS if the packet length is 32-bit wide.

Figure 323. Audio sampling frequency definition

16-or 32-bit left 16-or 32-bit

channel right channel

32- or 64-bits
FS
sampling point sampling point

FS : audio sampling frequency

MS30108V1

When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.

Figure 324. I2S clock generator architecture

MCK

I²SxCLK 8-bit linear divider

+ reshaping stage 0
Div2 0
Divider by 4 1 CK
1

MCKOE
I²SMOD

CHLEN

MCKOE ODD I²SDIV[7:0]

MS30109V1

1. Where x can be 2 or 3.

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Figure 324 presents the communication clock architecture. The I2SxCLK clock is provided
by the reset and clock controller (RCC) of the product. The I2SxCLK clock can be
asynchronous with respect to the SPI/I2S APB clock.

Warning: In addition, it is mandatory to keep the I2SxCLK frequency

higher or equal to the APB clock used by the SPI/I2S block. If
this condition is not respected, the SPI/I2S does not work
properly.

The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range).
In order to reach the desired frequency, the linear divider needs to be programmed
according to the formulas below:

For I2S modes:

When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):

Fs = F I2SxCLK
--------------------------------------------------------------------------------------------------------
256 × ( ( 2 × I2SDIV ) + ODD )

When the master clock is disabled (MCKOE bit cleared):

Fs = F I2SxCLK
--------------------------------------------------------------------------------------------------------------------------------------------------------------
32 × ( CHLEN + 1 ) × ( ( 2 × I2SDIV ) + ODD )
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.

For PCM modes:

When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):

Fs = F I2SxCLK
--------------------------------------------------------------------------------------------------------
128 × ( ( 2 × I2SDIV ) + ODD )

When the master clock is disabled (MCKOE bit cleared):

Fs = F I2SxCLK
--------------------------------------------------------------------------------------------------------------------------------------------------------------
16 × ( CHLEN + 1 ) × ( ( 2 × I2SDIV ) + ODD )
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
Where FS is the audio sampling frequency, and FI2SxCLKis the frequency of the kernel clock
provided to the SPI/I2S block.

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Note: Note that I2SDIV must be strictly higher than 1.

Table 131 provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.

Table 131. Audio-frequency precision using standard 8 MHz HSE(1)

SYSCLK Data Target fs
I2SDIV I2SODD MCLK Real fs (kHz) Error
(MHz) length (Hz)

48 16 8 0 No 96000 93750 2.3438%

48 32 4 0 No 96000 93750 2.3438%
48 16 15 1 No 48000 48387.0968 0.8065%
48 32 8 0 No 48000 46875 2.3438%
48 16 17 0 No 44100 44117.647 0.0400%
48 32 8 1 No 44100 44117.647 0.0400%
48 16 23 1 No 32000 31914.8936 0.2660%
48 32 11 1 No 32000 32608.696 1.9022%
48 16 34 0 No 22050 22058.8235 0.0400%
48 32 17 0 No 22050 22058.8235 0.0400%
48 16 47 0 No 16000 15957.4468 0.2660%
48 32 23 1 No 16000 15957.447 0.2660%
48 16 68 0 No 11025 11029.4118 0.0400%
48 32 34 0 No 11025 11029.412 0.0400%
48 16 94 0 No 8000 7978.7234 0.2660%
48 32 47 0 No 8000 7978.7234 0.2660%
48 16 2 0 Yes 48000 46875 2.3430%
48 32 2 0 Yes 48000 46875 2.3430%
48 16 2 0 Yes 44100 46875 6.2925%
48 32 2 0 Yes 44100 46875 6.2925%
48 16 3 0 Yes 32000 31250 2.3438%
48 32 3 0 Yes 32000 31250 2.3438%
48 16 4 1 Yes 22050 20833.333 5.5178%
48 32 4 1 Yes 22050 20833.333 5.5178%
48 16 6 0 Yes 16000 15625 2.3438%
48 32 6 0 Yes 16000 15625 2.3438%
48 16 8 1 Yes 11025 11029.4118 0.0400%
48 32 8 1 Yes 11025 11029.4118 0.0400%
48 16 11 1 Yes 8000 8152.17391 1.9022%
48 32 11 1 Yes 8000 8152.17391 1.9022%

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1. This table gives only example values for different clock configurations. Other configurations allowing
optimum clock precision are possible.

27.7.5 I2S master mode

The I2S can be configured in master mode. This means that the serial clock is generated on
the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not,
controlled by the MCKOE bit in the SPIx_I2SPR register.

Procedure
1. Select the I2SDIV[7:0] bits in the SPIx_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency. The ODD bit in the SPIx_I2SPR
register also has to be defined.
2. Select the CKPOL bit to define the steady level for the communication clock. Set the
MCKOE bit in the SPIx_I2SPR register if the master clock MCK needs to be provided
to the external DAC/ADC audio component (the I2SDIV and ODD values should be
computed depending on the state of the MCK output, for more details refer to
Section 27.7.4: Clock generator).
3. Set the I2SMOD bit in the SPIx_I2SCFGR register to activate the I2S functions and
choose the I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length
through the DATLEN[1:0] bits and the number of bits per channel by configuring the
CHLEN bit. Select also the I2S master mode and direction (Transmitter or Receiver)
through the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
4. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
5. The I2SE bit in SPIx_I2SCFGR register must be set.
WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in
SPIx_I2SPR is set.

Transmission sequence
The transmission sequence begins when a half-word is written into the Tx buffer.
Lets assume the first data written into the Tx buffer corresponds to the left channel data.
When data are transferred from the Tx buffer to the shift register, TXE is set and data
corresponding to the right channel have to be written into the Tx buffer. The CHSIDE flag
indicates which channel is to be transmitted. It has a meaning when the TXE flag is set
because the CHSIDE flag is updated when TXE goes high.
A full frame has to be considered as a left channel data transmission followed by a right
channel data transmission. It is not possible to have a partial frame where only the left
channel is sent.
The data half-word is parallel loaded into the 16-bit shift register during the first bit
transmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is
set after each transfer from the Tx buffer to the shift register and an interrupt is generated if
the TXEIE bit in the SPIx_CR2 register is set.
For more details about the write operations depending on the I2S standard mode selected,
refer to Section 27.7.2: Supported audio protocols).
To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR
register with the next data to transmit before the end of the current transmission.

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To switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.

Reception sequence
The operating mode is the same as for transmission mode except for the point 3 (refer to the
procedure described in Section 27.7.5: I2S master mode), where the configuration should
set the master reception mode through the I2SCFG[1:0] bits.
Whatever the data or channel length, the audio data are received by 16-bit packets. This
means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated
if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length
configuration, the audio value received for a right or left channel may result from one or two
receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the
I2S cell.
For more details about the read operations depending on the I2S standard mode selected,
refer to Section 27.7.2: Supported audio protocols.
If data are received while the previously received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I2S, specific actions are required to ensure that the I2S completes the
transfer cycle properly without initiating a new data transfer. The sequence depends on the
configuration of the data and channel lengths, and on the audio protocol mode selected. In
the case of:
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1)
using the LSB justified mode (I2SSTD = 10)
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait 17 I2S clock cycles (using a software loop)
c) Disable the I2S (I2SE = 0)
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in
MSB justified, I2S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11,
respectively)
a) Wait for the last RXNE
b) Then wait 1 I2S clock cycle (using a software loop)
c) Disable the I2S (I2SE = 0)
• For all other combinations of DATLEN and CHLEN, whatever the audio mode selected
through the I2SSTD bits, carry out the following sequence to switch off the I2S:
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait one I2S clock cycle (using a software loop)
c) Disable the I2S (I2SE = 0)
Note: The BSY flag is kept low during transfers.

27.7.6 I2S slave mode

For the slave configuration, the I2S can be configured in transmission or reception mode.
The operating mode is following mainly the same rules as described for the I2S master

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configuration. In slave mode, there is no clock to be generated by the I2S interface. The
clock and WS signals are input from the external master connected to the I2S interface.
There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
1. Set the I2SMOD bit in the SPIx_I2SCFGR register to select I2S mode and choose the
I2S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0]
bits and the number of bits per channel for the frame configuring the CHLEN bit. Select
also the mode (transmission or reception) for the slave through the I2SCFG[1:0] bits in
SPIx_I2SCFGR register.
2. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
3. The I2SE bit in SPIx_I2SCFGR register must be set.

Transmission sequence
The transmission sequence begins when the external master device sends the clock and
when the NSS_WS signal requests the transfer of data. The slave has to be enabled before
the external master starts the communication. The I2S data register has to be loaded before
the master initiates the communication.
For the I2S, MSB justified and LSB justified modes, the first data item to be written into the
data register corresponds to the data for the left channel. When the communication starts,
the data are transferred from the Tx buffer to the shift register. The TXE flag is then set in
order to request the right channel data to be written into the I2S data register.
The CHSIDE flag indicates which channel is to be transmitted. Compared to the master
transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the
external master. This means that the slave needs to be ready to transmit the first data
before the clock is generated by the master. WS assertion corresponds to left channel
transmitted first.
Note: The I2SE has to be written at least two PCLK cycles before the first clock of the master
comes on the CK line.
The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus)
during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first.
The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt
is generated if the TXEIE bit in the SPIx_CR2 register is set.
Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.
For more details about the write operations depending on the I2S standard mode selected,
refer to Section 27.7.2: Supported audio protocols.
To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR
register with the next data to transmit before the end of the current transmission. An
underrun flag is set and an interrupt may be generated if the data are not written into the
SPIx_DR register before the first clock edge of the next data communication. This indicates
to the software that the transferred data are wrong. If the ERRIE bit is set into the SPIx_CR2
register, an interrupt is generated when the UDR flag in the SPIx_SR register goes high. In
this case, it is mandatory to switch off the I2S and to restart a data transfer starting from the
left channel.
To switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and
BSY = 0.

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Reception sequence
The operating mode is the same as for the transmission mode except for the point 1 (refer to
the procedure described in Section 27.7.6: I2S slave mode), where the configuration should
set the master reception mode using the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
Whatever the data length or the channel length, the audio data are received by 16-bit
packets. This means that each time the RX buffer is full, the RXNE flag in the SPIx_SR
register is set and an interrupt is generated if the RXNEIE bit is set in the SPIx_CR2
register. Depending on the data length and channel length configuration, the audio value
received for a right or left channel may result from one or two receptions into the RX buffer.
The CHSIDE flag is updated each time data are received to be read from the SPIx_DR
register. It is sensitive to the external WS line managed by the external master component.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
For more details about the read operations depending the I2S standard mode selected, refer
to Section 27.7.2: Supported audio protocols.
If data are received while the preceding received data have not yet been read, an overrun is
generated and the OVR flag is set. If the bit ERRIE is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving
the last RXNE = 1.
Note: The external master components should have the capability of sending/receiving data in 16-
bit or 32-bit packets via an audio channel.

27.7.7 I2S status flags

Three status flags are provided for the application to fully monitor the state of the I2S bus.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates
the state of the communication layer of the I2S.
When BSY is set, it indicates that the I2S is busy communicating. There is one exception in
master receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.
The BSY flag is useful to detect the end of a transfer if the software needs to disable the
I2S. This avoids corrupting the last transfer. For this, the procedure described below must
be strictly respected.
The BSY flag is set when a transfer starts, except when the I2S is in master receiver mode.
The BSY flag is cleared:
• When a transfer completes (except in master transmit mode, in which the
communication is supposed to be continuous)
• When the I2S is disabled
When communication is continuous:
• In master transmit mode, the BSY flag is kept high during all the transfers
• In slave mode, the BSY flag goes low for one I2S clock cycle between each transfer
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the
TXE and RXNE flags instead.

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Tx buffer empty flag (TXE)

When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted
can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to
be transmitted. It is also reset when the I2S is disabled (I2SE bit is reset).

RX buffer not empty (RXNE)

When set, this flag indicates that there are valid received data in the RX Buffer. It is reset
when SPIx_DR register is read.

Channel Side flag (CHSIDE)

In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel
side to which the data to transfer on SD has to belong. In case of an underrun error event in
slave transmission mode, this flag is not reliable and I2S needs to be switched off and
switched on before resuming the communication.
In reception mode, this flag is refreshed when data are received into SPIx_DR. It indicates
from which channel side data have been received. Note that in case of error (like OVR) this
flag becomes meaningless and the I2S should be reset by disabling and then enabling it
(with configuration if it needs changing).
This flag has no meaning in the PCM standard (for both Short and Long frame modes).
When the OVR or UDR flag in the SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also
set, an interrupt is generated. This interrupt can be cleared by reading the SPIx_SR status
register (once the interrupt source has been cleared).

27.7.8 I2S error flags

There are three error flags for the I2S cell.

Underrun flag (UDR)

In slave transmission mode this flag is set when the first clock for data transmission appears
while the software has not yet loaded any value into SPIx_DR. It is available when the
I2SMOD bit in the SPIx_I2SCFGR register is set. An interrupt may be generated if the
ERRIE bit in the SPIx_CR2 register is set.
The UDR bit is cleared by a read operation on the SPIx_SR register.

Overrun flag (OVR)

This flag is set when data are received and the previous data have not yet been read from
the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated
if the ERRIE bit is set in the SPIx_CR2 register.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPIx_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPIx_DR register followed by a
read access to the SPIx_SR register.

Frame error flag (FRE)

This flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the
external master is changing the WS line while the slave is not expecting this change. If the

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synchronization is lost, the following steps are required to recover from this state and
resynchronize the external master device with the I2S slave device:
1. Disable the I2S.
2. Enable it again when the correct level is detected on the WS line (WS line is high in I2S
mode or low for MSB- or LSB-justified or PCM modes.
Desynchronization between master and slave devices may be due to noisy environment on
the CK communication clock or on the WS frame synchronization line. An error interrupt can
be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.

27.7.9 DMA features

In I2S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I2S mode since there is no data
transfer protection system.

27.8 I2S interrupts

Table 132 provides the list of I2S interrupts.

Table 132. I2S interrupt requests

Interrupt event Event flag Enable control bit

Transmit buffer empty flag TXE TXEIE

Receive buffer not empty flag RXNE RXNEIE
Overrun error OVR
Underrun error UDR ERRIE
Frame error flag FRE

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27.9 SPI and I2S registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR
in addition can be accessed by 8-bit access.

27.9.1 SPI control register 1 (SPIx_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIM CRCE CRCN RXONL LSBFIR
BIDIOE CRCL SSM SSI SPE BR[2:0] MSTR CPOL CPHA
ODE N EXT Y ST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 BIDIMODE: Bidirectional data mode enable.

This bit enables half-duplex communication using common single bidirectional data line.
Keep RXONLY bit clear when bidirectional mode is active.
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
Note: This bit is not used in I2S mode.
Bit 14 BIDIOE: Output enable in bidirectional mode
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional
mode.
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
This bit is not used in I2S mode.
Bit 13 CRCEN: Hardware CRC calculation enable
0: CRC calculation disabled
1: CRC calculation enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
This bit is not used in I2S mode.
Bit 12 CRCNEXT: Transmit CRC next
0: Next transmit value is from Tx buffer.
1: Next transmit value is from Tx CRC register.
Note: This bit has to be written as soon as the last data is written in the SPIx_DR register.
This bit is not used in I2S mode.
Bit 11 CRCL: CRC length
This bit is set and cleared by software to select the CRC length.
0: 8-bit CRC length
1: 16-bit CRC length
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
This bit is not used in I2S mode.

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Bit 10 RXONLY: Receive only mode enabled.

This bit enables simplex communication using a single unidirectional line to receive data
exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also
useful in a multislave system in which this particular slave is not accessed, the output from
the accessed slave is not corrupted.
0: Full-duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
Note: This bit is not used in I2S mode.
Bit 9 SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: This bit is not used in I2S mode and SPI TI mode.
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the I/O value of the NSS pin is ignored.
Note: This bit is not used in I2S mode and SPI TI mode.
Bit 7 LSBFIRST: Frame format
0: data is transmitted / received with the MSB first
1: data is transmitted / received with the LSB first
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in I2S mode and SPI TI mode.
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: When disabling the SPI, follow the procedure described in Procedure for disabling the
SPI on page 875.
This bit is not used in I2S mode.
Bits 5:3 BR[2:0]: Baud rate control
000: fPCLK/2
001: fPCLK/4
010: fPCLK/8
011: fPCLK/16
100: fPCLK/32
101: fPCLK/64
110: fPCLK/128
111: fPCLK/256
Note: These bits should not be changed when communication is ongoing.
These bits are not used in I2S mode.
Bit 2 MSTR: Master selection
0: Slave configuration
1: Master configuration
Note: This bit should not be changed when communication is ongoing.
This bit is not used in I2S mode.

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Bit 1 CPOL: Clock polarity

0: CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied
at TI mode.
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: This bit should not be changed when communication is ongoing.
This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied
at TI mode.

27.9.2 SPI control register 2 (SPIx_CR2)

Address offset: 0x04
Reset value: 0x0700

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA LDMA FRXT
Res. DS[3:0] TXEIE RXNEIE ERRIE FRF NSSP SSOE TXDMAEN RXDMAEN
_TX _RX H
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 LDMA_TX: Last DMA transfer for transmission
This bit is used in data packing mode, to define if the total number of data to transmit by DMA
is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set
and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit
wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 875 if the CRCEN bit is set.
This bit is not used in I²S mode.
Bit 13 LDMA_RX: Last DMA transfer for reception
This bit is used in data packing mode, to define if the total number of data to receive by DMA
is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set
and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit
wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 875 if the CRCEN bit is set.
This bit is not used in I²S mode.
Bit 12 FRXTH: FIFO reception threshold
This bit is used to set the threshold of the RXFIFO that triggers an RXNE event
0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Note: This bit is not used in I2S mode.

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Bits 11:8 DS[3:0]: Data size

These bits configure the data length for SPI transfers.
0000: Not used
0001: Not used
0010: Not used
0011: 4-bit
0100: 5-bit
0101: 6-bit
0110: 7-bit
0111: 8-bit
1000: 9-bit
1001: 10-bit
1010: 11-bit
1011: 12-bit
1100: 13-bit
1101: 14-bit
1110: 15-bit
1111: 16-bit
If software attempts to write one of the “Not used” values, they are forced to the value “0111”
(8-bit)
Note: These bits are not used in I2S mode.
Bit 7 TXEIE: Tx buffer empty interrupt enable
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
Bit 6 RXNEIE: RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
Bit 5 ERRIE: Error interrupt enable
This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).
0: Error interrupt is masked
1: Error interrupt is enabled
Bit 4 FRF: Frame format
0: SPI Motorola mode
1 SPI TI mode
Note: This bit must be written only when the SPI is disabled (SPE=0).
This bit is not used in I2S mode.
Bit 3 NSSP: NSS pulse management
This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two
consecutive data when doing continuous transfers. In the case of a single data transfer, it
forces the NSS pin high level after the transfer.
It has no meaning if CPHA = ’1’, or FRF = ’1’.
0: No NSS pulse
1: NSS pulse generated
Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
2. This bit is not used in I2S mode and SPI TI mode.

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Bit 2 SSOE: SS output enable

0: SS output is disabled in master mode and the SPI interface can work in multimaster
configuration
1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI
interface cannot work in a multimaster environment.
Note: This bit is not used in I2S mode and SPI TI mode.
Bit 1 TXDMAEN: Tx buffer DMA enable
When this bit is set, a DMA request is generated whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
Bit 0 RXDMAEN: Rx buffer DMA enable
When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

27.9.3 SPI status register (SPIx_SR)

Address offset: 0x08
Reset value: 0x0002

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCE
Res. Res. Res. FTLVL[1:0] FRLVL[1:0] FRE BSY OVR MODF UDR CHSIDE TXE RXNE
RR
r r r r r r r r rc_w0 r r r r

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:11 FTLVL[1:0]: FIFO transmission level
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)
Note: This bit is not used in I2S mode.
Bits 10:9 FRLVL[1:0]: FIFO reception level
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full
Note: These bits are not used in I²S mode and in SPI receive-only mode while CRC
calculation is enabled.
Bit 8 FRE: Frame format error
This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 27.5.11: SPI
error flags and Section 27.7.8: I2S error flags.
This flag is set by hardware and reset when SPIx_SR is read by software.
0: No frame format error
1: A frame format error occurred

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Bit 7 BSY: Busy flag

0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and
Procedure for disabling the SPI on page 875.
Bit 6 OVR: Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on
page 907 for the software sequence.
Bit 5 MODF: Mode fault
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault
(MODF) on page 885 for the software sequence.
Note: This bit is not used in I2S mode.
Bit 4 CRCERR: CRC error flag
0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
Note: This flag is set by hardware and cleared by software writing 0.
This bit is not used in I2S mode.
Bit 3 UDR: Underrun flag
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on
page 907 for the software sequence.
Note: This bit is not used in SPI mode.
Bit 2 CHSIDE: Channel side
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Note: This bit is not used in SPI mode. It has no significance in PCM mode.
Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty

27.9.4 SPI data register (SPIx_DR)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 15:0 DR[15:0]: Data register

Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 27.5.9: Data transmission and reception procedures).
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.

27.9.5 SPI CRC polynomial register (SPIx_CRCPR)

Address offset: 0x10
Reset value: 0x0007
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CRCPOLY[15:0]: CRC polynomial register

This register contains the polynomial for the CRC calculation.
The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be
configured as required.

Note: The polynomial value should be odd only. No even value is supported.

27.9.6 SPI Rx CRC register (SPIx_RXCRCR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC[15:0]
r r r r r r r r r r r r r r r r

Bits 15:0 RXCRC[15:0]: Rx CRC register

When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in
the SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY Flag is set could return an incorrect value.
These bits are not used in I2S mode.

27.9.7 SPI Tx CRC register (SPIx_TXCRCR)

Address offset: 0x18

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Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC[15:0]
r r r r r r r r r r r r r r r r

Bits 15:0 TXCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY flag is set could return an incorrect value.
These bits are not used in I2S mode.

27.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)

Address offset: 0x1C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTR
Res. Res. Res. I2SMOD I2SE I2SCFG[1:0] PCMSYNC Res. I2SSTD[1:0] CKPOL DATLEN[1:0] CHLEN
TEN
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 ASTRTEN: Asynchronous start enable.
0: The Asynchronous start is disabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and an appropriate transition is detected on the WS signal.
1: The Asynchronous start is enabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and the appropriate level is detected on the WS signal.
Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used,
or a rising edge for other standards.
The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high
level for other standards.
Please refer to Section 27.7.3: Start-up description for additional information.
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI is disabled.

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Bit 10 I2SE: I2S enable

0: I2S peripheral is disabled
1: I2S peripheral is enabled
Note: This bit is not used in SPI mode.
Bits 9:8 I2SCFG[1:0]: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: These bits should be configured when the I2S is disabled.
They are not used in SPI mode.
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used).
It is not used in SPI mode.
Bit 6 Reserved, must be kept at reset value.
Bits 5:4 I2SSTD[1:0]: I2S standard selection
00: I2S Philips standard
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I2S standards, refer to Section 27.7.2 on page 891
Note: For correct operation, these bits should be configured when the I2S is disabled.
They are not used in SPI mode.
Bit 3 CKPOL: Inactive state clock polarity
0: I2S clock inactive state is low level
1: I2S clock inactive state is high level
Note: For correct operation, this bit should be configured when the I2S is disabled.
It is not used in SPI mode.
The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and
WS signals.
Bits 2:1 DATLEN[1:0]: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I2S is disabled.
They are not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in.
Note: For correct operation, this bit should be configured when the I2S is disabled.
It is not used in SPI mode.

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27.9.9 SPIx_I2S prescaler register (SPIx_I2SPR)

Address offset: 0x20
Reset value: 0x0002

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. MCKOE ODD I2SDIV[7:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in
master mode.
It is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: Real divider value is = I2SDIV *2
1: Real divider value is = (I2SDIV * 2) + 1
Refer to Section 27.7.3 on page 898.
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in
master mode.
It is not used in SPI mode.
Bits 7:0 I2SDIV[7:0]: I2S linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 27.7.3 on page 898.
Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is
in master mode.
They are not used in SPI mode.

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 0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0454

27.9.10

SPIx_SR

SPIx_DR
SPIx_CR2
SPIx_CR1
Register

Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SPIx_I2SPR
SPIx_CRCPR

SPIx_TXCRCR
SPIx_RXCRCR

SPIx_I2SCFGR
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
SPI/I2S register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0454 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0

Res. Res. Res. Res. BIDIMODE 15

0
0
0
0
0
0

Res. Res. Res. LDMA_TX BIDIOE 14

0
0
0
0
0
0

Res. Res. Res. LDMA_RX CRCEN 13

0
0
0
0
0
0
0
0
Table 133 shows the SPI/I2S register map and reset values.

Res. ASTRTEN FRXTH CRCNEXT 12

FTLVL[1:0]

0
0
0
0
0
0
0
0

Res. I2SMOD CRCL 11

Table 133. SPI/I2S register map and reset values

0
0
0
0
0
0
1
0

Res. I2SE
FRLVL[1:0]
RXONLY 10
0
0

0
0
0
0
0
0
1

MCKOE SSM 9
DS[3:0]

Refer to Section 2.2 on page 44 for the register boundary addresses.

I2SCFG[1:0]

0
0
0
0

0
0
0
1
0

ODD FRE SSI 8

0
0
0
0
0
0
0
0

0
PCMSYNC BSY TXEIE LSBFIRST 7
DR[15:0]

0
0
0
0
0

0
0
0

TXCRC[15:0]
RXCRC[15:0]

Res. OVR RXNEIE SPE 6

CRCPOLY[15:0]

0
0
0
0
0

0
0
0
0

MODF ERRIE 5
I2SSTD

0
0
0
0
0

0
0
0
0

CRCERR FRF 4
BR [2:0]

0
0
0
0
0

0
0
0
0

CKPOL UDR NSSP 3

I2SDIV[7:0]
0
0
1
0
0

0
0
0
0

CHSIDE SSOE MSTR 2

DATLEN[1:0]
0
0
1
0
1
0
0

1
0
TXE TXDMAEN CPOL 1
0
0
1
0
0
0
0

0
0
CHLEN RXNE RXDMAEN CPHA 0
Serial peripheral interface / integrated interchip sound (SPI/I2S)

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28 Universal serial bus full-speed host/device interface

(USB)

28.1 Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported, which permits to stop the device clocks for low-power
consumption.

28.2 USB main features

• USB specification version 2.0 full-speed compliant
• Supports both Host and Device modes
• Configurable number of endpoints from 1 to 8
• Dedicated packet buffer memory (SRAM) of 2048 bytes
• Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint/channel support
• USB Suspend/Resume operations
• Frame locked clock pulse generation
• USB 2.0 Link Power Management support (Device mode only)
• Battery Charging Specification Revision 1.2 support (Device mode only)
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)

28.3 USB implementation

Table 134 describes the USB implementation in the devices.

Table 134. STM32G0x0 USB implementation

USB features(1) USB

Host mode X
Number of endpoints 8
Size of dedicated packet buffer memory SRAM 2048 bytes
Dedicated packet buffer memory SRAM access scheme 32 bits
USB 2.0 Link Power Management (LPM) support in device X
Battery Charging Detection (BCD) support for device X
Embedded pull-up resistor on USB_DP line X
1. X= supported

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28.4 USB functional description

Figure 325 shows the block diagram of the USB peripheral.

Figure 325. USB peripheral block diagram

DP DM NOE

USB PHY
USB clock (48 MHz)

Embedded Analog PCLK

BCD
pull-up transceiver

Suspend timer
Control
RX-TX Clock recovery
registers and logic

Endpoint/
Control
channel Interrupt
selection registers and logic
S.I.E.

Packet buffer Host frame

interface scheduler
Endpoint/channel Endpoint/channel
registers registers

Register
Register Interrupt
Arbiter Packet buffer mapper
mapper mapper
memory

APB wrapper

APB interface

PCLK APB bus IRQs to NVIC

MSv66262V2

General description and Device mode functionality

The USB peripheral provides a USB-compliant connection between the function
implemented by the microcontroller and an external USB function which could be a host PC
but also a USB Device. Data transfer between the external USB host or device and the
system memory occurs through a dedicated packet buffer memory accessed directly by the
USB peripheral. This dedicated memory size is 2048 bytes, and up to 16 mono-directional
or 8 bidirectional endpoints can be used. The USB peripheral interfaces with the external
USB Host or Device, detecting token packets, handling data transmission/reception, and
processing handshake packets as required by the USB standard. Transaction formatting is
performed by the hardware, including CRC generation and checking.

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Each endpoint/channel is associated with a buffer description block indicating where the
endpoint/channel-related memory area is located, how large it is or how many bytes must
be transmitted. When a token for a valid function/endpoint pair is recognized by the USB
peripheral, the related data transfer (if required and if the endpoint/channel is configured)
takes place. The data buffered by the USB peripheral are loaded in an internal 16-bit
register and memory access to the dedicated buffer is performed. When all the data have
been transferred, if needed, the proper handshake packet over the USB is generated or
expected according to the direction of the transfer.
At the end of the transaction, an endpoint/channel-specific interrupt is generated, reading
status registers and/or using different interrupt response routines. The microcontroller can
determine:
• which endpoint/channel has to be served,
• which type of transaction took place, if errors occurred (bit stuffing, format, CRC,
protocol, missing ACK, over/underrun, etc.).
Special support is offered to isochronous transfers and high throughput bulk transfers,
implementing a double buffer usage, which permits to always have an available buffer for
the USB peripheral while the microcontroller uses the other one.
A special bit THR512 in register USB_ISTR allows notification of 512 bytes being received
in (or transmitted from) the buffer. This bit must be used for long ISO packets (from 512 to
1023 bytes) as it facilitates early start or read/write of data. In this way, the first 512 bytes
can be handled by software while avoiding use of double buffer mode. This bit works when
only one ISO endpoint is configured.
The unit can be placed in low-power mode (SUSPEND mode), by writing in the control
register, whenever required. At this time, all static power dissipation is avoided, and the USB
clock can be slowed down or stopped. The detection of activity at the USB inputs, while in
low-power mode, wakes the device up asynchronously. A special interrupt source can be
connected directly to a wakeup line to permit the system to immediately restart the normal
clock generation and/or support direct clock start/stop.

Host mode and specific functionality

A single bit, HOST, in register USB_CNTR permits Host mode to be activated. Host mode
functionality permits the USB to talk to a remote peripheral. Supported functionality is
aligned to Device mode and uses the same register structures to manage the buffers. The
same number of endpoints can be supported in Host mode, however in Host mode the
terminology “channel” is preferred, as each channel is in reality a combination of the
connected device and the endpoint on that device. The basic mechanisms for packet
transmission and reception are the same as those supported in Device mode.
When operating in Host mode, the USB is in charge of the bus and in order to do this must
issue transaction requests corresponding to active periodic and non-periodic endpoints. A
host frame scheduler assures efficient use of the frame. Connection to hubs is supported.
Connection to low speed devices is supported, both with a direct connection and through a
hub.
Double-buffered mode, as previously described in Device mode, is also supported in Host
mode, in both bulk and isochronous channels. The THR512 functionality is also supported
(but as in Device mode) only for ISO traffic.
Note: Unlike in Device mode, where there is a detection of battery charging capability (in order to
facilitate fast charging), there is no integrated support in Host mode to present battery

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charging capability (CDP or DCP cases in the standard), the host port is always presented
as a default standard data port (SDP).
Note: For LPM (link power management) this feature is not supported in Host mode.

28.4.1 Description of USB blocks used in both Device and Host modes
The USB peripheral implements all the features related to USB interfacing, which include
the following blocks:
• USB physical interface (USB PHY): this block is maintaining the electrical interface to
an external USB host. It contains the differential analog transceiver itself, controllable
embedded pull-up resistor (connected to USB_DP line) and support for battery
charging detection (BCD), multiplexed on same USB_DP and USB_DM lines. The
output enable control signal of the analog transceiver (active low) is provided externally
on USB_NOE. It can be used to drive some activity LED or to provide information about
the actual communication direction to some other circuitry.
• Serial interface engine (SIE): the functions of this block include: synchronization
pattern recognition, bit-stuffing, CRC generation and checking, PID
verification/generation, and handshake evaluation. It must interface with the USB
transceivers and uses the virtual buffers provided by the packet buffer interface for
local data storage. This unit also generates signals according to USB peripheral
events, such as start of frame (SOF), USB_Reset, data errors etc. and to endpoint
related events like end of transmission or correct reception of a packet; these signals
are then used to generate interrupts.
• Timer: this block generates a start-of-frame locked clock pulse and detects a global
suspend (from the host) when no traffic has been received for 3 ms.
• Packet buffer interface: this block manages the local memory implementing a set of
buffers in a flexible way, both for transmission and reception. It can choose the proper
buffer according to requests coming from the SIE and locate them in the memory
addresses pointed by the endpoint/channel registers. It increments the address after
each exchanged byte until the end of packet, keeping track of the number of
exchanged bytes and preventing the buffer to overrun the maximum capacity.
• Endpoint/channel-related registers: each endpoint/channel has an associated register
containing the endpoint/channel type and its current status. For mono-
directional/single-buffer endpoints, a single register can be used to implement two
distinct endpoints. The number of registers is 8, allowing up to 16 mono-
directional/single-buffer or up to 7 double-buffer endpoints in any combination. For
example the USB peripheral can be programmed to have 4 double buffer endpoints
and 8 single-buffer/mono-directional endpoints.
• Control registers: these are the registers containing information about the status of the
whole USB peripheral and used to force some USB events, such as resume and
power-down.
• Interrupt registers: these contain the interrupt masks and a record of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.
Note: * Endpoint/channel 0 is always used for control transfer in single-buffer mode.
The USB peripheral is connected to the APB1 bus through an APB1 interface, containing
the following blocks:
• Packet memory: this is the local memory that physically contains the packet buffers. It
can be used by the packet buffer interface, which creates the data structure and can be

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accessed directly by the application software. The size of the packet memory is
2048 bytes, structured as 512 words of 32 bits.
• Arbiter: this block accepts memory requests coming from the APB1 bus and from the
USB interface. It resolves the conflicts by giving priority to APB1 accesses, while
always reserving half of the memory bandwidth to complete all USB transfers. This
time-duplex scheme implements a virtual dual-port SRAM that allows memory access,
while an USB transaction is happening. Multiword APB1 transfers of any length are
also allowed by this scheme.
• Register mapper: this block collects the various byte-wide and bit-wide registers of the
USB peripheral in a structured 32-bit wide word set addressed by the APB1.
• APB1 wrapper: this provides an interface to the APB1 for the memory and register. It
also maps the whole USB peripheral in the APB1 address space.
• Interrupt mapper: this block is used to select how the possible USB events can
generate interrupts and map them to the NVIC.

28.4.2 Description of host frame scheduler (HFS) specific to Host mode

The host frame scheduler is the hardware machine in charge to submit host channel
requests on the bus according to the USB priority order and bandwidth access rules.
Host channels are divided in two categories:
– Periodic channels: isochronous and interrupt traffic types. With guaranteed
bandwith access.
– Non-periodic channels: bulk and control traffic types. With best effort service.
The host frame scheduler organizes the full-speed frame in 3 sequential windows
– Periodic service window
– Non-periodic service window
– Black security window
At the start of a new frame the host scheduler:
1. First considers all periodic channels which were active (STAT bits VALID) at the start of
frame
2. Executes single round of service of periodic channels, the periodic service window, in
hardware priority order from CH#1 to CH#8. For bidirectional channels it executes the
OUT direction first
3. When the periodic round is finished, HFS closes the periodic service window and stops
servicing periodic traffic even if some periodic channel was re-enabled or some new
channel was enabled after the SOF.
4. Starts servicing all non-periodic channels which are currently active (STAT bits VALID)
in hardware priority order from CH#1 to CH#8. For bidirectional channels it executes
the OUT direction first.
5. Executes multiple round-robin service cycles of non-periodic channels until almost the
end of frame
6. Non periodic traffic can be requested at any time and is serviced by HFS with best
effort latency, with the exception of a black security window at the end of the frame
where new injected requests are directly postponed to the next frame to avoid babbles.
This is also true for pending transactions which have not been serviced ahead of the
security window.

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28.5 Programming considerations for Device and Host modes

In the following sections, the expected interactions between the USB peripheral and the
application program are described, in order to ease application software development.

28.5.1 Generic USB Device programming

This part describes the main tasks required of the application software in order to obtain
USB compliant behavior. The actions related to the most general USB events are taken into
account and paragraphs are dedicated to the special cases of double-buffered endpoints
and isochronous transfers. Apart from system reset, an action is always initiated by the USB
peripheral, driven by one of the USB events described below.

28.5.2 System and power-on reset

Upon system and power-on reset, the first operation the application software should perform
is to provide all required clock signals to the USB peripheral and subsequently de-assert its
reset signal so to be able to access its registers. The whole initialization sequence is
hereafter described.
As a first step application software needs to activate register macrocell clock and de-assert
macrocell specific reset signal using related control bits provided by device clock
management logic.
After that, the analog part of the device related to the USB transceiver must be switched on
using the PDWN bit in CNTR register, which requires a special handling. This bit is intended
to switch on the internal voltage references that supply the port transceiver. This circuit has
a defined startup time (tSTARTUP specified in the datasheet) during which the behavior of the
USB transceiver is not defined. It is thus necessary to wait this time, after setting the PDWN
bit in the CNTR register, before removing the reset condition on the USB part (by clearing
the USBRST bit in the CNTR register). Clearing the ISTR register removes any spurious
pending interrupt before any other macrocell operation is enabled.
At system reset, the microcontroller must initialize all required registers and the packet
buffer description table, to make the USB peripheral able to properly generate interrupts and
data transfers. All registers not specific to any endpoint/channel must be initialized
according to the needs of application software (choice of enabled interrupts, chosen
address of packet buffers, etc.). Then the process continues as for the USB reset case (see
further paragraph).

USB bus reset (RST_DCON interrupt) in Device mode

When this event occurs, the USB peripheral is put in the same conditions it is left by the
system reset after the initialization described in the previous paragraph: communication is
disabled in all endpoint registers (the USB peripheral does not respond to any packet). As a
response to the USB reset event, the USB function must be enabled, having as USB
address 0, implementing only the default control endpoint (endpoint address is 0 too). This
is accomplished by setting the enable function (EF) bit of the USB_DADDR register and
initializing the CHEP0R register and its related packet buffers accordingly. During USB
enumeration process, the host assigns a unique address to this device, which must be
written in the ADD[6:0] bits of the USB_DADDR register, and configures any other
necessary endpoint.

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When a RST_DCON interrupt is received, the application software is responsible to enable

again the default endpoint of USB function 0 within 10 ms from the end of the reset
sequence which triggered the interrupt.

USB bus reset in Host mode

In Host mode a bus reset is activated by setting the USBRST bit of the USB_CNTR register.
It should subsequently be cleared by software once the minimum active reset time from the
standard has been respected.

Structure and usage of packet buffers

Each bidirectional endpoint may receive or transmit data over the bus. The received data is
stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request
and waits for its acknowledgment. Since the packet buffer memory has also to be accessed
by the microcontroller, an arbitration logic takes care of the access conflicts, using half
APB1 cycle for microcontroller access and the remaining half for the USB peripheral
access. In this way, both agents can operate as if the packet memory would be a dual-port
SRAM, without being aware of any conflict even when the microcontroller is performing
back-to-back accesses. The USB peripheral logic uses a dedicated clock. The frequency of
this dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this
can be different from the clock used for the interface to the APB1 bus. Different clock
configurations are possible where the APB1 clock frequency can be higher or lower than the
USB peripheral one.
Note: Due to USB data rate and packet memory interface requirements, the APB1 clock must
have a minimum frequency of 12 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory. Each table entry is associated to an endpoint register and it is
composed of two 32-bit words so that table start address must always be aligned to an 8-
byte boundary. Buffer descriptor table entries are described in Section 28.6.2: Buffer
descriptor table. If an endpoint is unidirectional and it is neither an isochronous nor a
double-buffered bulk, only one packet buffer is required (the one related to the supported
transfer direction). Other table locations related to unsupported transfer directions or
unused endpoints, are available to the user. Isochronous and double-buffered bulk
endpoints have special handling of packet buffers (Refer to Section 28.5.5: Isochronous
transfers in Device mode and Section 28.5.3: Double-buffered endpoints and usage in
Device mode respectively). The relationship between buffer description table entries and
packet buffer areas is depicted in Figure 326.
For Host mode different sections explain the buffer usage model, notably Section 28.5.6:
Isochronous transfers in Host mode and Section 28.5.4: Double buffered channels: usage in
Host mode.

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Figure 326. Packet buffer areas with examples of buffer description table locations

Available buffer descriptor Available buffer address range

address range starting from offset 0x40
starting from offset 0x00

Buffer for
double-buffered
IN endpoint 3
..
.
Buffer for
double-buffered
OUT endpoint 2
..
.
Transmission buffer
for
single-buffered
endpoint 1
..
0x1C CHEP_RXTXBD_3* [TX] .
0x18 CHEP_TXRXBD_3 [TX]
0x14 CHEP_RXTXBD_2 [RX] Reception buffer for
0x10 CHEP_TXRXBD_2* [RX] endpoint 0
0x0C CHEP_RXTXBD_1 [RX]
Not used
0x08 CHEP_TXRXBD_1 [TX]
0x04 CHEP_RXTXBD_0 [RX]
0x00 CHEP_TXRXBD_0 [TX] Transmission buffer
for endpoint 0

Packet buffers
(*) indicates alternate mode. MSv32129V2

Each packet buffer is used either during reception or transmission starting from the bottom.
The USB peripheral never changes the contents of memory locations adjacent to the
allocated memory buffers; if a packet bigger than the allocated buffer length is received
(buffer overrun condition) the data is copied to the memory only up to the last available
location.

Endpoint initialization
The first step to initialize an endpoint is to write appropriate values to the
ADDRn_TX/ADDRn_RX fields in the CHEP_TXBD_n and CHEP_RXBD_n registers (in
SRAM) so that the USB peripheral finds the data to be transmitted already available and the
data to be received can be buffered. The UTYPE bits in the USB_CHEPnR register must be
set according to the endpoint type, eventually using the EPKIND bit to enable any special
required feature. On the transmit side, the endpoint must be enabled using the STATTX bits
in the USB_CHEPnR register and COUNTn_TX must be initialized. For reception, STATRX
bits must be set to enable reception and COUNTn_RX must be written with the allocated
buffer size using the BLSIZE and NUM_BLOCK fields. Unidirectional endpoints, except
isochronous and double-buffered bulk endpoints, need to initialize only bits and registers
related to the supported direction. Once the transmission and/or reception are enabled,
register USB_CHEPnR and locations ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX
(respectively), should not be modified by the application software, as the hardware can

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change their value on the fly. When the data transfer operation is completed, notified by a
CTR interrupt event, they can be accessed again to re-enable a new operation.

Data transmission in Device mode (IN packets)

When receiving an IN token packet, if the received address matches a configured and valid
endpoint, the USB peripheral accesses the contents of CHEP_TXBD_n (fields ADDRn_TX
and COUNTn_TX) inside the buffer descriptor table entry related to the addressed endpoint.
The content of these locations is stored in its internal 16-bit registers ADDR and COUNT
(not accessible by software). The packet memory is accessed again to read the first byte to
be transmitted (refer to Structure and usage of packet buffers on page 926) and the USB
peripheral starts sending a DATA0 or DATA1 PID according to USB_CHEPnR bit DTOGTX.
When the PID is completed, the first byte, read from buffer memory, is loaded into the output
shift register to be transmitted on the USB bus. After the last data byte is transmitted, the
computed CRC is sent. If the addressed endpoint is not valid, a NAK or STALL handshake
packet is sent instead of the data packet, according to STATTX bits in the USB_CHEPnR
register.
The ADDRn_TX field in the internal register CHEP_TXBD_n is used as a pointer to the
current buffer memory location while COUNT is used to count the number of remaining
bytes to be transmitted. Each half-word read from the packet buffer memory is transmitted
over the USB bus starting from the least significant byte. Transmission buffer memory is
read starting from the address pointed by ADDRn_TX for COUNTn_TX/4 words. If a
transmitted packet is composed of an odd number of bytes, only the lower half of the last
half-word accessed is used.
On receiving the ACK receipt by the host, the USB_CHEPnR register is updated in the
following way: DTOGTX bit is toggled, the endpoint is made invalid by setting
STATTX = 10 (NAK) and bit VTTX is set. The application software must first identify the
endpoint, which is requesting microcontroller attention by examining the IDN and DIR bits in
the USB_ISTR register. Servicing of the VTTX event starts, clearing the interrupt bit; the
application software then prepares another buffer full of data to be sent, updates the
COUNTn_TX table location with the number of byte to be transmitted during the next
transfer, and finally sets STATTX to 11 (VALID) to re-enable transmission. While the
STATTX bits are equal to 10 (NAK), any IN request addressed to that endpoint is NAKed,
indicating a flow control condition: the USB host retries the transaction until it succeeds. It is
mandatory to execute the sequence of operations in the above mentioned order to avoid
losing the notification of a second IN transaction addressed to the same endpoint
immediately following the one which triggered the CTR interrupt.

Data transmission in Host mode (OUT packets)

Data transmission in Host mode follows the same general principles as Device mode. The
main differences are due to the protocol. For example the host initiates the transmission
whereas the device responds to the incoming token.
ADDRn_TX should be set to the location in the packet memory reserved for the packet for
transmission. The contents of an OUT packet are then written to that address in the packet
memory and COUNTn_TX should be updated (when necessary) to indicate the number of
bytes in the packet.
DEVADDR should be written for the correct endpoint and then STATTX should be set to 11
(VALID) in order to trigger the transmit. The transmission is then scheduled by the HFS.
After a successful transmission the CTR interrupt (correct transfer) is triggered. By
examining IDN and DIR bits, the corresponding channel and direction is understood. On the

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indicated channel, the STATTX field now has transitioned to DISABLE. In the case of a NAK
being received (when the peripheral is not ready) STATTX is now in NAK. In the case of a
STALL response, STATTX is in STALL. In this last case, the bus should be reset.
On receiving the ACK receipt by the device, the USB_CHEPnR register is updated in the
following way: DTOGTX bit is toggled.
An error condition is signaled via the bits VTTX and ERR_TX in the case of:
• No handshake being received in time
• False EOP
• Bit stuffing error
• Invalid handshake PID

Data reception in Device mode (OUT and SETUP packets)

These two tokens are handled by the USB peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
fields inside the buffer descriptor table entry related to the addressed endpoint. The content
of the ADDRn_RX field is stored directly in its internal register ADDR. Internal register
COUNT is now reset and the values of BLSIZE and NUM_BLOCK bit fields, which are read
within USB_CHEP_RXBD_n content, are used to initialize BUF_COUNT, an internal 16-bit
counter, which is used to check the buffer overrun condition (all these internal registers are
not accessible by software). Data bytes subsequently received by the USB peripheral are
packed in half-words (the first byte received is stored as least significant byte) and then
transferred to the packet buffer starting from the address contained in the internal ADDR
register while BUF_COUNT is decremented and COUNT is incremented at each byte
transfer. When the end of DATA packet is detected, the correctness of the received CRC is
tested and only if no errors occurred during the reception, an ACK handshake packet is sent
back to the transmitting host.
In case of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.), data
bytes are still copied in the packet memory buffer, at least until the error detection point, but
the ACK packet is not sent and the ERR bit in USB_ISTR register is set. However, there is
usually no software action required in this case: the USB peripheral recovers from reception
errors and remains ready for the next transaction to come. If the addressed endpoint is not
valid, a NAK or STALL handshake packet is sent instead of the ACK, according to bits
STATRX in the USB_CHEPnR register, and no data is written in the reception memory
buffers.
Reception memory buffer locations are written starting from the address contained in the
ADDRn_RX for a number of bytes corresponding to the received data packet length, or up
to the last allocated memory location, as defined by BLSIZE and NUM_BLOCK, whichever
comes first. In this way, the USB peripheral never writes beyond the end of the allocated
reception memory buffer area. If the length of the data packet payload (actual number of
bytes used by the application) is greater than the allocated buffer, the USB peripheral
detects a buffer overrun condition. In this case, a STALL handshake is sent instead of the
usual ACK to notify the problem to the host, no interrupt is generated and the transaction is
considered failed.
When the transaction is completed correctly, by sending the ACK handshake packet, the
internal COUNT register is copied back in the COUNTn_RX location inside the buffer
description table entry, leaving unaffected BLSIZE and NUM_BLOCK fields, which normally

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do not require to be re-written, and the USB_CHEPnR register is updated in the following
way: DTOGRX bit is toggled, the endpoint is made invalid by setting STATRX = 10 (NAK)
and bit VTRX is set. If the transaction has failed due to errors or buffer overrun condition,
none of the previously listed actions take place. The application software must first identify
the endpoint, which is requesting microcontroller attention by examining the IDN and DIR
bits in the USB_ISTR register. The VTRX event is serviced by first determining the
transaction type (SETUP bit in the USB_CHEPnR register); the application software must
clear the interrupt flag bit and get the number of received bytes reading the COUNTn_RX
location inside the buffer description table entry related to the endpoint being processed.
After the received data is processed, the application software should set the STATRX bits to
11 (VALID) in the USB_CHEPnR, enabling further transactions. While the STATRX bits are
equal to 10 (NAK), any OUT request addressed to that endpoint is NAKed, indicating a flow
control condition: the USB host retries the transaction until it succeeds. It is mandatory to
execute the sequence of operations in the above mentioned order to avoid losing the
notification of a second OUT transaction addressed to the same endpoint following
immediately the one which triggered the CTR interrupt.
Data reception in Host mode (IN packets)
Data reception in Host mode follows the same general principles as Device mode. The main
differences are again due to the protocol. In the device, data can be received or not,
depending on readiness after previous operations, whereas the host only requests receive
data when it is ready and able to store them.
ADDRn_TX should be set to the location in the packet memory reserved for the packet for
transmission. The contents received in the data phase response to the IN token packet are
then written to that address in the packet memory and COUNTn_TX gets updated by
hardware during this process to indicate the number of bytes in the packet.
DEVADDR should be written for the correct endpoint and then STATRX should be set to
VALID in order to trigger the reception. The reception is then scheduled by the HFS.
After a successful reception the interrupt CTR (correct transfer) is triggered. By examining
IDN and DIR bits, the corresponding channel and direction is understood. On the indicated
channel, the STATRX field now has transitioned to DISABLE. In the case of a NAK being
received (when the peripheral is not ready) STATRX now is in NAK. In the case of a STALL
response, STATRX is in STALL. In this last case, the bus should be reset. During an IN
packet an error condition is signaled via the bits VTRX and ERR_RX in case of:
• False EOP
• Bit stuffing error
• Wrong CRC

Control transfers in Device mode

Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only and are very similar to
OUT ones (data reception) except that the values of DTOGTX and DTOGRX bits of the
addressed endpoint registers are set to 1 and 0 respectively, to initialize the control transfer,
and both STATTX and STATRX are set to 10 (NAK) to let software decide if subsequent
transactions must be IN or OUT depending on the SETUP contents. A control endpoint must
check SETUP bit in the USB_CHEPnR register at each VTRX event to distinguish normal
OUT transactions from SETUP ones. A USB Device can determine the number and
direction of data stages by interpreting the data transferred in the SETUP stage, and is

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required to STALL the transaction in the case of errors. To do so, at all data stages before
the last, the unused direction should be set to STALL, so that, if the host reverses the
transfer direction too soon, it gets a STALL as a status stage.
While enabling the last data stage, the opposite direction should be set to NAK, so that, if
the host reverses the transfer direction (to perform the status stage) immediately, it is kept
waiting for the completion of the control operation. If the control operation completes
successfully, the software changes NAK to VALID, otherwise to STALL. At the same time, if
the status stage is an OUT, the STATUS_OUT (EPKIND in the USB_CHEPnR register) bit
should be set, so that an error is generated if a status transaction is performed with non-
zero data. When the status transaction is serviced, the application clears the STATUS_OUT
bit and sets STATRX to VALID (to accept a new command) and STATTX to NAK (to delay a
possible status stage immediately following the next setup).
Since the USB specification states that a SETUP packet cannot be answered with a
handshake different from ACK, eventually aborting a previously issued command to start
the new one, the USB logic does not permit a control endpoint to answer with a NAK or
STALL packet to a SETUP token received from the host.
When the STATRX bits are set to 01 (STALL) or 10 (NAK) and a SETUP token is received,
the USB accepts the data, performing the required data transfers and sends back an ACK
handshake. If that endpoint has a previously issued VTRX request not yet acknowledged by
the application (for example VTRX bit is still set from a previously completed reception), the
USB discards the SETUP transaction and does not answer with any handshake packet
regardless of its state, simulating a reception error and forcing the host to send the SETUP
token again. This is done to avoid losing the notification of a SETUP transaction addressed
to the same endpoint immediately following the transaction, which triggered the VTRX
interrupt.

Control transfers in Host mode

Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only. A control endpoint
must set the SETUP bit in the USB_CHEPnR register. The values of DTOGTX and
DTOGRX bits of the addressed endpoint registers are set to 0. Depending on whether it is a
control write or control read then STATTX or STATRX are set to 11 (ACTIVE) in order to
trigger the control transfer via the host frame scheduler.
On receiving a CTR interrupt the channel (device address and endpoint) can be determined
by examining IDN and DIR bits. Devices are expected to NAK every control unless the
packet is corrupted in which case they do not acknowledge. The situation is reflected in the
value of STATTX.
In the case of an error condition the ERR bit gets set. One possible case is where a CRC
error is seen at the device, in this case no ACK is returned to the host. The host sees no
ACK and after an appropriate delay this generates a timeout error with ERR_TX set (which
can generate an interrupt).

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28.5.3 Double-buffered endpoints and usage in Device mode

All different endpoint types defined by the USB standard represent different traffic models,
and describe the typical requirements of different kind of data transfer operations. When
large portions of data are to be transferred between the host PC and the USB function, the
bulk endpoint type is the most suited model. This is because the host schedules bulk
transactions so as to fill all the available bandwidth in the frame, maximizing the actual
transfer rate as long as the USB function is ready to handle a bulk transaction addressed to
it. If the USB function is still busy with the previous transaction when the next one arrives, it
answers with a NAK handshake and the host PC issues the same transaction again until the
USB function is ready to handle it, reducing the actual transfer rate due to the bandwidth
occupied by re-transmissions. For this reason, a dedicated feature called ‘double-buffering’
can be used with bulk endpoints.
When ‘double-buffering’ is activated, data toggle sequencing is used to select, which buffer
is to be used by the USB peripheral to perform the required data transfers, using both
‘transmission’ and ‘reception’ packet memory areas to manage buffer swapping on each
successful transaction in order to always have a complete buffer to be used by the
application, while the USB peripheral fills the other one. For example, during an OUT
transaction directed to a ‘reception’ double-buffered bulk endpoint, while one buffer is being
filled with new data coming from the USB host, the other one is available for the
microcontroller software usage (the same would happen with a ‘transmission’ double-
buffered bulk endpoint and an IN transaction).
Since the swapped buffer management requires the usage of all 4 buffer description table
locations hosting the address pointer and the length of the allocated memory buffers, the
USB_CHEPnR registers used to implement double-buffered bulk endpoints are forced to be
used as unidirectional ones. Therefore, only one STAT bit pair must be set at a value
different from 00 (DISABLED): STATRX if the double-buffered bulk endpoint is enabled for
reception, STATTX if the double-buffered bulk endpoint is enabled for transmission. In case
it is required to have double-buffered bulk endpoints enabled both for reception and
transmission, two USB_CHEPnR registers must be used.
To exploit the double-buffering feature and reach the highest possible transfer rate, the
endpoint flow control structure, described in previous chapters, has to be modified, in order
to switch the endpoint status to NAK only when a buffer conflict occurs between the USB
peripheral and application software, instead of doing it at the end of each successful
transaction. The memory buffer which is currently being used by the USB peripheral is
defined by the DTOG bit related to the endpoint direction: DTOGRX (bit 14 of
USB_CHEPnR register) for ‘reception’ double-buffered bulk endpoints or DTOGTX (bit 6 of
USB_CHEPnR register) for ‘transmission’ double-buffered bulk endpoints. To implement the
new flow control scheme, the USB peripheral should know which packet buffer is currently
in use by the application software, so to be aware of any conflict. Since in the
USB_CHEPnR register, there are two DTOG bits but only one is used by USB peripheral for
data and buffer sequencing (due to the unidirectional constraint required by double-buffering
feature) the other one can be used by the application software to show which buffer it is
currently using. This new buffer flag is called SW_BUF. In the following table the
correspondence between USB_CHEPnR register bits and DTOG/SW_BUF definition is
explained, for the cases of ‘transmission’ and ‘reception’ double-buffered bulk endpoints.

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Table 135. Double-buffering buffer flag definition

Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint

DTOG DTOGTX (USB_CHEPnR bit 6) DTOGRX (USB_CHEPnR bit 14)

SW_BUF USB_CHEPnR bit 14 USB_CHEPnR bit 6

The memory buffer which is currently being used by the USB peripheral is defined by DTOG
buffer flag, while the buffer currently in use by application software is identified by SW_BUF
buffer flag. The relationship between the buffer flag value and the used packet buffer is the
same in both cases, and it is listed in the following table.

Table 136. Bulk double-buffering memory buffers usage (Device mode)

Endpoint Packet buffer used by Packet buffer used by
DTOG SW_BUF
type USB peripheral Application Software

USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
0 1 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_1 / COUNTn_TX_1)
Buffer description table locations. Buffer description table locations
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
1 0 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_0 / COUNTn_TX_0)
Transmit Buffer description table locations Buffer description table locations.
(IN) USB_CHEP_TXRXBD_0
0 0 None (1) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations.
USB_CHEP_RXTXBD_0
1 1 None (1) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations.
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
(ADDRn_RX_0 / (ADDRn_RX_0 /
0 1
COUNTn_RX_0) COUNTn_RX_0)
Buffer description table locations. Buffer description table locations.
USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
(ADDRn_RX_0 / (ADDRn_RX_0 /
1 0
COUNTn_RX_0) COUNTn_RX_0)
Receive Buffer description table locations Buffer description table locations.
(OUT) USB_CHEP_RXTXBD_0
(1) (ADDRn_RX_0 /
0 0 None
COUNTn_RX_0)
Buffer description table locations.
USB_CHEP_TXRXBD_0
(ADDRn_RX_0 /
1 1 None (1)
COUNTn_RX_0)
Buffer description table locations.
1. Endpoint in NAK Status.

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Double-buffering feature for a bulk endpoint is activated by:

• Writing UTYPE bit field at 00 in its USB_CHEPnR register, to define the endpoint as a
bulk, and
• Setting EPKIND bit at 1 (DBL_BUF), in the same register.
The application software is responsible for DTOG and SW_BUF bits initialization according
to the first buffer to be used; this has to be done considering the special toggle-only property
that these two bits have. The end of the first transaction occurring after having set
DBL_BUF, triggers the special flow control of double-buffered bulk endpoints, which is used
for all other transactions addressed to this endpoint until DBL_BUF remain set. At the end of
each transaction the VTRX or VTTX bit of the addressed endpoint USB_CHEPnR register is
set, depending on the enabled direction. At the same time, the affected DTOG bit in the
USB_CHEPnR register is hardware toggled making the USB peripheral buffer swapping
completely software independent. Unlike common transactions, and the first one after
DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value
remains 11 (VALID). However, as the token packet of a new transaction is received, the
actual endpoint status is masked as 10 (NAK) when a buffer conflict between the USB
peripheral and the application software is detected (this condition is identified by DTOG and
SW_BUF having the same value, see Table 136 on page 933). The application software
responds to the CTR event notification by clearing the interrupt flag and starting any
required handling of the completed transaction. When the application packet buffer usage is
over, the software toggles the SW_BUF bit, writing 1 to it, to notify the USB peripheral about
the availability of that buffer. In this way, the number of NAKed transactions is limited only by
the application elaboration time of a transaction data: if the elaboration time is shorter than
the time required to complete a transaction on the USB bus, no re-transmissions due to flow
control takes place and the actual transfer rate is limited only by the host PC.
The application software can always override the special flow control implemented for
double-buffered bulk endpoints, writing an explicit status different from 11 (VALID) into the
STAT bit pair of the related USB_CHEPnR register. In this case, the USB peripheral always
uses the programmed endpoint status, regardless of the buffer usage condition.

28.5.4 Double buffered channels: usage in Host mode

In Host mode the underlying transmit and receive methods for double buffered channels are
the same as those described for Device mode.
Similar to the Device mode table, a new table below Table 137: Bulk double-buffering
memory buffers usage (Host mode) shows the programming settings for OUT and IN
tokens.

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Table 137. Bulk double-buffering memory buffers usage (Host mode)

Endpoint Packet buffer used by Packet buffer used by
DTOG SW_BUF
type USB peripheral Application Software

USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
0 1 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_1 / COUNTn_TX_1)
Buffer description table locations. Buffer description table locations
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
1 0 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_0 / COUNTn_TX_0)
Transmit Buffer description table locations Buffer description table locations.
(OUT) USB_CHEP_TXRXBD_0
0 0 None (1) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations.
USB_CHEP_RXTXBD_0
1 1 None (1) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations.
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
(ADDRn_RX_0 / (ADDRn_RX_0 /
0 1
COUNTn_RX_0) COUNTn_RX_0)
Buffer description table locations. Buffer description table locations.
USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
(ADDRn_RX_0 / (ADDRn_RX_0 /
1 0
COUNTn_RX_0) COUNTn_RX_0)
Receive Buffer description table locations Buffer description table locations.
(IN) USB_CHEP_RXTXBD_0
(1) (ADDRn_RX_0 /
0 0 None
COUNTn_RX_0)
Buffer description table locations.
USB_CHEP_TXRXBD_0
(ADDRn_RX_0 /
1 1 None (1)
COUNTn_RX_0)
Buffer description table locations.
1. Endpoint in NAK Status.

28.5.5 Isochronous transfers in Device mode

The USB standard supports full speed peripherals requiring a fixed and accurate data
production/consume frequency, defining this kind of traffic as ‘isochronous’. Typical
examples of this data are: audio samples, compressed video streams, and in general any
sort of sampled data having strict requirements for the accuracy of delivered frequency.
When an endpoint is defined to be ‘isochronous’ during the enumeration phase, the host
allocates in the frame the required bandwidth and delivers exactly one IN or OUT packet
each frame, depending on endpoint direction. To limit the bandwidth requirements, no re-
transmission of failed transactions is possible for isochronous traffic; this leads to the fact
that an isochronous transaction does not have a handshake phase and no ACK packet is
expected or sent after the data packet. For the same reason, isochronous transfers do not
support data toggle sequencing and always use DATA0 PID to start any data packet.

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The isochronous behavior for an endpoint is selected by setting the UTYPE bits at 10 in its
USB_CHEPnR register; since there is no handshake phase the only legal values for the
STATRX/STATTX bit pairs are 00 (DISABLED) and 11 (VALID), any other value produces
results not compliant to USB standard. Isochronous endpoints implement double-buffering
to ease application software development, using both ‘transmission’ and ‘reception’ packet
memory areas to manage buffer swapping on each successful transaction in order to have
always a complete buffer to be used by the application, while the USB peripheral fills the
other.
The memory buffer which is currently used by the USB peripheral is defined by the DTOG
bit related to the endpoint direction (DTOGRX for ‘reception’ isochronous endpoints,
DTOGTX for ‘transmission’ isochronous endpoints, both in the related USB_CHEPnR
register) according to Table 138.

Table 138. Isochronous memory buffers usage

Endpoint DTOG bit Packet buffer used by the Packet buffer used by the
Type value USB peripheral application software

USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
0 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_1 / COUNTn_TX_1)
Transmit Buffer description table locations. Buffer description table locations
(IN) USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
1 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations Buffer description table locations.
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
0 (ADDRn_RX_0 / COUNTn_RX_0) (ADDRn_RX_0 / COUNTn_RX_0)
Receive Buffer description table locations. Buffer description table locations.
(OUT) USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
1 (ADDRn_RX_0 / COUNTn_RX_0) (ADDRn_RX_0 / COUNTn_RX_0)
Buffer description table locations Buffer description table locations.

As it happens with double-buffered bulk endpoints, the USB_CHEPnR registers used to

implement isochronous endpoints are forced to be used as unidirectional ones. In case it is
required to have isochronous endpoints enabled both for reception and transmission, two
USB_CHEPnR registers must be used.
The application software is responsible for the DTOG bit initialization according to the first
buffer to be used; this has to be done considering the special toggle-only property that these
two bits have. At the end of each transaction, the VTRX or VTTX bit of the addressed
endpoint USB_CHEPnR register is set, depending on the enabled direction. At the same
time, the affected DTOG bit in the USB_CHEPnR register is hardware toggled making buffer
swapping completely software independent. STAT bit pair is not affected by transaction
completion; since no flow control is possible for isochronous transfers due to the lack of
handshake phase, the endpoint remains always 11 (VALID). CRC errors or buffer-overrun
conditions occurring during isochronous OUT transfers are anyway considered as correct
transactions and they always trigger a VTRX event. However, CRC errors set the ERR bit in
the USB_ISTR register anyway, in order to notify the software of the possible data
corruption.

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28.5.6 Isochronous transfers in Host mode

From the host point of view isochronous packets are issued or requested one by frame by
the host frame scheduler. There is no NAK/ACK protocol and no resend of data or token.
The mechanism is based on a table very similar to that for Device mode. See Table 139
below to understand the relationship between the DTOG bit buffers and the buffer usage.

Table 139. Isochronous memory buffers usage

Endpoint DTOG bit Packet buffer used by the Packet buffer used by the
Type value USB peripheral application software

USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
0 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_1 / COUNTn_TX_1)
Transmit Buffer description table locations. Buffer description table locations
(OUT) USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
1 (ADDRn_TX_0 / COUNTn_TX_0) (ADDRn_TX_0 / COUNTn_TX_0)
Buffer description table locations Buffer description table locations.
USB_CHEP_RXTXBD_0 USB_CHEP_TXRXBD_0
0 (ADDRn_RX_0 / COUNTn_RX_0) (ADDRn_RX_0 / COUNTn_RX_0)
Receive Buffer description table locations. Buffer description table locations.
(IN) USB_CHEP_TXRXBD_0 USB_CHEP_RXTXBD_0
1 (ADDRn_RX_0 / COUNTn_RX_0) (ADDRn_RX_0 / COUNTn_RX_0)
Buffer description table locations Buffer description table locations.

The isochronous behavior for an endpoint is selected by setting the UTYPE bits at 10 in its
USB_CHEPnR register; since there is no handshake phase the only legal values for the
STATRX/STATTX bit pairs are 00 (DISABLED) and 11 (VALID),
Just as in Device mode, the mechanism allows automatic toggle of the DTOG bit. Note that
in Host mode, at the same time as this toggle, the STATTX or STATRX of the completed
buffer is automatically set to DISABLED, permitting the future buffer to be accessed before
re-enabling it by setting it to 11 (VALID).

28.5.7 Suspend/resume events

The USB standard defines a special peripheral state, called SUSPEND, in which the
average current drawn from the USB bus must not be greater than 2.5 mA. This
requirement is of fundamental importance for bus-powered devices, while self-powered
devices are not required to comply to this strict power consumption constraint. In suspend
mode, the host PC sends the notification by not sending any traffic on the USB bus for more
than 3 ms: since a SOF packet must be sent every 1 ms during normal operations, the USB
peripheral detects the lack of 3 consecutive SOF packets as a suspend request from the
host PC and set the SUSP bit to 1 in USB_ISTR register, causing an interrupt if enabled.
Once the device is suspended, its normal operation can be restored by a so called
RESUME sequence, which can be started from the host PC or directly from the peripheral
itself, but it is always terminated by the host PC. The suspended USB peripheral must be
anyway able to detect a RESET sequence, reacting to this event as a normal USB reset
event.

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The actual procedure used to suspend the USB peripheral is device dependent since
according to the device composition, different actions may be required to reduce the total
consumption.
A brief description of a typical suspend procedure is provided below, focused on the USB-
related aspects of the application software routine responding to the SUSP notification of
the USB peripheral:
1. Set the SUSPEN bit in the USB_CNTR register to 1. This action activates the suspend
mode within the USB peripheral. As soon as the suspend mode is activated, the check
on SOF reception is disabled to avoid any further SUSP interrupts being issued while
the USB is suspended.
2. Remove or reduce any static power consumption in blocks different from the USB
peripheral.
3. Set SUSPRDY bit in USB_CNTR register to 1 to remove static power consumption in
the analog USB transceivers but keeping them able to detect resume activity.
4. Optionally turn off external oscillator and device PLL to stop any activity inside the
device.
When an USB event occurs while the device is in SUSPEND mode, the RESUME
procedure must be invoked to restore nominal clocks and regain normal USB behavior.
Particular care must be taken to insure that this process does not take more than 10 ms
when the wakening event is an USB reset sequence (see “Universal Serial Bus
Specification” for more details). The start of a resume or reset sequence, while the USB
peripheral is suspended, clears the SUSPRDY bit in USB_CNTR register asynchronously.
Even if this event can trigger a WKUP interrupt if enabled, the use of an interrupt response
routine must be carefully evaluated because of the long latency due to system clock restart;
to have the shorter latency before re-activating the nominal clock it is suggested to put the
resume procedure just after the end of the suspend one, so its code is immediately
executed as soon as the system clock restarts. To prevent ESD discharges or any other kind
of noise from waking-up the system (the exit from suspend mode is an asynchronous
event), a suitable analog filter on data line status is activated during suspend; the filter width
is about 70 ns.
The following is a list of actions a resume procedure should address:
1. Optionally turn on external oscillator and/or device PLL.
2. Clear SUSPEN bit of USB_CNTR register.
3. If the resume triggering event has to be identified, bits RXDP and RXDM in the
USB_FNR register can be used according to Table 140, which also lists the intended
software action in all the cases. If required, the end of resume or reset sequence can
be detected monitoring the status of the above mentioned bits by checking when they
reach the “10” configuration, which represent the idle bus state; moreover at the end of
a reset sequence the RST_DCON bit in USB_ISTR register is set to 1, issuing an
interrupt if enabled, which should be handled as usual.

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Table 140. Resume event detection

[RXDP,RXDM] status Wakeup event Required resume software action

“00” Root reset None

“10” None (noise on bus) Go back in Suspend mode
“01” Root resume None
“11” Not allowed (noise on bus) Go back in Suspend mode

A device may require to exit from suspend mode as an answer to particular events not
directly related to the USB protocol (for example a mouse movement wakes up the whole
system). In this case, the resume sequence can be started by setting the L2RES bit in the
USB_CNTR register to 1 and resetting it to 0 after an interval between 1 ms and 15 ms (this
interval can be timed using ESOF interrupts, occurring with a 1 ms period when the system
clock is running at nominal frequency). Once the L2RES bit is clear, the resume sequence is
completed by the host PC and its end can be monitored again using the RXDP and RXDM
bits in the USB_FNR register.
Note: The L2RES bit must be anyway used only after the USB peripheral has been put in suspend
mode, setting the SUSPEN bit in USB_CNTR register to 1.

Suspend and resume in Host mode

The basics of the suspend and resume mechanism has been described in the previous
section.
From the host stand-point, suspend is entered by writing the SUSPEN bit in USB_CNTR.
When suspend entry is confirmed, SUSPRDY (also in USB_CNTR) is set.
Once in suspend, and when the application want to resume the bus, this can be done by
setting the L2RES bit in USB_CNTR to 1.
Below in Table 141, the different actions recommended after a wakeup event are indicated.
According to the different line states after a wakeup event, the interpretation of the event
and the suggested behavior are shown. Note that, this table here is somewhat expanded
when compared to the previously shown device table, as the host may encounter both full
speed and low speed devices which use different line states for both suspend and resume.

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Table 141. Resume event detection for host

[RXDP,RXDM] status Wakeup event Required resume software action

“00” Not allowed (noise on bus) Go back in Suspend mode

Full speed capable device:
Not allowed (noise on bus) None
“10”
Low speed device: Device
remote wakeup resume
Full speed capable device:
Device remote wakeup
resume
“01” None
Low speed device:
Not allowed (noise on bus)
“11” Not allowed (noise on bus) Go back in Suspend mode

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28.6 USB and USB SRAM registers

The USB peripheral registers can be divided into the following groups:
• Common registers: interrupt and control registers
• endpoint/channel registers: endpoint/channel configuration and status
The USB SRAM registers cover:
• Buffer descriptor table: location of packet memory used to locate data buffers (see
Section 2.2: Memory organization to find USB SRAM base address).
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address, except the buffer descriptor table locations, which starts at the USB SRAM
base address.
Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by words (32-bit).

28.6.1 Common registers

These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.

USB control register (USB_CNTR)

Address offset: 0x40
Reset value: 0x0000 0003

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THR
HOST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
512M
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMA WKUP SUSP RST_D ESOF L1REQ L1RE L2RE SUS SUSP USB
CTRM ERRM SOFM Res. PDWN
OVRM M M CONM M M S S PEN RDY RST
rw rw rw rw rw rw rw rw rw rw rw rw r rw rw

Bit 31 HOST: HOST mode

HOST bit selects betweens host or device USB mode of operation. It must be set before
enabling the USB peripheral by the function enable bit.
0: USB Device function
1: USB host function
Bits 30:17 Reserved, must be kept at reset value.
Bit 16 THR512M: 512 byte threshold interrupt mask
0: 512 byte threshold interrupt disabled
1: 512 byte threshold interrupt enabled
Bit 15 CTRM: Correct transfer interrupt mask
0: Correct transfer (CTR) interrupt disabled.
1: CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.

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Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask

0: PMAOVR interrupt disabled.
1: PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
Bit 13 ERRM: Error interrupt mask
0: ERR interrupt disabled.
1: ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 12 WKUPM: Wakeup interrupt mask
0: WKUP interrupt disabled.
1: WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 11 SUSPM: Suspend mode interrupt mask
0: Suspend mode request (SUSP) interrupt disabled.
1: SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 10 RST_DCONM: USB reset request (Device mode) or device connect/disconnect (Host mode)
interrupt mask
0: RESET interrupt disabled.
1: RESET interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 9 SOFM: Start of frame interrupt mask
0: SOF interrupt disabled.
1: SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 8 ESOFM: Expected start of frame interrupt mask
0: Expected start of frame (ESOF) interrupt disabled.
1: ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 7 L1REQM: LPM L1 state request interrupt mask
0: LPM L1 state request (L1REQ) interrupt disabled.
1: L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 6 Reserved, must be kept at reset value.
Bit 5 L1RES: L1 remote wakeup / resume driver
– Device mode
Software sets this bit to send a LPM L1 50 μs remote wakeup signaling to the host. After the
signaling ends, this bit is cleared by hardware.
0: No effect
1: Send 50 μs remote-wakeup signaling to host

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Bit 4 L2RES: L2 remote wakeup / resume driver

– Device mode
The microcontroller can set this bit to send remote wake-up signaling to the host. It must be
activated, according to USB specifications, for no less than 1 ms and no more than 15 ms
after which the host PC is ready to drive the resume sequence up to its end.
– Host mode
Software sets this bit to send resume signaling to the device.
Software clears this bit to send end of resume to device and restart SOF generation.
In the context of remote wake up, this bit is to be set following the WAKEUP interrupt.
0: No effect
1: Send L2 resume signaling to device
Bit 3 SUSPEN: Suspend state enable
– Condition: Device mode
Software can set this bit when the SUSP interrupt is received, which is issued when no traffic
is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ
interrupt is received with positive acknowledge sent.
As soon as the suspend state is propagated internally all device activity is stopped, USB
clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by
hardware. In the case that device application wants to pursue more aggressive power saving
by stopping the USB clock source and by moving the microcontroller to stop mode, as in the
case of bus powered device application, it must first wait few cycles to see the
SUSPRDY = 1 acknowledge the suspend request.
This bit is cleared by hardware simultaneous with the WAKEUP flag set.
0: No effect.
1: Enter L1/L2 suspend
– Condition: Host mode
Software can set this bit when host application has nothing scheduled for the next frames
and wants to enter long term power saving. When set, it stops immediately SOF generation
and any other host activity, gates the USB clock and sets the transceiver in low power mode.
If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end
of the current transaction.
As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is
set. In the case that host application wants to pursue more aggressive power saving by
stopping the USB clock source and by moving the micro-controller to STOP mode, it must
first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request.
This bit is cleared by hardware simultaneous with the WAKEUP flag set.
0: No effect.
1: Enter L1/L2 suspend
Bit 2 SUSPRDY: Suspend state effective
This bit is set by hardware as soon as the suspend state entered through the SUSPEN
control gets internally effective. In this state USB activity is suspended, USB clock is gated,
transceiver is set in low power mode by disabling the differential receiver. Only
asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup
or resume events.
Software must poll this bit to confirm it to be set before any STOP mode entry.
This bit is cleared by hardware simultaneously to the WAKEUP flag being set.
0: Normal operation
1: Suspend state

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Bit 1 PDWN: Power down

This bit is used to completely switch off all USB-related analog parts if it is required to
completely disable the USB peripheral for any reason. When this bit is set, the USB
peripheral is disconnected from the transceivers and it cannot be used.
0: Exit power down.
1: Enter power down mode.
Bit 0 USBRST: USB Reset
– Condition: Device mode
Software can set this bit to reset the USB core, exactly as it happens when receiving a
RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its
internal protocol state machine. Reception and transmission are disabled until the
RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must
explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely
delivered, and any transaction immediately followed by a RESET can be completed). The
function address and endpoint registers are reset by an USB reset event.
0: No effect
1: USB core is under reset
– Condition: Host mode
Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset
terminates as soon as this bit is cleared by software.
0: No effect
1: USB reset driven

USB interrupt status register (USB_ISTR)

Address offset: 0x44
Reset value: 0x0000 0000
This register contains the status of all the interrupt sources permitting application software to
determine which events caused an interrupt request.
The upper part of this register contains single bits, each of them representing a specific
event. These bits are set by the hardware when the related event occurs; if the
corresponding bit in the USB_CNTR register is set, a generic interrupt request is generated.
The interrupt routine, examining each bit, performs all necessary actions, and finally it clears
the serviced bits. If any of them is not cleared, the interrupt is considered to be still pending,
and the interrupt line is kept high again. If several bits are set simultaneously, only a single
interrupt is generated.
Endpoint/channel transaction completion can be handled in a different way to reduce
interrupt response latency. The CTR bit is set by the hardware as soon as an
endpoint/channel successfully completes a transaction, generating a generic interrupt
request if the corresponding bit in USB_CNTR is set. An endpoint/channel dedicated
interrupt condition is activated independently from the CTRM bit in the USB_CNTR register.
Both interrupt conditions remain active until software clears the pending bit in the
corresponding USB_CHEPnR register (the CTR bit is actually a read only bit). For endpoint-
/channel-related interrupts, the software can use the direction of transaction (DIR) and IDN
read-only bits to identify which endpoint/channel made the last interrupt request and called
the corresponding interrupt service routine.
The user can choose the relative priority of simultaneously pending USB_ISTR events by
specifying the order in which software checks USB_ISTR bits in an interrupt service routine.
Only the bits related to events, which are serviced, are cleared. At the end of the service
routine, another interrupt is requested, to service the remaining conditions.

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To avoid spurious clearing of some bits, it is recommended to clear them with a load
instruction where all bits which must not be altered are written with 1, and all bits to be
cleared are written with 0 (these bits can only be cleared by software). Read-modify-write
cycles should be avoided because between the read and the write operations another bit
could be set by the hardware and the next write clears it before the microprocessor has the
time to service the event.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LS_ DCON_ THR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DCON STAT 512
r r rc_w0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMA RST_
CTR ERR WKUP SUSP SOF ESOF L1REQ Res. Res. DIR IDN[3:0]
OVR DCON
r rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r

Bit 31 Reserved, must be kept at reset value.

Bit 30 LS_DCON: Low speed device connected
– Host mode:
This bit is set by hardware when an LS device connection is detected. Device connection is
signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz)
from the unconnected state.
Bit 29 DCON_STAT: Device connection status
– Host mode:
This bit contains information about device connection status. It is set by hardware when a
LS/FS device is attached to the host while it is reset when the device is disconnected.
0: No device connected
1: FS or LS device connected to the host
Bits 28:17 Reserved, must be kept at reset value.
Bit 16 THR512: 512 byte threshold interrupt
This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during
isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no
effect. Note that no information is available to indicate the associated channel/endpoint,
however in practice only one ISO endpoint/channel with such large packets can be
supported, so that channel.
Bit 15 CTR: Completed transfer in host mode
This bit is set by the hardware to indicate that an endpoint/channel has successfully
completed a transaction; using DIR and IDN bits software can determine which
endpoint/channel requested the interrupt. This bit is read-only.
Bit 14 PMAOVR: Packet memory area over / underrun
This bit is set if the microcontroller has not been able to respond in time to an USB memory
request. The USB peripheral handles this event in the following way: During reception an
ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the
transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt
should never occur during normal operations. Since the failed transaction is retried by the
host, the application software has the chance to speed-up device operations during this
interrupt handling, to be ready for the next transaction retry; however this does not happen
during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss
of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect.

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Bit 13 ERR: Error

This flag is set whenever one of the errors listed below has occurred:
NANS: No ANSwer. The timeout for a host response has expired.
CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in
the data, was wrong.
BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or
CRC.
FVIO: Framing format violation. A non-standard frame was received (EOP not in the right
place, wrong token sequence, etc.).
The USB software can usually ignore errors, since the USB peripheral and the PC host
manage retransmission in case of errors in a fully transparent way. This interrupt can be
useful during the software development phase, or to monitor the quality of transmission over
the USB bus, to flag possible problems to the user (for example loose connector, too noisy
environment, broken conductor in the USB cable and so on). This bit is read/write but only 0
can be written and writing 1 has no effect.
Bit 12 WKUP: Wakeup
This bit is set to 1 by the hardware when, during suspend mode, activity is detected that
wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the
CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of
the device (for example wakeup unit) about the start of the resume process. This bit is
read/write but only 0 can be written and writing 1 has no effect.
Bit 11 SUSP: Suspend mode request
– Device mode
This bit is set by the hardware when no traffic has been received for 3 ms, indicating a
suspend mode request from the USB bus. The suspend condition check is enabled
immediately after any USB reset and it is disabled by the hardware when the suspend mode
is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can
be written and writing 1 has no effect.
Bit 10 RST_DCON: USB reset request (Device mode) or device connect/disconnect (Host mode)
– Device mode
This bit is set by hardware when an USB reset is released by the host and the bus returns to
idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles.
– Host mode
This bit is set by hardware when device connection or device disconnection is detected.
Device connection is signaled after J state is sampled for 22 cycles consecutively from
unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times
consecutively from connected state.
Bit 9 SOF: Start of frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives
through the USB bus. The interrupt service routine may monitor the SOF events to have a
1 ms synchronization event to the USB host and to safely read the USB_FNR register which
is updated at the SOF packet reception (this could be useful for isochronous applications).
This bit is read/write but only 0 can be written and writing 1 has no effect.
Bit 8 ESOF: Expected start of frame
– Device mode
This bit is set by the hardware when an SOF packet is expected but not received. The host
sends an SOF packet each 1 ms, but if the device does not receive it properly, the suspend
timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example
three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is
generated. This bit is set even when the missing SOF packets occur while the suspend timer
is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect.

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Bit 7 L1REQ: LPM L1 state request

– Device mode
This bit is set by the hardware when LPM command to enter the L1 state is successfully
received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has
no effect.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 DIR: Direction of transaction
This bit is written by the hardware according to the direction of the successful transaction,
which generated the interrupt request.
If DIR bit = 0, VTTX bit is set in the USB_CHEPnR register related to the interrupting
endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to
the host PC).
If DIR bit = 1, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to
the interrupting endpoint. The interrupting transaction is of OUT type (data received by the
USB peripheral from the host PC) or two pending transactions are waiting to be processed.
This information can be used by the application software to access the USB_CHEPnR bits
related to the triggering transaction since it represents the direction having the interrupt
pending. This bit is read-only.
Bits 3:0 IDN[3:0]: Device Endpoint / host channel identification number
These bits are written by the hardware according to the host channel or device endpoint
number, which generated the interrupt request. If several endpoint/channel transactions are
pending, the hardware writes the identification number related to the endpoint/channel
having the highest priority defined in the following way: two levels are defined, in order of
priority: isochronous and double-buffered bulk channels/endpoints are considered first and
then the others are examined. If more than one endpoint/channel from the same set is
requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the
lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so
on. The application software can assign a register to each endpoint/channel according to this
priority scheme, so as to order the concurring endpoint/channel requests in a suitable way.
These bits are read only.

USB frame number register (USB_FNR)

Address offset: 0x48
Reset value: 0x0000 0XXX (where X is undefined)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP RXDM LCK LSOF[1:0] FN[10:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 RXDP: Receive data + line status
This bit can be used to observe the status of received data plus upstream port data line. It
can be used during end-of-suspend routines to help determining the wakeup event.
Bit 14 RXDM: Receive data - line status
This bit can be used to observe the status of received data minus upstream port data line. It
can be used during end-of-suspend routines to help determining the wakeup event.

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Bit 13 LCK: Locked

– Device mode
This bit is set by the hardware when at least two consecutive SOF packets have been
received after the end of an USB reset condition or after the end of an USB resume
sequence. Once locked, the frame timer remains in this state until an USB reset or USB
suspend event occurs.
Bits 12:11 LSOF[1:0]: Lost SOF
– Device mode
These bits are written by the hardware when an ESOF interrupt is generated, counting the
number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are
cleared.
Bits 10:0 FN[10:0]: Frame number
This bit field contains the 11-bits frame number contained in the last received SOF packet.
The frame number is incremented for every frame sent by the host and it is useful for
isochronous transfers. This bit field is updated on the generation of an SOF interrupt.

USB Device address (USB_DADDR)

Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. EF ADD[6:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 EF: Enable function
This bit is set by the software to enable the USB Device. The address of this device is
contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled,
irrespective of the settings of USB_CHEPnR registers.
Bits 6:0 ADD[6:0]: Device address
– Device mode
These bits contain the USB function address assigned by the host PC during the
enumeration process. Both this field and the endpoint/channel address (EA) field in the
associated USB_CHEPnR register must match with the information contained in a USB
token in order to handle a transaction to the required endpoint.
– Host mode
These bits contain the address transmitted with the LPM transaction

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LPM control and status register (USB_LPMCSR)

Address offset: 0x54
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REM LPM LPM
Res. Res. Res. Res. Res. Res. Res. Res. BESL[3:0] Res.
WAKE ACK EN
r r r r r rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 BESL[3:0]: BESL value
– Device mode
These bits contain the BESL value received with last ACKed LPM Token
Bit 3 REMWAKE: bRemoteWake value
– Device mode
This bit contains the bRemoteWake value received with last ACKed LPM Token
Bit 2 Reserved, must be kept at reset value.
Bit 1 LPMACK: LPM token acknowledge enable
– Condition: Device mode:
0: the valid LPM token is NYET.
1: the valid LPM token is ACK.
The NYET/ACK is returned only on a successful LPM transaction:
No errors in both the EXT token and the LPM token (else ERROR)
A valid bLinkState = 0001B (L1) is received (else STALL)
Bit 0 LPMEN: LPM support enable
– Device mode
This bit is set by the software to enable the LPM support within the USB Device. If this bit is
at 0 no LPM transactions are handled.

Battery charging detector (USB_BCDR)

Address offset: 0x58
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU_ PS2 DC DCD BCD
Res. Res. Res. Res. Res. Res. Res. SDET PDET SDEN PDEN
DPD DET DET EN EN
rw r r r r rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bit 15 DPPU_DPD: DP pull-up / DPDM pull-down
– Device mode
This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be
used to signal disconnect to the host when needed by the user software.
– Host mode
This bit is set by software to enable the embedded pull-down on DP and DM lines.
Bits 14:8 Reserved, must be kept at reset value.
Bit 7 PS2DET: DM pull-up detection status
– Device mode
This bit is active only during PD and gives the result of comparison between DM voltage
level and VLGC threshold. In normal situation, the DM level should be below this threshold. If
it is above, it means that the DM is externally pulled high. This can be caused by connection
to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not
following the BCD specification.
0: Normal port detected (connected to SDP, ACA, CDP or DCP).
1: PS2 port or proprietary charger detected.
Bit 6 SDET: Secondary detection (SD) status
– Device mode
This bit gives the result of SD.
0: CDP detected.
1: DCP detected.
Bit 5 PDET: Primary detection (PD) status
– Device mode
This bit gives the result of PD.
0: no BCD support detected (connected to SDP or proprietary device).
1: BCD support detected (connected to ACA, CDP or DCP).
Bit 4 DCDET: Data contact detection (DCD) status
– Device mode
This bit gives the result of DCD.
0: data lines contact not detected.
1: data lines contact detected.
Bit 3 SDEN: Secondary detection (SD) mode enable
– Device mode
This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.

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Bit 2 PDEN: Primary detection (PD) mode enable

– Device mode
This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.
Bit 1 DCDEN: Data contact detection (DCD) mode enable
– Device mode
This bit is set by the software to put the BCD into DCD mode. Only one detection mode
(DCD, PD, SD or OFF) should be selected to work correctly.
Bit 0 BCDEN: Battery charging detector (BCD) enable
– Device mode
This bit is set by the software to enable the BCD support within the USB Device. When
enabled, the USB PHY is fully controlled by BCD and cannot be used for normal
communication. Once the BCD discovery is finished, the BCD should be placed in OFF
mode by clearing this bit to 0 in order to allow the normal USB operation.

Host channel-specific/device endpoint-specific registers

The number of these registers varies according to the number of endpoints or host channels
that the USB peripheral is designed to handle. The USB peripheral supports up to 8
bidirectional endpoints or host channels. Each USB Device must support a control
endpoint/channel whose address (EA bits) must be set to 0. The USB peripheral behaves in
an undefined way if multiple endpoints are enabled having the same endpoint/channel
number value. For each endpoint, an USB_CHEPnR register is available to store the
endpoint/channel specific information.

USB endpoint/channel n register (USB_CHEPnR)

Address offset: 0x00 + 0x4 * n, (n = 0 to 7)
Reset value: 0x0000 0000
They are also reset when an USB reset is received from the USB bus or forced through bit
USBRST in the CTLR register, except the VTRX and VTTX bits, which are kept unchanged
to avoid missing a correct packet notification immediately followed by an USB reset event.
Each endpoint/channel has its USB_CHEPnR register where n is the endpoint/channel
identifier.
Read-modify-write cycles on these registers should be avoided because between the read
and the write operations some bits could be set by the hardware and the next write would
modify them before the CPU has the time to detect the change. For this purpose, all bits
affected by this problem have an ‘invariant’ value that must be used whenever their
modification is not required. It is recommended to modify these registers with a load
instruction where all the bits, which can be modified only by the hardware, are written with
their ‘invariant’ value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR_R ERR_T
Res. Res. Res. Res. Res. LS_EP NAK DEVADDR[6:0]
X X
rc_w0 rc_w0 rw rc_w0 rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTOG EP DTOG
VTRX STATRX[1:0] SETUP UTYPE[1:0] VTTX STATTX[1:0] EA[3:0]
RX KIND TX
rc_w0 t t t r rw rw rw rc_w0 t t t rw rw rw rw

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Bits 31:27 Reserved, must be kept at reset value.

Bit 26 ERR_RX: Received error for an IN transaction
– Host mode
This bit is set by the hardware when an error (for example no answer by the device, CRC
error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction
on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register
is set, a generic interrupt condition is generated together with the channel related flag, which
is always activated.
Bit 25 ERR_TX: Received error for an OUT/SETUP transaction
– Host mode
This bit is set by the hardware when an error (for example no answer by the device, CRC
error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP
transaction on this channel. The software can only clear this bit. If the ERRM bit in
USB_CNTR register is set, a generic interrupt condition is generated together with the
channel related flag, which is always activated.
Bit 24 LS_EP: Low speed endpoint – host with HUB only
– Host mode
This bit is set by the software to send an LS transaction to the corresponding endpoint.
0: Full speed endpoint
1: Low speed endpoint
Bit 23 NAK:
– Host mode
This bit is set by the hardware when a device responds with a NAK. Software can use this bit
to monitor the number of NAKs received from a device.
Bits 22:16 DEVADDR[6:0]:
– Host mode
Device address assigned to the endpoint during the enumeration process.

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Bit 15 VTRX: USB valid transaction received

– Device mode
This bit is set by the hardware when an OUT/SETUP transaction is successfully completed
on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register
is set accordingly, a generic interrupt condition is generated together with the endpoint
related interrupt condition, which is always activated. The type of occurred transaction, OUT
or SETUP, can be determined from the SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only 0 can be written, writing 1 has no effect.
– Host mode
This bit is set by the hardware when an IN transaction is successfully completed on this
channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a
generic interrupt condition is generated together with the channel related flag, which is
always activated.

- A transaction ended with a NAK sets this bit and NAK answer is reported to application
reading the NAK state from the STATRX field of this register. One NAKed transaction keeps
pending and is automatically retried by the host at the next frame, or the host can
immediately retry by resetting STATRX state to VALID.

- A transaction ended by STALL handshake sets this bit and the STALL answer is reported
to application reading the STALL state from the STATRX field of this register. Host
application should consequently disable the channel and re-enumerate.

- A transaction ended with ACK handshake sets this bit

If double buffering is disabled, ACK answer is reported by application reading the DISABLE
state from the STATRX field of this register. Host application should read received data from
USBRAM and re-arm the channel by writing VALID to the STATRX field of this register.
If double buffering is enabled, ACK answer is reported by application reading VALID state
from the STATRX field of this register. Host application should read received data from
USBRAM and toggle the DTOGTX bit of this register.

- A transaction ended with error sets this bit

This bit is read/write but only 0 can be written, writing 1 has no effect.

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Bit 14 DTOGRX: Data Toggle, for reception transfers

If the endpoint/channel is not isochronous, this bit contains the expected value of the data
toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles
this bit, when the ACK handshake is sent following a data packet reception having a
matching data PID value; if the endpoint is defined as a control one, hardware clears this bit
at the reception of a SETUP PID received from host (in device) or acknowledged by device
(in host).
If the endpoint/channel is using the double-buffering feature this bit is used to support packet
buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in
Device mode).
If the endpoint/channel is isochronous, this bit is used only to support packet buffer
swapping for data transmission since no data toggling is used for this kind of
channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5:
Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data
packet reception, since no handshake is used for isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the
application software writes 0, the value of DTOGRX remains unchanged, while writing 1
makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.

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Bits 13:12 STATRX[1:0]: Status bits, for reception transfers

– Device mode
These bits contain information about the endpoint status, which are listed in Table 142:
Reception status encoding on page 958. These bits can be toggled by software to initialize
their value. When the application software writes 0, the value remains unchanged, while
writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a
correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only)
transaction addressed to this endpoint, so the software has the time to elaborate the
received data before it acknowledges a new transaction.
Double-buffered bulk endpoints implement a special transaction flow control, which control
the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered
endpoints and usage in Device mode).
If the endpoint is defined as isochronous, its status can be only “VALID” or “DISABLED”, so
that the hardware cannot change the status of the endpoint after a successful transaction. If
the software sets the STATRX bits to ‘STALL’ or ‘NAK’ for an isochronous endpoint, the USB
peripheral behavior is not defined. These bits are read/write but they can be only toggled by
writing 1.
– Host mode
These bits are the host application controls to start, retry, or abort host transactions driven
by the channel.
These bits also contain information about the device answer to the last IN channel
transaction and report the current status of the channel according to the following STATRX
table of states:
- DISABLE
DISABLE value is reported in case of ACK acknowledge is received on a single-buffer
channel. When in DISABLE state the channel is unused or not active waiting for application
to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a
transaction. In this case the transaction is immediately removed from the host execution
list. If the aborted transaction was already under execution it is regularly terminated on the
USB but the relative VTRX interrupt is not generated.
- VALID
A host channel is actively trying to submit USB transaction to device only when in VALID
state.VALID state can be set by software or automatically by hardware on a NAKED
channel at the start of a new frame. When set to VALID, an host channel enters the host
execution queue and waits permission from the host frame scheduler to submit its
configured transaction.
VALID value is also reported in case of ACK acknowledge is received on a double-buffered
channel. In this case the channel remains active on the alternate buffer while application
needs to read the current buffer and toggle DTOGTX. In case software is late in reading
and the alternate buffer is not ready, the host channel is automatically suspended
transparently to the application. The suspended double buffered channel is re-activated as
soon as delay is recovered and DTOGTX is toggled.
- NAK
NAK value is reported in case of NAK acknowledge received. When in NAK state the
channel is suspended and does not try to transmit. NAK state is moved to VALID by
hardware at the start of the next frame, or software can change it to immediately retry
transmission by writing it to VALID, or can disable it and abort the transaction by writing
DISABLE
- STALL
STALL value is reported in case of STALL acknowledge received. When in STALL state the
channel behaves as disabled. Application should not retry transmission but reset the USB
and re-enumerate.

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Bit 11 SETUP: Setup transaction completed

– Device mode
This bit is read-only and it is set by the hardware when the last completed transaction is a
SETUP. This bit changes its value only for control endpoints. It must be examined, in the
case of a successful receive transaction (VTRX event), to determine the type of transaction
occurred. To protect the interrupt service routine from the changes in SETUP bits due to
next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when
VTRX is at 0. This bit is read-only.
– Host mode
This bit is set by the software to send a SETUP transaction on a control endpoint. This bit
changes its value only for control endpoints. It is cleared by hardware when the SETUP
transaction is acknowledged and VTTX interrupt generated.
Bits 10:9 UTYPE[1:0]: USB type of transaction
These bits configure the behavior of this endpoint/channel as described in Table 143:
Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control
endpoint/channel and each USB function must have at least one control endpoint/channel
which has address 0, but there may be other control channels/endpoints if required. Only
control channels/endpoints handle SETUP transactions, which are ignored by endpoints of
other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control
endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a
receive error, in the receive direction when a SETUP transaction is received. If the control
endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is
accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT
transactions is handled in the normal way, even if the endpoint/channel is a control one.
Bulk and interrupt endpoints have very similar behavior and they differ only in the special
feature available using the EPKIND configuration bit.
The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous
transfers in Device mode
Bit 8 EPKIND: endpoint/channel kind
The meaning of this bit depends on the endpoint/channel type configured by the UTYPE
bits. Table 144 summarizes the different meanings.
DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk
endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3:
Double-buffered endpoints and usage in Device mode.
STATUS_OUT: This bit is set by the software to indicate that a status out transaction is
expected: in this case all OUT transactions containing more than zero data bytes are
answered ‘STALL’ instead of ‘ACK’. This bit may be used to improve the robustness of the
application to protocol errors during control transfers and its usage is intended for control
endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of
bytes, as required.
Bit 7 VTTX: Valid USB transaction transmitted
– Device mode
This bit is set by the hardware when an IN transaction is successfully completed on this
endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is
set accordingly, a generic interrupt condition is generated together with the endpoint related
interrupt condition, which is always activated.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only 0 can be written.
– Host mode
Same as VTRX behavior but for USB OUT and SETUP transactions.

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Bit 6 DTOGTX: Data toggle, for transmission transfers

If the endpoint/channel is non-isochronous, this bit contains the required value of the data
toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware
toggles this bit when the ACK handshake is received from the USB host, following a data
packet transmission. If the endpoint/channel is defined as a control one, hardware sets this
bit to 1 at the reception of a SETUP PID addressed to this endpoint.
If the endpoint/channel is using the double buffer feature, this bit is used to support packet
buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in
Device mode)
If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping
since no data toggling is used for this sort of endpoints and only DATA0 packet are
transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware
toggles this bit just after the end of data packet transmission, since no handshake is used for
isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage.
When the application software writes 0, the value of DTOGTX remains unchanged, while
writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by
writing 1.
Bits 5:4 STATTX[1:0]: Status bits, for transmission transfers
– Device mode
These bits contain the information about the endpoint status, listed in Table 145. These bits
can be toggled by the software to initialize their value. When the application software writes
0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware
sets the STATTX bits to NAK, when a correct transfer has occurred (VTTX = 1)
corresponding to a IN or SETUP (control only) transaction addressed to this
channel/endpoint. It then waits for the software to prepare the next set of data to be
transmitted.
Double-buffered bulk endpoints implement a special transaction flow control, which controls
the status based on buffer availability condition (Refer to Section 28.5.3: Double-buffered
endpoints and usage in Device mode).
If the endpoint is defined as isochronous, its status can only be “VALID” or “DISABLED”.
Therefore, the hardware cannot change the status of the channel/endpoint/channel after a
successful transaction. If the software sets the STATTX bits to ‘STALL’ or ‘NAK’ for an
isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are
read/write but they can be only toggled by writing 1.
– Host mode
The STATTX bits contain the information about the channel status. Refer to Table 145 for the
full descriptions (“Host mode” descriptions). Whereas in Device mode, these bits contain the
status that are given out on the following transaction, in Host mode they capture the status
last received from the device. If a NAK is received, STATTX contains the value indicating
NAK.
Bits 3:0 EA[3:0]: endpoint/channel address
– Device mode
Software must write in this field the 4-bit address used to identify the transactions directed to
this endpoint. A value must be written before enabling the corresponding endpoint.
– Host mode
Software must write in this field the 4-bit address used to identify the channel addressed by
the host transaction.

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Table 142. Reception status encoding

STATRX[1:0] Meaning

00 DISABLED: all reception requests addressed to this endpoint/channel are ignored.

STALL:
Device mode: the endpoint is stalled and all reception requests result in a STALL
01
handshake.
Host mode: this indicates that the device has STALLed the channel.
NAK:
Device mode: the endpoint is NAKed and all reception requests result in a NAK
10
handshake.
Host mode: this indicates that the device has NAKed the reception request.
11 VALID: this endpoint/channel is enabled for reception.

Table 143. Endpoint/channel type encoding

UTYPE[1:0] Meaning

00 BULK
01 CONTROL
10 ISO
11 INTERRUPT

Table 144. Endpoint/channel kind meaning

UTYPE[1:0] EPKIND meaning

00 BULK DBL_BUF
01 CONTROL STATUS_OUT
SBUF_ISO: This bit is set by the software to enable the
10 ISO
single-buffering feature for isochronous endpoint
11 INTERRUPT Not used

Table 145. Transmission status encoding

STATTX[1:0] Meaning

DISABLED: all transmission requests addressed to this endpoint/channel are

00
ignored.
STALL:
Device mode: the endpoint is stalled and all transmission requests result in a
01
STALL handshake.
Host mode: this indicates that the device has STALLed the channel.

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Table 145. Transmission status encoding (continued)

STATTX[1:0] Meaning

NAK:
Device mode: the endpoint is NAKed and all transmission requests result in a
10
NAK handshake.
Host mode: this indicates that the device has NAKed the transmission request.
11 VALID: this endpoint/channel is enabled for transmission.

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28.6.2 Buffer descriptor table

Note: The buffer descriptor table is located inside the packet buffer memory in the separate "USB
SRAM" address space.
Although the buffer descriptor table is located inside the packet buffer memory ("USB
SRAM" area), its entries can be considered as additional registers used to configure the
location and size of the packet buffers used to exchange data between the USB macro cell
and the device.
The first packet memory location is located at USB SRAM base address. The buffer
descriptor table entry associated with the USB_CHEPnR registers is described below. The
memory should be addressed using Word (32-bit) accesses.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page 926.

Channel/endpoint transmit buffer descriptor n (USB_CHEP_TXRXBD_n)

Address offset: n*8
This register description applies when corresponding CHEPnR register does not program
the use of double buffering (otherwise refer to following register description)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. COUNTn_TX[9:0]

rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_TX[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:16 COUNTn_TX[9:0]: Transmission byte count
These bits contain the number of bytes to be transmitted by the endpoint/channel associated
with the USB_CHEPnR register at the next IN token addressed to it.
Bits 15:0 ADDRn_TX[15:0]: Transmission buffer address
These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint/channel associated with the USB_CHEPnR register at the next IN token
addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is word
wide and all packet buffers must be word aligned.

Channel/endpoint receive buffer descriptor n [alternate]

(USB_CHEP_TXRXBD_n)
Address offset: n*8
This register description applies when corresponding CHEPnR register programs the use of
double buffering and activates receive buffers (otherwise refer to previous register
description).
This table location is used to store two different values, both required during packet
reception. The most significant bits contains the definition of allocated buffer size, to allow
buffer overflow detection, while the least significant part of this location is written back by the
USB peripheral at the end of reception to give the actual number of received bytes. Due to

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the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint/channel descriptor and it is normally defined during
the enumeration process according to its maxPacketSize parameter value (see “Universal
Serial Bus Specification”).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0]

rw rw rw rw rw rw r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_RX[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 BLSIZE: Block size

This bit selects the size of memory block used to define the allocated buffer area.
– If BLSIZE = 0, the memory block is 2-byte large, which is the minimum block
allowed in a half-word wide memory. With this block size the allocated buffer size
ranges from 2 to 62 bytes.
– If BLSIZE = 1, the memory block is 32-byte large, which permits to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size theoretically ranges from 32 to 1024 bytes, which is the longest
packet size allowed by USB standard specifications. However, the applicable size is
limited by the available buffer memory.
Bits 30:26 NUM_BLOCK[4:0]: Number of blocks
These bits define the number of memory blocks allocated to this packet buffer. The actual
amount of allocated memory depends on the BLSIZE value as illustrated in Table 146.
Bits 25:16 COUNTn_RX[9:0]: Reception byte count
These bits contain the number of bytes received by the endpoint/channel associated with the
USB_CHEPnR register during the last OUT/SETUP transaction addressed to it.
Bits 15:0 ADDRn_RX[15:0]: Reception buffer address
These bits point to the starting address of the packet buffer, which contains the data received
by the endpoint/channel associated with the USB_CHEPnR register at the next OUT/SETUP
token addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is
word wide and all packet buffers must be word aligned.

Table 146. Definition of allocated buffer memory

Value of Memory allocated Memory allocated
NUM_BLOCK[4:0] when BLSIZE=0 when BLSIZE=1

0 (00000) Not allowed 32 bytes

1 (00001) 2 bytes 64 bytes
2 (00010) 4 bytes 96 bytes
3 (00011) 6 bytes 128 bytes
... ... ...
14 (01110) 28 bytes 480 bytes
15 (01111) 30 bytes

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Table 146. Definition of allocated buffer memory (continued)

Value of Memory allocated Memory allocated
NUM_BLOCK[4:0] when BLSIZE=0 when BLSIZE=1

16 (10000) 32 bytes
... ... ...
29 (11101) 58 bytes ...
30 (11110) 60 bytes 992 bytes
31 (11111) 62 bytes 1023 bytes

Channel/endpoint receive buffer descriptor n

(USB_CHEP_RXTXBD_n)
Address offset: n*8 + 4
This register description applies when corresponding CHEPnR register does not program
use of double buffering (otherwise refer to following register description).
This table location is used to store two different values, both required during packet
reception. The most significant bits contains the definition of allocated buffer size, to allow
buffer overflow detection, while the least significant part of this location is written back by the
USB peripheral at the end of reception to give the actual number of received bytes. Due to
the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint/channel descriptor and it is normally defined during
the enumeration process according to its maxPacketSize parameter value (see “Universal
Serial Bus Specification”).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0]

rw rw rw rw rw rw r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_RX[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 BLSIZE: Block size

This bit selects the size of memory block used to define the allocated buffer area.
– If BLSIZE = 0, the memory block is 2-byte large, which is the minimum block
allowed in a half-word wide memory. With this block size the allocated buffer size
ranges from 2 to 62 bytes.
– If BLSIZE = 1, the memory block is 32-byte large, which permits to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size theoretically ranges from 32 to 1024 bytes, which is the longest
packet size allowed by USB standard specifications. However, the applicable size is
limited by the available buffer memory.
Bits 30:26 NUM_BLOCK[4:0]: Number of blocks
These bits define the number of memory blocks allocated to this packet buffer. The actual
amount of allocated memory depends on the BLSIZE value as illustrated in Table 146.

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Bits 25:16 COUNTn_RX[9:0]: Reception byte count

These bits contain the number of bytes received by the endpoint/channel associated with the
USB_CHEPnR register during the last OUT/SETUP transaction addressed to it.
Bits 15:0 ADDRn_RX[15:0]: Reception buffer address
These bits point to the starting address of the packet buffer, which contains the data received
by the endpoint/channel associated with the USB_CHEPnR register at the next OUT/SETUP
token addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is
word wide and all packet buffers must be word aligned.

Channel/endpoint transmit buffer descriptor n [alternate]

(USB_CHEP_RXTXBD_n)
Address offset: n*8 + 4
This register description applies when corresponding CHEPnR register programs use of
double buffering and activates transmit buffers (otherwise refer to previous register
description).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. COUNTn_TX[9:0]

rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_TX[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:16 COUNTn_TX[9:0]: Transmission byte count
These bits contain the number of bytes to be transmitted by the endpoint/channel associated
with the USB_CHEPnR register at the next IN token addressed to it.
Bits 15:0 ADDRn_TX[15:0]: Transmission buffer address
These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint/channel associated with the USB_CHEPnR register at the next IN token
addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is word
wide and all packet buffers must be word aligned.

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28.6.3 USB register map

The table below provides the USB register map and reset values.

Table 147. USB register map and reset values

Offset Register 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DTOGRX

DTOGTX
ERR_RX
ERR_TX
STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
NAK
Res.
Res.
Res.
Res.
Res.
USB_CHEP0R DEVADDR[6:0] RX E X EA[3:0]
0x00
[1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOGRX

DTOGTX
ERR_RX
ERR_TX
STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
Res.
Res.
Res.
Res.
Res.

NAK
USB_CHEP1R DEVADDR[6:0] RX E X EA[3:0]
0x04 [1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
NAK
Res.
Res.
Res.
Res.
Res.

USB_CHEP2R DEVADDR[6:0] RX E X EA[3:0]

0x08
[1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
NAK
Res.
Res.
Res.
Res.
Res.

USB_CHEP3R DEVADDR[6:0] RX E X EA[3:0]

0x0C [1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
Res.
Res.
Res.
Res.
Res.

NAK

USB_CHEP4R DEVADDR[6:0] RX E X EA[3:0]

0x10 [1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
NAK
Res.
Res.
Res.
Res.
Res.

USB_CHEP5R DEVADDR[6:0] RX E X EA[3:0]

0x14
[1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP EPKIND STATT

SETUP
LS_EP

VTRX

VTTX
NAK
Res.
Res.
Res.
Res.
Res.

USB_CHEP6R DEVADDR[6:0] RX E X EA[3:0]

0x18
[1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTOGRX

DTOGTX
ERR_RX
ERR_TX

STAT UTYP STATT

EPKIND
SETUP
LS_EP

VTRX

VTTX
Res.
Res.
Res.
Res.
Res.

NAK

USB_CHEP7R DEVADDR[6:0] RX E X EA[3:0]

0x1C
[1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x20-
Reserved
0x3F
RST_DCONM
PMAOVRM

SUSPRDY
THR512M

SUSPEN
L1REQM

USBRST
WKUPM
SUSPM

ESOFM

L1RES
L2RES

PDWN
ERRM
CTRM

SOFM
HOST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

USB_CNTR
0x40

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
DCON_STAT

RST_DCON
LS_DCON

PMAOVR
THR512

L1REQ
WKUP

ESOF
SUSP
ERR
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CTR

SOF

DIR

USB_ISTR IDN[3:0]
0x44

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXDM
RXDP

LSOF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

LCK

USB_FNR FN[10:0]
0x48 [1:0]
Reset value 0 0 0 0 0 x x x x x x x x x x x
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

USB_DADDR EF ADD[6:0]
0x4C
Reset value 0 0 0 0 0 0 0 0

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0x54
Offset
RM0454

Register

Reset value

Reset value
USB_BCDR
USB_LPMCSR
Res. Res. 31
Res. Res. 30
Res. Res. 29
Res. Res. 28
Res. Res. 27
Res. Res. 26
Res. Res. 25
Res. Res. 24
Res. Res. 23
Res. Res. 22
Res. Res. 21
Res. Res. 20
Res. Res. 19
Res. Res. 18
Res. Res.

RM0454 Rev 5
17
Res. Res. 16
0

DPPU_DPD Res. 15
Res. Res. 14
Res. Res. 13
Res. Res. 12
Res. Res. 11
Res. Res. 10
Res. Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.

Res. Res.
Table 147. USB register map and reset values (continued)

8
0
0

PS2DET 7
0
0

SDET 6
0
0

PDET 5
BESL[3:0]

0
0

DCDET 4
0
0

SDEN REMWAKE 3
0

PDEN Res. 2
0
0

DCDEN LPMACK 1
0
0

BCDEN LPMEN
Universal serial bus full-speed host/device interface (USB)

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29 Debug support (DBG)

29.1 Overview
The STM32G0x0 devices are built around a Cortex®-M0+ core which contains hardware
extensions for advanced debugging features. The debug extensions allow the core to be
stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When
stopped, the core’s internal state and the system’s external state may be examined. Once
examination is complete, the core and the system may be restored and program execution
resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32G0x0 MCUs.
One interface for debug is available:
• Serial wire

Figure 327. Block diagram of STM32G0x0 MCU and Cortex®-M0+-level debug support

STM32 MCU debug suppo rt

Cortex-M0 debug support

Bus matrix
System
interface

Cortex-M0
Core

Debug AP

SWDIO Bridge DBGMCU

SW-DP
SWCLK
Debug AP
NVIC

DWT

BPU

MS19240V2

1. The debug features embedded in the Cortex®-M0+ core are a subset of the Arm CoreSight Design Kit.
®
The Arm Cortex -M0+ core provides integrated on-chip debug support. It is comprised of:
• SW-DP: Serial wire
• BPU: Break point unit
• DWT: Data watchpoint trigger

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It also includes debug features dedicated to the STM32G0x0:

• Flexible debug pinout assignment
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm Cortex®-M0+ core, refer
to the Cortex®-M0+ Technical Reference Manual (see Section 29.2: Reference Arm
documentation).

29.2 Reference Arm documentation

• Cortex®-M0+ Technical Reference Manual (TRM), available from
http://infocenter.arm.com
• Arm Debug Interface V5
• Arm CoreSight Design Kit revision r1p1 Technical Reference Manual

29.3 Pinout and debug port pins

The STM32G0x0 MCUs are available in various packages with different numbers of
available pins.

29.3.1 SWD port pins

Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os.
These pins are available on all packages.

Table 148. SW debug port pins

SW debug port
Pin
SW-DP pin name
assignment
Type Debug assignment

SWDIO I/O Serial Wire Data Input/Output PA13

SWCLK I Serial Wire Clock PA14

29.3.2 SW-DP pin assignment

After reset (SYSRESETn or PORESETn), the pins used for the SW-DP are assigned as
dedicated pins which are immediately usable by the debugger host.
However, the MCU offers the possibility to disable the SWD port and can then release the
associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable
SW-DP port pins, refer to Section 6.3.2: I/O pin alternate function multiplexer and mapping
on page 175.

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29.3.3 Internal pull-up & pull-down on SWD pins

Once the SW I/O is released by the user software, the GPIO controller takes control of these
pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:
• SWDIO: input pull-up
• SWCLK: input pull-down
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.

29.4 ID codes and locking mechanism

There are several ID codes inside the MCU. ST strongly recommends the tool
manufacturers (for example Keil, IAR, Raisonance) to lock their debugger using the MCU
device ID located at address 0x40015800.
Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools
(the revision ID must not be taken into account).

29.5 SWD port

29.5.1 SWD protocol introduction

This synchronous serial protocol uses two pins:
• SWCLK: clock from host to target
• SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.

29.5.2 SWD protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

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Table 149. Packet request (8-bits)

Bit Name Description

0 Start Must be “1”

0: DP Access
1 APnDP
1: AP Access
0: Write Request
2 RnW
1: Read Request
Address field of the DP or AP registers (refer to Table 153 on
4:3 A[3:2]
page 971)
5 Parity Single bit parity of preceding bits
6 Stop 0
Not driven by the host. Must be read as “1” by the target
7 Park
because of the pull-up

Refer to the Cortex®-M0+ TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

Table 150. ACK response (3 bits)

Bit Name Description

001: FAULT
0..2 ACK 010: WAIT
100: OK

The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.

Table 151. DATA transfer (33 bits)

Bit Name Description

WDATA or
0..31 Write or Read data
RDATA
32 Parity Single parity of the 32 data bits

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

29.5.3 SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm one and is set to
0x0BB11477 (corresponding to Cortex®-M0+).

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Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
• The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
• The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
• After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT
acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Cortex®-M0+ TRM and the
CoreSight Design Kit r1p0 TRM.

29.5.4 DP and AP read/write accesses

• Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
• Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
• The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
• Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it fails.

29.5.5 SW-DP registers

Access to these registers are initiated when APnDP=0

Table 152. SW-DP registers

CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register

The manufacturer code is set to the default

00 Read IDCODE Arm code for Cortex®-M0+:
0x0BC11477 (identifies the SW-DP)
00 Write ABORT

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Table 152. SW-DP registers (continued)

CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register

Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
01 Read/Write 0 DP-CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-up
acknowledges)
Purpose is to configure the physical serial
WIRE
01 Read/Write 1 port protocol (like the duration of the
CONTROL
turnaround time)
Enables recovery of the read data from a
READ
10 Read corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
The purpose is to select the current access
10 Write SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
11 Read/Write READ BUFFER transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction

29.5.6 SW-AP registers

Access to these registers are initiated when APnDP=1
There are many AP Registers addressed as the combination of:
• The shifted value A[3:2]
• The current value of the DP SELECT register.

Table 153. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A[3:2] value Description

0x0 00 Reserved, must be kept at reset value.

DP CTRL/STAT register. Used to:
– Request a system or debug power-up
0x4 01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)

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Table 153. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A[3:2] value Description

DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
0x8 10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
0xC 11 after a sequence of operations (without requesting new JTAG-DP
operation)

29.6 Core debug

Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the debug access port. It consists of four registers:

Table 154. Core debug registers

Register Description

The 32-bit Debug Halting Control and Status Register

DHCSR This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
DCRSR
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
DCRDR This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
DEMCR
This provides Vector Catching and Debug Monitor Control.

These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Cortex®-M0+ TRM for further details.
To Halt on reset, it is necessary to:
• enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
• enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register

29.7 BPU (Break Point Unit)

The Cortex®-M0+ BPU implementation provides four breakpoint registers. The BPU is a
subset of the Flash Patch and Breakpoint (FPB) block available in Armv7-M (Cortex-M3 &
Cortex-M4).

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29.7.1 BPU functionality

The processor breakpoints implement PC based breakpoint functionality.
Refer the Armv6-M Arm and the Arm CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.

29.8 DWT (Data Watchpoint)

The Cortex®-M0+ DWT implementation provides two watchpoint register sets.

29.8.1 DWT functionality

The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the Armv6-M Arm.

29.8.2 DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the Armv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the Armv6-M Arm for more information.
The Cortex®-M0+ DWT_PCSR records both instructions that pass their condition codes and
those that fail.

29.9 MCU debug component (DBG)

The MCU debug component helps the debugger provide support for:
• Low-power modes
• Clock control for timers, watchdog and I2C during a breakpoint

29.9.1 Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
• In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.
• In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.
This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.

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29.9.2 Debug support for timers, watchdog and I2C

During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
• They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.

29.10 DBG registers

29.10.1 DBG device ID code register (DBG_IDCODE)

The STM32G0x0 products integrate a device ID code identifying the device and its die
revision.
This code is accessible by the software debug port (two pins) or by the user software.

DBG_IDCODE
Address offset: 0x00
Only 32-bit access supported. Read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DEV_ID
r r r r r r r r r r r r

Bits 31:16 REV_ID[15:0] Revision identifier

This field indicates the revision of the device. Refer to Table 155.
Bits 15:12 Reserved: read 0b0110.
Bits 11:0 DEV_ID[11:0]: Device identifier
This field indicates the device ID. Refer to Table 155.

Table 155. DEV_ID and REV_ID field values

Device DEV_ID Revision code Revision number REV_ID

STM32G0B0xx 0x467 A 1.0 0x1000

A 1.0 0x1000
STM32G070xx 0x460 Z 1.1 0x1000
B 2.0 0x2000
STM32G050xx 0x456 A 1.0 0x1000
A 1.0 0x1000
STM32G030xx 0x466
Z 1.1 0x1001

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29.10.2 DBG configuration register (DBG_CR)

This register configures the low-power modes of the MCU under debug.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
If the debugger host does not support this feature, it is still possible for the user software to
write to this register.
Address offset: 0x04
POR Reset: 0x0000 0000 (not reset by system reset)
Only 32-bit access supported

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_
DBG_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. STAND Res.
STOP
BY
rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DBG_STANDBY: Debug Standby mode
Debug options in Standby modemode.
0: Digital part powered. From software point of view, exiting Standby mode is identical as
fetching reset vector (except for status bits indicating that the MCU exits Standby)
1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator
remaining active. The MCU generates a system reset so that exiting Standby mode has the
same effect as starting from reset.
Bit 1 DBG_STOP: Debug Stop mode
Debug options in Stop mode.
0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked
by the HSI internal RC oscillator.
1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If
Systick is enabled, it may generate periodic interrupt and wake up events.

Upon Stop mode exit, the software must re-establish the desired clock configuration.

29.10.3 DBG APB freeze register 1 (DBG_APB_FZ1)

This register configures the clocking of timers, RTC, IWDG, WWDG, and I2C SMBUS
peripherals of the MCU under debug:
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Power on reset (POR): 0x0000 0000 (not reset by system reset)
Only 32-bit access are supported.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG_I2C2_SMBUS_TIMEOUT(1)

DBG_I2C1_SMBUS_TIMEOUT
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_WWDG_STOP
DBG_IWDG_STOP

DBG_TIM7_STOP

DBG_TIM6_STOP

DBG_TIM3_STOP
DBG_RTC_STOP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
rw rw rw rw rw rw

1. Only significant on devices integrating I2C2, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.
Bits 29:23 Reserved, must be kept at reset value.
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Clocking of IWDG counter when the core is halted
This bit enables/disables the clock to the counter of IWDG when the core is halted:
0: Enable
1: Disable
Bit 11 DBG_WWDG_STOP: Clocking of WWDG counter when the core is halted
This bit enables/disables the clock to the counter of WWDG when the core is halted:
0: Enable
1: Disable
Bit 10 DBG_RTC_STOP: Clocking of RTC counter when the core is halted
This bit enables/disables the clock to the counter of RTC when the core is halted:
0: Enable
1: Disable
Bits 9:6 Reserved, must be kept at reset value.

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Bit 5 DBG_TIM7_STOP: Clocking of TIM7 counter when the core is halted.

This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
0: Enable
1: Disable
Bit 4 DBG_TIM6_STOP: Clocking of TIM6 counter when the core is halted
This bit enables/disables the clock to the counter of TIM6 when the core is halted:
0: Enable
1: Disable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 DBG_TIM3_STOP: Clocking of TIM3 counter when the core is halted
This bit enables/disables the clock to the counter of TIM3 when the core is halted:
0: Enable
1: Disable
Bit 0 Reserved, must be kept at reset value.

29.10.4 DBG APB freeze register 2 (DBG_APB_FZ2)

This register configures the clocking of timer counters when the MCU is under debug.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address offset: 0x0C
POR: 0x0000 0000 (not reset by system reset)
Only 32-bit access is supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG_TIM15_STOP(1)
DBG_TIM17_STOP

DBG_TIM16_STOP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM14_STOP

DBG_TIM1_STOP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw rw

1. Only significant on devices integrating TIM15, otherwise reserved. Refer to Section 1.4: Availability of peripherals

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Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DBG_TIM17_STOP: Clocking of TIM17 counter when the core is halted
This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0: Enable
1: Disable
Bit 17 DBG_TIM16_STOP: Clocking of TIM16 counter when the core is halted
This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0: Enable
1: Disable
Bit 16 DBG_TIM15_STOP: Clocking of TIM15 counter when the core is halted
This bit enables/disables the clock to the counter of TIM15 when the core is halted:
0: Enable
1: Disable
Bit 15 DBG_TIM14_STOP: Clocking of TIM14 counter when the core is halted
This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0: Enable
1: Disable
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: Clocking of TIM1 counter when the core is halted
This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0: Enable
1: Disable
Bits 10:0 Reserved, must be kept at reset value.

29.10.5 DBG register map

The following table summarizes the Debug registers.
.

Table 156. DBG register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DBG_
Res.
Res.
Res.
Res.

REV_ID DEV_ID
0x00 IDCODE

Reset value(1) X X X X X X X X X X X X X X X X 0 1 1 0 X X X X X X X X X X X X
DBG_STANDBY
DBG_STOP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

DBG_CR
0x04

Reset value 0 0

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0x0C
Offset
RM0454

DBG_
DBG_

(DBG_IDCODE).
APB_FZ2
APB_FZ1
Register

Reset value
Reset value
Res. Res. 31
Res. Res. 30
Res. Res. 29
Res. Res. 28
Res. Res. 27
Res. Res. 26
Res. Res. 25
Res. Res. 24
Res. Res. 23
0

Res. DBG_I2C2_SMBUS_TIMEOUT 22
0

Res. DBG_I2C1_SMBUS_TIMEOUT 21
Res. Res. 20
Res. Res. 19
0
0 DBG_TIM17_STOP Res. 18
DBG_TIM16_STOP Res.

RM0454 Rev 5
17
0

DBG_TIM15_STOP Res. 16
0

DBG_TIM14_STOP Res. 15
Res. Res. 14
Res. Res. 13
0

Res. DBG_IWDG_STOP 12
0
0

DBG_TIM1_STOP DBG_WWDG_STOP 11
0

Res. DBG_RTC_STOP 10
Res. Res. 9
Refer to Section 2.2 on page 44 for the register boundary addresses.

Res. Res. 8
Table 156. DBG register map and reset values (continued)

Res. Res. 7
Res. Res. 6
0

Res. DBG_TIM7_STOP 5
0

Res. DBG_TIM6_STOP 4
1. The reset value is product dependent. For more information, refer to Section 29.10.1: DBG device ID code register

Res. Res. 3
Res. Res. 2
0

Res. DBG_TIM3_STOP 1
Res. Res. 0

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30 Device electronic signature

The device electronic signature is stored in the System memory area of the Flash memory
module, and can be read using the debug interface or by the CPU. It contains factory-
programmed identification and calibration data that allow the user firmware or other external
devices to automatically match to the characteristics of the STM32G0x0 microcontroller.

30.1 Flash memory size data register

Base address: 0x1FFF 75E0
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_SIZE
r r r r r r r r r r r r r r r r

Bits 15:0 FLASH_SIZE[15:0]: Flash memory size

This bitfield indicates the size of the device Flash memory expressed in Kbytes.
As an example, 0x040 corresponds to 64 Kbytes.

30.2 Package data register

Base address: 0x1FFF 7500
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKG[3:0]
r r r r

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Bits 15:4 Reserved

Bits 3:0 PKG[3:0]: Package type
For STM32G070xx:
0100: LQFP32
1000: LQFP48
1100: LQPF64
Others: Reserved
For STM32G030xx and STM32G050xx:
0100: LQFP32
0111: LQFP48
1100: LQPF64
Others: Reserved
For STM32G0B0xx:
0000: LQFP100
0001: LQFP32
0100: LQFP48
0111: LQFP64
Others: Reserved

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31 Revision history

Table 157. Document revision history

Date Revision Changes

21-Nov-2018 1 Initial release

Integration of STM32G030xx, affecting:
– Section 1.4: Availability of peripherals
– Figure 2: Memory map
– Table 4: STM32G030xx and STM32G050xx memory boundary addresses
(added)
– Section 2.3: Embedded SRAM
– Section 2.5: Boot configuration
– Section 3.3: FLASH functional description
– Section Table 8.: Flash memory organization for single-bank devices (title
modified)
– Section 4: Power control (PWR) (indication of bits not available on
STM32G030xx)
– Figure 8: Clock tree
– Section 5: Reset and clock control (RCC) (indication of bits not available on
STM32G030xx)
– Section 7: System configuration controller (SYSCFG) (indication of bits not
17-Apr-2019 2
available on STM32G030xx)
– Section 7.1.2: SYSCFG configuration register 2 (SYSCFG_CFGR2)
(clamping diode enable bits added)
– Section 9.1: Introduction
– Table 33: DMA implementation
– Table 38: DMAMUX instantiation
– Section 11.3: Interrupt and exception vectors
– Section 12: Extended interrupt and event controller (EXTI) (indication of bits
not available on STM32G030xx)
– Figure 115: General-purpose timer block diagram and Figure 138: External
trigger input block
– Section 20: Infrared interface (IRTIM)
– Table 121: USART features
– Table 155: DEV_ID and REV_ID field values
– Table 29.10.4: DBG APB freeze register 2 (DBG_APB_FZ2)
– Section 30.2: Package data register
– Empty check section
– Section 3.3.8: FLASH Main memory programming sequences
– User and read protection option bytes section
– Option byte loading section
27-May-2020 3 – Table 14: Access status versus protection level and execution modes
– Section 3.7.1: FLASH access control register (FLASH_ACR)Section 3.7.8:
FLASH option register (FLASH_OPTR) (BORR_LEV[1:0] swapped with
BORF_LEV[1:0]
– Section 6.3: GPIO functional description: introductory information modified
– Former USB PD / Dead battery section removed

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RM0454 Revision history

Table 157. Document revision history (continued)

Date Revision Changes

– Section 30.1: Flash memory size data register: reset value corrected
– Table 35: Programmable data width and endian behavior (when
PINC = MINC = 1): NDT in the first row corrected from 8 to 4
– Table 39: DMAMUX: assignment of multiplexer inputs to resources:
TIM16/17_TRG_COM corrected to TIM16/17_COM
– Section 14.2: ADC main features: VTS corrected to VSENSE
– Section 14.3.1: ADC pins and internal signals: tables and their organization
(External triggers table brought to this section)
– Table 58: Latency between trigger and start of conversion: latency values
– Section : Calculating the actual VREF+ voltage using the internal reference
voltage - corrected from VDDA to VREF+
– Section 15: Advanced-control timer (TIM1): general update
– Figure 141: Capture/Compare channel 1 main circuit and Figure 142: Output
stage of Capture/Compare channel (channel 1) updated
– Figure 159: Master/slave connection example with 1 channel only timers
added
– Table 74: Output control bit for standard OCx channels updated
3 – Section 16.4.24: TIM3 timer input selection register (TIM3_TISEL): removed
27-May-2020
cont’d TI4SEL[3:0] and TI3SEL[3:0]
– Figure 175: General-purpose timer block diagram (TIM14): updated
– Figure 186: Capture/compare channel 1 main circuit and Figure 187: Output
stage of capture/compare channel (channel 1) updated
– Section 18.3.11: Using timer output as trigger for other timers (TIM14) added
– Figure 205: Capture/compare channel 1 main circuit updated
– Section 19.4.23: Using timer output as trigger for other timers
(TIM16/TIM17) added
– Former Section 28.3.4 Advanced watchdog interrupt feature moved to
Section 22.4: WWDG interrupts
– Section 25.4.3: I2C pins and internal signals added
– Section 25.7.3: I2C own address 1 register (I2C_OAR1) and Section 25.7.8:
I2C interrupt clear register (I2C_ICR) updated
– Section 26.4: USART implementation updated - tables reorganized
– Section 38: USB Type-C™ / USB Power Delivery interface (UCPD): general
update
– Table 155: DEV_ID and REV_ID field values
– Section 29.10.2: DBG configuration register (DBG_CR)

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Table 157. Document revision history (continued)

Date Revision Changes

6-Oct-2020 4 Updated Section 3.4.2: FLASH option byte programming.

Extension of the document scope to cover STM32G050xx and STM32G0B0
devices, with corresponding addition or update of:
– Section 1.1: General information
– Section 1.4: Availability of peripherals
– Section 2.2: Memory organization
– Section 3: Embedded Flash memory (FLASH)
– Section 4: Power control (PWR)
– Section 5: Reset and clock control (RCC)
– Section 7: System configuration controller (SYSCFG)
– Section 8: Interconnect matrix
– Section 9: Direct memory access controller (DMA)
– Section 10: DMA request multiplexer (DMAMUX)
– Section 11: Nested vectored interrupt controller (NVIC)
20-Nov-2020 5
– Section 12: Extended interrupt and event controller (EXTI)
– Section 14: Analog-to-digital converter (ADC)
– Section 15: Advanced-control timer (TIM1)
– Section 16: General-purpose timers (TIM3/TIM4)
– Section 18: General-purpose timers (TIM14)
– Section 19: General-purpose timers (TIM15/TIM16/TIM17)
– Section 24: Tamper and backup registers (TAMP)
– Section 25: Inter-integrated circuit (I2C) interface
– Section 26: Universal synchonous receiver transmitter (USART)
– Section 27: Serial peripheral interface / integrated interchip sound (SPI/I2S)
– Section 28: Universal serial bus full-speed host/device interface (USB)
– Section 29: Debug support (DBG)
– Section 30: Device electronic signature

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 Index

Index

A EXTI_FPR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 261
EXTI_FTSR1 . . . . . . . . . . . . . . . . . . . . . . . . . 260
ADC_AWD1TR . . . . . . . . . . . . . . . . . . . . . . .324
EXTI_IMR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 263
ADC_AWD2CR . . . . . . . . . . . . . . . . . . . . . . .330
EXTI_RPR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 261
ADC_AWD2TR . . . . . . . . . . . . . . . . . . . . . . .325
EXTI_RTSR1 . . . . . . . . . . . . . . . . . . . . . . . . . 259
ADC_AWD3CR . . . . . . . . . . . . . . . . . . . . . . .330
EXTI_SWIER1 . . . . . . . . . . . . . . . . . . . . . . . . 260
ADC_AWD3TR . . . . . . . . . . . . . . . . . . . . . . .329
ADC_CALFACT . . . . . . . . . . . . . . . . . . . . . . .331
ADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .331 F
ADC_CFGR1 . . . . . . . . . . . . . . . . . . . . . . . . .318 FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . .322 FLASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC_CHSELR . . . . . . . . . . . . . . . . . . . . 326-327 FLASH_ECCR . . . . . . . . . . . . . . . . . . . . . . . . . 79
ADC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 FLASH_ECCR2 . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 FLASH_KEYR . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 FLASH_OPTKEYR . . . . . . . . . . . . . . . . . . . . . 75
ADC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 FLASH_OPTR . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC_SMPR . . . . . . . . . . . . . . . . . . . . . . . . . .323 FLASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
FLASH_WRP1AR . . . . . . . . . . . . . . . . . . . . . . 82
C FLASH_WRP1BR . . . . . . . . . . . . . . . . . . . . . . 82
FLASH_WRP2AR . . . . . . . . . . . . . . . . . . . . . . 83
CRC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
FLASH_WRP2BR . . . . . . . . . . . . . . . . . . . . . . 84
CRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
CRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
CRC_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 G
CRC_POL . . . . . . . . . . . . . . . . . . . . . . . . . . .272 GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 187
GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 186
D GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 187
GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 184
DBG_APB_FZ1 . . . . . . . . . . . . . . . . . . . . . . .975
GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 184
DBG_APB_FZ2 . . . . . . . . . . . . . . . . . . . . . . .977
GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 185
DBG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .975
GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 182
DBG_IDCODE . . . . . . . . . . . . . . . . . . . . . . . .974
GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 184
DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .226
GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 183
DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .230
GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 182
DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .229
GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 183
DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .230
DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .225
DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 I
DMAMUX_CFR . . . . . . . . . . . . . . . . . . . . . . .245 I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
DMAMUX_CSR . . . . . . . . . . . . . . . . . . . . . . .245 I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
DMAMUX_CxCR . . . . . . . . . . . . . . . . . . . . . .244 I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
DMAMUX_RGCFR . . . . . . . . . . . . . . . . . . . .247 I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
DMAMUX_RGSR . . . . . . . . . . . . . . . . . . . . . .247 I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
DMAMUX_RGxCR . . . . . . . . . . . . . . . . . . . . .246 I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
E I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . . 767
EXTI_EMR1 . . . . . . . . . . . . . . . . . . . . . . . . . .264
I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . . . 766
EXTI_EXTICRx . . . . . . . . . . . . . . . . . . . . . . .262
I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . 772-773

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Index

IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . .638 RTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . . 682

IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . .639 RTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . . . 683
IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . .640 RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . . 676
IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .641 RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . . .642 RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
RTC_ICSR . . . . . . . . . . . . . . . . . . . . . . . . . . 669
RTC_MISR . . . . . . . . . . . . . . . . . . . . . . . . . . 684
P
RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . . 671
PWR_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .104 RTC_SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
PWR_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .105 RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . 677
PWR_CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . .106 RTC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
PWR_CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . .107 RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
PWR_PDCRA . . . . . . . . . . . . . . . . . . . . . . . .111 RTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
PWR_PDCRB . . . . . . . . . . . . . . . . . . . . . . . .112 RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . . 678
PWR_PDCRC . . . . . . . . . . . . . . . . . . . . . . . .113 RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . . 679
PWR_PDCRD . . . . . . . . . . . . . . . . . . . . 114-115 RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . . 678
PWR_PDCRF . . . . . . . . . . . . . . . . . . . . . . . .116 RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
PWR_PUCRA . . . . . . . . . . . . . . . . . . . . . . . .111 RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . 672
PWR_PUCRB . . . . . . . . . . . . . . . . . . . . . . . .112
PWR_PUCRC . . . . . . . . . . . . . . . . . . . . . . . .113
PWR_PUCRD . . . . . . . . . . . . . . . . . . . . 114-115 S
PWR_PUCRF . . . . . . . . . . . . . . . . . . . . . . . .115 SPIx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
PWR_SCR . . . . . . . . . . . . . . . . . . . . . . . . . . .110 SPIx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
PWR_SR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .108 SPIx_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . 915
PWR_SR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .109 SPIx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
SPIx_I2SCFGR . . . . . . . . . . . . . . . . . . . . . . . 916
SPIx_I2SPR . . . . . . . . . . . . . . . . . . . . . . . . . 918
R
SPIx_RXCRCR . . . . . . . . . . . . . . . . . . . . . . . 915
RCC_AHBENR . . . . . . . . . . . . . . . . . . . . . . .152 SPIx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
RCC_AHBRSTR . . . . . . . . . . . . . . . . . . . . . .147 SPIx_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . 915
RCC_AHBSMENR . . . . . . . . . . . . . . . . . . . . .158 SYSCFG_CFGR1 . . . . . . . . . . . . . . . . . . . . . 189
RCC_APBENR1 . . . . . . . . . . . . . . . . . . . . . . .153 SYSCFG_CFGR2 . . . . . . . . . . . . . . . . . . . . . 192
RCC_APBENR2 . . . . . . . . . . . . . . . . . . . . . . .155 SYSCFG_ITLINE0 . . . . . . . . . . . . . . . . . . . . 194
RCC_APBRSTR1 . . . . . . . . . . . . . . . . . . . . .148 SYSCFG_ITLINE10 . . . . . . . . . . . . . . . . . . . 198
RCC_APBRSTR2 . . . . . . . . . . . . . . . . . . . . .150 SYSCFG_ITLINE11 . . . . . . . . . . . . . . . . . . . 198
RCC_APBSMENR1 . . . . . . . . . . . . . . . . . . . .159 SYSCFG_ITLINE12 . . . . . . . . . . . . . . . . . . . 199
RCC_APBSMENR2 . . . . . . . . . . . . . . . . . . . .161 SYSCFG_ITLINE13 . . . . . . . . . . . . . . . . . . . 199
RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . .165 SYSCFG_ITLINE14 . . . . . . . . . . . . . . . . . . . 199
RCC_CCIPR . . . . . . . . . . . . . . . . . . . . . . . . .163 SYSCFG_ITLINE16 . . . . . . . . . . . . . . . . . . . 200
RCC_CCIPR2 . . . . . . . . . . . . . . . . . . . . . . . .164 SYSCFG_ITLINE17 . . . . . . . . . . . . . . . . . . . 200
RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . .137 SYSCFG_ITLINE18 . . . . . . . . . . . . . . . . . . . 200
RCC_CICR . . . . . . . . . . . . . . . . . . . . . . . . . . .145 SYSCFG_ITLINE19 . . . . . . . . . . . . . . . . . . . 201
RCC_CIER . . . . . . . . . . . . . . . . . . . . . . . . . . .143 SYSCFG_ITLINE2 . . . . . . . . . . . . . . . . . . . . 194
RCC_CIFR . . . . . . . . . . . . . . . . . . . . . . . . . . .143 SYSCFG_ITLINE20 . . . . . . . . . . . . . . . . . . . 201
RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 SYSCFG_ITLINE21 . . . . . . . . . . . . . . . . . . . 201
RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .167 SYSCFG_ITLINE22 . . . . . . . . . . . . . . . . . . . 202
RCC_ICSCR . . . . . . . . . . . . . . . . . . . . . . . . .136 SYSCFG_ITLINE23 . . . . . . . . . . . . . . . . . . . 202
RCC_IOPENR . . . . . . . . . . . . . . . . . . . . . . . .151 SYSCFG_ITLINE24 . . . . . . . . . . . . . . . . . . . 202
RCC_IOPRSTR . . . . . . . . . . . . . . . . . . . . . . .146 SYSCFG_ITLINE25 . . . . . . . . . . . . . . . . . . . 203
RCC_IOPSMENR . . . . . . . . . . . . . . . . . . . . .157 SYSCFG_ITLINE26 . . . . . . . . . . . . . . . . . . . 203
RCC_PLLCFGR . . . . . . . . . . . . . . . . . . . . . . .140 SYSCFG_ITLINE27 . . . . . . . . . . . . . . . . . . . 204
RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . .680 SYSCFG_ITLINE28 . . . . . . . . . . . . . . . . . . . 204
RTC_ALRMASSR . . . . . . . . . . . . . . . . . . . . .681

986/989 RM0454 Rev 5

 Index

SYSCFG_ITLINE29 . . . . . . . . . . . . . . . . . . . .204 TIM14_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 544

SYSCFG_ITLINE3 . . . . . . . . . . . . . . . . . . . . .195 TIM14_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
SYSCFG_ITLINE4 . . . . . . . . . . . . . . . . . . . . .195 TIM14_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 545
SYSCFG_ITLINE5 . . . . . . . . . . . . . . . . . . . . .196 TIM15_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 608
SYSCFG_ITLINE6 . . . . . . . . . . . . . . . . . . . . .196 TIM15_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . 602
SYSCFG_ITLINE7 . . . . . . . . . . . . . . . . . . . . .196 TIM15_BDTR . . . . . . . . . . . . . . . . . . . . . . . . 604
SYSCFG_ITLINE8 . . . . . . . . . . . . . . . . . . . . .197 TIM15_CCER . . . . . . . . . . . . . . . . . . . . . . . . 599
SYSCFG_ITLINE9 . . . . . . . . . . . . . . . . . . . . .197 TIM15_CCMR1 . . . . . . . . . . . . . . . . . . . 595-596
TIM15_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . 603
TIM15_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . 604
T
TIM15_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . 602
TAMP_BKPxR . . . . . . . . . . . . . . . . . . . . . . . .702 TIM15_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 587
TAMP_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . .695 TIM15_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 588
TAMP_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . .696 TIM15_DCR . . . . . . . . . . . . . . . . . . . . . . . . . 607
TAMP_FLTCR . . . . . . . . . . . . . . . . . . . . . . . .697 TIM15_DIER . . . . . . . . . . . . . . . . . . . . . . . . . 591
TAMP_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .698 TIM15_DMAR . . . . . . . . . . . . . . . . . . . . . . . . 607
TAMP_MISR . . . . . . . . . . . . . . . . . . . . . . . . .700 TIM15_EGR . . . . . . . . . . . . . . . . . . . . . . . . . 594
TAMP_SCR . . . . . . . . . . . . . . . . . . . . . . . . . .701 TIM15_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 602
TAMP_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .699 TIM15_RCR . . . . . . . . . . . . . . . . . . . . . . . . . 603
TIM1_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . .428 TIM15_SMCR . . . . . . . . . . . . . . . . . . . . . . . . 590
TIM1_AF2 . . . . . . . . . . . . . . . . . . . . . . . . . . .429 TIM15_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
TIM1_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . .417 TIM15_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 608
TIM1_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .420 TIM16_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 629
TIM1_CCER . . . . . . . . . . . . . . . . . . . . . . . . . .414 TIM16_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 629
TIM1_CCMR1 . . . . . . . . . . . . . . . . . . . . 407-408 TIM17_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 630
TIM1_CCMR2 . . . . . . . . . . . . . . . . . . . . 411-412 TIM17_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 630
TIM1_CCMR3 . . . . . . . . . . . . . . . . . . . . . . . .426 TIM3_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
TIM1_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . . .418 TIM3_TISEL . . . . . . . . . . . . . . . . . . . . . . . . . 502
TIM1_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . .419 TIM4_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
TIM1_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . .419 TIM4_TISEL . . . . . . . . . . . . . . . . . . . . . . . . . 503
TIM1_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . .420 TIMx_ARR . . . . . . . . . . . . . . . . . . . 498, 519, 623
TIM1_CCR5 . . . . . . . . . . . . . . . . . . . . . . . . . .427 TIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . . 625
TIM1_CCR6 . . . . . . . . . . . . . . . . . . . . . . . . . .428 TIMx_CCER . . . . . . . . . . . . . . . . . . . . . 495, 620
TIM1_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . .417 TIMx_CCMR1 . . . . . . . . . . . . 489, 491, 617-618
TIM1_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .396 TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . 493-494
TIM1_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .397 TIMx_CCR1 . . . . . . . . . . . . . . . . . . . . . . 498, 624
TIM1_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . .424 TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 499
TIM1_DIER . . . . . . . . . . . . . . . . . . . . . . . . . .402 TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 499
TIM1_DMAR . . . . . . . . . . . . . . . . . . . . . . . . .425 TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 500
TIM1_EGR . . . . . . . . . . . . . . . . . . . . . . . . . . .406 TIMx_CNT . . . . . . . . . . . . . . . 496-497, 518, 622
TIM1_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . .417 TIMx_CR1 . . . . . . . . . . . . . . . . . . . 479, 515, 612
TIM1_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . .418 TIMx_CR2 . . . . . . . . . . . . . . . . . . . 480, 517, 613
TIM1_SMCR . . . . . . . . . . . . . . . . . . . . . . . . .400 TIMx_DCR . . . . . . . . . . . . . . . . . . . . . . . 501, 628
TIM1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .404 TIMx_DIER . . . . . . . . . . . . . . . . . . 485, 517, 614
TIM1_TISEL . . . . . . . . . . . . . . . . . . . . . . . . . .430 TIMx_DMAR . . . . . . . . . . . . . . . . . . . . . 501, 628
TIM14_ARR . . . . . . . . . . . . . . . . . . . . . . . . . .544 TIMx_EGR . . . . . . . . . . . . . . . . . . . 488, 518, 616
TIM14_CCMR1 . . . . . . . . . . . . . . . . . . . 539-540 TIMx_PSC . . . . . . . . . . . . . . . . . . . 497, 519, 623
TIM14_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . .544 TIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
TIM14_CNT . . . . . . . . . . . . . . . . . . . . . . . . . .543 TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . . . . . 482
TIM14_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . .536 TIMx_SR . . . . . . . . . . . . . . . . . . . . 486, 518, 615
TIM14_DIER . . . . . . . . . . . . . . . . . . . . . . . . .537
TIM14_EGR . . . . . . . . . . . . . . . . . . . . . . . . . .538

RM0454 Rev 5 987/989

Index

U
USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . .843
USART_CR1 . . . . . . . . . . . . . . . . . . . . .827, 831
USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .834
USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . .838
USART_GTPR . . . . . . . . . . . . . . . . . . . . . . . .843
USART_ICR . . . . . . . . . . . . . . . . . . . . . . . . . .857
USART_ISR . . . . . . . . . . . . . . . . . . . . . .846, 852
USART_PRESC . . . . . . . . . . . . . . . . . . . . . . .860
USART_RDR . . . . . . . . . . . . . . . . . . . . . . . . .859
USART_RQR . . . . . . . . . . . . . . . . . . . . . . . . .845
USART_RTOR . . . . . . . . . . . . . . . . . . . . . . . .844
USART_TDR . . . . . . . . . . . . . . . . . . . . . . . . .859
USB_BCDR . . . . . . . . . . . . . . . . . . . . . . . . . .949
USB_CHEP_RXTXBD_n . . . . . . . . . . . . . . . .963
USB_CHEP_TXRXBD_n . . . . . . . . . . . .960, 962
USB_CHEPnR . . . . . . . . . . . . . . . . . . . . . . . .951
USB_CNTR . . . . . . . . . . . . . . . . . . . . . . . . . .941
USB_DADDR . . . . . . . . . . . . . . . . . . . . . . . . .948
USB_FNR . . . . . . . . . . . . . . . . . . . . . . . . . . .947
USB_ISTR . . . . . . . . . . . . . . . . . . . . . . . . . . .944
USB_LPMCSR . . . . . . . . . . . . . . . . . . . . . . . .949

W
WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .648
WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .647
WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .649

988/989 RM0454 Rev 5

RM0454

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RM0454 Rev 5 989/989

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