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Mid 1 Q

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K.M. Abir Mahmud Moin
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© © All Rights Reserved
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EEE 416 (VLSI CIRCUITS AND SYSTEMS)

MID I TIME 70 MINUTES


FACULTY OF SCIENCES & ENGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC
ENGINEERING

(EACH QUESTION HAS 10 MARKS: 4×10=10)

1. Design a circuit that can tarnasfer signal without any distortion and explain your
design with signals. Draw tentative top view layout of the switch. Your design
supposed to be in the 0.12 micron node considering the fact that a standard nMOS
in this node can carry 1 mA current whereas your design should be able to withstand
4 mA current. MARKS 10.

2. Latchup effect is known to be a fundamental concern in CMOS based integrated circuits.


Explain latch up effect in detail using appropriate diagrams. How latch up can be
avoided in CMOS based circuits? 10

3. When multiple inverters are connected to a common bus bar whar problems might
arise? How this problem can be avoided using modified inverter? Explain your
proposed inverter operation with circuit diagram and draw an optimised layout
diagram of such an inverter. 10

4. Design a CMOS inverter block in 0.12 micron node. It is known that an inverter in
this node which comprise one nMOS and pMOS devices standarad block
corressponds to a current rating of 1 mA whereas your design should have a rating
of 4 mA. Your layout should be optimised in terms of area saving and output node
capaciatnce inssues. 10

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