Performance Improvement of Flash Memory By

Error Pre-checking Scheme and Error Correction

Helen Mary Anjana Devi S
2024 1st International Conference on Trends in Engineering Systems and Technologies (ICTEST) | 979-8-3503-0779-5/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICTEST60614.2024.10576188

Department of Electronics Engineering Department of Electronics Engineering

Model Engineering College, Thrikkakara, Kochi Model Engineering College, Thrikkakara, Kochi
APJ Abdul Kalam Technological University APJ Abdul Kalam Technological University
Kerala, India Kerala, India
[email protected] [email protected]

Abstract—Flash memory serves as a pivotal nonvolatile data improved if the decision-making process can be partially
storage technology, ensuring data persistence even in the absence skipped.
of power, and is ubiquitous in devices such as USB drives,
Preliminary analysis shows that early NAND flash data are
SSDs, and memory cards. The reliability of this technology is
paramount for safeguarding valuable data. Establishing robust error-free. These data errors can be avoided when performing
error check systems, adhering to stringent data integrity policies, LDPC processing. However, if all data, including error data,
and meticulously preventing data corruption during write oper- is checked before a decision is made, it will cause further
ations are imperative practices to maintain data integrity. Em- preflight delay and reduce readability.
ploying pre-error checking procedures can bolster control over
error data, thus diminishing erroneous decisions. Introducing a Inspired by these observations and analysis, in this paper, we
Dynamic Error Pre-Check Strategy (DEPS) offers a proactive propose an error precheck (DEPS) to improve the readability
approach to detecting and mitigating data imperfections in of SSDs. This method dynamically combines fast-forward
Flash memory, thereby enhancing its reliability and performance. processing with LDPC decision-making for data exchange
Furthermore, enhancing SSD readability can be accomplished errors[13,14]. To maximize efficiency, DEPS has adopted a
by partitioning large files into smaller pages, a strategy that
not only enhances SSD readability but also augments average subpage procedure for reporting erroneous information. DEPS
reading speed, optimizes space utilization, and curtails energy is also implementing a new forward control (PC) system [11].
consumption in flash memory systems. This optimized approach To my knowledge, this is the first time we have used a pre-
results in notable reductions in area, on-chip power, junction flight in 3D NAND flash memory, which has not been covered
temperature, and process delay by 60.19%, 65.86%, 51.7%, and in previous articles [12]. Models for predicting data on defec-
66.5% respectively. These reductions signify improved resource
efficiency, decreased power consumption, improved thermal man- tive products, dynamic use of preliminary inspection, subpage
agement, and, ultimately, increased reliability and performance plans, and control of computer processes are completely new.
of Flash memory systems. In general, this method can be effectively used to improve
Keywords—Flash Memory, Error Pre-Checking, Error Correc- the readability of SSDs. The main results of this article are
tion summarized below. We collected minor errors in different P/E
cycles and RTs in flash memory. A significant portion of the
I. I NTRODUCTION
data showed that there were no errors during the initial life of
High capacity flash memory has become a promising the 3D NAND flash memory.
method for processing large amounts of data [1, 2]. As 3D
NAND flash memory capacity increases, data reliability is II. R ELATED W ORK
affected due to program/erase (P/E) cycles, data retention time
(RT) [3, 4], and other factors [5]. To ensure data reliability The general design of DEPS is shown in Fig. 1 [1]. Each
from high error correction, low-density parity check (LDPC) subpage (logical page) uses a flag to register if there is a bit
codes are used [6, 7]. However, due to the complexity of the error. The flag vector contains a bitmap cached in the SSD
decision, the use of LDPC codes may lead to reduced readabil- RAM. All flags are initialized to 0. A value of 0 indicates
ity and high power consumption [8, 9]. Especially when the that there have been no errors since the last write or read
SSD is equipped with many ways to improve performance, to NAND flash memory, and the data should be checked for
the inconsistency of read requests will be fed to the LDPC errors. DEPS replaces SSD reading and writing. When issuing
decoder, creating a closed line of code. Therefore, the LDPC a read command, DEPS first determines whether the historical
decision becomes the basis for the design of advanced SSDs. RBER of the block exceeds the RBER threshold (RBERth )
Although the adoption of more LDPC decoders could reduce determined by the R-SWBE-RBER formula. If RBER exceeds
this decision, the number of LDPC decoders is limited by RBERth , it will be evaluated directly, as is repeated to check
chip area and power consumption [10], and LDPC decoders data error. If not and the flag is equal to 0, a check will be
will generate a lot of heat. However, reading can be greatly performed to determine whether the data contains errors. When

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 Fig. 1. The Overview Design of DEPS [1]

a data error is detected, the bit flag should be set to 1 and the the NAND flash memory. Generate a CRC code based on the
data should be sent to the LDPC decoder for processing. data content and appends it to the stored information.
DEPS replaces SSD reading and writing. When issuing a Real-time Error Detection: During read operations, the
read command, DEPS first determines whether the historical CRC code is recalculated, and any discrepancy between the
RBER of the block exceeds the RBER threshold (RBERth ) calculated and stored CRC codes indicates the presence of er-
determined by the R-SWBE-RBER formula. If RBER exceeds rors. This enables real-time error detection without significant
RBERth , it will be evaluated directly, as is repeated to computational overhead.
check data error. If not and the flag is equal to 0, a check Early Error Identification: By identifying errors at an early
will be performed to determine whether the data contains stage, the proposed CRC prechecking mechanism allows for
errors. When a data error is detected, the bit flag should be proactive error management, contributing to improved data in-
set to 1 and the data should be sent to the LDPC decoder tegrity. Low Overhead: The CRC pre-checking process incurs
for processing. However, if the results of the check show minimal computational overhead, making it suitable for high-
that the data are error-free, they will be used directly. Since speed data access scenarios.
control latency is lower than LDPC, overall performance will
increase [11].When typing the command, the PC is calculated
simultaneously with the LDPC encoding. At the same time,
the flag will also be set to 0. Due to the parallelism between B. Error Correcting Code using LDPC Algorithm
PC computation and LDPC encoding, DEPS does not reduce
the write performance of the SSD. A body page can be The second component focuses on error correction using
divided into several content pages (sub-pages) using traditional the low-density parity check (LDPC) encoding algorithm, a
information placement strategies. The user area stores user powerful technique to correct errors with a low redundancy
information, and the OOB area stores service information, overhead.
such as ECC, page numbers, or status pages. DEPS uses a LDPC Encoding: LDPC codes are applied to the data,
preflight algorithm to check whether the data contains minor introducing redundancy that facilitates error correction. The
errors. Therefore, it requires the entry of an additional pre- encoding process is optimized to ensure minimal impact on
check code (PC) [11]. overall storage space.
Syndrome Calculation: During read operations, the LDPC
III. P ROPOSED WORK
decoder calculates syndromes based on the received data and
A. Error Prechecking using CRC Algorithm compares them with precomputed syndromes. Discrepancies
The first component of our proposed method involves im- are indicative of errors that can be corrected.
plementing a robust error prechecking mechanism using the High Error Correction Capability: LDPC codes provide a
Cyclic Redundancy Check (CRC) algorithm. CRC is known high degree of error correction capability, addressing both
for its efficiency in detecting errors in data transmission and random and burst errors commonly encountered in NAND
storage. flash memory. Space-Efficient Encoding: The LDPC encoding
Dynamic CRC Prechecking: The CRC pre-checking algo- algorithm is chosen for its ability to achieve substantial error
rithm dynamically evaluates the integrity of the data stored in correction with minimal additional storage requirements.

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 Fig. 2. Block Diagram of the proposed work

C. Integration of Error Prechecking and Error Correcting processes operate in parallel, minimizing latency during read
Code operations.
Dynamic Adaptation: The system dynamically adapts the
The final step involves the seamless integration of the CRC-
error correction strength based on the severity and nature of
based error prechecking and LDPC-based error correction into
errors detected during pre-checking.
the NAND flash memory module Fig. 3.
Enhanced Read Speed: Coordinated operation of error pre-
checking and error correction minimizes the time required for
error detection and correction, leading to better read speeds.
Optimized Resource Utilization: The integration is designed
to optimize the utilization of resources, ensuring that error
correction is performed efficiently without unnecessary redun-
dancy.
The proposed method Fig. 2 combines the strengths of
CRC-based error prechecking and LDPC-based error cor-
rection to create a synergistic approach to enhance NAND
flash memory performance. By strategically integrating these
components, we aim to achieve a balance between early error
detection, high correction capability, and minimal impact on
storage space, ultimately contributing to the efficiency and
reliability of NAND flash memory systems.
IV. E VALUATION AND E XPERIMENTAL R ESULTS
The work was implemented as a series of blocks and then
integrated to obtain the final complete block. The entire work
is composed of CRC Encoder, CRC Decoder (prechecked),
LDPC Encoder (Error Correcting Code), LDPC Decoder (Er-
ror Correcting Code) Fig. 2, all the blocks were separately
implemented to verify the results separately.
The primary output of a CRC encoder is the CRC checksum,
which is appended to the original data. This checksum serves
as a reliable means of error detection and data integrity
verification when data are received or retrieved, ensuring that
Fig. 3. Flow chart of the HDL model of the proposed work transmitted or stored data remains reliable and uncorrupted.
The output of a CRC checker is the CRC checksum value,
Parallel Processing: Error pre-checking and error correction which is generated on the basis of the input data. This

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 Fig. 4. Power Analysis

checksum serves as a digital signature for error detection, flash memory systems.
ensuring that transmitted or stored data remains reliable and The chip area occupied by the error-pre-checking and en-
uncorrupted. coding circuits is a critical aspect of semiconductor design.
The primary output of an LDPC encoder is a set of Smaller areas lead to cost-effective and space-efficient memory
codewords. A codeword is a sequence of bits that includes solutions. The additional chip area required for integrating
both the original data (message) and additional redundant bits error prechecking and LDPC encoding blocks into the flash
(parity bits).LDPC encoding adds redundant bits to the original memory controller was evaluated. Results indicated a man-
data to create codewords. The redundant bits included in the ageable increase in chip area, which was outweighed by the
codewords provide error-correction capability. These bits allow advantages of improved data integrity and extended flash
the decoder to detect and correct errors that may occur during memory lifespan.
data transmission or storage. Latency or delay in data access is a crucial consideration
LDPC decoding involves correcting errors introduced dur- in storage systems. Error pre-checking introduced minimal
ing data transmission or storage. The decoder identifies and additional delay during read operations due to checksum
corrects errors in the redundant bits (parity bits) of the received calculations, while LDPC encoding added a slight delay during
codeword. In cases where the received codeword contains too write operations. These delays were deemed acceptable, con-
many errors for correction within the code’s capabilities, the sidering the substantial gains in data reliability and durability
LDPC decoder may indicate the presence of uncorrectable achieved through error management techniques.
errors. This output alerts the system that the data cannot be
recovered successfully. TABLE I
A comprehensive analysis of the impact on power con- P ERFORMANCE C OMPARISON TABLE
sumption Fig. 4, chip area, and latency introduced by the Parameter [1] Proposed Model
implementation of error pre-checking using CRC-32 and error Area 103 LUT 41 LUT
encoding using LDPC encoder techniques was carried out. On Chip Power 48.63 W 16.6 W
Dynamic Power 47.8 W 16.4 W
These factors are pivotal in evaluating the practical viability Junction Temperature 116.6 C 56.3 C
and efficiency of the proposed improvements Process Delay 338 s 113 s
Implementing error prechecking and encoding mechanisms
can influence power consumption in flash memory devices.
This work scrutinized power consumption patterns during V. C ONCLUSION
read-and-write operations. The findings revealed that while
error pre-checking slightly increased power usage during read The method discussed in [1] was implemented using Xil-
operations due to additional processing, LDPC encoding con- inx Vivado, and the results were incorporated into Table
tributed to power savings during write operations by reducing 1. The proposed work focused on enhancing flash memory
the need for extensive error correction. Overall, the work performance by employing error prechecking and error encod-
demonstrated a balanced trade-off between increased power ing techniques. Specifically, error pre-checking was achieved
in certain scenarios and reduced power in others, showcasing through CRC-32 (Cyclic Redundancy Check), while error en-
the importance of efficient error management techniques in coding utilized LDPC (Low-Density Parity Check) encoding.

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