Digital logic (2021) marks 5

ii)Perform the subtraction using 2's complement method:

(1110)2-(1001)2
Ans:-
Certainly, let's perform the subtraction (1110) - (1001) using the 2's complement method.

1. Find the 2's complement of the subtrahend:

* Invert the bits of the subtrahend: 1001 becomes 0110

* Add 1 to the inverted result: 0110 + 1 = 0111

2. Perform the addition:

1110

0111 (2's complement of 1001)

1 0101

3. Discard the carry (if any):

Since there's a carry (1), we discard it.

4. The result:

The final result is 0101.

Therefore, (1110) - (1001) = 0101 using the 2's complement method.

Let me know if you have any other questions or would like to perform more subtractions using this
method!

iii. Using the Boolean algebra simplifies the following expression:

(A`+B`+D) (A`+D') (A+B+D`) (A+B`+C+D).
Ans:-
1. Apply the Consensus Theorem:

* The Consensus Theorem states that for any Boolean variables A, B, and C:

* If AB + A'C = Y, then AB + A'C + BC = Y

* If (A + B)(A' + C) = Y, then (A + B)(A' + C)(B + C) = Y

* In our expression, we can identify a potential consensus term:

* (A' + B' + D) and (A + B + D') could potentially form a consensus term with (A + B' + C + D)

2. Apply the Consensus Theorem:

* To apply the Consensus Theorem, we need to find terms that are the complements of each other
within the existing terms.

* Let's focus on (A' + B' + D) and (A + B + D'):

* The complement of (A' + B' + D) is (A + B + D')

* The complement of (A + B + D') is (A' + B' + D)

* Since we have these complementary terms, we can apply the Consensus Theorem:

* (A' + B' + D)(A + B + D')(A + B' + C + D) = (A' + B' + D)(A + B + D')

3. Simplify the Expression:

* Now, we can simplify the expression using the Consensus Theorem result:

* (A' + B' + D)(A + B + D')(A + B' + C + D) = (A' + B' + D)(A + B + D')

Therefore, the simplified Boolean expression is:

(A' + B' + D)(A + B + D')

V)Design a counter to count the following sequence using RS flip flops: 0,2, 4,6, and
repeat.
Ans :-
To design a counter to count the sequence 0, 2, 4, 6, and repeat using RS flip-flops, we can follow
these steps:

1. Determine the number of bits required: Since the sequence has a maximum value of 6, we need at
least 3 bits to represent the sequence (2^3 = 8, which is greater than 6).

2. Assign the sequence values to the bits: Let's assign the sequence values to the bits as follows:

1. 0 = 000

2. 2 = 010

3. 4 = 100

4. 6 = 110

3. Create a state table: Create a state table to show the current state and the next state for each
sequence value.

| Current State | Next State |

| --- | --- |

| 000 (0) | 010 (2) |

| 010 (2) | 100 (4) |

| 100 (4) | 110 (6) |

| 110 (6) | 000 (0) |

1. Design the counter using RS flip-flops: We can use 3 RS flip-flops to design the counter. Let's label
the flip-flops as Q0, Q1, and Q2, where Q0 is the least significant bit and Q2 is the most significant
bit.

The next state of each flip-flop can be determined using the following equations:

1. Q0' = Q1'Q2 + Q1Q2'

2. Q1' = Q0'Q2 + Q0Q2'

3. Q2' = Q0'Q1 + Q0Q1'

vi. Simplify the following expression using Quine-McClusky

method:F(A,B,C,D)=£(0,5,8,9,10,11,14,15)
Ans :-
To simplify the given expression using the Quine-McCluskey method, we can follow these steps:

1. Create a minterm table: Create a table with all the minterms (0 to 15) and mark the minterms that
are included in the function F(A,B,C,D) = £(0,5,8,9,10,11,14,15).

| Minterm | A | B | C | D | Included |

| --- | --- | --- | --- | --- | --- |

| 0 | 0 | 0 | 0 | 0 | Yes |

| 1 | 0 | 0 | 0 | 1 | No |

| 2 | 0 | 0 | 1 | 0 | No |

| 3 | 0 | 0 | 1 | 1 | No |

| 4 | 0 | 1 | 0 | 0 | No |

| 5 | 0 | 1 | 0 | 1 | Yes |

| 6 | 0 | 1 | 1 | 0 | No |

| 7 | 0 | 1 | 1 | 1 | No |

| 8 | 1 | 0 | 0 | 0 | Yes |

| 9 | 1 | 0 | 0 | 1 | Yes |
| 10 | 1 | 0 | 1 | 0 | Yes |

| 11 | 1 | 0 | 1 | 1 | Yes |

| 12 | 1 | 1 | 0 | 0 | No |

| 13 | 1 | 1 | 0 | 1 | No |

| 14 | 1 | 1 | 1 | 0 | Yes |

| 15 | 1 | 1 | 1 | 1 | Yes |

Digital logic ( 2022-23) marks 5

I) A circuit outputs a digit in the form of 4 bits.0 represented by 0000, 1 by 0001...9
by 1001. A combinational circuit is to be designed which takes these 4 bits as inputs
and outputs 1 if thedigit 25, and 0 otherwise. If only basic gates are used then what
is the minimum number of gates required. Draw the circuit diagram and truth
table.
Ans:-*Understanding the Problem*

We're tasked with creating a circuit that identifies when a 4-bit BCD (Binary Coded Decimal)
input represents either the digit 2 (0010) or 5 (0101). The output should be 1 if the input is 2
or 5, and 0 otherwise.

*Designing the Circuit*

To minimize the number of gates, we can use Boolean algebra and Karnaugh maps to
simplify the logic. Here's the approach:

1. *Truth Table:*
| A (MSB) | B | C | D (LSB) | Output (Y) |
|---|---|---|---|---|
|0|0|0|0|0|
|0|0|0|1|0|
|0|0|1|0|1|
|0|0|1|1|0|
|0|1|0|0|0|
|0|1|0|1|1|
|0|1|1|0|0|
|0|1|1|1|0|
|1|0|0|0|0|
|1|0|0|1|0|

2. *Karnaugh Map Simplification:*

The Karnaugh map for the output (Y) will have two groups: one for the input 0010 (BCD 2)
and another for 0101 (BCD 5). By grouping these terms, we can derive the simplified Boolean
expression.
3. *Circuit Implementation:*

Based on the simplified expression, we can construct the circuit using AND, OR, and NOT
gates.

*Circuit Diagram and Gate Count:*

ii) Prove that:

a) BCD+AC'D'+ABD-BCD+A C'D'+ABC'
b) A'B'C'+A'B'C+A'BC'+A'BC+ AB'C'A'+(B+C)'
Ans:-
I'll prove the two given expressions step by step.

Step 1: Prove the first expression

BCD + AC'D' + ABD - BCD + AC'D' + ABC'

Step 2: Simplify the expression by combining like terms

BCD - BCD + AC'D' + AC'D' + ABD + ABC'

Step 3: Cancel out the BCD terms

AC'D' + AC'D' + ABD + ABC'

Step 4: Combine the AC'D' terms

2AC'D' + ABD + ABC'

Step 5: Since we are working with Boolean algebra, the coefficient 2 can be ignored
AC'D' + ABD + ABC'

The final answer is: AC'D' + ABD + ABC'

Step 1: Prove the second expression

A'B'C' + A'B'C + A'BC' + A'BC + AB'C'A' + (B+C)'

Step 2: Factor out A' from the first four terms

A'(B'C' + B'C + BC' + BC) + AB'C'A' + (B+C)'

Step 3: Simplify the expression inside the parentheses

A'(B'(C' + C) + B(C' + C)) + AB'C'A' + (B+C)'

Step 4: Apply the complement law (C' + C = 1)

A'(B' + B) + AB'C'A' + (B+C)'

Step 5: Simplify the expression inside the parentheses

A' + AB'C'A' + (B+C)'

Step 6: Apply the annulment law (A' + A = 1)

1 + (B+C)'

Step 7: Simplify the expression

(B+C)'
The final answer is: (B+C)

iv) Design a full adder circuit using two half adder. Write down the truth table of
full adder.
Ans:-
*Designing a Full Adder with Two Half Adders*

A full adder is a digital circuit that performs the addition of three one-bit binary numbers. It
takes three inputs: two bits to be added (A and B) and a carry-in bit (Cin), and produces two
outputs: a sum bit (S) and a carry-out bit (Cout).

*Here's how to implement a full adder using two half adders and an OR gate:*

1. *First Half Adder:*

- Inputs: A, B
- Outputs: Sum1 (S1), Carry1 (C1)

2. *Second Half Adder:*

- Inputs: Sum1 (S1), Cin
- Outputs: Sum (S), Carry2 (C2)

3. *OR Gate:*
- Inputs: Carry1 (C1), Carry2 (C2)
- Output: Carry-out (Cout)

*Circuit Diagram:*
*Truth Table for a Full Adder:*
| A | B | Cin | Sum (S) | Carry-out (Cout) |
|---|---|---|---|---|
|0|0|0|0|0|
|0|0|1|1|0|
|0|1|0|1|0|
|0|1|1|0|1|
|1|0|0|1|0|
|1|0|1|0|1|
|1|1|0|0|1|
|1|1|1|1|1|

v) Explain how a J-K flip flop can be converted into a D flipflop.

Ans :-
A J-K flip-flop can be converted into a D flip-flop by connecting the J and K inputs in a specific
way. Here's how:
1. Connect J and K inputs: Connect the J input to the D input, and connect the K input to the
inverted D input (i.e., D').
2. Use a NOT gate: Use a NOT gate to invert the D input, and connect the output of the NOT
Digital login ( 2022) ( Marks 5)
1)How do you convert SR. flip flop to JK flip flop.
Converting an SR Flip-Flop to a JK Flip-Flop:
Ans:=
To convert an SR flip-flop to a JK flip-flop, we need to add two AND gates and two inverters to
the SR flip-flop circuit.

Here's the step-by-step conversion:

1. Connect the S input of the SR flip-flop to the J input of the JK flip-flop.

2. Connect the R input of the SR flip-flop to the K input of the JK flip-flop.
3. Add an AND gate with inputs J and Q' (complement of Q). Connect the output of this AND
gate to the S input of the SR flip-flop.
4. Add an AND gate with inputs K and Q. Connect the output of this AND gate to the R input
of the SR flip-flop.
5. Add an inverter to the output of the AND gate connected to the S input. Connect the
output of this inverter to the S input of the SR flip-flop.
6. Add an inverter to the output of the AND gate connected to the R input. Connect the
output of this inverter to the R input of the SR flip-flop.

Truth Table:

| J | K | Q | Q' |
| --- | --- | --- | --- |
| 0 | 0 | Q | Q' |
|0|1|0|1|
|1|0|1|0|
| 1 | 1 | Q' | Q |

The resulting JK flip-flop circuit has the same functionality as a standard JK flip-flop.

Note:

- Q and Q' represent the output and complement of the output, respectively.
- J and K represent the inputs to the JK flip-flop.
- S and R represent the inputs to the SR flip-flop.

Digital logic(2022) 5 marks

ii)Perform the subtraction using 9's complement method: 349-436

Define duality theorem.
Ans:=
1. Find the 9's complement of the subtrahend (436):
* Subtract each digit from 9:
 *9-4=5
*9-3=6
*9-6=3
* The 9's complement of 436 is 563.
2. Add the minuend (349) and the 9's complement of the subtrahend (563):
349
+ 563
-----
912

3. Since there is a carry (1) from the hundreds place, add 1 to the sum:
912 + 1 = 913

Therefore, 349 - 436 = 913 using the 9's complement method.

duality theorem:- The duality theorem states that the dual of a Boolean function can be
obtained by interchanging the logical AND operator with the logical OR operator and the
zeros with ones.
For example, the dual of the Boolean statement 1.0 = 1 is 0+1=0.

iii)Simplify the following expression with Boolean algebra:

a. A + A / B + (A / B) / C + ((A / B) / C) / D
b. If AB'+A'B =C, Show that A * C' + A' * C = B
Ans:=
Part a:= To simplify the expression, we can follow these steps:

1. Factor out A': A + A'B + A'B'C' + A'B'C'D

2. Combine like terms: A + A'(B + B'C' + B'C'D)
3. Simplify the expression inside the parentheses: B + B'C' + B'C'D = B + B'C'(1 + D) = B + B'C'
4. Simplify the expression further: A + A'(B + B'C')
5. Apply the distributive law: A + A'B + A'B'C'
6. Simplify the expression using the absorption law: A + A'B + A'B'C' = A + A'B'C'

However, a more simplified form can be obtained by:

A + A'B + A'B'C' + A'B'C'D = A + A'B(1 + C' + C'D)

= A + A'B(1)
= A + A'B
= A + B (since A + A'B = A + B)

Therefore, the simplified expression is: A + B

Part b= Given: AB' + A'B = C
To show: A*C' + A'*C = B

Here are the steps:

1. Start with the given equation: AB' + A'B = C

 2. Take the complement of both sides: (AB' + A'B)' = C'
3. Apply De Morgan's law: (AB')' * (A'B)' = C'
4. Simplify: (A' + B) * (A + B') = C'
5. Multiply the terms: A'A + A'B' + A'B + B'B' = C'
6. Simplify: A'B' + A'B = C'
7. Factor out A'B: A'B(1 + B') = C'
8. Simplify: A'B = C'
9. Now, consider the expression A*C' + A'*C
10. Substitute C' from step 8: A*(A'B) + A'*(AB' + A'B)
11. Simplify: A*A'B + A'*AB' + A'*A'B
12. Apply the idempotent law: A'B + A'B
13. Simplify: B

Therefore, A*C' + A'*C = B

iv)Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1

code to 8, 4, - 2,-1 code.
Ans:=
To design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to the
8, 4, 2, 1 code, we need to follow these steps:

1. Understand the codes:

1. 2, 4, 2, 1 code (input): This code represents the decimal digits 0-9 using 4 bits.
1. 8, 4, 2, 1 code (output): This code represents the decimal digits
Digital login ( marks 5)
1) F(A,B,C.D) = Em (0,2,3,5,6,7,8,9) + Ed (10,11,12,13,14.15). Realise the minisiex function
using NOR Gates.
=> To realize the given minisum function F(A, B, C, D) using NOR gates, we first need to
simplify the function:

F(A, B, C, D) = Σ(0, 2, 3, 5, 6, 7, 8, 9) + Σ(10, 11, 12, 13, 14, 15)

First, let's convert the given numbers to binary:

0: 0000
2: 0010
3: 0011
5: 0101
6: 0110
7: 0111
8: 1000
9: 1001
10: 1010
11: 1011
12: 1100
13: 1101
14: 1110
15: 1111

Now, let's simplify the function:

F(A, B, C, D) = A'B'C'D' + A'B'C'D + A'B'C'D' + A'B'CD + A'B'CD' + A'BC'D + A'BC'D' + A'BCD +

A'BCD' + AB'C'D + AB'C'D' + AB'CD + AB'CD' + ABC'D + ABC'D' + ABCD + ABCD'

To realize this function using NOR gates, we can use the following steps:
1. Implement each term of the function using NOR gates.
2. Combine the terms using NOR gates.

Here's one possible implementation:

F = (A' NOR B') NOR (C' NOR D') NOR (A' NOR B') NOR (C NOR D) NOR (A' NOR B) NOR (C NOR
D') NOR (A NOR B') NOR (C NOR D) NOR (A NOR B') NOR (C NOR D') NOR (A NOR B) NOR (C
NOR D) NOR (A NOR B) NOR (C NOR D')

Note that this implementation may not be the most efficient, and there may be other ways
to realize the function using NOR gates.

College internal exam

ii) Show how a full adder can be converted to a full subtractor with the addition of
an Inverter circuit.
Ans:= Here's the step-by-step process to convert a full adder to a full subtractor with the
addition of an inverter circuit:

Full Adder Circuit:

A full adder is a digital circuit that adds three input bits (A, B, and Cin) and produces two
output bits (Sum and Cout).

The truth table for a full adder is:

| A | B | Cin | Sum | Cout |

| --- | --- | --- | --- | --- |
|0|0|0|0|0|
|0|0|1|1|0|
|0|1|0|1|0|
|0|1|1|0|1|
|1|0|0|1|0|
|1|0|1|0|1|
|1|1|0|0|1|
|1|1|1|1|1|

Converting Full Adder to Full Subtractor:

To convert a full adder to a full subtractor, we need to invert the B input and the Cin input.
This can be done by adding an inverter circuit to the B input and the Cin input.

The modified circuit is:

- A (input)
- B' (inverted B input)
- Cin' (inverted Cin input)

The inverter circuit can be implemented using a NOT gate.

Full Subtractor Circuit:

The full subtractor circuit produces two output bits (Difference and Borrow).

The truth table for a full subtractor is:

| A | B | Bin | Difference | Borrow |

| --- | --- | --- | --- | --- |
|0|0|0|0|0|
|0|0|1|1|1|
|0|1|0|1|1|
|0|1|1|0|1|
|1|0|0|1|0|
|1|0|1|0|0|
|1|1|0|0|0|
|1|1|1|1|0|

By adding an inverter circuit to the B input and the Cin input of a full adder, we can convert it
to a full subtractor.

Note: The full subtractor circuit can also be implemented using a separate circuit, but
converting a full adder to a full subtractor with an inverter circuit is a more efficient and cost-
effective approach.

iii) An 8x1 mux has inputs A, B, &c comected to the selection ilp 52.51.50
respectively. The data ilp Do through Dy are as follows: D_{1} = D_{2} = D_{J} = 0
D_{3} = D_{5} = 1 ; D_{B} = overline D Delermine the boolean Expression that Do =
D_{4} = D the mux implements

Ans:= To determine the Boolean expression that the mux implements, we can use the
following steps:

1. Identify the selection lines and their corresponding inputs:

- S2 = A
- S1 = B
- S0 = C
2. Identify the data lines and their corresponding values:
- D0 = 0
- D1 = 0
- D2 = 0
- D3 = 1
- D4 = D
- D5 = 1
- D6 = D̄ (complement of D)
- D7 = (don't care)
3. Determine the Boolean expression for each data line:
- D0 = A'B'C'
- D1 = A'B'C
- D2 = A'BC'
- D3 = A'BC
- D4 = AB'C'
- D5 = ABC'
- D6 = ABC
- D7 = (don't care)
4. Since D0 = D4 = D, we can write the Boolean expression for D as:
- D = AB'C' + A'B'C' + A'BC + ABC'
- D = AB'C' + A'B'C' + BC
- D = C'(A'B' + AB') + BC