DRV8231A

SLVSFZ8 – NOVEMBER 2021

DRV8231A 3.7-A Brushed DC Motor Driver with Integrated Current Sense and
Regulation

1 Features 3 Description
• N-channel H-bridge brushed DC motor driver The DRV8231A device is an integrated motor driver
• 4.5-V to 33-V operating supply voltage range with N-channel H-bridge, charge pump, current sense
• Pin-to-pin, RDS(on), voltage, and current sense/ feedback, current regulation, and protection circuitry.
regulation variants (external shunt resistor and The charge pump improves efficiency by supporting
integrated current mirror) N-channel MOSFET half bridges and 100% duty cycle
driving.
– DRV8870: 6.5-V to 45-V, 565-mΩ, shunt
– DRV8251: 4.5-V to 48-V, 450-mΩ, shunt An internal current mirror architecture on the IPROPI
– DRV8251A: 4.5-V to 48-V, 450-mΩ, mirror pin implements current sensing and regulation. This
– DRV8231: 4.5-V to 33-V, 600-mΩ, shunt eliminates the need for a large power shunt resistor,
– DRV8231A: 4.5-V to 33-V, 600-mΩ, mirror saving board area and reducing system cost. The
• High output current capability: 3.7-A Peak IPROPI current-sense output allows a microcontroller
• PWM control interface to detect motor stall or changes in load conditions.
• Supports 1.8-V, 3.3-V, and 5-V logic inputs The external voltage reference pin, VREF, determines
• Integrated IPROPI current sensing for stall the threshold of current regulation during start-up and
detection and current regulation stall events without interaction from a microcontroller.
• Low-power sleep mode
A low-power sleep mode achieves ultra-low quiescent
– <1-µA at VVM = 24-V, TJ = 25°C current draw by shutting down most of the internal
• Small package and footprint circuitry. Internal protection features include supply
– 8-Pin WSON with PowerPAD™, 2.0 × 2.0 mm undervoltage lockout, output overcurrent, and device
– 8-Pin HSOP with PowerPAD™, 4.9 × 6.0 mm overtemperature.
• Integrated protection features
– VM undervoltage lockout (UVLO) The DRV8231A is part of a family of devices which
– Auto-retry overcurrent protection (OCP) come in pin-to-pin, scalable RDS(on) and supply
– Thermal shutdown (TSD) voltage options to support various loads and supply
rails with minimal design changes. See Section 5 for
2 Applications information on the devices in this family. View the full
• Printers portfolio of brushed motor drivers on ti.com.
• Vacuum robot Device Information (1)
• Washer and dryer PART NUMBER PACKAGE BODY SIZE (NOM)
• Coffee machine HSOP (8) 4.90 mm × 6.00 mm
• POS printer DRV8231A
WSON (8) 2.00 mm × 2.00 mm
• Electricity meter
• ATMs (Automated Teller Machines) (1) For all available packages, see the orderable addendum at
• Ventilators the end of the data sheet.
• Surgical equipment
Simplified Schematic
• Electronic hospital bed and bed control
• Fitness machine 4.5 to 33 V

DRV8231A
IN1
H-Bridge
Controller

IN2 Motor Driver

VREF Current Sense
IPROPI
RIPROPI

Protec on

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 Device Functional Modes..........................................17
2 Applications..................................................................... 1 8.6 Pin Diagrams............................................................ 18
3 Description.......................................................................1 9 Application and Implementation.................................. 19
4 Revision History.............................................................. 2 9.1 Application Information............................................. 19
5 Device Comparison......................................................... 3 9.2 Typical Application.................................................... 19
6 Pin Configuration and Functions...................................3 9.3 Current Capability and Thermal Performance.......... 26
7 Specifications.................................................................. 4 10 Power Supply Recommendations..............................32
7.1 Absolute Maximum Ratings........................................ 4 10.1 Bulk Capacitance.................................................... 32
7.2 ESD Ratings............................................................... 4 11 Layout........................................................................... 33
7.3 Recommended Operating Conditions.........................4 11.1 Layout Guidelines................................................... 33
7.4 Thermal Information....................................................4 11.2 Layout Example...................................................... 33
7.5 Electrical Characteristics.............................................5 12 Device and Documentation Support..........................35
7.6 Typical Characteristics................................................ 6 12.1 Documentation Support.......................................... 35
7.7 Timing Diagrams......................................................... 8 12.2 Receiving Notification of Documentation Updates..35
8 Detailed Description........................................................9 12.3 Community Resources............................................35
8.1 Overview..................................................................... 9 12.4 Trademarks............................................................. 35
8.2 Functional Block Diagram........................................... 9 13 Mechanical, Packaging, and Orderable
8.3 External Components................................................. 9 Information.................................................................... 35
8.4 Feature Description...................................................11

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
November 2021 * Initial Release

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5 Device Comparison
Table 5-1. Device Comparison Table
Device Supply RDS(on) Current Current-sense Overcurrent Pin-to-pin
Package
name voltage (V) (mΩ) regulation feedback protection response devices
DRV8870 6.5 to 45 565 Automatic Retry HSOP (4.9x6)
DRV8870,
DRV8251 4.5 to 48 450 External Shunt External Latched Disable HSOP (4.9x6)
DRV8251,
Resistor Amplifier
HSOP (4.9x6) DRV8231
DRV8231 4.5 to 33 600 Automatic Retry
WSON (2x2)
DRV8251A 4.5 to 48 450 Automatic Retry HSOP (4.9x6)
DRV8251A,
Internal current mirror (IPROPI) HSOP (4.9x6)
DRV8231A 4.5 to 33 600 Automatic Retry DRV8231A
WSON (2x2)

6 Pin Configuration and Functions

IPROPI 1 8 OUT2 IPROPI 1 8 OUT2

IN2 2 7 GND IN2 2 7 GND

Thermal Thermal
IN1 3 Pad 6 OUT1 IN1 3 Pad 6 OUT1

VREF 4 5 VM VREF 4 5 VM

Figure 6-1. DDA Package 8-Pin HSOP Top View Figure 6-2. DSG Package 8-Pin HSOP Top View

Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
GND 7 PWR Device power ground. Connect to system ground.
IN1 3 I Logic inputs. Controls the H-bridge output. Has internal pulldowns. See Table 8-2.
IN2 2 I Logic inputs. Controls the H-bridge output. Has internal pulldowns. See Table 8-2.
IPROPI 1 PWR Analog current output proportional to load current. Section 8.4.2.1.
OUT1 6 O H-bridge output. Connect directly to the motor or other inductive load.
OUT2 8 O H-bridge output. Connect directly to the motor or other inductive load.
4.5-V to 48-V power supply. Connect a 0.1-µF bypass capacitor to ground, as well as
VM 5 PWR
sufficient bulk capacitance, rated for the VM voltage.
Analog input. Apply a voltage between 0 to 5 V. For information on current regulation, see
VREF 4 I
the Section 8.4.2.1 section.
Thermal pad. Connect to board ground. For good thermal dissipation, use large ground
PAD —
planes on multiple layers, and multiple nearby vias connecting those planes.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage VM -0.3 35 V
Power supply transient voltage ramp VM 0 2 V/µs
Logic pin voltage INx -0.3 7 V
Reference input pin voltage VREF -0.3 6 V
Output pin voltage OUTx -0.7 VM + 0.7 V
Current sense input pin voltage IPROPI -0.3 5.75 V
Internally Internally
Output current OUTx A
Limited Limited
Junction temperature, TA Junction temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±
2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500
V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVM Power supply voltage VM 4.5 33 V
VVREF Reference voltage VREF 0 3.6 V
VIN Logic input voltage INx 0 5.5 V
fPWM PWM frequency INx 0 200 kHz
IOUT (1) Peak output current OUTx 0 3.7 A
IIPROPI Peak output current IPROPI 0 3 mA
TJ Operating junction temperature –40 150 °C

(1) Power dissipation and thermal limits must be observed

7.4 Thermal Information

DRV8231A DRV8231A
THERMAL METRIC(1) DDA (HSOP) DSG (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 42.8 66.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.6 77.8 °C/W
RθJB Junction-to-board thermal resistance 16.8 32.8 °C/W

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DRV8231A DRV8231A
THERMAL METRIC(1) DDA (HSOP) DSG (WSON) UNIT
8 PINS 8 PINS
ΨJT Junction-to-top characterization parameter 5.4 2.2 °C/W
ΨJB Junction-to-board characterization parameter 16.8 32.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.2 12.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 33 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 25 °C and VVM = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VM)
IVMQ VM sleep mode current VVM = 24 V, IN1 = IN2 = 0, TJ = 25°C 1 µA
IVM VM active mode current VVM = 24 V, IN1 = IN2 = 1 3 4 mA
tWAKE Turnon time Control signal to active mode 250 µs
tSLEEP Turnoff time Control signal to sleep mode 0.8 1.5 ms
LOGIC-LEVEL INPUTS (INx)
VIL Input logic low voltage 0.5 V
VIH Input logic high voltage 1.5 V
VHYS Input hysteresis 200 mV
IIL Input logic low current VIN = 0 V -1 1 µA
IIH Input logic high current VIN = 3.3 V 33 100 µA
RPD Input pulldown resistance To GND 100 kΩ
DRIVER OUTPUTS (OUTx)
RDS(on)_HS High-side MOSFET on resistance VVM = 24 V, I = 1 A, fPWM = 25 kHz 300 mΩ
RDS(on)_LS Low-side MOSFET on resistance VVM = 24 V, I = 1 A, fPWM = 25 kHz 300 mΩ
VSD Body diode forward voltage IOUT = 1 A 0.8 V
tRISE Output rise time VVM = 24 V, OUTx rising from 10% to 90% 220 ns
tFALL Output fall time VVM = 24 V, OUTx falling from 90% to 10% 220 ns
tPD Input to output propagation delay INx to OUTx 0.7 1 µs
tDEAD Output dead time 200 ns
INTEGRATED CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI Current mirror scaling factor 1500 µA/A
AERR Current mirror total error IOUT = 1 A, VVM ≥ 6.5 V, VIPROPI ≤ 3.0 V -6 6 %
tOFF Current regulation off time 25 µs
tBLK Current regulation blanking time 1.4 µs
tDELAY Current sense delay time 1.1 µs
tDEG Current regulation deglitch time 0.7 µs
PROTECTION CIRCUITS
Supply rising 4.15 4.3 4.45 V
VUVLO Supply undervoltage lockout (UVLO)
Supply falling 4.05 4.2 4.35 V
VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV
tUVLO Supply undervoltage deglitch time 10 µs
IOCP Overcurrent protection trip point 3.7 A
tOCP Overcurrent protection deglitch time 1.5 µs
tRETRY Overcurrent protection retry time 3 ms

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4.5 V ≤ VVM ≤ 33 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 25 °C and VVM = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TTSD Thermal shutdown temperature 150 175 °C
THYS Thermal shutdown hysteresis 40 °C

7.6 Typical Characteristics

0.75 0.75

0.7
IVMQ Supply Sleep Current (A)

0.6
0.65

0.6 0.45

IVMQ (A)
0.55
0.3
0.5
TJ = -40°C VVM = 4.5 V
0.45 TJ = 27°C VVM = 6.5 V
0.15 VVM = 12 V
TJ = 85°C
0.4 TJ = 125°C VVM = 24 V
TJ = 150°C VVM = 33 V
0.35 0
3 6 9 12 15 18 21 24 27 30 33 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) Junction Temperature (°C)

Figure 7-1. Sleep Current (IVMQ) vs. Supply Voltage Figure 7-2. Sleep Current (IVMQ) vs. Junction
(VVM) Temperature (TJ)
2.2 2.3

2.15 2.2
IVM Supply Active Current (mA)

IVM Supply Active Current (mA)

2.1 2.1

2.05 2

2 1.9

1.95 1.8
TJ = -40°C VVM = 4.5 V
1.9 TJ = 27°C 1.7 VVM = 6.5 V
TJ = 85°C VVM = 12 V
1.85 TJ = 125°C 1.6 VVM = 24 V
TJ = 150°C VVM = 33 V
1.8 1.5
3 6 9 12 15 18 21 24 27 30 33 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) Junction Temperature (°C)
Figure 7-3. Active Current (IVM) vs. Supply Voltage Figure 7-4. Active Current (IVM) vs. Junction
(VVM) Temperature (TJ)
600 440
TJ = -40°C
560 420
TJ = 27°C
520 TJ = 85°C 400
TJ = 125°C
380
480 TJ = 150°C
RDS(on)_HS (m)
RDS(on)_HS (m)

360
440
340
400
320
360
300
320 280 VVM = 4.5 V
VVM = 6.5 V
280 260 VVM = 12 V
240 VVM = 24 V
240
VVM = 33 V
200 220
3 6 9 12 15 18 21 24 27 30 33 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) Junction Temperature (°C)

Figure 7-5. High-Side RDS(on) vs. VM Supply Voltage Figure 7-6. High-Side RDS(on) vs. Junction
Temperature (TJ)

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600 440
TJ = -40°C
560 420
TJ = 27°C
520 TJ = 85°C 400
TJ = 125°C
380
480 TJ = 150°C

RDS(on)_LS (m)
RDS(on)_LS (m)

360
440
340
400
320
360
300
320 280 VVM = 4.5 V
VVM = 6.5 V
280 260 VVM = 12 V
240 VVM = 24 V
240
VVM = 33 V
200 220
3 6 9 12 15 18 21 24 27 30 33 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) Junction Temperature (°C)

Figure 7-7. Low-Side RDS(on) vs. VM Supply Voltage Figure 7-8. Low-Side RDS(on) vs. Junction
Temperature (TJ)
35
30 +6 standard deviation error (%)
25 -6 standard deviation error (%)
20
AIPROPI Gain Error (%)

15
10
5
0
-5
-10
-15
-20
-25
-30
-35
0 0.5 1 1.5 2 2.5 3 3.5
IOUT_LS current (A)
6.5 V ≤ VVM ≤ 33 V 0 V ≤ VIPROPI ≤ 3 V -40 °C ≤ TJ ≤ 150 °C

Figure 7-9. Gain error of AIPROPI vs. Motor Current

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7.7 Timing Diagrams

IN1 (V)

IN2 (V) tPD

tPD
tPD
OUT1 (V) Z Z

tPD

OUT2 (V) Z Z

90% 90%

OUTx (V)

10%
10%

tRISE tFALL

Figure 7-10. Input-to-Output Timing

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8 Detailed Description
8.1 Overview
The DRV8231A is an 8-pin device for driving brushed DC motors from a 4.5-V to 33-V supply rail. Two logic
inputs control the H-bridge driver, which consists of four N-channel MOSFETs that have a typical RDS(on) of
600 mΩ (including one high-side and one low-side FET). A single power input, VM, serves as both device
power and the motor winding bias voltage. The integrated charge pump of the device boosts VM internally and
fully enhances the high-side FETs. Motor speed can be controlled with pulse-width modulation at frequencies
between 0 to 200 kHz. The device enters a low-power sleep mode by bringing both inputs low.
The DRV8231A also integrates current sense feedback to a microcontroller using current mirrors on the low-side
power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the MOSFETs.
This current can be converted to a proportional voltage using an external resistor (RIPROPI). This integrated
current sensing scheme out-performs traditional external shunt resistor sensing by providing current information
even during the off-time slow decay recirculating period and removing the need for an external power shunt
resistor. The integrated current regulation feature allows the device to limit the output current with a fixed off-time
PWM chopping scheme. The VREF pin configures the current regulation level during motor operation to limit the
load current.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD).
8.2 Functional Block Diagram

VCP VM
Power
VM VM VCP
bulk 0.1 µF OUT2
Charge Gate
Pump Drive
OCP
Logic
ISEN1
Core Logic BD
C
IN2 VCP VM BDC

Control
IN1 Overcurrent OUT1
Inputs Gate
Undervoltage Drive
OCP
Thermal GND
VREF
+
ISEN2
IPROPI -
Clamp
IPROPI Current
Sense ISEN1
RIPROPI

ISEN2

8.3 External Components

Table 8-1 lists the recommended external components for the device.

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Table 8-1. Recommended external components

COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated.
CVM2 VM GND Section 10.1, VM-rated.

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8.4 Feature Description

8.4.1 Bridge Control
The DRV8231A output consists of four N-channel MOSFETs that are designed to drive high current. These
outputs are controlled by the two logic inputs IN1 and IN2 as listed in Table 8-2.
Table 8-2. H-Bridge Control
IN1 IN2 OUT1 OUT2 DESCRIPTION
0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after 1 ms)
0 1 L H Reverse (Current OUT2 → OUT1)
1 0 H L Forward (Current OUT1 → OUT2)
1 1 L L Brake; low-side slow decay

The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM, switching between driving and braking typically works best. For
example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period,
and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current
decay is also available. Figure 8-1 shows how the motor current flows through the H-bridge. The input pins can
be powered before VM is applied.
VM VM

1 Forward drive 1 Reverse drive

2 Slow decay (brake) 22 Slow decay (brake)

1 1
3 High-Z (coast) 3 High-Z (coast)
OUT1 OUT2 OUT1 OUT2
2 2
3 3

Forward Reverse

Figure 8-1. H-Bridge Current Paths

When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically
inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the
output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the
pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above
VM. This diode is the body diode of the high-side or low-side FET.
The propagation delay time (tPD) is measured as the time between an input edge to output change. This time
accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents
noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn
on or turn off times (tRISE and tFALL).
Figure 8-2 below shows the timing of the inputs and outputs of the motor driver.

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IN1 (V)

IN2 (V)

OUT1 (V)

tPD tRISE tDEAD tPD tFALL tDEAD

OUT2 (V)

tPD tFALL tDEAD tPD tRISE tDEAD

Figure 8-2. H-Bridge Current Paths

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8.4.2 Current Sense and Regulation (IPROPI)

The DRV8231A device integrates current sensing, regulation, and feedback as part of the IPROPI feature.
These features allow the device to sense the output current without an external sense resistor or sense circuitry
reducing system size, cost, and complexity. This also allows for the device to limit the output current in the case
of motor stall or high torque events and give detailed feedback to the controller about the load current through a
current proportional output. Figure 8-3 shows the IPROPI timings specified in the Electrical Characteristics table.

INx
tRISE tFALL

ttPDt

OUT1 (V)

ttBLANKt ttOFFt

ITRIP
OUTx (A)

tDEG

VREF
IPROPI (V)

ttDELAYt

Figure 8-3. Detailed IPROPI Timing Diagram

8.4.2.1 Current Sensing

The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power
MOSFETs in the H-bridge scaled by AIPROPI. The IPROPI output current can be calculated by Equation 1. The
ILSx in Equation 1 is only valid when the current flows from drain to source in the low-side MOSFET. If current
flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if
the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in
one of the low-side MOSFETs.

IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) (1)

The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It
indicates the combined effect of offset error added to the IOUT current and gain error.
The motor current is measured by an internal current mirror architecture on the low-side FETs which removes
the need for an external power sense resistor as shown in Figure 8-4. The current mirror architecture allows
for the motor winding current to be sensed in both the drive and brake low-side slow-decay periods allowing
for continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the
current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be
sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before
switching back to coast mode again.

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Control OUT
Inputs ILOAD

VREF
+ LS
±

IPROPI GND
Clamp
Integrated
Current Sense
MCU IPROPI IPROPI
ADC
+
VPROPI RIPROPI AIPROPI
±

Copyright © 2017, Texas Instruments Incorporated

Figure 8-4. Integrated Current Sensing

The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a
proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the
load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital
converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that
the full range of the controller ADC is utilized. Additionally, the DRV8251A device implements an internal IPROPI
voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case
of output overcurrent or unexpected high current events.
The corresponding IPROPI voltage to the output current can be calculated by Equation 2.

VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) (2)

The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit.
This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output
being ready.
If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side
MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If
a command on the INx pins disables the low-side MOSFETs (according to the logic tables in Section 8.4.1), the
IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current
as they disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time),
IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.
8.4.2.2 Current Regulation
The DRV8231A device integrates current regulation using a fixed off-time current chopping scheme. This allows
the devices to limit the output current in case of motor stall, high torque, or other high current load events without
involvement from the external controller as shown in Figure 8-5.

ITRIP
IMOTOR

VMOTOR

Control Input
(IN1 or IN2)
tOFF tOFF tOFF

Figure 8-5. Off-Time Current-Regulation

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The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI
output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to
VVREF with an internal comparator.

ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) (3)

For example, if VVREF = 3.3 V, RIPROPI = 1375 Ω, and AIPROPI = 1500 μA/A, then ITRIP will be approximately 1.6
A.
The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge
automatically enables after the tOFF period and does not require a new control input edge on the INx pins to
reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping
mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both
low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to
the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period
of brake/low-side slow decay for tOFF. If the state of the INx control pins changes during the tOFF time, the
remainder of the tOFF time is ignored, and the outputs will again follow the inputs.
The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time
helps to prevent voltage and current transients during output switching from effecting the current regulation.
These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals.
The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In
certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the
IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not
prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow
down the response time of the current regulation circuitry.
The internal current regulation and current feedback can be disabled by tying IPROPI to GND and setting the
VREF pin voltage greater than GND. If current feedback is required and current regulation is not required, set
VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current
regulation circuit, VVREF must be within the range of the VREF pin voltages specified in the Recommended
Operating Conditions table.

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8.4.3 Protection Circuits

The DRV8231A device is fully protected against VM undervoltage, overcurrent, and overtemperature events.
8.4.3.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally.
If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will
disable. The driver re-enables after the OCP retry period (tRETRY) has passed. If the fault condition is still
present, the cycle repeats as shown in Figure 8-6.
Overshoot due to OCP
deglitch time (tOCP)
IOCP

Motor
Current

tOCP Time
tRETRY

Figure 8-6. OCP Operation

Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short
to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection
does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and
IPROPI settings.
8.4.3.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled. After the die temperature has
fallen to a safe level, operation automatically resumes.
8.4.3.3 VM Undervoltage Lockout (UVLO)
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, the output FETS are disabled, and all internal logic is reset. Operation continues when the
VVM voltage rises above the UVLO rising threshold as shown in Figure 8-7.

VUVLO (max) rising

VUVLO (min) rising

VUVLO (max) falling

VUVLO (min) falling VVM

Device enabled,
Device status Device enabled, active mode Device disabled, fault mode
active mode

Time

Figure 8-7. VM UVLO Operation

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8.5 Device Functional Modes

Table 8-3 summarizes the DRV8231A functional modes described in this section.
Table 8-3. Modes of Operation
MODE CONDITION H-BRIDGE INTERNAL CIRCUITS
Active Mode IN1 or IN2 = logic high Operating Operating
Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled
Fault Mode Any fault condition met Disabled See Table 8-4

8.5.1 Active Mode

After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the INx pins are in a state
other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the H-bridge,
charge pump, and internal logic are active and the device is ready to receive inputs.
8.5.2 Low-Power Sleep Mode
When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8231A device enters a low-power sleep mode.
In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ). If
the device is powered up while all inputs are low, it immediately enters sleep mode. After any of the input pins
are set high for longer than the duration of tWAKE, the device becomes fully operational. Figure 8-8 shows an
example timing diagram for entering and leaving sleep mode.

Sleep
Active Mode Wakeup Active Mode
Mode

IN1

tSLEEP tWAKE

IN2

OUT1 Hi-Z

OUT2 Hi-Z

Figure 8-8. Sleep Mode Entry and Wakeup Timing Diagram

8.5.3 Fault Mode

The DRV8231A device enters a fault mode when a fault is encountered. This is utilized to protect the device
and the output load. The device behavior in the fault mode is described in Table 8-4 and depends on the fault
condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is met.
Table 8-4. Fault Conditions Summary
FAULT CONDITION H-BRIDGE INTERNAL CIRCUITS RECOVERY
VM undervoltage (UVLO) VM < VUVLO,falling Disabled Disabled VM > VUVLO,rising
Overcurrent (OCP) IOUT > IOCP Disabled Operating IOUT < IOCP
Thermal Shutdown (TSD) TJ > TTSD Disabled Operating TJ < TTSD – THYS

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8.6 Pin Diagrams

8.6.1 Logic-Level Inputs
Figure 8-9 shows the input structure for the logic-level input pins IN1, IN2, PH/IN1, and EN/IN2.

100 k

Figure 8-9. Logic-level input

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The DRV8231A device is typically used to drive one brushed DC motor.
9.2 Typical Application
9.2.1 Brush DC Motor
3.3 V
RIPROPI

IPROPI OUT2
Controller
IN2 GND BDC
DRV8231A
IN1 OUT1
3.3 V
VREF VM
PPAD + 4.5 to 33 V
0.1 µF 47 µF
± Power Supply

Figure 9-1. Typical Connections

9.2.1.1 Design Requirements

The table below lists the design parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor voltage VVM 12 V
Average motor current IAVG 0.8 A
Motor inrush (startup) current IINRUSH 2.1 A
Motor stall current ISTALL 2.1 A
Motor current trip point ITRIP 1.9 A
VREF voltage VREF 3.3 V
IPROPI sense resistance RIPROPI 1.5 kΩ
PWM frequency fPWM 50 kHz

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Motor Voltage
The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.

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9.2.1.2.2 Motor Current

Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at
motor startup is sometimes called inrush current. The current regulation feature in the DRV8231A can help to
limit these large currents. Figure 9-4 and Figure 9-5 show examples of limiting inrush current.
Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup
time.
9.2.1.3 Application Curves

Stall Current

Inrush Current
Motor Stall Occurs Inrush Current Motor Stall Occurs
Stall Current

Average Running Current

Average Running Current

Ch 1 (Yellow) = IN1 Signal Ch 2 (Magenta) = IN2 Signal Ch 1 (Yellow) = IN1 Signal Ch 2 (Magenta) = IN2 Signal
Ch 3 (Blue) = OUT1 Voltage Ch 7 (Red) = Motor Current Ch 4 (Green) = OUT2 Voltage Ch 7 (Red) = Motor Current

Figure 9-2. Motor startup at 100% duty cycle Figure 9-3. Motor startup at 50% duty cycle

Current Regula
on Threshold (ITRIP)

Inrush Current Motor Stall Occurs Inrush Current Current Regula
on Threshold (ITRIP) Motor Stall Occurs

Stall Current Stall

Current

Average Running Current Average Running Current

Ch 1 (Yellow) = IN1 Signal Ch 3 (Blue) = OUT1 Voltage Ch 1 (Yellow) = IN1 Signal Ch 4 (Green) = OUT2 Voltage
Ch 6 (Purple) = IPROPI Signal Ch 7 (Red) = Motor Current Ch 6 (Purple) = IPROPI Signal Ch 7 (Red) = Motor Current

Figure 9-4. Motor startup at 100% duty cycle with Figure 9-5. Motor startup at 50% duty cycle with
current regulation current regulation

9.2.2 Stall Detection

Some applications require stall detection to notify the microcontroller of a locked rotor condition. A stall could be
caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained
travel path. By using the IPROPI analog current sense feedback of the DRV8231A, the system can implement a
simple stall detection scheme.
The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions
as shown in Figure 9-6. To implement stall detection, the microcontroller reads the voltage on the IPROPI pin
using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be
used to set this threshold as well.

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Stall Motor driver

Motor Start
detected disabled
IN1

IN2

ITRIP
threshold
Motor
current
OUTx OUTx
disabled Inrush Average running Stall disabled
current current Current

Stall threshold
in
rmware
VIPROPI

STALL

tINRUSH tSTALL
Figure 9-6. Motor Current Profile with STALL Signal

9.2.2.1 Design Requirements

The table below lists the design parameters.
Table 9-2. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor voltage VM 14.4 V
Motor current trip point ITRIP 900 mA
VREF voltage VREF 2V
IPROPI resistance RIPROPI 1.5 kΩ
Stall current trip point ISTALL 500 mA
Stall IPROPI voltage trip point VIPROPI,STALL 1V
Inrush current ignore time tINRUSH 65 ms
Stall detection time tSTALL 65 ms

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Stall Detection Timing
The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush
current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current
drops to an average level because the back electromotive force (EMF) in the motor increases with speed.
The inrush current should not be mistaken for a stall condition. One way to do this is for the microcontroller
to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH,
at startup. The tINRUSH timing should be determined experimentally because it depends on motor parameters,
supply voltage, and mechanical load response times.

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When a stall condition occurs, the motor current will increase from the average running current level because
the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in
case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque
condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before
the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be
desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a
shorter tSTALL time in the microcontroller.
Figure 9-6 illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform.
9.2.2.2.2 Stall Threshold Selection
The stall detection threshold in firmware should be chosen at a current level between the maximum stall current
and the average running current of the motor as shown in Figure 9-6.
9.2.2.3 Application Curves

Current Regula
on Threshold (ITRIP)

Inrush Current Inrush Current

Current Regula
on Threshold (ITRIP)

Motor Stall Occurs Stall Current
Average Running Current Motor Stall Occurs
Average Running Current

Stall Current

MCU Detects Stall

MCU Detects Stall

Ch 1 (Yellow) = VIPROPI Ch 2 (Magenta) = IN1 Signal

Ch 1 (Yellow) = VIPROPI Ch 2 (Magenta) = IN1 Signal
Ch 3 (Blue) = Stall Indication Ch 4 (Green) = Motor Current
Ch 3 (Blue) = Stall Indication Ch 4 (Green) = Motor Current
Figure 9-7. Example Waveform of Stall Detection
Figure 9-8. Stall Detected on IPROPI While Current
Regulation Limits Inrush and Stall Currents

9.2.3 Relay Driving

The PWM interface may also be used to drive single- and dual-coil latching relays, as shown in the figures
below.
VCC
DRV8251A/31A
Controller
IPROPI
OUT2 Single-
1 8
coil
PWM IN2 GND relay
2 7
Thermal
PWM IN1 OUT1
3 Pad 6
VCC VM
VREF VM
4 5

0.1 μF CBulk

Figure 9-9. Single-Coil Relay Driving

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VCC
DRV8251A/31A
VM
Controller Dual-
IPROPI coil
OUT2
1 8 relay
IN2 GND
PWM 2 7
Thermal
PWM IN1 OUT1
3 Pad 6
VCC VM
VREF VM
4 5

0.1 μF CBulk

Figure 9-10. Dual-Coil Relay Driving

9.2.3.1 Design Requirements

Table 9-3 provides example requirements for a single- or dual-coil relay application. Current regulation may also
be configured to ensure the relay current is within the relay specification. This is important if the VM supply
voltage is higher than the voltage rating of the relay.
Table 9-3. System design requirements
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor supply voltage VM 12 V
Microcontroller supply voltage VCC 3.3 V
Single coil relay current IRelay 500 mA pulse for 200 ms
Dual coil relay current IOUT1, IOUT2 100 mA pulse for 200 ms

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 Control Interface for Single-Coil Relays
The PWM interface can be used to drive single-coil relays. To actuate the relay, the driver needs to drive current
with either the forward or reverse states in the PWM table. After driving the relay, the outputs can be disabled
(IN1=IN2=0) to put the driver to sleep and save energy. Alternatively, the outputs can be put into brake mode
briefly after actuation to avoid back EMF effects from the relay or causing current to flow back from the relay into
the VM supply node.
9.2.3.2.2 Control Interface for Dual-Coil Relays
A dual coil relay only require two low-side drivers if the center tap is connected to VM. The body diodes of
the unused FETs act as freewheeling diodes, so additional freewheeling diodes are not needed when driving a
dual-coil relay with the DRV8231A. The PWM interface can be used to control the dual-coil relay. The following
figures show the schematic and timing diagram for driving dual-coil relays.

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VM Sleep Sleep Sleep

Drive Coil1 Drive Coil2
mode mode mode

IN1

IN2
VM
Coil1 Coil2 VM
Hi-Z Hi-Z Hi-Z
VOUT1 VOUT2 VOUT1
IOUT1 IOUT2 GND

Dual-coil
relay VM
Hi-Z Hi-Z Hi-Z
VOUT2

GND

IOUT1
Figure 9-11. Schematic of dual-coil relay driven by
the OUTx H-bridge
IOUT2

Figure 9-12. Timing diagram for driving a dual-coil

relay with PWM interface

Table 9-4 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and
output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will
go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true
when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so
extra external diodes are not needed. Figure 9-15 shows oscilloscope traces for this application.
Table 9-4. PWM control table for dual-coil relay driving
IN1 IN2 OUT1 OUT2 DESCRIPTION
0 0 Hi-Z Hi-Z Outputs disabled (H-Bridge Hi-Z)
0 1 L H Drive Coil1
1 0 H L Drive Coil2
Drive Coil1 and Coil2 (invalid state for a
1 1 L L
dual-coil latching relay)

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9.2.3.3 Application Curves

A. Ch 1 = IN1 Ch 2 = IN2 Ch 3 = VOUT1 A. Ch 1 = IN1 Ch 2 = IN2 Ch 3 = VOUT1

Ch 4 = VOUT2 Ch 6 = Relay Ch 7 = Relay Coil Ch 4 = VOUT2 Ch 6 = Relay Ch 7 = Relay Coil
Switch Current Switch Current

Figure 9-13. PWM driving for a single-coil latching Figure 9-14. PWM driving for a single-coil latching
relay with driving profile FORWARD → COAST → relay with driving profile FORWARD → BRAKE →
REVERSE → COAST REVERSE → BRAKE

A. Ch 1 = IN1 Ch 2 = IN2 Ch 3 = VOUT1

Ch 4 = VOUT2 Ch 6 = Relay Switch Ch 7 = Relay Coil1 Current
Ch 8 = Relay Coil2 Current

Figure 9-15. PWM driving for dual-coil relay

9.2.4 Multi-Sourcing with Standard Motor Driver Pinout

The DRV8870, DRV8251, and DRV8231 devices come in an industry standard package footprint in the DDA
package. When the system needs current sensing, a current-sense amplifier may be used across the RSENSE
resistor to provide an amplifed signal back to an microcontroller ADC as shown in Figure 9-16. To reduce the
size of the system bill of materials and cost, the IPROPI function in DRV8231A/51A can replace the current
sense amplifer. During the board design process, both solutions, IPROPI and industry standard shunt devices,
can be accomodated in the same board layout by placing and not placing (DNP) components as shown in Figure
9-17. This allows the system to be flexible for lowest cost with the DRV8231A/51A or for use with second-source
devices with the same pinout as DRV8870, DRV8231, and DRV8251.

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0
To ADC

DNP

GND
1 8 OUT2
0 ISEN
IN1 2 DRV8870, 7
Rsense
0.5

DRV8231,
IN2 3 DRV8251 6 OUT1
Sense
VREF 4 5 VM Amp

Figure 9-16. Standard Pinout with Current Sense Amplifier

DNP
To ADC

0
IPROPI
1 8 OUT2
Ripropi GND
1.5 k IN1 2 7
0

DRV8231A,
DRV8251A
IN2 3 6 OUT1
Sense
VREF 4 5 VM Amp DNP

Figure 9-17. DRV8231A/51A Device Using IPROPI to Integrate The Current Sense Function into The
Motor Driver

9.3 Current Capability and Thermal Performance

The output current and power dissipation capabilities of the driver depends heavily on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
9.3.1 Power Dissipation and Output Current Capability
Total power dissipation for the device consists of three main components: quiescent supply current dissipation
(PVM), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction) losses (PRDS).
While other factors may contribute additional power losses, they are typically insignificant compared to the three
main items.
PTOT = PVM + PSW + PRDS
PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current
specification.

PVM = VVM x IVM (4)

PVM = 96 mW = 24 V x 4 mA (5)

PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IAVG), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.

PSW = PSW_RISE + PSW_FALL (6)

PSW_RISE = 0.5 x VM x IAVG x tRISE x fPWM (7)

PSW_FALL = 0.5 x VM x IAVG x tFALL x fPWM (8)

PSW_RISE = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz (9)

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PSW_FALL = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz (10)

PSW = 53 mW = 26.4 mW + 26.4 mW (11)

PRDS can be calculated from the device RDS(on) and average output current (IAVG).

PRDS = IAVG 2 x (RDS(ON)_HS + RDS(ON)_LS) (12)

RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85
°C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows this
derating factor. Alternatively, Section 7.6 shows curves that plot how RDS(on) changes with temperature.

PRDS = 225 mW = (0.5 A)2 x (300 mΩ x 1.5 + 300 mΩ x 1.5) (13)

Based on the example calculations above, the expressions below calculate the total expected power dissipation
for the device.
PTOT = PVM + PSW + PRDS
PTOT = 374 mW = 96 mW + 53 mW + 225 mW (14)

The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking
around the device. Section 9.3.2 describes this dependence in greater detail.

TJ = (PTOT x RθJA) + TA (15)

TJ = 100 °C = (0.374 W x 40.4 °C/W) + 85°C (16)

The device junction temperature should remain below its absolute maximum rating for all system operating
conditions. The calculations in this section provide reasonable estimates for junction temperature. However,
other methods based on temperature measurements taken during system operation are more realistic and
reliable. Additional information on motor driver current ratings and power dissipation can be found in Section
9.3.2 and Section 12.1.1.
9.3.2 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria.
HSOP (DDA package)
Table 9-5. Simulation PCB Stackup Summary for HSOP package
Layer 2-layer 4-layer
Top Layer HSOP footprint with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally
connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from HSOP thermal
pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper
plane area, thermally connected to HSOP thermal pad
through vias.
Layer 3, internal supply N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper
plane area, not connected to other layers.
Bottom Layer Ground plane with 1- or 2-oz copper thickness. See 1- or 2-oz copper thickness. Copper area fixed at 4.90
Table 9-6 for copper area varied in simulation. Thermally mm × 6.00 mm in simulation. Thermally connected to
connected to HSOP thermal pad through vias. HSOP thermal pad through vias.

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Figure 9-18 shows an example of the simulated board for the HSOP package. Table 9-6 shows the dimensions
of the board that were varied for each simulation.

Figure 9-18. HSOP PCB model top layer

Table 9-6. Dimension A for 8-pin HSOP (DDA) package

Cu area (cm2) Dimension A (mm)
0.069 Package thermal pad dimensions
2 16.40
4 22.32
8 30.64
16 42.38

WSON (DSG package)

Table 9-7. Simulation PCB Stackup Summary for WSON package
Layer 2-layer 4-layer
Top Layer WSON footprint with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally
connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from WSON thermal
pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper
plane area, thermally connected to HSOP thermal pad
through vias.
Layer 3, internal supply N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper
plane area, not connected to other layers.
Bottom Layer Ground plane with 1- or 2-oz copper thickness. See 1- or 2-oz copper thickness. Copper area fixed at 2.00
Table 9-8 for copper area varied in simulation. Thermally mm × 2.00 mm in simulation. Thermally connected to
connected to WSON thermal pad through vias. WSON thermal pad through vias.

Figure 9-19 shows an example of the simulated board for the WSON package. Table 9-8 shows the dimensions
of the board that were varied for each simulation.

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www.ti.com SLVSFZ8 – NOVEMBER 2021

Figure 9-19. WSON PCB model top layer

Table 9-8. Dimension A for 8-pin WSON package

Cu area (mm2) Dimension A (mm)
0.015 Package thermal pad dimensions
2 15.11
4 20.98
8 29.27
16 40.99

9.3.2.1 Steady-State Thermal Performance

"Steady-state" conditions assume that the motor driver operates with a constant average current over a long
period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter)
change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more
layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the
PCB layout.

200 50
4 layer, 2 oz 4 layer, 2 oz
180 4 layer, 1 oz 45 4 layer, 1 oz
2 layer, 2 oz 2 layer, 2 oz
160 2 layer, 1 oz 2 layer, 1 oz
40
140
35
RJA (C/W)

JB (C/W)

120
30
100
25
80

60 20

40 15

20 10
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Top layer copper area (cm2) Top layer copper area (cm2)
Figure 9-20. HSOP, PCB junction-to-ambient Figure 9-21. HSOP, junction-to-board
thermal resistance vs copper area characterization parameter vs copper area

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275 80
4 layer, 2 oz 75 4 layer, 2 oz
250 4 layer, 1 oz 4 layer, 1 oz
2 layer, 2 oz 70 2 layer, 2 oz
225
2 layer, 1 oz 65 2 layer, 1 oz
200 60
55
RJA (C/W)

175

JB (C/W)
50
150
45
125
40
100 35
75 30
25
50
20
25 15
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Top layer copper area (cm2) Top layer copper area (cm2)
Figure 9-22. WSON, PCB junction-to-ambient Figure 9-23. WSON, junction-to-board
thermal resistance vs copper area characterization parameter vs copper area

9.3.2.2 Transient Thermal Performance

The motor driver may experience different transient driving conditions that cause large currents to flow for a
short duration of time. These may include
• Motor start-up when the rotor is initially stationary.
• Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent
protection triggers.
• Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance in
addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the
junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances
for 1-oz and 2-oz copper layouts for the HSOP and WSON packages. These graphs indicate better thermal
performance with short current pulses. For short periods of drive time, the device die size and package
dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on
thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and
copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state
performance.
200

100
70
50
40
30
ZJA (C/W)

20

10
7
0.069 cm2, 2 layer
5 2 cm2, 2 layer
4 4 cm2, 2 layer
3 8 cm2, 2 layer
0.069 cm2, 4 layer
2 2 cm2, 4 layer
4 cm2, 4 layer
8 cm2, 4 layer
1
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 20 30 50 70 100 200300 500 1000
Pulse duration (s)

Figure 9-24. HSOP package junction-to-ambient thermal impedance for 1-oz copper layouts

30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

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200

100
70
50
40
30
ZJA (C/W)

20

10
7
0.69 cm2, 2 layer
5 2 cm2, 2 layer
4 4 cm2, 2 layer
3 8 cm2, 2 layer
0.69 cm2, 4 layer
2 2 cm2, 4 layer
4 cm2, 4 layer
8 cm2, 4 layer
1
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 20 30 50 70 100 200300 500 1000
Pulse Duration (s)

Figure 9-25. HSOP package junction-to-ambient thermal impedance for 2-oz copper layouts
300

200

100
70
50
40
ZJA (C/W)

30

20

10 0.015 cm2, 2 layer

2 cm2, 2 layer
7 4 cm2, 2 layer
8 cm2, 2 layer
5 0.015 cm2, 4 layer
4 2 cm2, 4 layer
3 4 cm2, 4 layer
8 cm2, 4 layer
2
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 20 30 50 70 100 200300 500 1000
Pulse duration (s)

Figure 9-26. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts
300

200

100
70
50
40
ZJA (C/W)

30

20

10 0.015 cm2, 2 layer

2 cm2, 2 layer
7 4 cm2, 2 layer
8 cm2, 2 layer
5 0.015 cm2, 4 layer
4 2 cm2, 4 layer
3 4 cm2, 4 layer
8 cm2, 4 layer
2
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 20 30 50 70 100 200300 500 1000
Pulse duration (s)

Figure 9-27. WSON package junction-to-ambient thermal impedance for 2-oz copper layouts

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10 Power Supply Recommendations

10.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance of the power supply and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VBB

+ + Motor
± Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.

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 DRV8231A
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11 Layout
11.1 Layout Guidelines
Since the DRV8231A integrates power MOSFETs capable of driving high current, careful attention should be
paid to the layout design and external component placement. Some design and layout guidelines are provided
below.
• Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are
recommended.
• The VM power supply capacitors should be placed as close to the device as possible to minimize the loop
inductance.
• The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as
close as possible to the device to minimize the loop inductance.
• VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground.
Thick metal routing should be utilized for these traces as is feasible.
• The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
• A recommended land pattern for the thermal vias is provided in the package drawing section.
• The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
11.2 Layout Example

IPROPI 1 8 OUT2

IN2 2 7 GND
Thermal

IN1 3 Pad 6 OUT1

VREF 4 5 VM

Figure 11-1. Layout Recommendation for DSG package

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IPROPI 1 8 OUT2

IN2 2 7 GND
Thermal

IN1 3 Pad 6 OUT1

VREF 4 5 VM

Figure 11-2. Layout Recommendation for DDA Package

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 DRV8231A
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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
PowerPAD™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: DRV8231A
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8231ADDAR ACTIVE SO PowerPAD DDA 8 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 150 DRV8231A Samples

DRV8231ADSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 31A Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Apr-2023

Addendum-Page 2
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DSG 8 WSON - 0.8 mm max height
2 x 2, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224783/A

www.ti.com
 PACKAGE OUTLINE
DSG0008A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2.1 B
A
1.9

0.32
PIN 1 INDEX AREA 0.18
2.1
1.9

0.4
0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8 C
0.7

SEATING PLANE
0.05 SIDE WALL
0.08 C
0.00 METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2

EXPOSED
THERMAL PAD 0.9 0.1 (DIM A) TYP

4 5

6X 0.5

2X
9
1.5 1.6 0.1

8
1

PIN 1 ID 0.32
8X
(45 X 0.25) 0.4 0.18
8X
0.2 0.1 C A B
0.05 C

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.9) ( 0.2) VIA

8X (0.5)
TYP
1
8

8X (0.25)
(0.55)
SYMM 9
(1.6)

6X (0.5)
5
4

(R0.05) TYP SYMM

(1.9)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5) SYMM METAL

1
8

8X (0.25)
(0.45)
SYMM
9

6X (0.5) (0.7)

5
4

(R0.05) TYP (0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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