ARM 11 MICROCONTROLLER

3.1 ARM ARCHITECTURE

Introduction
ARM is a 32-bit RISC processor architecture developed by the ARM corporation. ARM
processors possess a unique combination of features that makes ARM the most popular
embedded architecture today. First, ARM cores are very simple compared to most other general-
purpose processors, which means that they can be manufactured using a comparatively small
number of transistors, leaving plenty of space on the chip for application specific macro cells. A
typical ARM chip can contain several peripheral controllers, a digital signal processor, and some
amount of on-chip memory, along with an ARM core. Second, both ARM ISA and pipeline
design are aimed at minimizing energy consumption — a critical requirement in mobile
embedded systems. Third, the ARM architecture is highly modular: the only mandatory
component of an ARM processor is the integer pipeline; all other components, including caches,
MMU, floating point and other co-processors are optional, which gives a lot of flexibility in
building application-specific ARM-based processors. Finally, while being small and low-power,
ARM processors provide high performance for embedded applications.
For example, the PXA255 XScale processor running at 400MHz provides performance
comparable to Pentium 2 at 300MHz, while using fifty times less energy.
3.2 ARM vs RISC
In most respects, ARM is a RISC architecture. Like all RISC architectures, the ARM ISA
is a load-store one, that is, instructions that process data operate only on registers and are
separate from instructions that access memory. All ARM instructions are 32-bit long and most of
them have a regular three-operand encoding. Finally, the ARM architecture features a large
register file with 16 general-purpose registers. All of the above features facilitate pipelining of
the ARM architecture. However, the ARM architecture deviated from the RISC architecture in
some respects to improve its performance. The ARM did not include register windows that were
used by original RISC architectures to reduce complexity. The ARM architecture introduced an
auto-indexing addressing mode, where the value of an index register is incremented or
decremented while a load or store is in progress. ARM supports multiple register- transfer
instructions that allow loading or storing up to 16 registers at once.
3.3 Thumb instruction set extension
The Thumb instruction set was introduced in the fourth version of the ARM architecture
in order to achieve higher code density for embedded applications. Thumb provides a subset of
the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide
opcodes. On execution, these 16-bit instructions can be either decompressed to full 32- bit ARM
instructions or executed directly using a dedicated Thumb decoding unit. Although Thumb code
uses 40% more instructions than equivalent 32-bit ARM code, it typically requires 30% less
space. Thumb code is 40% slower than ARM code; therefore Thumb is usually used only in non-
performance-critical routines in order to reduce memory and power consumption of the system.
RASPBERRY PI BOARD

The Raspberry Pi is a credit-card-sized single-board computer developed in the UK by the

Raspberry Pi Foundation with the intention of promoting the teaching of basic computer science
in schools.
The Raspberry Pi is manufactured in two board configurations through licensed manufacturing
deals with Newark element14 (Premier Farnell), RS Components and Egoman. These companies
sell the Raspberry Pi online. Egoman produces a version for distribution solely in China and
Taiwan, which can be distinguished from other Pis by their red coloring and lack of FCC/CE
marks. The hardware is the same across all manufacturers.
The Raspberry Pi has a Broadcom BCM2835 system on a chip (SoC), which includes an
ARM1176JZF-S 700 MHz processor, Video Core IV GPU, and was originally shipped with
256 megabytes of RAM, later upgraded to 512 MB. It does not include a built-in hard disk or
solid-state drive, but uses an SD card for booting and persistent storage.
The Foundation provides Debian and Arch Linux ARM distributions for download. Tools are
available for Python as the main programming language, with support for BBC BASIC (via the
RISC OS image or the Brandy Basic clone for Linux),C, Java and Perl.

3.5 BOARD FEATURES

BCM 5825 FEATURES.

 CPU: 533 MHz Samsung S3C6410A ARM11

 RAM: up to 256 MB DDR RAM, 32 bit Bus

 Flash: up to 1GB NAND Flash

 EEPROM: 256 Byte (I2C)

 Ext. Memory: SD-Card socket

 Serial Ports: 1x DB9 connector (RS232), total: 4x serial port connectors

 IR: Infrared Receiver

 USB: 1x USB-A Host 1.1, 1x miniUSB Slave/OTG 2.0

 Audio Output: 3.5 mm stereo jack

 Audio Input: Condenser microphone

 Ethernet: RJ-45 10/100M (DM9000)

 RTC: Real Time Clock with battery

 Beeper: PWM buzzer

 Camera: 20 pin (2.0 mm) Camera interface

 TV Output: AV Out

 LCD Interface: 40 pin (2.0 mm) and 41 pin connector for FriendlyARM Displays and
VGA Board

 User Inputs: 8x push buttons and 1x A/D pot

 User Outputs: 4x LEDs

 Expansion: 40 pin System Bus, 30 pin GPIO, 20 pin SDIO (SD, SPI, I2C), 10 pin
Buttons (2.0 mm)

 Debug: 10 pin JTAG (2.0 mm)

 Power: regulated 5V

 Power Consumption: Mini6410: 0.25 A, Mini6410 + 4.3" LCD: 0.5 A

 OS Support

o Windows CE 6

o Linux

o Android

o Ubuntu
FEATURES:

ARCHITECTURE:

 Integrated system for hand-held devices and general embedded applications.

 16/32-Bit RISC architecture and powerful Instruction set with ARM920T CPU core.
 Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
 Instruction cache, data cache, writes buffer and Physical address TAG RAM to reduce
the effect of main memory bandwidth and latency on Performance.
 ARM920T CPU core supports the ARM debug Architecture.
 Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).
3.7 SYSTEM MANAGER:

 Little/Big Endean support.

 Support Fast bus mode and Asynchronous bus mode.
 Address space: 128M bytes for each bank (total 1G bytes).
 Supports programmable 8/16/32-bit data bus width for each bank.
 Fixed bank start address from bank 0 to bank 6.
 Programmable bank start address and bank size for bank 7.
 Eight memory banks:
o Six memory banks for ROM, SRAM, and others.
 Two memory banks for ROM/SRAM/Synchronous DRAM.
 Complete Programmable access cycles for all memory banks.
 Supports external wait signals to expand the bus cycle.
 Supports self-refresh mode in SDRAM for power down.
 Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others).
3.8 NAND Flash Boot Loader

 Supports booting from NAND flash memory.

 4KB internal buffer for booting.
 Supports storage memory for NAND flash memory after booting.
 Supports Advanced NAND flash
3.9 Cache Memory
  64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
 8words length per line with one valid bit and two dirty bits per line.
 Pseudo random or round robin replacement algorithm.
 Write-through or write-back cache operation to update the main memory.
 The write buffer can hold 16 words of data and four addresses.
3.10 CLOCK & POWER MANAGER

 On-chip MPLL and UPLL: UPLL generates the clock to operate USB
 Host/Device. MPLL generates the clock to operate MCU at maximum 400MHz @ 1.3V.
 Clock can be fed selectively to each function block by software.
 Power mode: Normal, Slow, Idle, and Sleep mode
o Normal mode: Normal operating mode
o Slow mode: Low frequency clock without PLL
o Idle mode: The clock for only CPU is stopped.
o Sleep mode: The Core power including all peripherals is shut down.
 Woken up by EINT[15:0] or RTC alarm interrupt from Sleep mode
3.11 INTERRUPT CONTROLLER

 60 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4
DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and
2 Camera), 1 AC97
 Level/Edge mode on external interrupt source
 Programmable polarity of edge and level
 Supports Fast Interrupt request (FIQ) for very urgent interrupt request
3.12 TIMER WITH PULSE WIDTH MODULATION (PWM)

 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-
based operation
 Programmable duty cycle, frequency, and polarity
 Dead-zone generation
 Supports external clock sources
3.13 RTC (REAL TIME CLOCK)
  Full clock feature: msec, second, minute, hour, date, day, month, and year
 32.768 KHz operation
 Alarm interrupt
 Time tick interrupt
3.14 GENERAL PURPOSE INPUT/OUTPUT PORTS

 24 external interrupt ports

 130 Multiplexed input/output ports
3.15 DMA CONTROLLER

 4-ch DMA controller

 Supports memory to memory, IO to memory, memory to IO, and IO to IO transfers
 Burst transfer mode to enhance the transfer rate
3.16 LCD CONTROLLER STN LCD DISPLAYS FEATURE

 Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan
display type
 Supports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors
for STN LCD
 Supports multiple screen size
o Typical actual screen size: 640x480, 320x240, 160x160, and others.
o Maximum frame buffer size is 4 Mbytes.
o Maximum virtual screen size in 256 color
o mode: 4096x1024, 2048x2048, 1024x4096 and others
3.17 TFT(THIN FILM TRANSISTOR) COLOR DISPLAYS FEATURE

 Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT

 Supports 16, 24 bpp non-palette true-color displays for color TFT
 Supports maximum 16M color TFT at 24 bpp mode
 LPC3600 Timing controller embedded for LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait /
256Kcolor/Reflective a-Si TFT LCD)
 LCC3600 Timing controller embedded for LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait /
256Kcolor/Transflective a-Si TFT LCD)
  Supports multiple screen size
o Typical actual screen size: 640x480, 320x240, 160x160, and others.
o Maximum frame buffer size is 4Mbytes.
o Maximum virtual screen size in 64K color
o mode: 2048x1024, and others
3.18 UART

 3-channel UART with DMA-based or interrupt based operation

 Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx)
 Supports external clocks for the UART operation (UEXTCLK)
 Programmable baud rate
 Supports IrDA 1.0
 Loopback mode for testing
 Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO.
3.19 A/D CONVERTER & TOUCH SCREEN INTERFACE

 8-ch multiplexed ADC

 Max. 500KSPS and 10-bit Resolution
 Internal FET for direct Touch screen interface
3.20 WATCHDOG TIMER

 16-bit Watchdog Timer

 Interrupt request or system reset at time-out
3.21 IIC-BUS INTERFACE

 1-ch Multi-Master IIC-Bus

 Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.
3.22 IIS-BUS INTERFACE

 1-ch IIS-bus for audio interface with DMA-based operation

 Serial, 8-/16-bit per channel data transfers
 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx
  Supports IIS format and MSB-justified data format

3.23 AC97 AUDIO-CODEC INTERFACE

 Support 16-bit samples

 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs 1-ch MIC input
3.24 USB HOST

 2-port USB Host

 Complies with OHCI Rev. 1.0
 Compatible with USB Specification version 1.1
3.25 USB DEVICE

 1-port USB Device

 5 Endpoints for USB Device
 Compatible with USB Specification version 1.1
3.26 SD HOST INTERFACE

 Normal, Interrupt and DMA data transfer mode (byte, halfword, word transfer)
 DMA burst4 access support (only word transfer)
 Compatible with SD Memory Card Protocol version 1.0
 Compatible with SDIO Card Protocol version 1.0
 64 Bytes FIFO for Tx/Rx
 Compatible with Multimedia Card Protocol version 2.11
3.27 SPI INTERFACE

 Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11

 2x8 bits Shift register for Tx/Rx
 DMA-based or interrupt-based operation
CAMERA INTERFACE

 ITU-R BT 601/656 8-bit mode support

 DZI (Digital Zoom In) capability
 Programmable polarity of video sync signals
  Max. 4096 x 4096 pixels input support (2048 x 2048 pixel input support for scaling)
 Image mirror and rotation (X-axis mirror, Y-axis mirror, and 180° rotation)
 Camera output format (RGB 16/24-bit and YCbCr 4:2:0/4:2:2 format)
3.29 Operating Voltage Range

 Core: 1.20V for 300MHz

 1.30V for 400MHz
 Memory: 1.8V/ 2.5V/3.0V/3.3V
 I/O: 3.3V
3.30 Operating Frequency

 Fclk Up to 400MHz
 Hclk Up to 136MHz
 Pclk Up to 68MHz

HARDWARE COMPONENTS
Raspberry Pi Basic Hardware
Extra Hardware You Will Need
• The Raspberry Pi board contains a processor and graphics chip, program memory (RAM)
and various interfaces and connectors for external devices. Some of these devices are
essential, others are optional. It operates in the same way as a standard PC, requiring a
keyboard for command entry, a display unit and a power supply.

Why Extra Hardware You Will Need:

 Since raspberry Pi board operates like PC it requires ‘mass-storage’, but a hard disk
drive of the type found in a typical PC is not really in keeping with the miniature size of
RPi.
  Instead we will use an SD Flash memory card normally used in digital cameras,
configured in such a way to ‘look like’ a hard drive to RPi’s processor.
 RPi will ‘boot’ (load the Operating System into RAM) from this card in the same way as
a PC ‘boots up’ into Windows from its hard disk.
 The following are essential to get started:
 SD card containing Linux Operating system
 USB keyboard
 TV or monitor (with HDMI, DVI, Composite or SCART input)
 Power supply (see Section 1.6 below)
 Video cable to suit the TV or monitor used
Operating System in SD Card
 As the RPi has no internal mass storage or built-in operating system it requires an SD
card preloaded with a version of the Linux Operating System.
 You can create your own preloaded card using any suitable SD card (4GBytes or above)
you have to hand. We suggest you use a new blank card to avoid arguments over lost
pictures.
 Keyboard & Mouse
 Most standard USB keyboards and mice will work with the RPi. Wireless
keyboard/mice should also function, and only require a single USB port for an RF
dongle.
 Display
 HD TVs and many LCD monitors can be connected using a full-size 'male' HDMI
cable, and with an inexpensive adaptor if DVI is used. HDMI versions 1.3 and 1.4 are
supported and a version 1.4 cable is recommended. The RPi outputs audio and video via
HMDI, but does not support HDMI input.
 Power Supply
 A standard modern phone charger with a micro USB connector will do, providing it can
supply at least 700mA at +5Vdc.

 Cables
 You will need one or more cables to connect up your RPi system.
  Video cable alternatives:
 HDMI-A cable
 HDMI-A cable + DVI adapter
 Composite video cable
 Composite video cable + SCART adaptor
 Audio cable (not needed if you use the HDMI video connection to a TV)
 Ethernet/LAN cable
 Internet Connectivity
 This may be via an Ethernet/LAN cable (standard RJ45 connector) or a USB WiFi
adaptor.
 The Rpi Model B Ethernet port is auto-sensing which means that it may be connected to a
router or directly to another computer (without the need for a crossover cable).

Ethernet :

Ethernet is a family of computer networking technologies for local area networks

(LANs) commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely
replaced competing wired LAN technologies.

Systems communicating over Ethernet divide a stream of data into individual packets
called frames. Each frame contains source and destination addresses and error-checking data
so that damaged data can be detected and re-transmitted.

The standards define several wiring and signaling variants. The original 10BASE5
Ethernet used coaxial cable as a shared medium. Later the coaxial cables were replaced by
twisted pair and fiber optic links in conjunction with hubs or switches. Data rates were
periodically increased from the original 10 megabits per second, to 100 gigabits per second.
ETHERNET CABLE RJ45

Since its commercial release, Ethernet has retained a good degree of compatibility.
Features such as the 48-bit MAC address and Ethernet frame format have influenced other
networking protocols

Ethernet initially competed with two largely proprietary systems, Token Ring and Token Bus.
Because Ethernet was able to adapt to market realities and shift to inexpensive and ubiquitous
twisted pair wiring, these proprietary protocols soon found themselves competing in a market
inundated by Ethernet products and by the end of the 1980s, Ethernet was clearly the
dominant network technology. In the process, 3Com became a major company. 3Com shipped
its first 10 Mbit/s Ethernet 3C100 transceiver in March 1981, and that year started selling
adapters for PDP-11s and VAXes, as well as Multibus-based Intel and Sun Microsystems
computers. This was followed quickly by DEC's Unibus to Ethernet adapter, which DEC sold and
used internally to build its own corporate network, which reached over 10,000 nodes by 1986,
making it one of the largest computer networks in the world at that time. Evolution:

Ethernet evolved to include higher bandwidth, improved media access control methods,
and different physical media. The coaxial cable was replaced with point-to-point links
connected by Ethernet repeaters or switches to reduce installation costs, increase reliability,
and improve management and troubleshooting. Many variants of Ethernet remain in common
use.
 Ethernet stations communicate by sending each other data packets: blocks of data
individually sent and delivered. As with other IEEE 802 LANs, each Ethernet station is given a
48-bit MAC address. The MAC addresses are used to specify both the destination and the
source of each data packet. Ethernet establishes link level connections, which can be defined
using both the destination and source addresses. On reception of a transmission, the receiver
uses the destination address to determine whether the transmission is relevant to the station
or should be ignored. Network interfaces normally do not accept packets addressed to other
Ethernet stations. Adapters come programmed with a globally unique address. An Ethertype
field in each frame is used by the operating system on the receiving station to select the
appropriate protocol module (i.e. the Internet protocol module). Ethernet frames are said to be
self-identifying, because of the frame type. Self-identifying frames make it possible to intermix
multiple protocols on the same physical network and allow a single computer to use multiple
protocols together. Despite the significant changes in Ethernet, all generations of Ethernet
(excluding early experimental versions) use the same frame formats (and hence the same
interface for higher layers), and can be readily interconnected through bridging.

ETHERNET (TCP/IP PROTOCOL)

Ethernet LAN Features:

 Bus topology, Wired LAN in IEEE 802.3 physical layer standard
 10 Mbps, 100 Mbps (Unshielded and Shielded wires) and 4 Gbps (in twisted pair wiring
mode)
 Broadcast medium─ Passive, Wired connections based.
 Frame format like the IEEE 802.2

 SNMP (Simple Network Management Protocol) Open system (therefore allows equipment
of different specifications)
 Each one connected to a common communication channel in the network listens and if the
channel is idle then transmits. If not idle, waits and tries again.
 Multi access is like in a Packet switched network
5.11 Ethernet LAN

 Passive, connection based

 Media access control (MAC) 48-bit address for transmitting and forwarding frames on
same LAN only.
 Can also use multicast addressing─for sending frames to all or few select types of
Ethernet devices

5.12 Connectivity to Internet

 Outside a LAN the Internet Protocol addresses sent

 Address Resolution Protocol (ARP) for resolving 32 bits Internet protocol
Addresses with the 48 bit destination host media address. RARP (reverse ARP) for vice
versa

5.13 Header Bytes in Ethernet Frame

 A data for transmission fragments into the frames.

 Frame has a header.
 Firstly, the header has eight bytes, which defines a preamble.
 The preamble is for indicating start of a frame and is used for synchronization.
 Then the header has six bytes (48-bits) of destination MAC address.
 Six bytes (48-bits) of the source MAC address follow the destination MAC.

5.14 Data in Ethernet Frame:

 Then there are six bytes. These are for the type field. These are meaningful only for the
higher network layers and the length definition.
 Minimum 72 bytes and maximum 1500 bytes of data follow the length definition.
 Lastly, there are 4 bytes for CRC check for the frame sequence check
5.15 UVC CAMERA

5.15.1 What is a UVC driver?

A UVC (or Universal Video Class) driver is a USB-category driver. A driver enables a device,
such as your webcam, to communicate with your computer’s operating system. And USB (or
Universal Serial Bus) is a common type of connection that allows for high-speed data transfer.
Devices that are equipped with a UVC driver, such as the Logitech® QuickCam® Pro 9000 for
Business, are capable of streaming video.

In other words, with a UVC driver, you can simply plug your webcam into your computer and
it’ll be ready to use.

5.15.2What does a UVC driver have to do with my webcam being plug and play?

It is the UVC driver that enables the webcam to be plug and play. A webcam with a UVC driver
does not need any additional software to work.

Once you plug your webcam in, it can work with a video-calling application, such as Skype®,
Windows Live Messenger®, or Microsoft Office® Communicator.

5.15.3 Are there different kinds of webcam drivers?

Yes, there are two kinds of webcam drivers:

 The one included with the installation disc that came with your product. For your
webcam to work properly, this driver requires some time to install. It is specifically tuned
for your webcam, designed by your webcam manufacturer and optimized for webcam
performance.
 A UVC driver

You can only use one driver at a time, but either one will allow you to use your webcam with
various applications.
5.15.4 The following Logitech webcams support UVC:

 Logitech® QuickCam® Pro 9000 for Business

 Logitech® QuickCam® Pro for Notebooks Business

 Logitech® QuickCam® Communicate MP for Business

 Logitech® QuickCam® Deluxe for Notebooks Business

 Logitech® QuickCam® 3000 for Business

5.15.5 Does my computer support UVC?

Most current operating systems support UVC. Although UVC is a relatively new format, it is
quickly becoming common.

5.15.6 Which operating systems support UVC?

There are more environments that support UVC, but what follows is a listing of the most
common:

5.15.6 Windows:

 Windows® XP Service Pack 2 and higher

 Windows Vista®

5.15.7 Mac:

 Tiger® OS (versions 10.4.9 and higher)

 Leopard® OS (versions 10.5.1 and higher)

5.15.8 Linux:

There are many different versions of Linux. Please check with your distribution vendor to
determine if your version supports UVC.