Diploma Engineering

Laboratory Manual
(VLSI)
(4361102)

[EC semester 6]
Enrolment No
Name
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Academic Term
Institute

Directorate Of Technical Education

Gandhinagar - Gujarat
Course Name (Course Code)

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Enrolment No. ………….……………. of …….………. Semester of Diploma
in……………………………………………………………………………………………………….……..of
………………………………………………………………………. (GTU Code) has satisfactorily completed the
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VLSI (4361102)

Preface
The primary aim of any laboratory/Practical/field work is enhancement of required skills as well
as creative ability amongst students to solve real time problems by developing relevant competencies in
psychomotor domain. Keeping in view, GTU has designed competency focused outcome-based
curriculum -2021 (COGC-2021) for Diploma engineering programmes. In this more time is allotted to
practical work than theory. It shows importance of enhancement of skills amongst students and it pays
attention to utilize every second of time allotted for practical amongst Students, Instructors and Lecturers
to achieve relevant outcomes by performing rather than writing practice in study type. It is essential for
effective implementation of competency focused outcome- based Green curriculum-2021. Every
practical has been keenly designed to serve as a tool to develop & enhance relevant industry needed
competency in each and every student. These psychomotor skills are very difficult to develop through
traditional chalk and board content delivery method in the classroom. Accordingly, this lab manual has
been designed to focus on the industry defined relevant outcomes, rather than old practice of conducting
practical to prove concept and theory.

By using this lab manual, students can read procedure one day in advance to actual performance
day of practical experiment which generates interest and also, they can have idea of judgement of
magnitude prior to performance. This in turn enhances predetermined outcomes amongst students. Each
and every Experiment /Practical in this manual begins by competency, industry relevant skills, course
outcomes as well as practical outcomes which serve as a key role for doing the practical. The students
will also have a clear idea of safety and necessary precautions to be taken while performing experiment.

This manual also provides guidelines to lecturers to facilitate student-centred lab activities for
each practical/experiment by arranging and managing necessary resources in order that the students
follow the procedures with required safety and necessary precautions to achieve outcomes. It also gives
an idea that how students will be assessed by providing Rubrics.
This is an advance course, for electronic engineers. Digital integrated circuits are integral part of
electronic equipment/gadgets starting from small toys to complex computer systems including personal
digital assistants, mobile phones and Multimedia agents. This course will enable the students to acquire
the basic skills to develop codes for VLSI circuits through Verilog programming. This course will also enable
them to use FPGA and ASIC chips for design and development of various applications.

Although we try our level best to design this lab manual, but always there are chances of
improvement. We welcome any suggestions for improvement.

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VLSI (4361102)

Programme Outcomes (POs):

1. Basic and Discipline specific knowledge: Apply knowledge of basic mathematics, science
and engineering fundamentals and engineering specialization to solve the engineering
problems.

2. Problem analysis: Identify and analyse well-defined engineering problems using codified
standard methods.

3. Design/ development of solutions: Design solutions for engineering well-defined technical

problems and assist with the design of systems components or processes to meet specified
needs.

4. Engineering Tools, Experimentation and Testing: Apply modern engineering tools and
appropriate technique to conduct standard tests and measurements.

5. Engineering practices for society, sustainability and environment: Apply appropriate

technology in context of society, sustainability, environment and ethical practices.

6. Project Management: Use engineering management principles individually, as a team

member or a leader to manage projects and effectively communicate about well-defined
engineering activities.

7. Life-long learning: Ability to analyse individual needs and engage in updating in the context
of technological changes in field of engineering.

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VLSI (4361102)

Practical Outcome - Course Outcome matrix

Course Outcomes (COs):

CO1 Describe working of MOSFET system.

CO2 Maintain MOS inverters.

CO3 Maintain MOS circuits

CO4 Describe fabrication process for MOS

CO5 Develop VERILOG Programs for combinational and sequential circuits.

CO1 CO2 CO3 CO4 CO5

S. No. Practical Outcome

1. Identify Verilog modules and coding styles √

2. Simulate the Basic logic gates using Verilog √ √

3. Simulate universal gates using Verilog √ √

4. Simulate XOR and XNOR using Verilog √ √

5. Simulate Half adder using Verilog √ √

6.
Simulate full adder using half adder in √ √
Verilog
7. Simulate four-bit adder using Verilog √
√

8. Simulate 4 x1 multiplexer using Verilog √

√

9.
Simulate 1 x 4 de-mux using Verilog √
√

10. Simulate 3: 8 decoder using Verilog √

√

11. Simulate 8: 3 encoder using Verilog √

√

12. Simulate Parity generator and checker using √

√
Verilog
13. Simulate flip-flops (SR, D, T, JK) using Verilog √
√

14.
Simulate 4-bit Up counter using Verilog √
√

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VLSI (4361102)

15.
Simulate 4-bit shift register using Verilog √
√

16.
Verify digital circuits by implementing √
√
testbench for it in Verilog
17.
Hardware implementation of above √
√ √
programs

Industry Relevant Skills

The following industry relevant skills are expected to be developed in the students by
performance of experiments of this course.

• Develop Verilog programs for VLSI based electronic systems

• Develop testbench in Verilog to test digital circuits.
• Debug program to fix errors.
• Follow Coding Guidelines.

Guidelines to Course Faculty

1. Course faculty should demonstrate experiment with all necessary implementation
strategies described in curriculum.
2. Course faculty should explain industrial relevance before starting of each experiment.
3. Course faculty should involve & give opportunity to all students for hands on experience.
4. Course faculty should ensure mentioned skills are developed in the students by asking.
5. Utilise 2 hrs of lab hours effectively and ensure completion of write up with quiz also.
6. Encourage peer to peer learning by doing same experiment through fast learners.

Instructions for Students

1. Student shall develop skill to install and work on different IDEs.
2. Students shall develop maintenance skill as expected by industries.
3. Student shall attempt to develop related hand-on skills and build confidence.
4. Student shall develop the habits of evolving more ideas, innovations, skills etc.
5. Student shall refer technical magazines and data books.
6. Student should develop habit to submit the practical on date and time.
7. Student should well prepare while submitting write-up of exercise.

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Continuous Assessment Sheet

Enrolment No: Name
Name: Term:
Sr no Title of experiment Marks
Page Sign
Date (25)

1. To develop a Verilog code to understand module

definition and coding styles
2. To develop and simulate basic logic gates using
Verilog
3. To develop and simulate universal gates using
Verilog
4. To develop and simulate XOR and XNOR using
Verilog
5. To develop and simulate Half adder using Verilog

6. To develop and simulate full adder using half adder

in Verilog
7. To develop and simulate four-bit adder using
Verilog
8. To develop and simulate 4 x1 multiplexer using
Verilog
9. To develop and simulate 1 x 4 de-mux using Verilog

10. To develop and simulate 3: 8 decoder using

Verilog
11. To develop and simulate 8: 3 encoder using Verilog

12. To develop and simulate Parity generator and

checker using Verilog
13. To develop and simulate flip-flops (SR, D, T, JK)
using Verilog
14. To develop and simulate 4-bit Up counter using
Verilog using Verilog
15. To develop and simulate 4-bit shift register using
Verilog
16. Verify digital circuits by implementing testbench
for it in Verilog
17. Hardware implementation of Digital circuits

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VLSI (4361102)

Date: ……………
Practical No.1: To develop a Verilog code to understand module definition and coding styles

A. Objective: Student will be able to install the required software and write Verilog
code with understanding of coding styles.
B. Expected Program Outcomes (POs) PO1, PO4

C. Expected Skills to be developed based on competency:

• Installing and configuring software as per the requirements.

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes (COs): CO 5
E. Practical Outcome (PRO): Install and Identify Verilog modules and coding styles
F. Expected Affective domain Outcome (ADOs)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Prerequisite Theory:
Hardware description languages such as Verilog, differ from software programming
languages because they include ways of describing the propagation of time and signal
dependencies(sensitivity). Since these concepts are part of Verilog language semantics,
designers could quickly write descriptions of large circuits, in a relatively compact and
concise form.
A Verilog is a case sensitive, has a basic preprocessor and equivalent control flow keywords
(ifelse, while, for, case etc) and compatible operator precedence.
A Verilog design consist of a hierarchy of modules. Modules encapsulate design hierarchy,
and communicate with other modules through a set of declared input, output and in out
ports.
Internally a module can contain any combination of the following-Net/variable declaration
such as wire, register, integer etc, concurrent and sequential statement blocks and
instances of other modules (sub-hierarchies). Sequential statements are placed inside a
begin/end block and executed in sequential order within the block. But the block
themselves are executed concurrently, qualifying Verilog as a dataflow language.

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A Verilog code can be written in the following styles:

• Dataflow style
• Behavioural style
• Structural style
• Mixed style
In data flow style of modelling, logic blocks are realized by writing their Boolean expressions
or logical equations. The specification is comprised of expressions made up of input signals
and assigned to outputs. Looking towards this design, one can realize how data flows
between hardware registers and how the data is processed in the design.
In the behavioural style of modelling instead of writing Boolean expressions, the behaviour
of the logic block is described. This is the highest level of abstraction provided by Verilog
HDL. Here module is designed without concern of the hardware implementation details. It
specifies the circuit in terms of its expected behaviour.
The structural style/ Gate level is a hierarchical design style in which a logic block is realized
in terms of its basic sub-blocks and its interconnections. A sub-block can be a logic gate or
any complex logic block. It resembles a schematic drawing with components connected
with signals.
In mixed style, one can mix up the design styles in their program.
Verilog supports switch level implementation. Here switch is a transistor. Transistor level
design can also be performed using Verilog.
H. Experimental set up:

User Guide for Quartus II Evaluation version:

1. Start the Quartus II software.
2. Select File > New Project Wizard, which asks for the name and directory of the project.
3. The project must have a name, which is usually the same as the top-level design entity
that will be included in the project.
4. Specify the type of device in which the designed circuit will be implemented.
5. Click Next and verify the project summary.
6. Click finish to complete the project creation.
7. Select File > New and choose Verilog HDL File, and click OK.
8. Write the Verilog code in the desired style and specify a name for the file that will be
created
9. Add file to current project, by choosing Project > Add/Remove Files in Project.

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10. Run the Compiler by selecting Processing > Start Compilation, or by clicking on the
toolbar icon that looks like a purple triangle.
Simulate the design by following below mentioned steps:
1. Open the Waveform Editor window by selecting File > New, choose Vector Waveform File
and click OK.
2. Save the file with ‘. vwf’ extension.
3. Click Edit > Insert > Insert Node or Bus to include the input and output nodes of the circuit
to be simulated. Click on button labelled Node Finder, set the filter to Pins: all and then click
on list button
4. Click on the required signal in nodes found and add them for simulation using > sign.
5. To assign signal values click on the waveform name and then by using the Edit > Value
command, or via the toolbar for the Waveform Editor set the desired signal for all the
required inputs.
6. To perform the functional simulation, select Assignments > Settings to open the Settings
window. On the left side of this window click on Simulator Settings and choose Functional
as the simulation mode, and click OK
7. Before running the functional simulation, it is necessary to create the required netlist, which
is done by selecting Processing > Generate Functional Simulation Netlist.
8. A simulation run is started by Processing > Start Simulation, or by using the icon .
User Guide for ISE design suit:
1. Open ISE Design Suite 14.5.
2. Click on File > NewProject
3. Give a name to the project and click on [Next]. Select the device on which the design is to
be implemented.
4. Right click in “Hierarchy” > New source > select Verilog module and give name of the module
and click next.
5. Give input and output parameters and click next and finish.
6. Write and save Verilog code as per the design style.
7. In the process pane expand ‘Synthesize – XST’. Run ‘Check Syntax’ to check the syntax of the
written Verilog code.
8. Goto ‘Simulation’ in view pane. Then right click again in ‘Hierarchy’ and select ‘New Source.
9. Set the values for inputs as clock or 0 or 1 or as per the need.
10. Run the ‘Behavioural Check Syntax’ and ‘Simulate Behavioural Model’ and verify the design
behaviour.
I. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity

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VLSI (4361102)

/Components/Trainer kit

1. Software: Quartus / Xilinx /EDA

Computer System playground
Processor:
RAM:
Operating System:

J. Sample Codes for different coding styles:

• Dataflow style
module notgate(a, abar);
input a;
output abar;
assign abar = ~a;
endmodule
• Behavioural style
module notgate(a, abar);
input a;
output reg abar;
always @(a)
begin
if (a == 1'b0)
abar = 1'b1;
else
abar = 1'b0;
end
endmodule
• Structural style/Gate level modelling
module notgate(input a, output abar);
not (abar, a);
endmodule

Follow the procedure and simulate NOT gate using all three modelling styles.

K. Interpretation of Results.
RTL view and simulation result:

a abar

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L. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
M. Practical related Quiz.
1. Identify the modelling styles in the codes given below:
a) module halfadder_gate (s,c,a,b);
input a,b;
output s,c;

xor(s,a,b);
and(c,a,b);

endmodule
Style: ____________________________
b) module t_ff_beh(T,CLK,RST,Q,Qbar);
output Q,Qbar;
input T,CLK,RST;
reg Q;
always @(posedge CLK)

begin // positive-edge triggered

if (!RST) // synchronous reset, active low
Q <= 1'b0;
else
Q <= T^Q;
//Q <= (~T&Q)|(T&~Q); // characteristic equation
end
assign Qbar = ~ Q ;
endmodule
Style: ___________________________

c) module comparator(
input [3:0] A, B,
output reg A_grt_B, A_less_B, A_eq_B);

always@(*) begin

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A_grt_B = 0; A_less_B = 0; A_eq_B = 0;

if(A>B) A_grt_B = 1'b1;
else if(A<B) A_less_B = 1'b1;
else A_eq_B = 1'b1;
end
endmodule
Style: _________________________
d) module half_adder(input a, b, output s, Cout);
assign S = a ^ b;
assign Cout = a & b;
endmodule
Style:_ _________________________
N. References:
1. https://www.intel.com/content/www/us/en/software-kit/666221/intel-
quartus-ii-web-edition-design-software-version-13-1-for-windows.html
2. https://www.xilinx.com/support/download/index.html/content/xilinx/en/d
ownloadNav/vivado-design-tools/archive-ise.html
O. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1
Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.

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All the test cases Reasonable test Test case design

Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

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Date: ……………
Practical No.2: To develop and Simulate the Basic logic gates using Verilog

A. Objective: Student will be able to write Verilog code and test its functionality by
simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate the basic logic gates using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Prerequisite Theory:
Verilog syntax:
Comments: For single line use // or use /* at starting of multiple lines and */ after last line.
Number Format: Decimal, hexadecimal, octal and binary number formats are supported.

For sized numbers:

width 'radix value // width is number of bits, radix is either b/o/d/h (b
for binary, o for octal, d for decimal and h for hexadecimal) and value is the value to be
assigned.
1’b0 //1 bit binary with value 0
16’h3F09 // 16 bit hexadecimal with value 3F09
Strings: Sequence of characters enclosed in “ ” is called as a string.

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Identifiers: It is the name of the variable, that can have any characters from a-z / A-Z with numbers
0-9 and may also have $ or _ . The identifiers are case sensitive.

Nets: It is used to connect hardware entities. To make such connections wire keyword is used.
wire a; // single bit wire
wire [3:0] a; // 4-bit wire

variables: They are used for data storage. For this reg keyword is used.

Data types: integer is used to store a 32-bit wide general-purpose variable. time is 64-bit
wide data type used to store the time quantities. real is used to store floating point values.

Module: Modules are basic building blocks that implements a certain functionality. It
represents a design unit that implements certain behavioural characteristic and will be
converted to a digital circuit on synthesis.
A Module in Verilog is declared within the pair of keywords module and endmodule.
Following the keyword module are the module name and port interface list.
Syntax:

Example:
module my_module ( a, b, c, d );
input a, b;
output c, d;
...
endmodule

assign: wire or similar data type variables requires continuous assignment of value. This is
done by keyword assign. Here changes in RHS (right hand side) expression is assigned to
LHS (left hand side) net.

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Operators:

OPERATOR TYPE OPERATOR SYMBOLS OPERATION PERFORMED

~ 1’compliment
& Bitwise AND
Bitwise | Bitwise OR
^ Bitwise XOR
~^ or ^~ Bitwise XNOR
! NOT
Logical && AND
|| OR
& Reduction AND
~& Reduction NAND
| Reduction OR
Reduction
~| Reduction NOR
^ Reduction XOR
~^ or ^~ Reduction XNOR
+ Addition
- Subtraction
- 2’s compliment
Arithmetic
* Multiplication
/ Division
** Exponent
> Greater than
< Lesser than
>= Greater than or equal to
<= Lesser than or equal to
Relational
== Logical equality
!= Logical inequality
=== 4-state logical equality
!== 4-state logical inequality
>> Logical right shift
<< Logical left shift
Shift
>>> Arithmetic right shift
<<< Arithmetic left shift
Concatenation {,} Concatenation
Replication {n{m}} Replicate value m for n times
Conditional ?: Conditional

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H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground

I. Write Verilog code to implement basic logic gates

1. Sample code for AND gate in dataflow modelling style:

2. Sample code for AND gate in structural modelling style:

3. Follow the procedure and simulate OR gate using data flow style. Write here
the implemented Verilog code

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4. Follow the procedure and simulate OR gate using structural modelling style.
Write here the implemented Verilog code

J. Interpretation of Results.
RTL view and simulation result for AND gate:

RTL for Dataflow style RTL for Gate level style

K. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
L. Practical related Quiz.

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1. ___________ indicates hardware component in Verilog.

a) Variable
b) module
c) function
2. _______ operator is used for concatenation in Verilog.
a) concat
b) {}
c) []
d) |
3. How is a multi-bit signal represented in Verilog?
a) Array of bits
b) Separate multiple single bit signal
c) String of characters
4. RTL stands for
a) Resistor Transistor Logic
b) Register Transfer Level
c) Register Transistor Level
d) Real Time Language

M. References:
1. https://www.chipverify.com/verilog/verilog-ports
2. https://vlsiverify.com/verilog/module-and-ports/

N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1
Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is
Code is
marginally minimally
Program completely
Code is functional with functional with
Completeness/ functional with
completely multiple errors significant
Correctness minor
functional and/or portion of the
implementation
incomplete code missing or
issues
code sections. incomplete

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Code is extremely Code is Code is Code is poorly

well organized,reasonably easy readable with organized with
properly to follow with significant little to no
Readability formatted and logically efforts. consistency in
easy to follow. grouped codes. Significant formatting and
Related code Minor problems with logical grouping.
sections areformatting code
logically grouped. problems. organization.
Reasonable test Test case design
All the test cases
cases are Testing of the is erroneous or
Design testing are covered with
covered with code with very inconsistent with
proper simulation
issues in very few test cases. the code.
results
few test cases
Code is Code unable to
Code is mostly marginally achieve the
Code is efficient efficient with a efficient with result with an
without scope to improve significant irrelevant
Efficiency sacrificing by selection of scope to patched coding
readability and different improve by
understanding constructs or changing
modelling coding styles
and constructs.
Code is well Code is well Significant Major portion of
documented with documented portions of the the code is not
related comments with minor code are documented or is
Documentation/ and design details. formatting undocumented with
Presentation No issues. Minimal or poorly wrong/irrelevant
typos/grammatical typing mistakes documented comments.
errors and grammatical
errors
Total marks

Sign with Date

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VLSI (4361102)

Date: ……………
Practical No.3: To develop and simulate universal gates using Verilog

A. Objective: Student will be able to write Verilog code for universal gates and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate the universal gates using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Prerequisite Theory:
Ports:
An interface to communicate with other modules or a testbench environment is
called a port. The input/ output pins of digital design are known as ports. Ports are
like pins that are used by the design to send and receive signals from outside world.
This interface is termed as a port interface or port list. Since the port list is available
for connection, internal design implementation can be hidden from other modules
or an environment.

Verilog keywords used for port declaration are as follows:

Port Type Keywords used Description
Input port input To receive signal values from another module
Output port output To send signal values to another module
Bidirectional inout To send or receive signal values to another module.
port

H. Resources/Equipment Required
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Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
I. Write Verilog code to implement universal logic gates
1. Sample code for NAND gate in dataflow modelling style:

2. Sample code for AND gate in structural modelling style:

3. Follow the procedure and simulate NOR gate using data flow style. Write here
the implemented Verilog code

4. Follow the procedure and simulate NOR gate using De-Morgan’s theorem.
Write here the implemented Verilog code
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J. Interpretation of Results.
RTL view and simulation result for NAND gate:

RTL for Dataflow style RTL for NAND (De-Morgan)

K. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

L. Practical related Quiz.

1. For Boolean equation 𝒚 = %
𝑨𝑩 + 𝑩𝑨 write the Verilog statement

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_______________________________________________________________
2. For Boolean equation Y= 𝑨% 𝑩 + 𝑩𝑪 + 𝑨𝑪 write the Verilog statement
_______________________________________________________________
3. Which Verilog style uses Boolean equation to model combinational logic?

_______________________________________________________________
M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1
Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant portion
Completeness/ Code is completely functional with
multiple errors of the code
Correctness functional minor
and/or missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is readable Code is poorly
Code is reasonably
well organized, with significant organized with
easy to follow with
properly formatted efforts. little to no
Readability logically grouped
and easy to follow. Significant consistency in
codes. Minor
Related code problems with formatting and
formatting
sections are code logical grouping.
problems.
logically grouped. organization.
Reasonable test Test case design is
All the test cases are Testing of the
Design testing cases are covered erroneous or
covered with proper code with very
with issues in very inconsistent with
simulation results few test cases.
few test cases the code.
Code is mostly Code unable to
Code is
efficient with a achieve the result
Code is efficient marginally
scope to improve with an irrelevant
Efficiency without sacrificing efficient with
by selection of patched coding
readability and significant scope
different
understanding to improve by
constructs or
changing coding
modelling

25
VLSI (4361102)

styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

26
VLSI (4361102)

Date: ……………
Practical No.4: To develop and simulate XOR and XNOR using Verilog

A. Objective: Student will be able to write Verilog code for XOR and XNOR gates and
test its functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate XOR and XNOR using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Prerequisite Theory:
Concatenation: Multi bit Verilog wires and variable can be joined together to form
multi bit input using { } operator. It can include expressions and sized constants as
input.
Example:

H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit

27
VLSI (4361102)

1. Software: Quartus / Xilinx /EDA

Computer System playground
Processor:
RAM:
Operating System:

I. Write Verilog code to implement XOR and XNOR logic gates

1. Sample code for XOR gate in dataflow modelling style:

2. Follow the procedure and simulate XOR gate using its Boolean equation in
data flow style. Write here the implemented Verilog code

3. Follow the procedure and simulate XNOR gate using its Boolean equation in
data flow style. Write here the implemented Verilog code

28
VLSI (4361102)

J. Interpretation of Results.
RTL view and simulation result for XOR gate:

K. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
L. Practical related Quiz.
1. What does Transfer in RTL refer to?
_______________________________________________________________
2. What is the purpose of RTL synthesis?
_______________________________________________________________
3. Write the operator for XOR
_______________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1
Max 25 marks

29
VLSI (4361102)

Assessment Excellent Very Good Good Fair Marks

criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is
Code is
marginally minimally
Program completely
Code is functional with functional with
Completeness/ functional with
completely multiple errors significant
Correctness minor
functional and/or portion of the
implementation
incomplete code missing or
issues
code sections. incomplete
Code is extremely Code is Code is Code is poorly
well organized, reasonably easy readable with organized with
properly to follow with significant little to no
Readability formatted and logically efforts. consistency in
easy to follow. grouped codes. Significant formatting and
Related code Minor problems with logical grouping.
sections are formatting code
logically grouped. problems. organization.
Reasonable test Test case design
All the test cases
cases are Testing of the is erroneous or
Design testing are covered with
covered with code with very inconsistent with
proper simulation
issues in very few test cases. the code.
results
few test cases
Code is Code unable to
Code is mostly marginally achieve the
Code is efficient efficient with a efficient with result with an
without scope to improve significant irrelevant
Efficiency sacrificing by selection of scope to patched coding
readability and different improve by
understanding constructs or changing
modelling coding styles
and constructs.
Code is well Code is well Significant Major portion of
documented with documented portions of the the code is not
related comments with minor code are documented or is
Documentation/ and design details. formatting undocumented with
Presentation No issues. Minimal or poorly wrong/irrelevant
typos/grammatical typing mistakes documented comments.
errors and grammatical
errors
Total marks

Sign with Date

30
VLSI (4361102)

Date: ……………
Practical No.5: To develop and simulate Half adder using Verilog

A. Objective: Student will be able to write Verilog code for half adder and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate Half adder using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Prerequisite Theory:
Module instantiation:
While designing complex digital circuits, usually it is split into various modules that
connect to have a top-level block. Thus, Verilog supports a hierarchical design
methodology. When a module is instantiated, a unique object is created and it has
a unique name. Similarly, a top-level design can also be instantiated while creating
a testbench. This module instantiation can be done in 2 ways:

1. Port connection by ordered list: connecting the signals of higher module to the
lower module is done in the order followed while declaring the lower module.
Example:
module mux_2_1(input sel, input i0, i1, output y); //
declaration of module while designing.
mux_2_1 mux(select, in0, in1, out); // At module
instantiation in top level
Here select signal of top level will be connected to the sel, in0 to input i0, in1 to
i1 and out to y.

31
VLSI (4361102)

2. Port connection by names: In this method, the order of port list connection does
not matter based on the port name, the connection is established.
Example:
module mux_2_1(input sel, input i0, i1, output y); // At design
mux_2_1 mux(.i0(in0), .sel(select), .y(out), .i1(in1)); // At testbench
Here . dot indicates the port of the instantiated design and ports/ signal within
the () indicates the higher module to which instantiated ports are to be
connected.
In the example select of the higher module is connected to sel of instantiated
module and so on.
H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:
I. Write Verilog code to implement Half adder using Verilog
1. Write the code for half adder in dataflow modelling style

32
VLSI (4361102)

2. Follow the procedure and simulate half adder using gate level design style.
Draw here the RTL for the implemented Verilog code

module halfadder( input a,

input b,

output sum,

output carry);

and u1(carry,a,b);

xor u2(sum,a,b);

endmodule

J. Interpretation of Results.

Complete the truth table based on the observed simulation results

A B Sum carry
0 0
0 1
1 0
1 1

K. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
L. Practical related Quiz.
1. What is the disadvantage of ordered listing in module instantiation?
_______________________________________________________________
_______________________________________________________________
2. Unconnected Ports in module instantiation will have a value of _______.

33
VLSI (4361102)

A. 0 B. 1 C. Z (high impedance)
3. Which one of the following is not a valid datatype of Verilog?
A. Integer B. wire C. float D. reg

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
A. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
Documentation/
documented with documented with portions of the the code is not
Presentation related comments minor formatting code are documented or is
and design details. issues. Minimal undocumented

34
VLSI (4361102)

No typing mistakes or poorly with

typos/grammatical and grammatical documented wrong/irrelevant
errors errors comments.

Total marks

Sign with Date

35
VLSI (4361102)

Date: ……………
Practical No.6: To develop and simulate full adder using half adder in Verilog

A. Objective: Student will be able to write Verilog code for full adder and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate Full adder using Half adder in Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Write Verilog code to implement Full adder using half adder in

Verilog
1. Write the code for full adder in structural modelling style (module instantiation)

36
VLSI (4361102)

Sample Code

Write your code here:

37
VLSI (4361102)

2. Follow the procedure and simulate full adder using structural level design
style and port connection by names for all the instantiation. Draw here the
RTL for the implemented Verilog code. (Sample is done for one module)

Sample Code

Write your code here:

38
VLSI (4361102)

I. Interpretation of Results.
Write the hierarchy list as seen in the RTL viewer for the implemented designs.

J. Conclusion:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
K. Practical related Quiz.
1. Define Hierarchy
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________
2. Define Modularity
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________
L. References:

39
VLSI (4361102)

https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
B. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for this course. There
are four categories under which your programs will be graded including functionality, readability,
documentation, Design testing. Each category will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion 5 or 4 marks 3 or 2 marks 1 or 0 mark
Code is Code is
Code is
marginally minimally
Program completely
functional with functional with
Completeness/ Code is completely functional with
multiple errors significant
functional minor
Correctness and/or portion of the
implementation
incomplete code code missing or
issues
sections. incomplete
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy with significant organized with
properly formatted to follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code sections codes. Minor problems with formatting and
are logically formatting code logical
grouped. problems. organization. grouping.
Reasonable test Test case design
All the test cases are cases are covered Testing of the is erroneous or
Design testing covered with proper with issues in code with very inconsistent
simulation results very few test few test cases. with the code.
cases
Code is Code unable to
Code is mostly
marginally achieve the
efficient with a
Code is efficient efficient with result with an
scope to improve
without sacrificing significant scope irrelevant
Efficiency by selection of
readability and to improve by patched coding
different
understanding changing coding
constructs or
styles and
modelling
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or
and design details. issues. Minimal undocumented is with
Presentation
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

40
VLSI (4361102)

Date: ……………
Practical No.7: To develop and simulate four-bit adder using Verilog

A. Objective: Student will be able to write Verilog code for four-bit adder and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate four-bit adder using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Pre-requisite Theory:
Scalar and Vector:
A net or a reg declaration without a range specification is called scalar
A net or a reg declaration with a range specified is called vector. Vector is a
multibit. LSB is specified at right while MSB at left in the range.

Bit selection:
Any bit from a vector can be assigned or addressed by using its index.
And a part of the range can also be addressed by giving start and stop range.

41
VLSI (4361102)

H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

I. Write Verilog code to implement four-bit adder using Verilog ( sample is given
try to implement without cout i.e. sum with 5 bits)

Write your code here:

42
VLSI (4361102)

2. Follow the procedure and simulate 4-bit adder using structural level design
style. Draw here the RTL for the implemented Verilog code.

Sample Code

Write your code here:

J. Interpretation of Results.

43
VLSI (4361102)

Write the hierarchy list as seen in the RTL viewer for the implemented designs.

Draw RTL of four-bit adder using data flow model

44
VLSI (4361102)

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
L. Practical related Quiz.
a. What should be changed in the adder circuit to make it a subtractor?
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks

45
VLSI (4361102)

Assessment Excellent Very Good Good Fair Marks

criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

46
VLSI (4361102)

Date: ……………
Practical No.8: To develop and Simulate 4 x1 multiplexer using Verilog
A. Objective: Student will be able to write Verilog code for 4x1 multiplexer and test
its functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate 4 x1 multiplexer using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Pre-requisite Theory:
Assignment:
In Verilog assignment can be done by 3 ways :
1. always @ (condition) : here Verilog statements are executed only when the
conditions are satisfied . Similar to the initial block, the always block is executed
sequentially. The sensitivity list or condition can be a single or multiple signals
placed within parentheses () after @ operator. Based on the change in any signal
value, it allows executing the always block.
e.g. always @(i1 or i2 or i3) begin
<statements>
End
Based on the change in signal value in anyone of the i1, i2, or i3 signals, the
always block will be executed.
2. initial: It will be executed only once when simulation begins.
3. assign [LHS] = [RHS] : here values on LHS will be updated on change of the
values in RHS.
Blocking & non-blocking:

47
VLSI (4361102)

Blocking assignments are done by “=”. The blocking assignment statements are
executed sequentially by evaluating the RHS operand and finishes the assignment to
LHS operand without any interruption from another Verilog statement. Hence, it
blocks other assignments until the current assignment completes and is named as
“blocking assignment”. A blocking assignment does not block the execution of a
statement in another procedural block. Race- around condition may occur.
Non-blocking assignment are done by “<=”. The non-blocking assignment statement
starts its execution by evaluating the RHS operand at the beginning of a time slot and
schedules its update to the LHS operand at the end of a time slot. Other Verilog
statements can be executed between the evaluation of the RHS operand and the
update of the LHS operand. As it does not block other Verilog statement
assignments, it is called a non-blocking assignment. Here no race-around condition
occurs, as RHS is evaluated at the start of the time slot but update on LHS is reflected
at the end of the slot, allowing other blocks to work in parallel.
• Use non-blocking assignments for modeling flip flops, latches, and sequential
logic.
• Use blocking assignment to implement combinational logic in always block.
• Use non-blocking assignment to implement sequential logic in always block.
• Do not mix blocking and non-blocking assignments in single always block i.e. For
the implementation of sequential and combination logic in a single ‘always’
block, use non-blocking assignments.
• Do not assign value to the same variable in the different procedural blocks.
• Use non-blocking assignments while modeling both combination and
sequential logic within the same always block.
• Avoid using #0 delay in the assignments.
Case:
The case statement has a given expression and it is checked if this expression
matched with the items in the list and branches accordingly and respective
statements are executed. If it does not match with any of the written expressions
of the list then, the default statement will be executed.
If the ‘default’ statement is not given and the given expression is not matched with
any expression in the list, then the case statement evaluation will exit.
Verilog case statement uses case, endcase, and default keywords.

48
VLSI (4361102)

Syntax:

Example:

H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:
I. Write Verilog code to implement 4x1 MUX using always and case
Sample code using dataflow:

module muxAssign(input i0,i1,i2,i3,s0,s1,output y);

wire s0bar,s1bar;
assign s0bar = ~s0;
assign s1bar = ~s1;
assign y = (s0bar & s1bar & i0) | (s0 & s1bar & i1) | (s0bar & s1 & i2) |(s0 & s1 & i3);
Endmodule

49
VLSI (4361102)

Sample code using case:

module muxCase(input i0,i1,i2,i3,input [1:0] sel,output reg y);

always @(sel or i0 or i1 or i2 or i3) begin
case (sel)
2'b00 : y = i0;
2'b01 : y = i1;
2'b10 : y = i2;
2'b11 : y = i3;
default: y = 1'bx;
endcase
end
endmodule

Write your code here for 2x1 mux using case and data flow:

50
VLSI (4361102)

J. Interpretation of Results.
RTL schematics:

Simulation Results

Draw RTL for 2x1 mux:

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________

51
VLSI (4361102)

L. Practical related Quiz.

a. What should be given as input to I0, I1 and selection line of 2x1 Mux to get
AND gate with A and B as input?
a. I0 to ‘0’, I1 to A, selection to B
b. I0 to ‘1’, I1 to 0, selection to B
c. I0 to ‘0’, I1 to B, selection to 0
b. What should be given as input to I0, I1 and selection line of 2x1 Mux to get OR
gate with A and B as input?
a. I0 to ‘0’, I1 to A, selection to B
b. I0 to ‘A’, I1 to 1, selection to B
c. I0 to ‘1’, I1 to A, selection to B
c. What should be given as input to I0, I1 and selection line of 2x1 Mux to get
XOR gate with A and B as input?
a. I0 to ‘A’, I1 to 𝐴̅, selection to B
b. I0 to 𝐴̅, I1 to A , selection to B
c. I0 to ‘0’, I1 to A, selection to B
M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion 5 or 4 marks 3 or 2 marks 1 or 0 mark
Code is Code is minimally
Code is
marginally functional with
Program completely
functional with significant
Code is completely functional with
Completeness/ multiple errors portion of the
functional minor
Correctness and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.

52
VLSI (4361102)

All the test cases Reasonable test Test case design

Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
without sacrificing
Efficiency by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
and design details. issues. Minimal undocumented with
Presentation
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

53
VLSI (4361102)

Date: ……………
Practical No.9: To develop and Simulate 1 x 4 de-mux using Verilog
A. Objective: Student will be able to write Verilog code for 1x4 de-multiplexer and
test its functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO3, CO5
E. Practical Outcome(PRo): Simulate 1 x 4 de-mux using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Pre-requisite Theory:
Conditional Statements:
The ‘If’ statement is a conditional statement based on which decision is made
whether to execute lines inside if block or not.
The begin and end are required in case of multiple lines present in ‘if’ block. For
single-line inside if statement may not require ‘begin..end’
The ‘if’ statement returns true if the expression calculates its value as 1 otherwise,
for 0, x, z values ‘if’ block will not be executed.
In case, ‘if’ statement does not hold true, ‘else if’ or ‘else’ will be executed. For any
condition hold true in ‘else if’ statement, subsequent ‘else if’ or ‘else’ statement will
not be checked.

54
VLSI (4361102)

Syntax:

H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:
I. Write Verilog code for 1 x 4 de-mux and simulate

55
VLSI (4361102)

Sample code using case:

module demuxif(input sig, input [1:0] sel, output reg y0,y1,y2,y3);

always @ (*)
begin
case (sel)
2'b00: {y0,y1,y2,y3} = {sig, 3'b000};
2'b01: {y0,y1,y2,y3} = {1'b0,sig, 2'b00};
2'b10: {y0,y1,y2,y3} = {2'b00,sig,1'b0};
2'b11: {y0,y1,y2,y3} = {3'b000,sig};
default: {y0,y1,y2,y3}= 4'bzzzz;
endcase
end
endmodule

Write code for 1x4 de-mux using if else

56
VLSI (4361102)

J. Interpretation of Results.
RTL schematics using Case

RTL schematics using if-else

Simulation Results

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________

57
VLSI (4361102)

L. Practical related Quiz.

a. What would be the value of selection line in 1x8 De-Mux if I6 is getting the
signal?
a. 001
b. 100
c. 110
b. If output Y = {3’b0, sig, 1’b0} what would be the value of selection line?
a. 5’b00010
b. 4’b0010
c. 5’b00001
M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is mostly Code is Code unable to
Efficiency Code is efficient
efficient with a marginally achieve the result
without sacrificing
scope to improve efficient with

58
VLSI (4361102)

readability and by selection of significant with an irrelevant

understanding different scope to patched coding
constructs or improve by
modelling changing coding
styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

59
VLSI (4361102)

Date: ……………
Practical No.10: To develop and Simulate 3 : 8 decoder using Verilog
A. Objective: Student will be able to write Verilog code for 3 : 8 decoder and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate 3 : 8 decoder using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Pre-requisite Theory:
Conditional operator:
This operator allows user to assign values to variables based on the condition. If the
condition is true then expression 1 is evaluated else expression 2 is evaluated.

Nesting of conditional operator can be done sacrificing the readability of the code.
Example:

Here out will have value of y if a <b and x%2 is true, out will have value as z if a<b
and x%2 is false and finally out will have value as 0 if a >b.
H. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit

60
VLSI (4361102)

1. Software: Quartus / Xilinx /EDA

Computer System playground
Processor:
RAM:
Operating System:
I. Write Verilog code to simulate 3 : 8 decoder
Sample code using conditional operator for 2:4 decoder:

module dccoder12( input [1:0]D,

output [3:0] y);

assign y[0] = (D == 2'b00)? 1 : 0;

assign y[1] = (D == 2'b01)? 1 : 0;
assign y[2] = (D == 2'b10)? 1 : 0;
assign y[3] = (D == 2'b11)? 1 : 0;
endmodule
Sample code using case:

module decoder( input [2:0] D,

output reg [7:0] y);

always@(D) begin
y <= 0;
case(D)
1'h000: y[0] <= 1'b1;
3'b001: y[1] <= 1'b1;
3'b010: y[2] <= 1'b1;
3'b011: y[3] <= 1'b1;
3'b100: y[4] <= 1'b1;
3'b101: y[5] <= 1'b1;
3'b110: y[6] <= 1'b1;
3'b111: y[7] <= 1'b1;
default: y <= 0;
endcase
end
endmodule

61
VLSI (4361102)

Write Verilog code using conditional operator to implment 3:8 decoder

J. Interpretation of Results.
RTL schematics using Case

62
VLSI (4361102)

RTL schematics using conditional operator

Simulation Results

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
L. Practical related Quiz.
a. What is the difference between decoder and de-multiplexer?

___________________________________________________________________
________________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/

63
VLSI (4361102)

N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

64
VLSI (4361102)

Date: ……………
Practical No.11: To develop and Simulate 8 : 3 encoder using Verilog
A. Objective: Student will be able to write Verilog code for 8 : 3 encoder and test its
functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate 8 : 3 encoder using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Verilog Testbench:
It is a simulation enviornment used to verify the functionality of the design written in
Verilog HDL. Testbench must include all the test cases. Test bench module is defined on top
of the module to be tested. This module do not have any input or output. But the inputs of
the design to be tested are added as a reg and output of the design to be tested as wire.
Similar to the gate level design the module to be tested is instantiated in testbench module.

Steps involved in writing a Verilog testbench:

1. Declare a testbench as a module.

65
VLSI (4361102)

2. Declare set signals that have to be driven to the DUT. The signals which are connected to the
input of the design can be termed as ‘driving signals’ whereas the signals which are
connected to the output of the design can be termed as ‘monitoring signals’. The driving
signal should be of reg type because it can hold a value and it is mainly assigned in a
procedural block (initial and always blocks). The monitoring signals should be of net (wire)
type that get value driven by the DUT.

3. Instantiate top-level design and connect DUT port interface with testbench variables or
signals.

4. Use an initial block to set variable values and it can be changed after some delay based on
the requirement. The initial block execution starts at the beginning of the simulation and
updated values will be propagated to an input port of the DUT.

5. An always block can also be used to perform certain actions throughout the simulation.

6. The endmodule keyword is used to complete the testbench structure.

Steps to simulate in Model sim- Altera:

1. Create a new Quartus Project & configure it for Altera-Modelsim. To configure Quartus to
use Altera-Modelsim as the simulator, first create a new project (or open an existing one)
and go to Assignments > Settings > EDA Tool Settings > Simulation. Make sure “Modelsim-
Altera”
2. Next go to Tools > Options > General > EDA Tools sure that the path next to ModelsimAltera
is configured correctly. If Quartus II with Altera-Modelsim is installed then the path should
be similar to the one shown in the figure below (i.e. on Windows:“C:\altera\13.0sp1\mode-
sim_ase\win32aloem”), otherwise browse to the installed Altera Modelsim and point it to
the win32aloem directory.
3. Create Unit Under Test & Testbench: Next write the Verilog code that is to be tested. Next
write the testbench for DUT.
4. Open altera-modelsim go to Tools > Simulation Tool > RTL Simulation.
5. To compile your Testbench go to Compile > Compile.. and select the file that contains
Verilog code that is to be tested and its testbench.
6. Once the file is selected click Compile, then after it has finished compiling, click Done.
7. To run the simulation right click on the testbench module that is to be simulated , or
simply double click on it.
8. Add the waves by selecting the signals to be simulated, and right click > add wave (or simply
use the hot key CTRL + W). This can also be done by selecting the signals you want and
clicking the icon of a green circle with a + in it at the top.
66
VLSI (4361102)

9. To run the simulation, click the click the icon that looks like a white page with a
down-arrow directly to the right of the box that says 100 ps

I. Write Verilog code to simulate 8 : 3 encoder

Sample code using conditional operator for 8 : 3 encoder with a test bench:

67
VLSI (4361102)

Write Verilog code to implement 4:2 encoder using case

J. Interpretation of Results.
RTL schematics using if else

68
VLSI (4361102)

Draw the RTL schematics for the 4:2 encoder using case

Simulation Results

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
L. Practical related Quiz.
a. What is the concurrent statement?

___________________________________________________________________
________________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
69
VLSI (4361102)

N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

70
VLSI (4361102)

Date: ……………
Practical No.12: To develop and Simulate Parity generator and checker using Verilog
A. Objective: Student will be able to write Verilog code for Parity generator and
checker and test its functionality by simulation.

B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills
• Debugging skills.

D. Expected Course Outcomes(Cos) : CO 3, CO5

E. Practical Outcome(PRo): Simulate Parity generator and checker using Verilog

F. Expected Affective domain Outcome(ADos)

a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Write Verilog code to simulate Parity generator and checker

Sample code for Parity generator and checker:

71
VLSI (4361102)

Write Verilog code to implement Parity generator and checker using data flow

I. Interpretation of Results.
RTL schematics for the Parity generator and checker

72
VLSI (4361102)

Simulation Results

J. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
K. Practical related Quiz.
a. What is the reduction operator?

___________________________________________________________________
________________________________________________________________

L. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
M. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded

73
VLSI (4361102)

including functionality, readability, documentation, Design testing. Each category

will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

74
VLSI (4361102)

Date: ……………
Practical No.13: To develop and Simulate flip-flops (SR , D, T, JK) using Verilog
A. Objective: Student will be able to write Verilog code for flip-flops (SR , D, T, JK)
and test its functionality by simulation.

B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO5
E. Practical Outcome(PRo): Simulate flip-flops (SR , D, T, JK) using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Sequential Circuits:
Flip flop types Sensitivity list
positive edge-triggered always @(posedge clk)
negative edge-triggered always @(negedge clk)
positive edge-triggered and
always @(posedge clk or posedge rst)
asynchronous active high reset
positive edge-triggered and
always @(posedge clk or negedge rst)
asynchronous active low reset

75
VLSI (4361102)

I. Write Verilog code to simulate flip-flops (SR , D, T, JK)

Sample code for flip-flops (SR) :

Write Verilog code to implement flip-flops (D, T, JK)

76
VLSI (4361102)

J. Interpretation of Results.
RTL schematics for the flip-flops (SR)

Simulation Results

K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
L. Practical related Quiz.
What is the difference between edge triggering and level triggering?

___________________________________________________________________
________________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
77
VLSI (4361102)

including functionality, readability, documentation, Design testing. Each category

will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

78
VLSI (4361102)

Date: ……………
Practical No.14: To develop and Simulate 4-bit Up counter using Verilog using Verilog
A. Objective: Student will be able to write Verilog code for 4-bit Up counter and test
its functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO 5
E. Practical Outcome(PRo): Simulate 4-bit Up counter using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Write Verilog code to simulate 4-bit Up counter

Sample code for 4-bit Up counter:

79
VLSI (4361102)

Write Verilog code to implement 4-bit down counter

80
VLSI (4361102)

I. Interpretation of Results.
RTL schematics for the 4-bit Up counter

Simulation Results

J. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
K. Practical related Quiz.
What is MOD-N counter? How many flip-flops would be required in it to count up
to N value?
___________________________________________________________________
________________________________________________________________

L. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
M. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded

81
VLSI (4361102)

including functionality, readability, documentation, Design testing. Each category

will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
properly formatted follow with efforts. little to no
Readability and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with formatting and
sections are formatting code logical grouping.
logically grouped. problems. organization.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

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VLSI (4361102)

Date: ……………
Practical No.15: To develop and Simulate 4-bit shift register using Verilog
A. Objective: Student will be able to write Verilog code for 4-bit shift register and test
its functionality by simulation.
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO 5
E. Practical Outcome(PRo): Simulate 4-bit shift register using Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Write Verilog code to 4-bit shift register

Sample Code

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Write Verilog code for Parallel in Serial Out shift register

I. Interpretation of Results.
RTL schematics for the 4-bit Shift register

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VLSI (4361102)

Simulation Results

J. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
K. Practical related Quiz.
Why non-blocking assignment is used with sequential logic?

___________________________________________________________________
________________________________________________________________

L. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
M. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair
criterion
5 or 4 marks 3 or 2 marks 1 or 0 mark Marks

Code is Code is minimally

Code is
marginally functional with
Program completely
functional with significant
Completeness/ Code is completely functional with
multiple errors portion of the
Correctness functional minor
and/or code missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is Code is readable Code is poorly
well organized, reasonably easy to with significant organized with
Readability properly formatted follow with efforts. little to no
and easy to follow. logically grouped Significant consistency in
Related code codes. Minor problems with

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sections are formatting code formatting and

logically grouped. problems. organization. logical grouping.
All the test cases Reasonable test Test case design
Testing of the
Design testing are covered with cases are covered is erroneous or
code with very
proper simulation with issues in very inconsistent with
few test cases.
results few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
efficient with a efficient with with an irrelevant
Code is efficient
scope to improve significant patched coding
Efficiency without sacrificing
by selection of scope to
readability and
different improve by
understanding
constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
Presentation and design details. issues. Minimal undocumented with
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

86
VLSI (4361102)

Date: ……………
Practical No.16: Verify digital circuits by implementing testbench for it in Verilog
A. Objective: Student will be able to verify digital circuits by implementing testbench
for it in Verilog
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO3, CO 5
E. Practical Outcome(PRo): Verify digital circuits by implementing testbench for it
in Verilog
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Timing control: In simulation timing control plays a crucial role. The timing control
is used to advance simulation time and it has two methods:
1. Delay timing control
2. Event timing control
Delay timing control:
The delay timing control allows to add up a delay between when the statement is
encountered and when it is executed by the simulator. The delay is specified with
the ‘#’ symbol.
There are three types of delay timing control as follows:

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Delay timing control types Declaration

Regular delay control The non-zero delay is specified at the LHS of the
procedural statement.
Intra-assignment delay control Delay is specified between the assignment
operator and the RHS operand.
Zero delay control The zero delay is specified at LHS of procedural
statement

Use Cases:
• Regular delay control, delays the execution of the entire statement by a
specified value.
Examples:
a. #5 data = i_value;
b. #(2:3:6) data = 20;
• Intra-assignment delay control delays computed value assignment by a
specified value. The RHS operand expression is evaluated at the current
simulation time and assigned to LHS operand after a specified delay value.
Example: data = #5 i_value;
• Zero delay control is used to control execution order when multiple
procedural blocks try to update values of the same variable. Both always and
initial blocks execution order is non-deterministic as they start evaluation at
the same simulation time. The statement having zero control delay executes
last, thus it avoids race conditions.
Example:
Without zero delay control, the ‘data’ variable may
have a value of either 2 or 3 due to race conditions.
Having zero delay statement as specified in the above
code guarantees outcome to be 3.

Event timing control: The event timing control method is used to trigger a statement
or procedural block execution due to a change in the value of a net or register. It can
be classified into four types:
Event timing control
Declaration
types
Regular event control An event control is specified using @ symbol
Multiple events are declared using the ‘or’ keyword or comma
Event OR control
‘,’ symbol.
The event declared using
Named event control 1. -> symbol as event triggering
@ symbol as waiting for event trigger.
Level sensitive timing
The ‘wait’ keyword is used in the declaration
control

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Regular event control: The statement or procedural block is executed based on

positive or negative edge transition in a signal value.
posedge – A posedge is used to execute statement/s whenever there is a transition
from 0 or X or Z to 1. e.g. @(posedge clk) q = d;
out = @(posedge clk) (a & b) // a & b will be evaluated
and value is assigned on positive edge of clock.
negedge – A negedge is used to execute statement/s whenever there is a transition
from 1 or X or Z to 0. e.g. @(negedge clk) q = d;
out = @(negedge clk) (a & b) // a & b will be evaluated
and value is assigned on positive edge of clock.

Event OR control: The statement or procedural block is executed based on positive

or negative edge or level transition of more signals by mentioning into the sensitivity
list using the ‘or’ keyword or comma ‘,’.
Examples Description
always @(clk or rst_n) Level sensitive for clk and rst_n signals using or keyword.
always @(posedge clk or Edge sensitive for clk and rst_n signals using or keyword.
negedge rst_n)
always @(clk, rst_n) Level sensitive for clk and rst_n signals using a comma.
always @(posedge clk, Edge sensitive for clk and rst_n signals using a comma.
negedge rst_n)

Level sensitive timing control

Along with the edge-sensitive construct (while waiting for an event trigger), Verilog
adds up the ‘wait’ level-sensitive construct to wait for a specified condition to be
true, and then only one or more statements will be executed. Thus, a set of
statements will be blocked until the ‘wait’ condition is evaluated to be true.
Syntax:
wait(<expression or variable>)
e.g. wait(count == 'd5);

I. Write Verilog code to Verify digital circuits by implementing testbench for it

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module comparator(
input [3:0] A, B,
output reg A_grt_B, A_less_B, A_eq_B);
always@(*) begin
A_grt_B = 0;
A_less_B = 0;
A_eq_B = 0;
if(A>B) A_grt_B = 1'b1;
else if(A<B) A_less_B = 1'b1;
else A_eq_B = 1'b1;
end
endmodule
module tb;
reg [3:0] A, B;
wire A_grt_B, A_less_B, A_eq_B;
reg clk;
comparator comp(A, B, A_grt_B, A_less_B, A_eq_B);
initial
begin
A = 4'b0000; B= 4'b0000;#10;
A = 4'b1110; B= 4'b1110; #10;
A = 4'b1110; B= 4'b1111; #10;
A = 4'b1111; B= 4'b1110; #10;
A = 4'b1011; B= 4'b1010; #10;

A = 4'b00011; B= 4'b1011; #10;

end
endmodule
J. Interpretation of Results.
RTL schematics for the 4-bit Up counter

Simulation Results

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K. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
L. Practical related Quiz.
Write example of level triggered and edge triggered signals.

___________________________________________________________________
________________________________________________________________

M. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
N. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment Excellent Very Good Good Fair Marks
criterion 5 or 4 marks 3 or 2 marks 1 or 0 mark
Code is Code is minimally
Code is
marginally functional with
Program completely
functional with significant portion
Code is completely functional with
Completeness/ multiple errors of the code
functional minor
Correctness and/or missing or
implementation
incomplete code incomplete
issues
sections.
Code is extremely Code is readable Code is poorly
Code is reasonably
well organized, with significant organized with
easy to follow with
properly formatted efforts. little to no
Readability logically grouped
and easy to follow. Significant consistency in
codes. Minor
Related code problems with formatting and
formatting
sections are code logical grouping.
problems.
logically grouped. organization.

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Reasonable test Test case design is

All the test cases are Testing of the
Design testing cases are covered erroneous or
covered with proper code with very
with issues in very inconsistent with
simulation results few test cases.
few test cases the code.
Code is Code unable to
Code is mostly
marginally achieve the result
efficient with a
Code is efficient efficient with with an irrelevant
scope to improve
without sacrificing significant scope patched coding
Efficiency by selection of
readability and to improve by
different
understanding changing coding
constructs or
styles and
modelling
constructs.
Code is well Code is well Significant Major portion of
documented with documented with portions of the the code is not
Documentation/ related comments minor formatting code are documented or is
and design details. issues. Minimal undocumented with
Presentation
No typing mistakes or poorly wrong/irrelevant
typos/grammatical and grammatical documented comments.
errors errors
Total marks

Sign with Date

92
VLSI (4361102)

Date: ……………
Practical No.17: Hardware implementation of Digital Circuits
A. Objective: Student will be able to implement designed circuits on hardware
B. Expected Program Outcomes (POs) PO1, PO2, PO3, PO4, PO7

C. Expected Skills to be developed based on competency:

• Programming skills.
• Debugging skills.
D. Expected Course Outcomes(Cos) : CO 3, CO 4, CO 5
E. Practical Outcome(PRo): Verify digital circuits by Hardware implementation
F. Expected Affective domain Outcome(ADos)
a) Work as a leader/a team member.
b) Follow ethical practices.
c) Follow Coding standards and practices.
d) Follow safety precautions.
G. Resources/Equipment Required
Sr.No. Instrument/Equipment
Specification Quantity
/Components/Trainer kit
1. Software: Quartus / Xilinx /EDA
Computer System playground
Processor:
RAM:
Operating System:

H. Verilog digital circuits (Half adder / full adder) by implementing on hardware

Steps for hardware implementation:

1. Write Verilog code for the design to be tested. Make sure to select the device
available while creating a new project.
2. Compile and verify the design by simulation
3. Set pin assignment for the device selected. It connects the ports of the module
to the hardware pins.

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VLSI (4361102)

a. Pin assignments are made by using the Assignment Editor. Select Assignments
> Assignment Editor to reach the window in Figure

b. Under Category select Pin.

c. Double-click on the entry <<new>> which is highlighted in blue in the column
labelled To. The drop-down menu in Figure will appear.

d. Click on a as the first pin to be assigned; this will enter a in the displayed table.
Follow this by double-clicking on the box to the right of this new a entry, in the
column labelled Location. Now, the drop-down menu as in Figure appears.

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VLSI (4361102)

e. Scroll down and select PIN_AB 1. Instead of scrolling down the menu to find the
desired pin, you can just type the name of the pin (AB 1) in the Location box.
Use the same procedure to assign input b, output carry and sum, which results
in the image in Figure

f. To save the assignments made, choose File > Save. You can also simply close
the Assignment Editor window; in which case a pop-up box will ask if you want
to save the changes to assignments; click Yes. Recompile the circuit, so that it
will be compiled with the correct pin assignments.
4. Programming and Configuring the FPGA Device: Devices can be programmed
using JTAG mode, where JTAG stands for Joint Test Action Group. This group
defined a simple way for testing digital circuits and loading data into them, which
became an IEEE standard. If the FPGA is configured in this manner, it will retain
its configuration as long as the power remains turned on. The configuration
information is lost when the power is turned off. The programming and
configuration task is performed as follows:
a. Select Tools > Programmer to reach the window as shown in figure given below:

b. Select JTAG in the mode box if not selected by default

c. Also, if the USB-Blaster is not chosen by default, press the Hardware Setup...
button and select the USB-Blaster in the window that pops up.
d. Observe that the configuration file light.sof is listed in the window in Figure 38.
If the file is not already listed, then click Add File and select it. This is a binary
file produced by the Compiler’s Assembler module, which contains the data
needed to configure the FPGA device. The extension .sof stands for SRAM
Object File.
e. Click on the Program/Configure check box

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VLSI (4361102)

f. Press Start in the window to load the bit file in the hardware. And now test the
design on the hardware.

I. Interpretation of Results.
Input the results as verified from the hardware:
A B Sum Carry

J. Conclusion:
___________________________________________________________________
___________________________________________________________________
________________________________________________________________
K. Practical related Quiz.
Write full form of:
JTAG: ______________________________________________________________
SOF: _______________________________________________________________

L. References:
https://www.chipverify.com/verilog/verilog-ports
https://vlsiverify.com/verilog/module-and-ports/
M. Assessment-Rubrics
The following rubric will be used in grading all Verilog source code submitted for
this course. There are four categories under which your programs will be graded
including functionality, readability, documentation, Design testing. Each category
will be assigned a specific rubric score (1-5).
Excellent = 5-4, Very good = 3, Good = 2, Fair= 1 Max 25 marks
Assessment criterion Excellent Very Good Good Fair Marks
5 or 4 marks 3 or 2 marks 1 or 0 mark
Code is Code is minimally
Code is completely
Program marginally functional with
functional with
Code is completely functional with significant portion
Completeness/ minor
functional multiple errors of the code missing
Correctness implementation
and/or incomplete or incomplete
issues
code sections.
Code is extremely Code is reasonably Code is readable Code is poorly
Readability well organized, easy to follow with with significant organized with little
properly formatted logically grouped efforts. to no consistency in

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VLSI (4361102)

and easy to follow. codes. Minor Significant formatting and

Related code sections formatting problems with logical grouping.
are logically grouped. problems. code organization.
Reasonable test Test case design is
All the test cases are Testing of the
cases are covered erroneous or
Design testing covered with proper code with very
with issues in very inconsistent with
simulation results few test cases.
few test cases the code.
Code is Code unable to
Code is mostly marginally achieve the result
Code is efficient efficient with a efficient with with an irrelevant
without sacrificing scope to improve by significant scope patched coding
Efficiency
readability and selection of different to improve by
understanding constructs or changing coding
modelling styles and
constructs.
Code is well Code is well Significant Major portion of the
documented with documented with portions of the code is not
Documentation/ related comments minor formatting code are documented or is
and design details. issues. Minimal undocumented or with
Presentation
No typing mistakes and poorly wrong/irrelevant
typos/grammatical grammatical errors documented comments.
errors
Total marks

Sign with Date

97