MPMC Unit-5 Notes

Unit-5

by
M.Ramanjaneyulu
Associte professor
Department of ECE

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 MPMC Unit-5 Notes

8051 Real Time control

Interrupt: Interrupts are the events that temporarily suspend the main program, pass the
control to the external sources and execute their task. It then passes the control to the main
program where it had left off.
Interrupt Structure: An interrupt is an external or internal event that disturbs the
microcontroller to inform it that a device needs its service. The program which is associated with
the interrupt is called the interrupt service routine (ISR) or interrupt handler. Upon receiving
the interrupt signal the Microcontroller, finish current instruction and saves the PC on stack.
Jumps to a fixed location in memory depending on type of interrupt Starts to execute the
interrupt service routine until RETI (return from interrupt)Upon executing the RETI the
microcontroller returns to the place where it was interrupted. Get pop PC from stack

The 8051 microcontroller has FIVE interrupts in addition to Reset. They are

 Timer 0 overflow Interrupt

 Timer 1 overflow Interrupt

 External Interrupt 0(INT0)

 External Interrupt 1(INT1)

 Serial Port events (buffer full, buffer empty, etc) Interrupt

Each interrupt has a specific place in code memory where program execution (interrupt service
routine) begins.

 External Interrupt 0: 0003 H

 Timer 0 overflow: 000B H

 External Interrupt 1: 0013 H

 Timer 1 overflow: 001B H

 Serial Interrupt : 0023 H

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Upon reset all Interrupts are disabled & do not respond to the Microcontroller. These
interrupts must be enabled by software in order for the Microcontroller to respond to them. This
is done by an 8-bit register called Interrupt Enable Register (IE).

Interrupt Enable Register: This register is responsible for enabling and disabling the interrupt.
EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts.

 EA : Global enable/disable. To enable the interrupts this bit must be set High.

 --- : Undefined-reserved for future use.

 ET2 : Enable /disable Timer 2 overflow interrupt.(for 8052 only)

 ES : Enable/disable Serial port interrupt.

 ET1 : Enable /disable Timer 1 overflow interrupt.

 EX1 : Enable/disable External interrupt1.

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 ET0 : Enable /disable Timer 0 overflow interrupt.

 EX0 : Enable/disable External interrupt0

Upon reset the interrupts have the following priority.(Top to down). The interrupt with the
highest PRIORITY gets serviced first.

1. External interrupt 0 (INT0)

2. Timer interrupt0 (TF0)

3. External interrupt 1 (INT1)

4. Timer interrupt1 (TF1)

5. Serial communication (RI+TI)

Priority can also be set to “high” or “low” by 8-bit IP register.

Interrupt priority register: We can change the priority levels of the interrupts by changing the
corresponding bit in the Interrupt Priority (IP) register as shown in the following figure.

 A low priority interrupt can only be interrupted by the high priority interrupt, but not
interrupted by another low priority interrupt.
 If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served.
 If the requests of the same priority levels are received simultaneously, then the internal
polling sequence determines which request is to be serviced.

IP.7: reserved

IP.6: reserved

IP.5: Timer 2 interrupt priority bit (8052 only)

IP.4: Serial port interrupt priority bit

IP.3: Timer 1 interrupt priority bit

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IP.2: External interrupt 1 priority bit

IP.1: Timer 0 interrupt priority bit

IP.0: External interrupt 0 priority bit

It is not possible to for seen when an interrupt request will arrive. If several interrupts are
enabled, it may happen that while one of them is in progress, another one is requested. In order
that the microcontroller knows whether to continue operation or meet a new interrupt request,
there is a priority list instructing it what to do.

The priority list offers 3 levels of interrupt priority:

1. Reset. When a reset request arrives, everything is stopped and the Microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.

The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources
have higher and which one has lower priority. Interrupt priority is usually specified at the
beginning of the program. According to that, there are several possibilities:

 If an interrupt of higher priority arrives while an interrupt is in progress, it will be

immediately stopped and the higher priority interrupt will be executed first.
 If two interrupt requests, at different priority levels, arrive at the same time then the
higher priority interrupt is serviced first.
 If the both interrupt requests, at the same priority level, occur one after another, the one
which came later has to wait until routine being in progress ends.
 If two interrupt requests of equal priority arrive at the same time then the interrupt to be
serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt
Handling Interrupt: When an interrupt request arrives the following occurs:
1. Instruction in progress is ended.
2. The address of the next instruction to execute is pushed on the stack.
3. Depending on which interrupt is requested, one of 5 vectors (addresses) is written to the
Program counter in accordance to the table below:
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Interrupt Source Vector (address)

IE0 03 h
TF0 0B h
TF1 13 h
RI, TI 23 h

4. These addresses store appropriate subroutines processing interrupts. Instead of them, there
are usually jump instructions specifying locations on which these subroutines reside.
5. When an interrupt routine is executed, the address of the next instruction to execute is
poped from the stack to the program counter and interrupted program resumes operation from
where it left off.

Program1.Write ALP 8051 to (a) Enable the serial interrupt, Timer 0 interrupt, and external
hardware interrupt1 (b) Disable the Timer 0 interrupt (c) disable all interrupts

(a)
B7 B6 B5 B4 B3 B2 B1 B0

1 0 0 1 0 1 1 0

=96

1) MOV IE,#10010110B

2) MOV IE,#96H

3) SETB IE.7

SETB IE.4
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SETB IE.2

SETB IE.1

b) CLR IE.1

c) CLR IE.7

TIMERS in 8051 Microcontrollers: The 8051 microcontroller has two 16-bit timers
Timer 0 (T0) and Timer 1(T1) which can be used either to generate accurate time delays or as
event counters. These timers are accessed as two 8-bit registers TLO, THO & TL1,TH1
because the 8051 microcontroller has 8-bit architecture.

TIMER 0 : The Timer 0 is a 16-bit register and can be treated as two 8-bit registers (TL0 &
TH0) and these registers can be accessed similar to any other registers like A,B or R1,R2,R3
etc…

TIMER 1 : The Timer 1 is also a 16-bit register and can be treated as two 8-bit registers (TL1
& TH1) and these registers can be accessed similar to any other registers like A,B or R1,R2,R3
etc…

TMOD Register: The various operating modes of both the timers T0 and T1 are set by an 8-bit
register called TMOD register. In this TMOD register the lower 4-bits are meant for Timer 0 and
the higher 4-bits are meant for Timer1.

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GATE: This bit is used to start or stop the timers by hardware .When GATE= 1 ,the timers can
be started / stopped by the external sources. When GATE= 0, the timers can be started or stopped
by software instructions like SETB TR0 or SETB TR1

C/T (clock/Timer): This bit decides whether the timer is used as delay generator or event
counter. When C/T = 0 , the Timer is used as delay generator and if C/T=1 the timer is used as
an event counter. The clock source for the time delay is the crystal frequency of 8051.

M1, M0 (Mode) : These two bits are the timer mode bits. The timers of the 8051 can be
configured in three modes.Mode0, Mode1 and Mode2. The selection and operation of the modes
is shown below.

S.No M0 M1 Mode Operation

1 0 0 0 13-bit Timer mode
8-bit Timer/counter. THx with TLx as 5-bit

2 0 1 1 16-bit Timer mode.16-bit timer /counter

3 1 0 2 8-bit auto reload. THx contains a value that

is to be loaded into TLx each time it
overflows
4 1 1 3 Split timer mode

Modes of 8051 Timer/Counter: The 8051 microcontroller provides four different modes of
operation, and a programmer can decide which mode to use according to their needs.

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Mode 1:- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into
the timer’s registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer
must be started.

We can do it by “SETB TR0” for timer 0 and “SETB TR1” for timer 1. After the timer is started.
It starts count up until it reaches its limit of FFFFH. When it rolls over from FFFF to 0000H, it
sets high a flag bit called TF (timer flag). This timer flag can be monitored. When this timer flag
is raised, one option would be stop the timer with the instructions “CLR TR0“ or CLR TR1 for
timer 0 and timer 1 respectively. Again, it must be noted that each timer flag TF0 for timer 0 and
TF1 for timer1. After the timer reaches its limit and rolls over, in order to repeat the process the
registers TH and TL must be reloaded with the original value and TF must be reset to 0.

Mode0:- Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit.
The 13-bit counter can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the
timer reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised.

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Mode 2:- It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the timer’s
register TH. After TH is loaded with 8 bit value,the 8051 gives a copy of it to TL. Then the timer
must be started. It is done by the instruction “SETB TR0” for timer 0 and “SETB TR1” for
timer1. This is like mode 1. After timer is started, it starts to count up by incrementing the TL
register. It counts up until it reaches its limit of FFH. When it rolls over from FFH to 00. It sets
high the TF (timer flag). If we are using timer 0, TF0 goes high; if using TF1 then TF1 is
raised. When Tl register rolls from FFH to 00 and TF is set to 1, TL is reloaded automatically
with the original value kept by the TH register. To repeat the process, we must simply clear TF
and let it go without any need by the programmer to reload the original value. This makes mode
2 auto reload, in contrast in mode 1 in which programmer has to reload TH and TL.

Mode3:- Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be
in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3;
timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3
causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer0.

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TCON register:- Bits and symbol and functions of every bits of TCON are as follows:

BIT Symbol Functions

7 TF1 Timer1 over flow flag. Set when timer rolls from all 1s to 0. Cleared
When the processor vectors to execute interrupt service routine
Located at program address 001Bh.

6 TR1 Timer 1 run control bit. Set to 1 by programmer to enable timer to

count; Cleared to 0 by program to halt timer.

5 TF0 Timer 0 over flow flag. Same as TF1.

4 TR0 Timer 0 run control bit. Same as TR1.

3 IE1 External interrupt 1 Edge flag. Not related to timer operations.

2 IT1 External interrupt1 signal type control bit. Set to 1 by program to

Enable external interrupt 1 to be triggered by a falling edge signal.
Set To 0 by program to enable a low level signal on external
Interrupt1 to generate an interrupt.
1 IE0 External interrupt 0 Edge flag. Not related to timer operations.

0 IT0 External interrupt 0 signal type control bit. Same as IT1.

Program2. Write 8051 program to initialize timer0 in mode2 and timer1 in mode1 and start
both timers. Reset timer0 on overflow

TMOD: =12H

Timer1 Timer 0

GATE C/T M1 M0 GATE C/T M1 M0

0 0 0 1 0 0 1 0

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Program :
ORG 0000H

MOV TMOD,#12H ; Timer0 in mode2 and Timer1 in Mode1

SETB TR0 ; To start the Timer 0,TR0=1

SETB TR1 ; To start the Timer 1,TR1=1

SELF:JNB TF0 SELF ;Self loop to check the timer0 over flow flag

CLR TR0 ;stop the timer0,TR0=0

CLR TF0 ;clear the timer0 over flow flag,TF0=0

END

Program3.Write 8051 ALP to generate a 5KHz square wave on P1.5 using timer0

Assumptions :

• Timer 0 is used in mode1 (16-bit Timer)

• Crystal frequency is 12MHz,the Timer 0 will use 1/12 of this frequency as

input=1MHz ,T=1micro second

• For 5KHz square wave , delay of 200 micro second is to be generated

TMOD: =01H
Timer1 Timer 0

GATE C/T M1 M0 GATE C/T M1 M0

0 0 0 0 0 0 0 1

Algorithm :

1. Load TMOD register such that Timer0 is in Mode1

2. Load TL0 and TH0 with initial values such that Timer0 over flows after 200 micro
seconds
3. Start Timer 0

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4. Monitor TF0 till it becomes high

5. Complement P1.5
6. Clear TF0
7. Go back to second step
The initial value of Timer0=0000H=0000D

The Final value of Timer0 =0FFFFH=65535

The starting count =65536-200=65336=0FF38H

TL0=38H,TH0=FF

Program:

ORG 0000H

MOV TMOD,#01H ;To operate Timer0 in Mode1

BACK:MOV TL0,#38H ;Load TL0 to Generate 200 us delay

MOV TH0,#0FFH ; Load TH0 to Generate 200 us delay

SETB TR0 ;start the Timer 0,TR0=1

SELF:JNB TF0,SELF ;Generate 200 us delay

CPL P1.5 ;changing the value at P1.5

CLR TF0 ;Clear TF0,TF0=0

SJMP BACK

Program4.Write 8051 ALP to count number of pulses received on T1(P3.5) in one

second.Send the number pulses count to P0 and P1

Assumptions :

• Timer 0 is used in mode1 (16-bit Timer)

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• Crystal frequency is 12MHz,the Timer 0 will use 1/12 of this frequency as

input=1MHz ,T=1micro second

• The duration of the pulse count=1 sec=1000 msec

• Initilize TL0 and TH0 such that delay of 50msec=50000 usec is achieved by running
timer0

• Run Timer0 for 20 (14H) times to get one second delay

Algorithm:

1. Timer0 is used as Timer in mode 1 as Timer and Timer1 used as counter in mode
0,so load TMOD accordingly.

2. Timer1 Timer 0

GATE C/T M1 M0 GATE C/T M1 M0

0 1 0 0 0 0 0 1

=41H

3. Configue P3.5 as input

4. Initilize TH1 and TL1 to 00H

5. Start Timer 1 as counter

6. Initilize delay repetation count for Timer 0

7. Initilize TL0 and TH0 to give 50 msee delay

8. Start Timer 0 as Timer

9. Wait for the Timer0 over flow flag to become high

10. Clear TR0

11. Clear TF0

12. Decrement delay repitation count ,if it is not zero go back to Step7

13. Read TH1 & TL1 and send to P1 and P0

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Caluclations: For 50 msee=50,000 usec delay,timer0 has to count 50000 (50000*1usec)

pulses.Hence initial value loaded is 65536-50000=15536=3CB0H

Program : ORG 0000H

MOV TMOD,#41H ;to operate T0 as Timer and T1 as counter

SETB P3.5 ; To configure P3.5 (T1) as input

;@@@@@ Configuration of Counter T1 @@@@@@

MOV TL1,#00H ;To Clear Counter TL1

MOV TH1,#00H ; To Clear Counter TH1

SETB TR1 ; Start the Timer

;@@@@@@@ Configure Timer0 T0 for introducing 1sec delay

MOV R2,#14H ;Intialize R2 to repeat the loop for 20 times

GOBACK:MOV TL0,#0B0H ; Intialize TL0 to generate 50 msec

MOV TH0,#3CH ; Intialize TH0 to generate 50 msec

SETB TR0 ; start the Timer0

SELF:JNB TF0,SELF ;To check overflow

CLR TR0 ;stop the timer

CLR TF0 ;Clear TF0

DJNZ R2,GOBACK

CLR TR1 ; stop the counter

MOV A,TL1 ;move count value in TL1 in to A

MOV P0,A ; move count value in A in to P0

MOV A,TH1 ; move count value in TH1 in to A

MOV P1,A ; move count value in A in to P1

END

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Serial Communication in 8051 Microcontroller:

 Microcontrollers need to communicate with external devices to collect data for

processing.
 Data communication is generally done by means of two methods – Parallel and Serial
mode.
 In parallel mode data bits are transferred faster using more data pins.
 Serial Communication uses only two data pins to establish communication between
Microcontroller and external devices.
 UART or Serial communication in 8051 microcontroller will allow the controller to send
and receive data’s just by using two pins TXD & RXD
 In this mode of communication data is transferred one bit at a time.
 The 8051 includes an on-chip serial port that can operate in several modes over a wide
range of frequencies.
 The essential function of the serial port is to perform parallel-to-serial conversion for
output data, and serial-to-parallel conversion for input data.
 Two special function registers provide software access to the serial port, SBUF and
SCON.

Serial communication Registers:

SBUF: Serial Buffer Register: This is the serial communication data register used to transmit or
receive data through it.

 The serial port buffer (SBUF) at address 99H is really two buffers.
 Writing to SBUF loads data to be transmitted, and reading SBUF accesses received data.
 These are two separate and distinct registers, the transmit write-only register, and the
receive read-only register
 There are two separate data lines, one for transmission (TXD) and one for reception
(RXD).

SCON: Serial Control Register

 The Serial Control or SCON is used to control the 8051 Microcontroller’s Serial Port.
 It is located as an address of 98H.
 Using SCON, you can control the Operation Modes of the Serial Port, Baud Rate of the
Serial Port and Send or Receive Data using Serial Port.

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 SCON Register also consists of bits that are automatically SET when a byte of data is
transmitted or received.

Mode 0:

• In this mode, the serial port works like a shift register and the data transmission works
synchronously with a clock frequency of fosc /12.
• Serial data is received and transmitted through RXD.
• 8 bits are transmitted/ received at a time.
• Pin TXD outputs the shift clock pulses of frequency fosc /12, which is connected to the
external circuitry for synchronization.
• The shift frequency or baud rate is always 1/12 of the oscillator frequency.

Mode 1

• In mode-1, the serial port functions as a standard Universal Asynchronous Receiver

Transmitter (UART) mode.
• 10 bits are transmitted through TXD or received through RXD.
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• The 10 bits consist of one start bit (which is usually '0'), 8 data bits (LSB is sent
first/received first), and a stop bit (which is usually '1').
• Once received, the stop bit goes into RB8 in the special function register SCON.
• The baud rate is variable.

Mode 2

• In this mode 11 bits are transmitted through TXD or received through RXD.
• The various bits are as follows: a start bit (usually '0'), 8 data bits (LSB first), a
programmable 9th (TB8 or RB8)bit and a stop bit (usually '1').
• While transmitting, the 9th data bit (TB8 in SCON) can be assigned the value '0' or '1'.
• The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency.
• f baud = (2SMOD /64) fosc.

Mode 3

• In this mode 11 bits are transmitted through TXD or received through RXD.
• The various bits are: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9th
bit and a stop bit (usually '1').
• Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable (i.e.,
just as in mode-1).
• f baud = (2 SMOD /32) * ( fosc / 12 (256-TH1)) .
• This baud rate holds when Timer-1 is programmed in Mode-2.

PCON (Power Control) Register:

 The PCON or Power Control register is used to control the 8051 Microcontroller’s Power
Modes and is located at 87H of the SFR Memory Space.
 Using two bits in the PCON Register, the microcontroller can be set to Idle Mode and
Power Down Mode.
 During Idle Mode, the Microcontroller will stop the Clock Signal to the ALU (CPU) but
it is given to other peripherals like Timer, Serial, Interrupts, etc.

 In order to terminate the Idle Mode, you have to use an Interrupt or Hardware Reset.

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 In the Power Down Mode, the oscillator will be stopped and the power will be reduced to
2V.

 To terminate the Power Down Mode, you have to use the Hardware Reset.

 The SMOD Bit in the PCON Register is used to control the Baud Rate of the Serial Port.

 There are two general purpose Flag Bits in the PCON Register, which can be used by the
programmer during execution.

PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT:

 TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is
transferred, indicating that the SBUF register is ready to transfer the next byte.

 RI (received interrupt), is raised when the entire frame of data, including the stop bit, is
received.

 In the interrupt method, we are notified when the 8051 has received a byte, or is ready to
send the next byte

 In the 8051 only one interrupt is set aside for serial communication.

 This interrupt is used to both send and receive data.

 If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the 8051
gets interrupted and jumps to memory address location 0023H to execute the ISR.
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 In that ISR we must examine the TI and RI flags to see which one caused the interrupt
and respond accordingly.

Program1: Write 8051 ALP to program to operate serial port at 2400 bauds using timer1

• 8051 uses Timer1 T1 for Generating the Baud rate for Serial Transmission.
• The Timer1 is operated in mode2 (Auto Reload Mode)

Baud Rate calculation:

 As we know that 8051 microcontrollers takes 12 clock cycles to complete one machine
cycle.

 So our effective Instruction execution frequency is Fosc/12. If we are using a crystal of

11.0592MHz; our effective frequency is somewhere around Feffective= 11.0592/12 MHz

=> 921.6KHz.

 8051 UART or serial communication block further divide this frequency (921.6 KHz) by 32
to generate its baud rate.

 The Effective frequency available to generate Baud rates is 921.6 KHz/32 = 28800 Hz.

 So for different standard baud rates the values of TH1 will be

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TMOD: 20H

Timer1 Timer 0
GATE C/T M1 M0 GATE C/T M1 M0
0 0 1 0 0 0 0 0

 For getting 2400 bauds ,TH1= 12

 Initial Count in TH1=256-12=244=0F4H

Program :

ORG 0000H

MOV TMOD,#20H

MOV TH1,0F4H

SETB TR1

END

Program2.Write 8051 ALP to transmit 8-bit character serially at 9600 bauds continuously

SCON: For Transmitting 8-bit character, operate Serial port in Mode 1

SM0 SM1 SM2 REN TB8 RB8 TI RI

0 1 0 0 0 0 0 0

• 8051 uses Timer1 T1 for Generating the Baud rate for Serial Transmission.

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• The Timer1 is operated in mode2 (Auto Reload Mode)

• For getting 9600 bauds ,TH1= 03

 Initial Count in TH1=256-03=253=0FDH

 Program:

MOV TMOD,#20H ;Timer1 in mode 1

MOV TH1,#0FDH ;Load TH1 for 9600 bauds

MOV SCON,#40H ;Mode1 transmission for serial port

SETB TR1 ;Start Timer1

CONTINUE: CLR TI ;Clear Transfer Interrupt

MOV SBUF,#’A’ ;Copy 8-bit data in to SBUF

SELF: JNB TI,SELF

SJMP CONTINUE

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ARM architecture
Introduction:
The ARM microcontroller stands for Advance RISC Machine; it is one of the extensive and
most licensed processor cores in the world. The first ARM processor was developed in the year
1978 by Cambridge University, and the first ARM RISC processor was produced by the Acorn
Group of Computers in the year 1985. These processors are specifically used in portable devices
like digital cameras, mobile phones, home networking modules and wireless communication
technologies and other embedded systems due to the benefits, such as low power consumption,
reasonable performance, etc.

The ARM architecture processor is an advanced reduced instruction set computing [RISC]
machine and it’s a 32-bit reduced instruction set computer (RISC) microcontroller. This ARM is
a family of microcontroller developed by makers like ST Microelectronics, Motorola, and so on.
The ARM architecture comes with totally different versions like ARMv1, ARMv2, etc., and,

ARM Architecture:
Data enters the processor core through the Data bus. The data may be an instruction to
execute or a data item. Figure shows a Von Neumann implementation of the ARM—data items
and instructions share the same bus. In contrast, Harvard implementations of the ARM use two
different buses.
The instruction decoder translates instructions before they are executed. Each instruction
executed belongs to a particular instruction set. The ARM processor, like all RISC processors,
uses a load-store architecture. This means it has two instruction types for transferring data in and
out of the processor: load instructions copy data from memory to registers in the core, and
conversely the store instructions copy data from registers to memory. There are no data
processing instructions that directly manipulate data in memory. Thus, data processing is carried
out solely in registers.
Data items are placed in the register file—a storage bank made up of 32-bit registers. Since
the ARM core is a 32-bit processor, most instructions treat the registers as holding signed or
unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit
values as they are read from memory and placed in a register.
ARM instructions typically have two source registers, Rn and Rm, and a single result or
destination register, Rd. Source operands are read from the register file using the internal buses A
and B, respectively.
The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values
Rn and Rm from the A and B buses and computes a result. Data processing instructions write the
result in Rd directly to the register file. Load and store instructions use the ALU to generate an
address to be held in the address register and broadcast on the Address bus.

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One important feature of the ARM is that register Rm alternatively can be preprocessed in
the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide
range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register file
using the Result bus. For load and store instructions the incrementer updates the address register
before the core reads or writes the next register value from or to the next sequential memory location.
The processor continues executing instructions until an exception or interrupt changes the normal
execution flow.

Arithmetic Logic Unit (ALU):

The ALU has two 32-bits inputs. The primary comes from the register file, whereas the other
comes from the shifter. Status registers flags modified by the ALU outputs. The V-bit output
goes to the V flag as well as the Count goes to the C flag. Whereas the foremost significant bit
really represents the S flag, the ALU output operation is done by NORed to get the Z
flag. The ALU has a 4-bit function bus that permits up to 16 opcode to be implemented.

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Barrel Shifter:

The barrel shifter features a 32-bit input to be shifted. This input is coming back from the
register file or it might be immediate data. The shifter has different control inputs coming back
from the instruction register. The Shift field within the instruction controls the operation of the
barrel shifter. This field indicates the kind of shift to be performed (logical left or right,
arithmetic right or rotate right). The quantity by which the register ought to be shifted is
contained in an immediate field within the instruction or it might be the lower 6 bits of a register
within the register file.

The shift_val input bus is 6-bits, permitting up to 32 bit shift. The shift type indicates the needed
shift sort of 00, 01, 10, 11 are corresponding to shift left, shift right, an arithmetic shift right and
rotate right, respectively. The barrel shifter is especially created with multiplexers.

Control Unit:
For any microprocessor, control unit is the heart of the whole process and it is responsible for the
system operation, so the control unit design is the most important part within the whole design.
The control unit is sometimes a pure combinational circuit design. Here, the control unit is
implemented by easy state machine. The processor timing is additionally included within the
control unit. Signals from the control unit are connected to each component within the processor
to supervise its operation.

ARM Microcontroller Register Modes:

An ARM Microcontroller is a load store reducing instruction set computer architecture means
the core cannot directly operate with the memory. The data operations must be done by the
registers and the information is stored in the memory by an address. The ARM consists of 37
register sets wherein 31 are general purpose registers and 6 are status registers. The ARM uses
seven processing modes to run the user task.

 USER Mode
 FIQ Mode
 IRQ Mode
 SVC Mode
 UNDEFINED Mode
 ABORT Mode
 Monitor Mode

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 MPMC Unit-5 Notes

ARM Microcontroller Register Modes

USER Mode: The user mode is a normal mode, which has the least number of registers. It
doesn’t have SPSR and has limited access to the CPSR.

FIQ and IRQ: The FIQ and IRQ are the two interrupt caused modes of the CPU. The FIQ is
processing interrupt and IRQ is standard interrupt. The FIQ mode has additional five banked
registers to provide more flexibility and high performance when critical interrupts are handled.

SVC Mode: The Supervisor mode is the software interrupt mode of the processor to start up or
reset.

Undefined Mode: The Undefined mode traps when illegal instructions are executed. The ARM
core consists of 32-bit data bus and faster data flow.

Some of the registers are reserved in each mode for the specific use of the core. The reserved
registers are

 Stack Pointer (SP).

 Link Register (LR).
 Program Counter (PC).
 Current Program Status Register (CPSR).
 Saved Program Status Register (SPSR).

The reserved registers are used for specific functions. The SPSR and CPSR contain the status
control bits which are used to store the temporary data. The SPSR and CPSR register have some
properties that are defined operating modes, Interrupt enable or disable flags and ALU status
flag. The ARM core operates in two states 32-bit state or THUMBS state.

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 MPMC Unit-5 Notes

Pipeline: The Process of fetching the next instruction while the current instruction is being
executed is called as “pipelining”. Pipelining is supported by the processor to increase the speed
of program execution. Increases throughput. Several operations take place simultaneously,
rather than serially in pipelining.
A pipeline is the mechanism of a RISC processor uses to execute instructions. Using a pipeline
speeds up execution by fetching the next instruction while other instructions are being decoded
and executed. One way to view the pipeline is to think of it as an automobile assembly line, with
each stage carrying out a particular task to manufacture the vehicle.

 Fetch loads an instruction from memory.

 Decode identifies the instruction to be executed.
 Execute processes the instruction and writes the result back to a register.
Figure 2.8 illustrates the pipeline using a simple example. It shows a sequence of three
instructions being fetched, decoded, and executed by the processor. Each instruction takes a
single cycle to complete after the pipeline is filled.
The three instructions are placed into the pipeline sequentially. In the first cycle the core
fetches the ADD instruction from memory. In the second cycle the core fetches the SUB
instruction and decodes the ADD instruction. In the third cycle, both the SUB and ADD
instructions are moved along the pipeline. The ADD instruction is executed, the SUB instruction
is decoded, and the CMP instruction is fetched. This procedure is called filling the pipeline. The
pipeline allows the core to execute an instruction every cycle.

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 MPMC Unit-5 Notes

As the pipeline length increases, the amount of work done at each stage is reduced, which
allows the processor to attain a higher operating frequency. This in turn increases the
performance. The system latency also increases because it takes more cycles to fill the pipeline
before the core can execute an instruction. The increased pipeline length also means there can be
data dependency between certain stages. You can write code to reduce this dependency by using
instruction scheduling
The pipeline design for each ARM family differs. For example, The ARM9 core
increases the pipeline length to five stages, as shown in Figure 2.9. The ARM9 adds a memory
and write back stage, which allows the ARM9 to process on average 1.1 Dhrystone MIPS per
MHz—an increase in instruction throughput by around 13% compared with an ARM7.The
maximum core frequency attainable using an ARM9 is also higher.

The ARM10 increases the pipeline length still further by adding a sixth stage, as shown
in Figure 2.10. The ARM10 can process on average 1.3 Dhrystone MIPS per MHz, about 34%
more throughput than an ARM7 processor core, but again at a higher latency cost. Even though
the ARM9 and ARM10 pipelines are different, they still use the same pipeline executing
characteristics as an ARM7. Code written for the ARM7 will execute on an ARM9 or ARM10.

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