Flip-Flops

1 In designing a Lamp control ...............................................................................................................................2

2 Clock ..................................................................................................................................................................2
3 Different types of triggering using clock:...........................................................................................................3
4 Combinational Circuit ........................................................................................................................................4
5 Sequential Circuits..............................................................................................................................................4
6 Flip-Flop .............................................................................................................................................................6
7 History ................................................................................................................................................................6
8 Uses of Flip-flop .................................................................................................................................................6
9 Timing analysis with flip-flops...........................................................................................................................7
10 Flip-Flop .........................................................................................................................................................7
11 Latch ...............................................................................................................................................................8
16 Flip-flop vs Latch .........................................................................................................................................10
17 Latch / Flip-flops ..........................................................................................................................................10
18 SR Flip-Flop .................................................................................................................................................11
19 Clocked SR Flip Flop ...................................................................................................................................12
20 D Flip-Flop ...................................................................................................................................................13
21 JK Flip-Flop..................................................................................................................................................14
22 Toggle Flip-Flop /T Flip Flop ......................................................................................................................16
23 Master-Slave JK Flip-Flop ...........................................................................................................................16
24 References: ...................................................................................................................................................18

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
1 In designing a Lamp control

Let us design a network to control a lamp from two pushbutton switches labeled S and R. If we push switch S the
light should turn on. If we then release S, the light should stay on. If we push switch R, the lamp should turn off
and stay off after releasing R. Assume that both S and R are not pushed at the same time.

2 Clock

The term "clock" in electronics is derived from the concept of measuring and controlling time, similar to how a
traditional clock measures time. The analogy works because, just as a mechanical or wall clock divides time into
equal units to track hours and minutes, an electronic clock signal divides time into precise intervals or "ticks" that
allow different parts of an electronic circuit to operate in sync.
Clock refers to a timing signal used to synchronize the operations of circuits and components within a system. This
clock signal is crucial for coordinating the timing of various processes in digital devices, including computers,
microcontrollers, and other electronic systems. Here’s a closer look at what a clock means in this context:
Characteristics of Clock Signals

• Frequency: The frequency of a clock signal determines how many cycles occur per second, usually
measured in hertz (Hz). Higher frequencies allow for faster processing speeds.
• Waveform: Clock signals typically have a square waveform, which alternates between high (logic 1) and
low (logic 0) states. The time spent in each state defines the clock period.
• Duty Cycle: The duty cycle is the ratio of the time the signal is high to the total period of the clock cycle.
A 50% duty cycle means the signal is high for half of the period and low for the other half.
Types of Clock Signals

• System Clock: This is the primary clock for a microprocessor, controlling the timing of all operations
within the CPU.

• Real-Time Clock (RTC): A clock that keeps track of the current time and date, even when the main power
is off, often found in computers and embedded systems.

• Clock Pulses: Used in digital circuits to trigger the operation of flip-flops, registers, and counters, ensuring
that data is processed at the correct times.
Applications of Clock Signals

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 • Data Synchronization: Ensures that data transfers occur at the right moments, preventing data corruption.
• Timing Control: Used in timers, counters, and sequencers to regulate the timing of operations in a circuit.
• Frequency Generation: Serves as a reference for generating other signals, such as in phase-locked loops
(PLLs).
Importance
In digital electronics, clock signals are vital for ensuring that components work together efficiently and effectively,
allowing for complex operations to be performed in a coordinated manner. Without proper clock signals, the timing
and functionality of electronic devices would be disrupted, leading to errors and malfunction.

A clock signal is produced by a clock generator. Although more complex arrangements are used, the most common
clock signal is in the form of a square wave with a 50% duty cycle, usually with a fixed, constant frequency. Circuits
using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case
of double data rate, both the rising and falling edges of the clock cycle.

Positive going transition (PGT) – when the clock pulse goes from 0 to 1.
Negative going transition (NGT) – when the clock pulse goes from 1 to 0.
Transitions are also called edges

3 Different types of triggering using clock:

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
4 Combinational Circuit

The combinational logic circuits, the output depends on the particular combination of logic states at the input
connections to the circuit. The Combinational Logic circuits change their state depending upon the actual signals
being applied to their inputs at that time.
In combinational circuits (AND, OR, NOR, NAND, etc,), the outputs depend only on the inputs.

5 Sequential Circuits

A sequential circuit is a combinational circuit with some feedback from the outputs. In a sequential circuit. the
output state depends on both the inputs and the outputs. The term "sequential" comes from the fact that the output
depends not only on the current states but on the states-immediately preceding (memory state). So, it requires the
use of storage elements (a Flip-flop). A Flip-flop. Is a sequential circuit, and an electronic circuit which has two
stable states and thereby is capable of serving as one bit of memory, bit 1 or, bit 0.

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
6 Flip-Flop

A Flip-flop is another name for a Bistable multivibrator, on whose output

is either- a low or a high voltage, a 0 or a 1. The output stays low or high;
to change it the circuit must be driven by an input called the trigger. Until
the trigger arrives, the output voltage remains low or high indefinitely. In
other words, Flip-flop has two stable states of complementary output
values.
In other words, Flip flop is a sequential circuit that generally samples its
inputs and changes its outputs only at particular instants of time and not
continuously. Flip-flop is said to be edge sensitive or edge-triggered
rather than being level-triggered like latches.

Figure 1: Flip-flop circuit (Bistable

multivibrator)
7 History

The first electronic Flip-flop was invented in 1918 by the British physicists William Eccles and F. W. Jordon. It
was initially called the Eccles-Jordan trigger circuit and consisted of two active elements (vacuum tubes). The
design was used in the 1943 British Colossus codebreaking computer and such circuits and their transistorized
versions were common in computers even after the introduction of integrated circuits, though flip-flops made from
logic gates are also common now. Early flip-flops were known variously as trigger circuits or multivibrators.

8 Uses of Flip-flop

Flip-flops and latches are a fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems. Flip-flop or Latch is just two inter-connected logic gates that
make up the basic form of the circuit whose output has two stable output states. When the circuit is triggered into
either one of these states by a suitable input pulse, it will 'remember' that state until it is changed by a further input
pulse, or until power is removed. Flip-flops can be used:
➢ For Memory circuits
➢ For Logic Control Devices
➢ For Counter Devices
➢ For Register Devices
A digital computer needs devices that can store information. A Flip-Flop is a binary storage device. It stores a single
bit (binary digit) of data; one of its two states represents a "one" and the other represents a "zero". It is also used in
many sequential logic circuits.
The basic formation of Flip-Flop is to store data because it can store binary bits either 0 or 1. It has two stable states
HIGH and LOW i.e. 1 and 0. It has the property to remain in one state indefinitely until it is directed by an input
signal to switch over to the other state.

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
9 Timing analysis with flip-flops

There are some important things to understand when we go to actually make and implement a circuit with flip-
flops. In reality, it takes time for gates to change their output values according to the input values - i.e., there are
propagation delays due to resistance, capacitance, etc.
➢ Changes in Flip-flop outputs occur at the active clock edge.
Three timing parameters are especially important:
➢ Setup Time (TSU): The setup time of a Flip-flop is the amount of time that the data inputs need to be held
stable (not changing) before the arrival of the active clock edge.
➢ Hold Time (TN): The hold time of a Flip-flop is the amount of time that the data inputs need to be held
stable (not changing) after the arrival of the active clock edge.
➢ Clock-To-Output (TCO): The clock-to-output time of a Flip-flop is the amount of time it takes for the
output to become stable (at its new value) after the arrival of the active clock edge.

10 Flip-Flop

A flip-flop is a fundamental digital circuit that can store a single bit of data (either 0 or 1). Flip-flops are sequential
logic devices, meaning they retain a memory of their previous state, unlike combinational logic circuits that produce
outputs solely based on the current inputs. Flip-flops are used extensively in memory units, registers, and counters,
and they play a crucial role in the timing and control operations of digital systems.
Key Features of Flip-Flops
1. Bistable: Flip-flops have two stable states, representing the binary values 0 and 1. They can remain in one
of these states until an input pulse changes them.
2. Clock Dependency: Flip-flops are generally synchronous devices, meaning they change state based on a
clock signal. They can be triggered on the rising or falling edge of a clock pulse, allowing precise timing
control.
3. Memory Retention: A flip-flop can hold a value (0 or 1) until it is instructed to change, making it a basic
unit of memory in digital systems.
Types of Flip-Flops
Each type of flip-flop has unique characteristics that make it suitable for specific functions:
1. SR Flip-Flop (Set-Reset Flip-Flop):
o Inputs: Set (S) and Reset (R).
o Function: When the Set input (S) is 1 and Reset (R) is 0, the output (Q) is set to 1. When S is 0
and R is 1, the output is reset to 0.
o Limitations: If both S and R are 1 simultaneously, the state is undefined. Some designs solve this
with an additional control mechanism.
2. D Flip-Flop (Data or Delay Flip-Flop):

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 o Input: Data (D) and clock input.
o Function: The output (Q) takes the value of D only at the clock's active edge (rising or falling,
depending on the design). When the clock is not active, the D flip-flop holds its state.
o Usage: D flip-flops are widely used for data storage in registers and for creating reliable, edge-
triggered memory.
3. JK Flip-Flop:
o Inputs: J and K, along with a clock.
o Function: If J and K are both 1, the output toggles (switches from 0 to 1 or 1 to 0) with each clock
pulse. If J = 1 and K = 0, the output is set to 1; if J = 0 and K = 1, the output is reset to 0.
o Advantages: Unlike the SR flip-flop, the JK flip-flop avoids the undefined state when both inputs
are high.
4. T Flip-Flop (Toggle Flip-Flop):
o Input: T (Toggle) and clock.
o Function: When T = 1, the output toggles its state with each clock pulse. If T = 0, the output
remains the same.
o Usage: Commonly used in counters and frequency dividers due to its ability to flip its output state.
Applications of Flip-Flops
1. Data Storage: Flip-flops store individual bits of data, forming the basis of larger memory structures like
registers and shift registers.
2. Counters: T flip-flops or JK flip-flops are used in counters to keep track of counts, often used in digital
clocks and timers.
3. Shift Registers: Flip-flops are used in shift registers to shift data bits left or right, enabling data
manipulation in serial-to-parallel and parallel-to-serial conversions.
4. State Machines: Flip-flops form the backbone of finite state machines, where they store and transition
between states based on input conditions and clock pulses.
5. Frequency Division: T flip-flops, when arranged in series, can divide an input frequency, making them
useful in frequency division applications.

11 Latch

A latch is a basic memory element in digital electronics similar to a flip-flop, but with a key difference in how it
responds to inputs and the clock signal. Latches are asynchronous, meaning they continuously respond to their
inputs when enabled, unlike flip-flops, which are usually synchronous and only change states at specific clock
edges.
12 Differences between a Latch and a Flip-Flop

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 1. Clock Dependency:
o Latch: Operates continuously when enabled, without depending on clock edges. As long as the
enable signal (often called "Enable" or "Gate") is active, the latch will update its output based on
the inputs.
o Flip-Flop: Only changes state in response to clock edges (either rising or falling), making it edge-
triggered and synchronous with the clock signal.
2. Level-Triggered vs. Edge-Triggered:
o Latch: Latches are level-triggered, meaning they change states as long as the enable signal is active
(either high or low, depending on the design).
o Flip-Flop: Flip-flops are edge-triggered, meaning they only change states when the clock signal
transitions (from low to high or high to low).
13 Types of Latches
1. SR Latch (Set-Reset Latch):
o Has two inputs: Set (S) and Reset (R).
o When S = 1 and R = 0, the latch is set, meaning its output (Q) goes high (1).
o When S = 0 and R = 1, the latch is reset, and Q goes low (0).
o If both S and R are 0, the latch retains its state.
o If both S and R are 1, the state is undefined (though some designs avoid this by using an additional
control mechanism).
2. D Latch (Data Latch):
o Has a data input (D) and an enable input (EN).
o When EN is active, the output (Q) follows the D input.
o When EN is inactive, the output retains its previous state.
o Commonly used as a basic data storage element in memory circuits.
14 Role of Latches in Flip-Flops
Flip-flops are typically built from two latches in a master-slave configuration:
• Master-Slave Flip-Flop: A D flip-flop, for example, can be constructed from two D latches connected in
series. The first latch (master) is enabled during one phase of the clock signal, while the second latch (slave)
is enabled during the opposite phase. This arrangement ensures that the flip-flop only changes state at clock
edges, effectively making it edge-triggered.
15 Applications of Latches
• Temporary Data Storage: Latches hold data temporarily and are commonly used in circuits where
continuous monitoring of inputs is needed (e.g., in memory buffers).

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 • Enabling Control Circuits: Latches are used in circuits where data should only be stored when a specific
condition (like a control or enable signal) is met.
• Debouncing: In digital systems, latches can help in stabilizing noisy signals, like those from mechanical
switches.

16 Flip-flop vs Latch

Latch
➢ Exhibits two stable operating points and one unstable operating point
➢ The latch needs to be triggered to change the stage
➢ The latch together with the triggering circuitry forms a flip-flop.
Latches and flip-flops are the basic building blocks of sequential circuits. Flip-flops can be either simple (transparent
or opaque) or clocked (synchronous or edge-triggered). Although the term Flip-flop has historically referred
generically to both simple and clocked circuits, in modern usage it is common to reserve the term Flip-flop
exclusively for discussing clocked circuits; the simple ones are commonly called latches.
Using this terminology, a latch is level-sensitive, whereas a Flip-flop is edge-sensitive. That is, when a latch is
enabled it becomes transparent, while a Flip-Flop's output only changes on a single type (positive going or negative
going) of clock edge.
➢ Fllp-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its
output only at times determined by a clocking signal.
➢ Latch: bistable memory device with level-sensitive triggering (no clock), watches all of its inputs
continuously and changes its outputs, independent of a clocking signal.

17 Latch / Flip-flops

The S-R (Set-Reset) Flip-flop is the simplest Flip-flop of all and easiest to understand. It is basically a device that
has two outputs, one output (Q) being the inverse or complement (Q') of the other, and two inputs. A pulse on one
of the inputs takes on a particular logical state. The outputs will then remain in this state until a similar pulse is
applied to the other input. The two inputs are called the Set and Reset inputs (sometimes called the Preset and Clear
inputs). Such a Flip-Flop can be made simply by cross-coupling two inverting gates either NAND or NOR gate
could be used Figure (a) shows an RS Flip-flop using NAND gates and Figure (b) shows the same circuit using
NOR gates.

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 Figure c: RS latch timing diagram

18 SR Flip-Flop

Coin Flip: Head/Tail (1 /0) Flip-Flop- switches back and forth between its possible output states.
A FF input has to be pulsed momentarily to cause a change in the FF output state, and the output will remain in that
state even the input pulse is over. In digital circuits, the flip-flop is a kind of bistable multivibrator. It is a Sequential
Circuits, an electronic circuit that has two stable states and thereby is capable of serving as one bit of memory, bit
1 or, bit 0.

• Whenever we refer to the state of the flip-flop, we refer to the state of its normal output (Q).
• Flip-flop circuit has a set input (S) and a reset input (R).
• Flip-flops have two outputs Q and Q'
• The set input causes the output of 0 (top output) and 1 (bottom output). The circuit outputs depend on the inputs
and also on the outputs.
The circuit is- SET means output =1
RESET means output = 0
Due to time-related characteristics of the Flip-flop:
- Qtn or Q: is the present state
- Qtn+ or Q+: is the next state

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
Truth Table of SR flip-flop:
Input Output Output
pulse now Qtn next Qtn+1 State Status
S R Q Q' Q Q'
No change output
1 1 0 1 0 1 Normal resting state Hold
1 on Q is remembered

SET mode
0 1 0 1 1 0 Set Q to 1
Storing 1

RESET mode
Reset
1 0 1 0 0 1 Storing 0
(i.e., Normal resting state)
Clear

Turn to Set and Reset at the INVALID/PROHIBITED

0 0 0 1 1? 1?
same time! Not allowed

An SR FIlp Flop is an arrangement of logic gates that maintains a stable output even after the inputs are turned off.
Table 1 Simple Truth table for the NAND S-R Flip-Flop
S R Q
0 0 Indeterminate
0 1 Set (1)
1 0 Reset (0)
1 1 No change

Table 2: Simple Truth table for the NOR Gate S-R Flip-Flop
S R Q
0 0 No change
0 1 Reset (0)
1 0 Set (1)
1 1 Indeterminate

19 Clocked SR Flip Flop

The SR latch Hip-flop required direct input but no clock. It is very useful to add a clock to control precisely the
time at which the Flip-Flop changes the state of its output.
In the clocked S-R Flip-Flop the appropriate levels applied to their inputs are blocked till the receipt of a pulse from
another source called clock. The Flip-Flop changes state only when the clock pulse is applied depending upon the
inputs. The basic circuit is shown in Figure 7. This circuit is formed by adding two AND gates at inputs to the Flip-
Flop. In addition, to control inputs Set (S) and Reset (R), there is a clock input (C) also.

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 Input pulse Output
̅̅̅̅̅̅ Status
CLK S R Q n+1 Q n+1

̅̅̅̅n No change
1 0 0 Qn Q

1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 1? 1? Indeterminate

a) Clocked RS Flip-flop b) Excitation table for SR flip-flop.

Figure: S-R latch using NAND gates with an additional enable (CLOCK) input.

20 D Flip-Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R
inputs. It has only one input. The input data appears at the output after some time. Due to this data delay between
input and output, it is called Delay Flip-flop. S and R will be complements of each other due to the NAND inverter.
A D type (Data or delay Flip-Flop) has a single data input in addition to the clock input as shown in Figure 8.

a) Block diagram b) Circuit diagram

Figure 7: Clocked D Flip-Flop
Basically, such type of Flip-Flop is a modification of clocked RS Flip-Flop gates from a basic Latch Flip-flop, and
NOR gates modify it into a clock RS Flip-Flop. The D input goes directly to the S input and its complement through
the NOT gate, is applied to the R input.
This kind of Flip-Flop prevents the value of D from reaching the output until a clock pulse occurs. The action of
the circuit is straightforward as follows:
When the clock is low, both AND gates are disabled, therefore D can change values without affecting the value of
Q. On the other hand, when the clock is high, both AND gates are enabled. In this case, Q is forced equal to D when

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
the clock again goes low, and Q retains or stores the last value of D. The truth fable for such a Flip-Flop is as given
below in Table 7.
Table 7: Excitation table for D Flip-Flop

Input pulse Output

Status
CLK D Q n+1 ̅̅̅̅̅̅
Q n+1

1 0 0 1 Reset

1 1 1 0 Set

21 JK Flip-Flop

One of the most useful and versatile Flip-Flops is the JK Flip-Flop (Jack-Kilby) the unique features of a JK Flip-
Flop are:
if the J and K input are both at 1 and the clock pulse is applied, then the output will change state, regardless of its
previous condition.
if both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output. There is no
indeterminate condition, in the operation of JK Flip-Flop i.e., it has no ambiguous state. The circuit diagram for a
JK Flip-Flop is shown in Figure 9.

a) Block diagram b) Circuit diagram

Figure 9: Clocked JK Flip-Flop

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
 Figure 10: Dual JK Flip-flop 74LS73: IC version

➢ When J = 0 and K 0 These J and K inputs disable the NAND gates, therefore clock pulse has no effect on
the Flip-Flop. In other words, Q returns its last value,
➢ When J = 0 and K 1, The upper NAND gate is disabled the lower NAND gate is enabled if Q is 1 therefore,
Flip-Flop will be reset (Q = 0, Q' =1) if not already in that stale.
➢ When J = 1 and K = 0 The lower NAND gate is disabled and the upper NAND gale is enabled if Q' is at 1,
As a result, we will be able to set the Flip-Flop (Q = 1, Q' = 0) if not already set
➢ When J = 1 and K = 1
➢ If Q = 0 the lower NAND gate is disabled the upper NAND gate is enabled. This will set the Flip-Flop and
hence Q will be 1. On the other hand if Q = 1, the lower NAND gate is enabled and Flip-Flop will be reset
and hence Q will be 0. In other words, when J and K are both high, the clock pulses cause the JK Flip-Flop
to toggle. The truth table for JK Flip-Flop is shown in the table:

Table: Excitation table for JK Flip-Flop

Input pulse Output Now Output next

Status
CLK J K Qn ̅̅̅̅n
Q Q n+1 ̅̅̅̅̅̅
Q n+1
0 1 0 1
No change
1 0 0 1 0 1 0
(Q n ) ̅̅̅̅n )
(Q
0 1 1 0
1 1 0 Set
1 0 1 0

1 0 0 1
1 0 1 Reset
0 1 0 1

0 1 1 0
1 1 1 Toggle
1 0 0 1
̅̅̅̅n )
(Q (Q n )

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
22 Toggle Flip-Flop /T Flip Flop

Toggle flip-flop is basically a JK flip-flop with J and K terminals permanently connected together, It has only input
denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the
block diagram.

a) Block Diagram
b) Circuit diagram
Figure 12: Toggle Flip Flop / T Flip Flop
Table: Truth table for Toggle Flip-Flop / T Flip-Flop

Input pulse Output Now Output next

Status
CLK T Qn ̅̅̅̅n
Q Q n+1 ̅̅̅̅̅̅
Q n+1
0 1 0 1
No change
1 0 1 0 1 0
(Q n ) ̅̅̅̅n )
(Q
0 1 1 0
1 1 Toggle
1 0 0 1
̅̅̅̅n )
(Q (Q n )

23 Master-Slave JK Flip-Flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with
the slave having an inverted clock pulse. The outputs from Q and Q ̅ from the "Slave" Flip-flop are fed back to the
inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave"
flip-flop.

𝑄𝑚
𝑄𝑠

a) Block diagram b) Circuit diagram

Figure 14: Master-Slave JK Flip-Flop

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
The Master-Slave Flip-Flop is basically a combination of two flip-flops (JK or SR) connected together in a series
configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop
is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop. In
addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse in such
a way that the inverted clock pulse is given to the slave flip-flop. In other words if clock pulse =0 for a master flip-
flop, then clock pulse =1 for a slave flip-flop and if clock pulse =1 for master flip flop then it becomes 0 for slave
flip flop. Working of a master slave flip flop –

• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The
slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is passed from
the master flip-flop to the slave and output is obtained.
• Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so
the master responds before the slave.
• If J=0 and K=1, the high 𝑄̅ output of the master goes to the K input of the slave and the clock forces the
slave to reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition
of the clock sets the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative
transition of the clock.
• If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023
24 References:

➢ Digital Systems Principles and Applications – Ronald Tocci

➢ https://www.electronics-tutorials.ws/sequential/seq_1.html
➢ https://www.circuitstoday.com/triggering-of-flip-flops
➢ https://www.geeksforgeeks.org/master-slave-jk-flip-flop/

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Md. Saifur Rahman, Assistant Professor, Department of Physics, University of Rajshahi/4H/Chapter-6/2023