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DSD Project

DSD project

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deepakvashishtt
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59 views4 pages

DSD Project

DSD project

Uploaded by

deepakvashishtt
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXPERIMENT – 10

AIM - To Design a 4-bit Binary Counter using VHDL and Verilog programs.

Apparatus Required: Xlinix Vivado Software.


Theory: A binary counter is a digital sequential circuit used for counting the number
of clock pulses in binary format. It is a type of counter circuit that counts in binary
numbers (0, 1, 10, 11, and so on). It is widely used in digital electronics for time
measurement, frequency division, or counting events.
Working Principle
A binary counter consists of a series of flip-flops connected in cascade. The flip-flops
toggle (change their state) in response to a clock signal. Each flip-flop represents one
bit, and the counter output is the binary representation of the number of pulses
counted.
The counter increases or decreases its value by one with each clock pulse,
depending on whether it is configured as an up-counter or a down-counter.
Verilog Implementation
module binary_counter (
input wire clk, // Clock signal
input wire reset, // Synchronous reset signal
output reg [3:0] count // 4-bit counter output
);
always @(posedge clk) begin
if (reset)
count <= 4'b0000; // Reset counter to 0
else
count <= count + 1; // Increment counter
end
endmodule
VHDL Implementation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_counter is
Port (
clk : in STD_LOGIC; -- Clock signal
reset : in STD_LOGIC; -- Synchronous reset signal
count : out STD_LOGIC_VECTOR(3 downto 0) -- 4-bit counter output
);
end binary_counter;
architecture Behavioral of binary_counter is
signal count_reg : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- Internal register
for the counter
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
count_reg <= "0000"; -- Reset counter to 0
else
count_reg <= count_reg + 1; -- Increment counter
end if;
end if;
end process;
count <= count_reg; -- Assign internal register to output
end Behavioral;
OUTPUT

RESULT
4-bit Binary Counter has been successfully implemented using Verilog and VHDL

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