Experiment No.

AIM: To write a verilog program for basic logic gates to synthesize and simulate using Xilinx software
tool.

SOFTWARE REQUIRED:
1. Xilinx ISE Design Suite 14.1

2. Spartan3E kit

THEORY:

AND GATE:

The AND gate performs logical multiplication which is most commonly known as the AND junction.
The operation of AND gate is such that the output is high only when all its inputs are high and when
any one of the inputs is low the output is low.

Y=a & b

OR GATE:

The OR gate performs logical addition which is most commonly known as the OR junction. The
operation of OR gate is such that the output is high only when any one of its input is high and when
both the inputs are low the output is low.

Y=a | b

NOT GATE:

The Inverter performs a basic logic gate function called Inversion or Complementation. The purpose of
an inverter is to change one logic level to opposite level. When a high level is applied top an inverter,
the low level will appear at the output and vice versa.

Y= ~a

NAND GATE:

The term NAND is derived from the complement of AND. It implies the AND junction with an
inverted output. The operation of NAND gate is such that the output is low only when all its inputs are
high and when any one of the inputs is low the output is high.

Y= ~ (a & b)
NOR GATE:

The term NOR is derived from the complement of OR. It implies the OR junction with an inverted
output. The operation of NOR gate is such that the output is high only when all its inputs are low and
when any one of the inputs is high the output is low,

Y= ~(a | b)

EX-OR GATE:

The output is high only when the inputs are at opposite level.

Y=a ^ b

EX-NOR GATE:

The output is high only when the inputs are at same level.

Y= ~(a ^ b)

RESULT:

Thus the basic logic gates verilog program for to synthesize and simulate using Xilinx software
tool was verified.
 Experiment No. 2
AIM: To write a verilog program for half adder and full adder to synthesize and simulate using
Xilinx software tool.

SOFTWARE REQUIRED:
1. Xilinx ISE Design Suite 14.1
2. Spartan3E kit

THEORY:

HALF ADDER:

The half adder consists of two input variables designated as Augends and Addend bits. Output
variables produce the Sum and Carry. The carry output is 1 only when both inputs are 1 and sum is 1 if
any one input is 1. The Boolean expression is given by,

sum = x ^ y
carry = x & y
FULL ADDER:

A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. In consists of 3
inputs and 2 outputs. The third input is the carry from the previous Lower Significant Position. The
two outputs are designated as Sum (S) and Carry (C). The binary variable 5 gives the value of the LSB
of the Sun. The output S-1 only if odd number of 1" s are present in the input and the output C-1 if two
or three inputs are 1.

sum= x ^ y ^ z

carry = (x & y) | (y & z) | (x & z)

PROCEDURE:

1. Click on the Xilinx ISE Design Suite 14. for Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.

5. The output can be observed by using model sim.

PROGRAM:

HALF ADDER

module
halfadder (a,b,sum, carry) ;
input a,b;
output sum,carry;
xor(sum,a,b);
and (carry,a,b) ;
endmodule

FULL ADDER

module full_adder
(a,b,c,sum, carry) ;
output sum,carry ;
input a,b,c ;
assign sum =a ^ b ^ c;
assign carry = (a&b) | (b&c)
(c&a);
endmodule

RESULT

Thus the for half adder and full adder verilog program for to synthesize and simulate using
Xilinx software tool was verified.
 Experiment No. 3
AIM: Common Drain Amplifier Circuit simulation using LTSpice.

SOFTWARE REQUIREMENT: S-edit tanner tool

THEORY:

The Common drain amplifier is a single transistor MOSFET amplifier, one of the basic fundamental
MOSFET amplifiers. The Common drain amplifiers are different from Common Source
Amplifier where the resistor connected across the drain.

The Common Drain Amplifier has

1) High Input Impedance

2) Low Output Impedance

3) Sub-unity voltage gain

Because of its low output impedance, it is used as a buffer for driving the low output impedance load.
Often in multistage amplifiers, while driving low impedance load, the source follower is used as an
output stage.

CIRCUIT DIAGRAM:

SIMULATION RESULTS:
 Experiment No. 4
AIM: To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic
entry.

FACILITIES REQUIRED:
1. S-Edit using Tanner Tool

PROCEDURE:
1. Draw the schematic of differential amplifier using S-edit and generate the symbol.
2. Draw the schematic of differential amplifier circuit using the generated Symbol.
3. Perform AC Analysis of the differential amplifier.
4. Obtain the frequency response from W-edit.
5. Obtain the spice code using T-edit.
SCHEMATIC DIAGRAM:
RESULT:

Thus the differential amplifier bandwidth and CMRR are calculated was verified through
schematic entry.
 Experiment No. 5
AIM: To simulate the schematic of the operational amplifier.

Tool:

Multisim 11.0.

Theory:

A Function generator is a circuit which generates Sine wave, square wave and Triangular wave. In our
design the circuit is an OP-AMP based square wave generator for producing the square wave and
two OP-AMP based integrators for the generation of triangular wave and sine wave as shown in the
above block diagram. Figure 3.1 shows the circuit diagram of the function generator. The square wave
generator section and the integrator section of the circuit are explained in detail below:

Square Wave Generator:

The square wave generator is based on a 741 OP-AMP IC. Resistor R1 and capacitor C1 determines
thefrequency of the square wave. Resistor R2 and R3 forms a voltage divider setup which feedbacks a
fixedfraction of the output to the non-inverting input of the IC. Initially, when power is not applied the
voltageacross the capacitor C1 is 0. When the power supply is switched on, C1 starts charging through
the resistorR1 and the output of the OP-AMP will be high (VCC). A fraction of this high voltage is fed
back to thenon-inverting pin by the resistor network R2, R3. When the voltage across the charging
capacitor isincreased to a point where the voltage at the inverting pin is higher than the non-inverting
pin, the outputof the OP-AMP swings to negative saturation (VEE). The capacitor quickly discharges
through R1 andstarts charging in the negative direction again through R1. Now a fraction of the
negative high output(VCC) is fed back to the non-inverting pin by the feedback network R2, R3. When
the voltage across thecapacitor has become so negative that the voltage at the inverting pin is less than
the voltage at the non-inverting pin, the output of the OP-AMP swings back to the positive saturation.
Now the capacitordischarges trough R1 and starts charging in positive direction. This cycle is repeated
over time and theresult is a square wave swinging between VCC (+15 V) and VEE (-15 V) at the
output of the OP-AMP.If the values of R2 and R3 are made equal, then the frequency of the square
wave can be expressed usingthe following equation.

f=1/2.1976R1C1

Integrator:

Next part of the function generator is the OP-AMP integrator The OP-AMP IC used in this stage is
also741. Resistor R4 in conjunction with R7 sets the gain of the integrator and resistor R4 in
conjunction withC2 sets the bandwidth. The square wave signal is applied to the inverting input of the
OP-AMP throughthe input resistor R7. The output of the first integrator will be a triangular wave
which is again applied toanother integrator which produces sine wave.

Circuit Diagram:

The following figure shows the circuit diagram of the function generator.
Result and Analysis:

Figure 3.3 shows the output of the function generator on a 4-channel oscilloscope.We have set the
amplitude scale at 10 V/division for channel A (Square wave) while for channel B(Triangular wave)
and C (Sine Wave) it is set to 5V/division.

Conclusion:

Waveform has been generated.

Possible sources of error:

1.Observational error

2.Gross error

Precautions:

1.Make sure the connections are correct.

2.Always ground the circuit.

 Experiment No. 6
AIM: To Design of 3-8 decoder using MOS technology.

SOFTWARE REQUIREMENTS: S-edit tanner tool

THEORY:

DECODER: In this tutorial, you learn about the Decoder which is one of the most important topics
in digital electronics. In this article we will talk about the Decoder itself, we will have a look at the 3 to
8 decoder, 3 to 8 line decoder designing steps, a technique to simplify the Boolean function, and in the
end, we will draw a logic diagram of the 3 to 8 decoder.

A digital decoder converts a set of digital signals into corresponding decimal code. A decoder is also
the most commonly used circuit prior to the use of an encoder. The encoded data is decoded for the
user interface in most of the output devices like monitors, calculator displays, printers, etc.

Difference Between Encoder and Decoder: On the contrary, a decoder accepts binary code as its
input. An encoder is a device that converts the active data signal into a coded message format.
However, a decoder performs the inverse operation of the encoder and thus converts the coded input
into original data input.

3 to 8 Decoder designing steps

 Problem: 3 to 8 line decoder.

 The number of available inputs are 3 and outputs are 8.

 Let us represent the inputs and outputs by symbol letters. Let us represent the inputs by x, y,
and z; and the outputs by D0, D1, D2, … D7.

 3 to 8 Decoder Truth Table:

Shemantic of 3:8 Decoder

RESULTS: Design of 3:8 decoder using MOS technology.

 Experiment No. 7
AIM: To design 4x1 digital multiplexer using pass transistor and transmission gate logic.

Introduction

A multiplexer or mux is a combinational circuits that selects several analog or digital input signals
and forwards the selected input into a single output line. A multiplexer of 2 n inputs has n selected lines,
are used to select which input line to send to the output.

Fig.1: The schematic diagram, boolean equation and the truth table of a 2:1 multiplexer with
inputs A and B, select input S and the output Z.

Figure 2 shows how a 4:1 MUX can be constructed out of two 2:1 MUXs.

Fig.2: Implementation of 4:1 MUX using 2:1 MUXs

Design using pass-transistor logic

A multiplexer can be designed using various logics. Fig.3 shows how a 2:1 MUX is implemented using
a pass-transistor logic

.
Fig.3. Design of a 2:1 MUX using pass-transistor logic

The pass-transistor logic attempts to reduce the number of transistors to implement a logic by allowing
the primary inputs to drive gate terminals as well as source-drain terminals. The implementation of a
2:1 MUX requires 4 transistors (including the inverter required to invert S), while a complementary
CMOS implementation would require 6 transistors. The reduced number of devices has the additional
advantage of lower capacitance.

Design using transmission gate logic

A transmission gate is an electronic element and good non mechanical relay built with CMOS
technology. It is made by parallel combination of nMOS and pMOS transistors with the input at the
gate of one transistor (C) being complementary to the input at the gate () of the other. The symbol of a
transmission gate is shown below in fig.4.

Fig.4: Symbol for transmission gate

The transmission gate acts as a bidirectional switch controlled by the gate signal C. When C=1, both
MOSFETs are on, allowing the signal to pass through the gate. In short, A=B, if C=1. On the other
hand, C=0, places both transistors in cut-off, creating an open circuit between nodes A and B. Fig.5
shows the implementation of a 2:1 MUX using transmission gate logic.

Fig.5: Circuit diagram of a 2:1 MUX using transmission gate logic

Here, the transmission gates selects input A or B on the basis of the value of the control signal S.
When S=0, Z=A and when S=1, Z=B.
 Experiment No. 8
AIM: To write a verilog program for various flip flops to synthesize and simulate using Xilinx
softwartool.

Software Required:
1. Xilinx ISE Design Suite 14.1
2. Spartan3E kit

THEORY:

D-FLIP FLOP:

It has only a single data input. That data input is connected to the S input of RS-flip flop, while the
inverse of D is connected to the R input. This prevents that the input combination ever occurs. To allow
the flip flop to be in holding state, a D-flip flop has a second input called “clock” .The clock input is
AND-ed with the D input, such that when clock=0, the R and S inputs of the RS-flip flop are 0 and the
state is held.

D-LATCH:

It has only a single data input. That data input is connected to the S input of RS-flip flop, while the
inverse of D is connected to the R input. This prevents that the input combination ever occurs. To allow
the flip flop to be in holding state, a D-flip flop has a second input called “enable”. The enable input is
AND-ed with the D input, such that when enable=0, the R and S inputs of the RS-flip flop are 0 and
the state is held.
D FLIP FLOP:

module D_Flip _Flop

(Q,clk,reset,d);
output Q;
input clk,reset,d;
reg Q;
always @(posedge clk)
if (reset)
begin
Q <= 0;
end
else begin
Q <= d;
end
endmodule
T FLIP FLOP:

module T Flip Flop

(Q,clk,reset,t);
output Q;
input clk,reset,t;
reg Q;
always @(posedge clk)
if (reset)
begin
Q <= 0;
end
else if (t == 0)
begin
Q <= Q;
end
else if (t == 1)
begin
Q <= ~Q;
end
endmodule

PROCEDURE:

1. Click on the Xilinx ISE Design Suite 14.lor Xilinx Project navigator icon on the
desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

RESULT:

Thus the various flip flops verilog program for to synthesize and simulate using Xilinx
software tool was verified.
 Experiment No. 9

AIM

To design and implement the layout of PMOS and NMOS transistors using CMOS technology, verify
compliance with design rules, and validate the functionality of the design through simulation.

THEORY

Introduction to Transistors in CMOS:

 PMOS (P-channel MOSFET): Operates when a negative voltage is applied to the gate, placed in an
n-well region.
 NMOS (N-channel MOSFET): Operates when a positive voltage is applied to the gate, placed in a p-
substrate.

Key Layers in Layout Design:

1. Active Area (Diffusion): Defines source and drain regions.

2. Polysilicon (Gate): Forms the transistor's control gate.
3. Well Regions: PMOS requires an n-well, and NMOS resides in the p-substrate or p-well.
4. Contacts: Metal connections for the source, drain, and gate.
5. Metal Layers: Used for interconnections between transistors and other components.

Design Constraints:

 Minimum Feature Size: Dependent on the technology node (e.g., 180 nm, 65 nm).
 Spacing and Overlap Rules: Ensure manufacturability and prevent electrical short circuits.

Transistor Design Rules:

1. Maintain proper spacing between layers.

2. Ensure well contacts to prevent floating wells.
3. Use guard rings or isolation to avoid latch-up.

PROCEDURE

1. Set Up the Design Environment:

2. Layout Design for NMOS Transistor:
o Active Area: Draw the p-substrate region and define n+ diffusion for source and drain.
o Gate: Place a polysilicon layer perpendicular to the diffusion area.
o Contacts: Add metal contacts to the source, drain, and gate regions.
o Connections: Use metal layers to connect terminals.
3. Layout Design for PMOS Transistor:
o N-Well: Draw an n-well region for the PMOS transistor.
o Active Area: Define p+ diffusion for source and drain regions within the n-well.
 o Gate: Place a polysilicon layer across the active area.
o Contacts and Connections: Add metal contacts and interconnections as required.
4. Combine PMOS and NMOS for CMOS:
o Align the PMOS and NMOS transistors such that their gates are shared (common gate
connection).
o Place power rails:
 VDD (Power Supply): Connected to the PMOS source.
 VSS (Ground): Connected to the NMOS source.
5. Verification Steps:
o Perform Design Rule Check (DRC): Ensures the layout adheres to the fabrication rules.
o Conduct Layout Versus Schematic (LVS): Verifies the layout matches the circuit schematic.
o Extract parasitic elements for simulation.
6. Simulation:
o Simulate the designed layout to verify transistor behavior and circuit performance.

RESULT

1. The layouts of PMOS and NMOS transistors were successfully designed.

2. DRC Results: Passed without any errors, indicating adherence to design rules.
3. LVS Results: Passed, confirming that the layout matches the circuit schematic.
4. The designed transistors exhibit the expected electrical characteristics during simulation.
 Experiment No. 10
AIM: To perform the functional verification of the CMOS Inverter through schematic entry.

FACILITIES REQUIRED:
1. S-Edit using Tanner Tool

PROCEDURE:

1. Draw the schematic of CMOS Inverter using S-edit

2. Perform Transient Analysis of the CMOS Inverter
3. Obtain the output wave form from W-edit
4. Obtain the spice code using T-edit

THEORY:

Inverter consists of nMOS and pMOS transistor in series connected between VDD and GND.
The gate of the two transistors are shorted and connected to the input. When the input to the inverter
A =0, nMOS transistor is OFF and pMOS transistor is ON. The output is pull-up to VDD.When the
input A=1, nMOS transistor is ON and pMOS transistor is OFF. The Output is Pull-down to GND.

CMOS INVERTER:
RESULT

Thus the functional verification of the CMOS Inverter was verified through schematic entry.