Date of Examination : 27. 05.

2021

AHSANULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

Department : Electrical and Electronic Engineering
Program : Bachelor of Science in Electrical and Electronic Engineering
Semester Final Evaluation, Spring 2020
Year: 4th Semester: 1st

Course No: EEE 4133 Course Name: VLSI-I

Time: 3(Three) hours Full marks: 60

Use Single answer script

Instructions: i) Answer script should be hand written and should be written in A4 white
paper.You must submit the hard copy of this answer script to the Department
when the university reopens.
ii) You must write the following information at the top page of each answer
script:
Department: Program:
Course no: Course Title:
Examination: Semester (Session):
Student ID: Signature and Date:
iii) Write down Student ID, Course number and put your signature on top of
every single page of the answer script.
iv) Write down page number at the bottom of every page of the answer script.
v) Upload the scan copy of your answer script in PDF format through
provided google form at the respective course site (i.e., google classroom)
using institutional email within the allocated time. Uploading clear and
readable scan copy (uncorrupted) is your responsibility and must cover the
full page of your answer script. However, for clear and readable scan copy
of the answer script student should use only one side of a page for
answering the questions.
vi) You must avoid plagiarism, maintain academic integrity, and ethics. You
are not allowed to take any help from another individual and if taken so can
result in stern disciplinary actions from the university authority.
vii) Marks allotted are indicated in the right margin.
viii) Necessary charts/tables are attached at the end of the question paper. You
may use graph papers where necessary.
ix) Assume any reasonable data if needed.
x) Symbols and characters have their usual meaning.
xi) Before uploading rename the PDF file as CourseNo_StudentID.pdf
e.g., EEE4133_170105001.pdf

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 There are 7 (Seven) Questions.
Answer Questions no. 1, 5 and any other 3 (three) from the rest 5 (Five)

1. a. Construct a stick diagram for the following Boolen equation (It depends on your student ID) and 6
estimate the silicon area
Ā= {(X logic_1 Y) + (P logic_2 Q)}+ M logic_3 XY
logic_1, logic_2 and logic_3 are to be selected from the follwing table based on the last 3 digits
(7th, 8th and 9th digit) of your Student ID:

7th digit logic_1 8th digit logic_2 9th digit logic_3

0 XOR 0 AND 0 NOR
1 AND 1 OR 1 XNOR
2 XNOR 2 OR 2 AND
3 NAND 3 AND 3 XOR
4 NOR 4 AND 4 XOR
5 XOR 5 OR 5 NAND
6 XNOR 6 AND 6 OR
7 XNOR 7 OR 7 AND
8 NOR 8 OR 8 NAND
9 NAND 9 AND 9 XOR

Example of generting your own Boolean equation: If your student ID is: 170105247, then 7th,
8th and 9th digits are 2, 4 and 7 respectively. And the logic_1, logic_2 and logic_3 are XNOR,
AND and AND gates respectively (shown in table as bold). So your Boolean equation will be as
follows:
Ā= {(X XNOR Y)+(P AND Q)}+ M AND XY
̅̅̅̅̅̅̅̅̅̅
𝐴̅ = {(𝑋 𝑌) + 𝑃𝑄} + 𝑀𝑋𝑌
b. For a transmission gate, the input and output volages (in volt) are represented by 0.5+7th digit and 6
0.3+9th digit of your students ID respectively. Threshold voltage is ±0.8 volt and supply voltage
(Vdd) is 10.0 volt. Calculate the total current following through the transmission gate.

2. a. Evaluate the time delay for the circuit representing by the Boolean equation of Question No. 1(a) 6
by employing linear model. Consider the circuit has a fanout of 5.
b. An IC contains 500 units of 2 inputs multiplexer circuits, which were fabricated in 32nm 6
technology.The capacitance is 0.08 fF/unit. Estimate the average dynamic power dissiation of the
IC during the operation at 2 GHz with a supply voltage of 1.2 volt.

3 a. For an inverter circuit, show that the noise marging for logic 1 (high) is given by: 6
(𝑉𝑑𝑑 +𝑉𝑡𝑝 +𝑘(2𝑉𝑜𝑢𝑡 +𝑉𝑡𝑛 )
𝑉𝑑𝑑 − 1+𝑘
where k=βn /βp

b Design a 2:1 MUX circuit with minimum number of transistors (Not more than 3 transistors). 6

4 a. For a transmission gate, show that the current flows only through the pMOS transistor, when high 6
input (logic 1) signal is applied.
b What type of Tap do you use in fabricating CMOS and what is the purpose of using that? Illustrate 6
with detail diagram.
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 5. a. Investigate the following CMOS diagram and draw a truth-table, then find the Boolen 6
expressions of the output Y. P1 to P5 are pMOS and N1 to N5 are nMOS transistors.

b. Simplify the circuit of Question No. 5(a) and then construct the circuit by using pass transistor 6
logic.

6 a Design the CMOS diagram of the following stick diagram. 6

b Calculate the parasitic delay for the circuit represented by the stick diagram of Question No. 6(a). 6

7 a Explain the operation of a 6-transistor static RAM for loading ‘0’ by overwriting ‘1’ and estimate 6
the cell ratio to avoid the problem of over writing.
b Analyze the non-ideal effect of DIBL in nMOS transistor current. 6

For Instructor’s Use Only

1(a)- CO2 1(b)- CO3 2(a)- CO3 2(b)- CO3 3(a)- CO3 3(b)- CO2 4(a)- CO1
4(b)- CO1 5(a)- CO1 5(b)- CO4 6(a)- CO2 6(b)- CO4 7(a)- CO4 7(b)- CO1

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