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Advanced_VLSI_QP3 (B)Final (1) (1)

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12 views

Advanced_VLSI_QP3 (B)Final (1) (1)

Uploaded by

Sowmya Bhat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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USN

SHRI MADHWA VADIRAJA INSTITUTE OF TECHNOLOGY & MANAGEMENT,


BANTAKAL
Department: ECE IA- III Academic Year: 2024-25
Class: VII ‘A’ & ‘B’ Course: Advanced VLSI Course Code: 21EC71
Date: 16/12/2024 Duration: 60 minutes Max. Marks: 20
QP Version: B
Note: Answer the following questions
Qn Ma
Question PI* BL TL
. rk
* O*
No s
Explain the purpose of a test bench in the verification 5 1.2. L2 3.
process. 1 1
1.a
1.b When would you prefer to use an associative array over a 5 1.2. L3 3.
queue in SystemVerilog? Justify your choice with an example. 1 2
OR

Explain the different testbench layers with the help of neat 1.2.
2.a diagrams. 5 1 L3 3.
1
What factors influence the width of an expression in 2.1.
2.b SystemVerilog, and how can you control it? 5 3 L2 3.
3

Describe the communication between DUT and testbench with 5 2.1.3 L3 4.


3.a suitable diagram and System Verilog code. 2
3.b Define Routing and explain various types of routing with the 5 1.2.1 L3 2.
help of neat diagrams. 3
OR
What is randomization? Explain randomization in system 5 1.2.1 L3 5.
4.a 1
verilog.
Why is functional coverage important in verification, and how 5 1.2.1 L3 5.
4.b 2
does it differ from code coverage?
BL* Bloom’s Taxonomy Level; TLO* Topic Level Outcome; PI- Performance Indicator

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