IIBRARY

U.S. NAVAL POSTGRAOaATf $CHC(5t

MONTEREY, CALIFORNIA
 -

UNITED STATES
NAVAL POSTGRADUATE SCHOOL

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THESIS

MAG>ffiTIC-<:ORE LOGIC FOR DIGITAL COMPUTERS

-by-

Lieutenant Charles E. Mertin, U.S.N.

-
tlAGNETIC-COHE LOGIC

FOR
DIGITAL COlvlPUTERS

Charles E, Martin
 MAGNETIC -COHE LOGIC FOR
DIGITAL COl^iPUTERS

by

Charles Elliott Martin

Lieutenant, United States Navy

Submitted in partial falf illment

of the requirements
for the degree of
MASTER OF SCIENCE
IN
ENGINEERING ELECTRONICS

United States Naval Postgraduate School

Monterey, California

19 5 5
n^sn
 This work is accepted as fulfilling

the thesis requirements for the degree of

MASTER OF SCIENCE
IN
ENGINEEHING ELECTRONICS

from the

United States Naval Postgraduate School

 PREFACE

The increasing use of digital computers, both indi-

vidually and as units of systems, and their inherent com-
plexity has led to considerable effort toward improving

their reliability. With this in mind, a project was

undertaken to investigate the feasibility of using mag-

netic cores instead of vacuum tubes in the arithmetic

unit of such computers. This involved the design and

testing of a magnetic-core shift register and circuits

to implement the logical OR and NOT operations with cores.

Using these as a basis, various logical designs for an

adder were investigated. The design of a simple all-core,

arithmetic unit is presented and compared with, its vacuiom

tube equivalent.

Most of the work described was done during the period

from January 3 "to March 18, 1955, at International Tele-
meter Corporation in Los Angeles, The author is especially

indebted to Dr. Louis N. Ridenour, Mr, Milton Rosenberg,

and Mr, Witold Modlinski for their cooperation and help-

ful suggestions during this period.

11
 TABLJi, OF CONTENTS

Item Title Page

Chapter I Introduction . 1

Chapter II Magnetic Materials 5

Chapter III Systems Considerations and

Comparisons 10

Chapter IV Test Equipment 13

Chapter V Design of Shift Register and

Logical Circuits 15

Chapter VI Adder Design 23

Chapter VII Experimental Results ......... 27

Chapter VIII Conclusions, -Recommendations,

and Possibilities 34

Illustrations AO

Bibliography $0

Appendix I Binary Logic 52

iii
 LIST OF ILLUSTRATIONS

Figure Page
1, Voltage output from switched core • • • • 40
2. Idealized slant hysteresis loop • • . . , kO

3« Operating conditions on slant-loop core • 40

4* Proposed magnetic-core arithmetic uiilt • . 41

$• Basic form of one-core-per-"blt

shift register ••••• 41

6« Basic form of two-cores-per-blt

shift register •••••41
?• Idealized square hysteresis loop
of ferrlte core ., ••.. 42
8# Time relationship of "A" and "B"
shift pulses • •••••••42
9« Logical OR circuit 42
10. Logical NOT circuit • • • 43

11. Three-Input adder •••• •• 43

12. Relationships existing In three-Input

adder of Figure 11 • .44
13. Truth table 44

14« Block diagram of modified half-adder ... 44

15 • Block diagram of full adder 45

16. Shift register output pulse , , 45

17 • Current pulse conditions In

complementing circuit ••••• 45

18. Schematic diagram of modified

half-adder 46

19. Block diagram of buffered half-adder ... 46

Iv
Figure Page
20, Block diagram of computer arithmetic
unit using magnetic cores • • , 47
21. Function table for comparison
of X and Y 48
22« Various forms of logical equations • • • 49
 LIST OF ABBREVIATIONS AND SYMBOLS

vmf Magnetomotive force

NI Ampere-turns

S/N Signal-to-noise ratio

H Coercive force or coercivity

Bp Residual flux density

Bg Saturation flux density ,

jisec Microseconds

DC Direct current

Kc Kilocycles

ma Milliamperes
H^ Applied magnetic field strength

vi
 CHAPTER I

INTRODUCTION

In the field of electronic computers of the digital

variety any physical device which exhibits two or more
stable states may be used to store information,^ Various
types of vaccum tube flip-flops have been used in this man-

ner for many years. Shortly after World War II with the ad-
vent of metals, and later ferrites, which were characterized

by relatively square hysteresis loops a new field of bista-

blli devices became available to scientists and engineers.

In general it v/as found convenient to form the magnetic core

material in the shape of a toroid. In the case of the metals

such as Deltamax and 4-79 Mo-Permallay the metal was rolled

into a thin strip which v/as generally wound on a ceramic

bobbin, proper precautions being taken to insulate one turn

from the next. The ferromagnetic ferrites were molded or

pressed into the desired toroidal form, then sintered.

The information storage is achieved by pulsing a wind-

ing which links the core with a current of magnitude suf-

ficient to cause the flux to reach a maximum along a major

hysteresis loop, either in a positive or negative direction

depending upon the sense of the drive winding. When the

1. Since most common storage devices presently in use are

restricted to two stable states the discussion v/hich
follows will be confined to bistable devices.
current pulse is removed the core returns along the loop

to its remanent state of magnetization and remains there in

the absence of further excitation. This magnetizing process

may be carried out by providing the net mmf necessary to

saturate the core by supplying current through more than

one winding simultaneously. This technique leads to the

familiar tjrpe of coincident-current magnetic-core matrix

memory which has gained considerable prominence among com-

puter storage systems in recent years as a result of its j

high reliability, high-speed random-access feature, good

S/N, potentially low cost per bit and high density storage

capacity. Such a memory consisting of 4096 words, each

40 bits long, was recently delivered to the Rand Corpo-

ration by International Telemeter Corporation,

Another computer application for v/hich magnetic cores

have recently been adopted is that of static delay lines or

shift registers in which information is propagated down a

series of cores, literally bit by bit. The method by which

this is accomplished utilizes the storage properties of the

core during part of the cycle and later the ability of the

core to act as a transformer in passing the stored informa-

tion to the following core. Inherent in such a gating oper-

ation are the possibilities of performing logical arithmetic

operations on the stored digits, either serially or in par-

allel. The purpose of the present investigation is to de-

termine the feasibility of using magnetic cores to perform

the logical operations normally handled by vacuum tubes.

The advantages are obvious. The reliability of cores is

exceedingly high. They are not subject to injury due to

accidental electrical overloads on the circuit. No deteri-

oration in the size or squareness of the hysteresis loop

has been noted as a function of aging. Once installed, main-

tenance is virtually unnecessary and, in fact, is limited

to the associated circuitry and connections, none is nec-

essary for the magnetic elements themselves. Although soae

power is required to shift the information along, none is

required to store it and a power failure does not destroy

the pattern stored. With filament heaters eliminated the

power requirements are reduced appreciably. The price of

a switch core is at present in the order of a dollar or less,

most of this due to the cost of testing and grading and there

is good reason to believe that mass production can be expected

to reduce the cost to about a tenth of this figure. The nu-

merical relationship between cores and tubes in performing

computing functions is difficult to establish generally, but
seems to run about one to one. Although' at present the current

pulses used to drive the cores are generally formed by vacuum

tubes, techniques common to pulse radar could be used to

relegate this function, too, to magnetic cores or saturable

reactors. The concept, then, of an electronic computer de-

void of vacuum tubes or transistors is not unthinicable.

The purpose of this thesis was to investigate the var-

ious implications of such a system including the properties

of the magnetic components themselves, the associated cir-

cuitry both from a logical design basis and electronic de-

sign practice, and the entire systems concept.

The design, construction, and testing of a magnetic-

core shift register are described. The various logical oper-

ations of binary arithmetic are investigated from the stand-

point of cores and circuits are described which were success-

fully used to perfonn these operations. Two types of adders

are discussed and the relative advantages and practical dif-

ficulties of each are considered. Finally, further possibil-

ities in the field of magnetic core logic are indicated.

It is concluded that an all-core, i,e,, no vacuum tubes

or transistors, computing system is completely feasible and

the design of a simple system of this type is presented. The

timing problems which occur in the logical portion of the sys-

tem Impose some degree of limitation upon the speed with which

the remainder of the system might theoretically operate, how-

ever, this restriction appears not to be too serious.

The experimental results of this investigation, together

with an analysis based on these results, Indicate the types

of logical operations which may be performed with cores, the

speed that may be obtained, the power requirements, and the

timing conditions that must be met. It is shown that magnet-

ic-core logic of the type discussed offers the advantages of

environmental ruggedness, general reliability, and economy

of size and power in systems operating below approximately

100 Kc.
 CHAPTER II
lUGNETIC MATERIALS

The recent widespread adoption of magnetic elements as

digital computer components has stimulated considerable re-

search in magnetic materials. For most computer applications

the desirable characteristics of a magnetic material are a

relatively square hysteresis loop, a short switching time,

and a low coercive force. In addition, the cores should be

easily manufactured in large quantities with a high degree of

uniformity.

Although this paper is v/ritten from an enginesring view-

point, it seems desirable to include at this point a brief

summary of some of the physicists' basic theory of the flux-

reversal mechanism in polycrystalline materials. Much work

in this field has been done recently by Goodenough /3,4/,

Menyuk /37, Kittel /"6/, Bozorth /!/ and others.

The latest theory of magnetization assumes that the mag-

netic material is composed of a number of small regions called

domains, within each of which the local magnetization is sat-

urated. The direction of magnetization of the various do-

mains need not necessarily be parallel however.

According to this domain theory of magnetization the

reversal of induction in a core results chiefly from the

nucleation of domains of reverse magnetization and motion of

the 180° Bloch walls which separate the grov/ing domains. The

centers of nucleation from which the domains of reverse mag-

netization first grow occur at lattice imperfections which
are, in most cases, grain boundaries. The squareness of the

hysteresis loop depends on the degree of alignment of the

axes of easy magnetization in the individual grains. For

this reason treatments such as magnetic anneal, grain ori-

entation, and the application of mechanical stress are

commonly used to further this alignment.

The switching time necessary for a complete flux rever-

sal within the core is directly related to the velocity of

the domain wall movement. This velocity is in turn limited

by a viscous damping term which is composed of two factors.

The first is a function of eddy currents and is negligible

in either ultra-thin metal tapes (of the order of 1/8 mil)

or in the ferrites which have resistivities of about 10

ohm-cm which is some lO-^^ times that of the metals. The

second factor is the relaxation contribution which arises

from the delayed response of the electron spin vectors in

aligning themselves in the direction of the applied field,

A switching coefficient, S^, has been de.fined as:

where Hjj^ is the applied field

Hq is the threshold field for irreversible

domain wall motion
and T is the switching time.

For a given material S is essentially constant for E^TiEfy

implying the inverse relationship of T and the .applied field.

S^ for metal cores is about half that for the ferrites.
Since, however, Hjj^ is limited to about 2Hq for coincident,

current memory applications, ferrite cores switch faster

solely by virtue of their higher coercivity. This fact,

coupled with the large number of cores usually needed for

practical memory applications, has lead to the almost exclu-

sive use of ferrite cores in memories. The S-1 ferrite

material now being used has a nominal switching time of

about one jisec.

The mechanisms of domain wall movement may be used to

explain the output voltage waveforms observed when a core is

switched under various conditions. For instance, if a core

is driven by a field only slightly greater than the coercive

force a voltage output similar to that shown in Figure 1 may

be observed. The first maximum is attributed to domain crea-

tion and reversible wall motion and its rise time appears

to be limited only by the rise time of the driving current

pulse. The second maximum, which occurs only when BL>Hq , is

thought to be due to the irreversible Wall motion of many

growing domains. This second maximum tends to increase in

amplitude and occur sooner as Hj^ is increased until eventu-

ally it blends into the first and its identity is lost.

By reducing the grain size more nucleating centers are
created and the switching time is speeded up; however, this

reduction in grain size also tends to increase the coercivity,

hence for any given material and application an optimum grain

size exists.

7.
 A high Curie point is desirable both to reduce the
relaxation losses and to pemit more stable operation at
higher pulse rates where heat dissipation may become a seri-
ous problem. The metal cores may be cooled v/ithout too

much difficulty but because of the poor heat conductivity

of the ferrites attempts to cool them succeed only in setting

up a temperature gradient within the core, A representative

Curie temperature for metals is about 460° Centigrade end

for ferrites about 300 Centigrade, This, and the fact that

metals usually have lov/er coercivities and higher flux den-

sities than the ferrites, has favored the use of metal cores

in shift registers and sv/itching circuits.

Work being done at the Naval Ordnance Laboratory,

Corona, on the evaporation of thin magnetic films gives

promise of very fast switching times fSJ

It may be well to note at this point that the square

hysteresis loop mentioned in the previous discussion is not

the only one which can be used for logical operations v/ith

cores, A material having hysteresis characteristics which

may be idealized as shown in Figure 2 may also be used for
gating operations, Ferramic I, one of the ferrites which

most closely approximates this ideal, has the following

nominal characteristics:

Bg = 1510 gauss
Bp • 725 gauss
Hq « .24 oersteds
The gating operation of such cores may be explained by re-

ferring to Figure 3« A DC bias current, when present, moves

8
thse operating point near saturation, hence any unipolar sig-
nal impressed on an input winding will produce little change

of flux and little output. Without the bias the core returns

to its remanent state and traverses a minor loop determined

by the amplitude of the input signal. The flux change for

this operation may be many times that v/hich occurred up on

the flat portion of the loop and a usable S/N can be realized

In „this way when only a voltage signal is required.

By confining operation to a minor loop the disadvantages

due to the heating effects of high pulse rates and the slower

switching times often associated with ferrites are minimized.

 CHAPTER III

SYSTEMS CONSIDERATIONS AND COMPARISONS

If magnetip cores are to be adopted for extensive use

in the arithmetic units of computers they must Stand on their

merits in competition against the devices now in Use for

such purposes, specifically vacuum tubes. This indicates the

desirability of a comparison of cores with tubes on the basis

of pertinent operating characteristics.

1. Speed
Cores of S-1 material have a nominal turnover time of

about one jLisec as pointed out in Chapter II. Faster operation

can be realized in other than coincident current applications

by increasing the driving mmf , but power dissipation at high

pulse rates soon becomes a problem, especially with the fer-

rites which are poor heat conductors.

In vacuum tube circuits, especially in applications as

adders, a tube may perform its designated function immedi-

ately upon receipt of the information from the preceding

stage. In cores, which are basically passive elements, the

operation must normally v/ait for the arrival of a clock or

shift pulse to supply the necessary power for transfer to the

succeeding stage.

In general, then, core operation will be slower than

tubes, but by a factor of less than ten,

2• Power
The power required from the source during switching of

10
a core which is driving another similar core has been shown

to be [\hj\

i*s = ^^s^t (1)

where Fg is NI required to switch a core in time T if

it has no load

1. is the output voltage per turn when a core is

switched in time T,

Experimental data on the cores used in this investigation

showed that about 2.3 NI v/as required to switch an unloaded

core in five psec with an output of about i volt per turn.

Substituting these values in (1),

P„s s 4x2. 3x^ =2.3 watts

which represents an energy loss of

PgT = 2.3x5x10" « 11.5 micro Joules per pulse,

or, for 50 Kc operation, a power dissipation of .575 watts.

This is substantially less than that sustained by a normal

computer type tube in standby condition, i.e., filament heat-

ers on, without considering any losses from the plate supply

necessary for the transfer of information.

3. Reliability
Although cores have been in use for a period of several

years the literature records no instance of the direct fail-

ure of a magnetic element but, of course, the associated elec-

tronic circuitry is subject to the same limitations as in

other applications. No gradual deterioration in performance

comparable to low emission in vacuum tubes is encountered.

11
Perhaps the weakest link, from the standpoint of reliability,
in the computing system outlined in this paper is in the use

of semi-conductor diodes. Recent manufacturing improvements

are claimed to have pushed the life expectancy of such units

above 20,000 hours.

On the other hand, premium quality computer tubes are

guaranteed for only 10,000 hours in most cases although con-,

servative circuit design and operation at reduced ratings have

pushed the actual life beyond this figure in some cases.

4« Cost

The present cost o-f graded switch cores is in the order

of one dollar but quantity production and increased automation

in processing and grading should reduce this figure by a

factor of ten.

Premium tubes of the type mentioned above are somewhat

more expensive than this.

5# General
To fully investigate all the ramifications and potenti-

alities of using magnetic cores in digital computers the sys-

tem in Figure 4 was chosen as a representative problem. It was

felt that if such a system could be designed in some detail and,

if possible, built and operated, using no vacuum tubes or trans-

istors it v/ould embody most of the essential features common

to modern electronic computers and would, in fact, consti-

tute in itself a simple computing system which could con-

ceivably be expanded into as complex a system as desired. The

.logical arrangement is a representative basic arithmetic unit

in itself.

12
 CHAPTER IV
TEST Ei^UIPMENT

The testing of the various circuits described in this

paper v/as greatly facilitated by the Magnetic Circuit Tester

developed by International Telemeter Corporation. This ver-

satile piece of test equipment provides four current pulse

drivers, two positive and two negative, which are independ-

ently variable in amplitude from 50 to 800 ma. An eight step

program is available, each of the eight "slots" being 50 psec

long and separated by 50 >isec from the next. Either one or

neither of two pulses, designated PI and P2, may be programmed

into each slot. PI is variable in duration from J to 40 >isec

and commences near the leading edge of the slot. P2 is also

variable from k "to 40 >isec and may be positioned at any

point within the slot. As an additional refinement it is

possible to alter the program to recycle the last two slots

either zero, six, or 20 extra times per cycle. This is in-

valuable for observing flux build-up under certain marginal

operating conditions. Synchronizing pulses are available at

an output terminal to enable the user to observe waveforms

in any specified on6 of the eight slots, or the output of

all eight may be presented simultaneously on eight succes-

sive sweeps of the oscilloscope.

Before leaving the test equipment it may be well to

discuss some of the terminology used in making the tests.

Operating characteristics inherent in the type of

13
magnetic circuits used, and further discussed in the next

chapter, lead to the convention of representing a binary "0"

by the absence of a pulse and a "1" by the presence of a

pulse. Following the tenijinology of sv.-itch-core circuits

these can be identified on the basis of their respective

origins as "disturbed" signals and "turnover" signals, A

further distinction can be made on the basis of their desira-
bility at a given point in the system as "unwanted" or "wanted"

and it is a short step from here to the familiar concept of .

signal-to-noise ratio, S/N, Furthermore, since the time inte-

gral of the observed voltage waveforms is a measure of the

total flux change and since an all-core system is basically

dependent on the efficiency of an operation which can be

thought of as flux transfer between stages, this area is a

more significant parameter than is the amplitude of the out-

put signal. For this reason the S/N as used in this paper

will refer to the ratio of the "wanted" to the "unwanted" sig-

nal on an area basis.

It is to be noted that in systems requiring a transi-

tion from magnetic to electronic devices, where relative flux

areas are not important, it is possible to take advantage of

further integration techniques or to "strobe" (sample) the

output at a time after the disturbed signal has died away but

while the turnover signal is near its maximum. Signal-to-

noise ratios obtained under these conditions may be very

high.

14
 CiiAPTJJiR V
DESIGN OF SHIFT REGISTER AND LOGICAL CIRCUITS

1, Background

The use of magnetic cores as storage elements for dig-

ital computers was proposed by Forrester at MIT in 1951 [2j

Further work in the field of magnetic-core matrix memories

and switching was done by Rajchman at RCA /10,ll7 and Pa plan

at MIT /97. Wang at Harvard A57, and later Sands A2,137

and Sims /\kj t investigated the design of magnetic-core
shift registers. The performance of logical arithmetic

operations with cores was covered theoretically by Guterman

et al £^J and Minnick flj while the requirements for a three-

input core adder were investigated at the Naval Ordnance Lab-

oratory, Corona £Qj

Z% Shift Register Design ,

It was first hoped to develop a shift register of the^

type shown in Figure 5 using only one core per bit of infor-

mation and operating at about 300 Kc with one psec pulses.

This type of register, while capable of high operating speeds,

tends to be somewhat critical in design due to the rather

delicate time-energy relationships which must exist in the

interstage delay netv/ork during transfer of information. This

consideration and limitations on the number of turns which

could be threaded on to the cores indicated the advisability

of abandoning this particular approach in favor of the two-

15
cores-per-bit register illustrated in Figure 6 which it was

felt could be more quickly brought to a state of satisfactory-

stable operation. It seems relatively certain that the above

mentioned problems were not insurmountable and, had this been

the predetermined major realm of endeavor, further investi-

gations would have been made.

The operation of the shift register shown in Figure 6

is briefly as follows. Suppose initially core #1 is set to

the "1" state, corresponding to the +Br position on the hys-

teresis loop of Figure 7'» by pulsing the input winding as

shown. All other cores are storing "0*s**, corresponding to

the -Bj. position. Shift pulse "A" (see Figure 8) is applied

to the shift winding of core #1 and all other odd numbered

cores as well. In all these cores except #1 the mmf due to

the current pulse merely pushes the core back along the loop

and no appreciable flux change occurs. In core #1, however,

the shift pulse causes a large flux change to occur as the

loop is traversed from +Bp to -B which induces a negative

voltage in the output v/inding. This signal passes through the

series diode and the input winding of core #2 which it sets to

the "1" state. The impedance relationships of output and in-

put circuits must be such that the flux change in core #2 is

completed before that occuring in core #1, Otherv;ise, once

the first core has reached saturation no energy can be trans-

ferred through it to the second. No signal output from core

#2 to #3 occurs during the above process because the signal is

16
of the wrong polarity to be passed by the series diode.

The seriesi resistor provides some degree of current reg-

ulation and impedance match necessary because the effective

impedance of the input winding changes as the core switch-

es from one state of magnetization to the other and, in

addition, serves to prevent the input winding from act-

ing as a "shorted turn" during re-set.

Now the "B" shift pulse (Figure 8) is applied to

core if-2 and all other even numbered cores. The "1" which

was stored in core #2 is now advanced to core #3 in pre-

cisely the same manner as that described previously. No

signal is fed back from core #2 to #1 because the output

winding of core #1 is et'fectively by-passed by the shunt

diode. Successive pairs of "A" and "B" pulses shift the

information down the register at the rate of two stages,

or one bit, per pair. 1

The cores used in this investigation were chosen

chiefly on the basis of their availability. They were a

General Ceramics type having the following nominal char-

'
*
acteristics:

Outside diameter .375 inches

Inside diameter ,187 inches
Thickness ,125 inches
He .65 oersteds
Bs 2000 gauss
1920 gauss
^r
Sands, in an analysis which is both theoretical

1, The convention v/ill be adopted of referring to each

core and its associated circuitry as a stage.

17
and empirical, derives from energy considerations an ex-

pression for the equivalent input resistance of a core

during switching by a current pulse A^/. The energy dis-

sipated in the core is equal to the input energy minus the

energy returned by the core at the end of the current pulse.

For cores having a ratio of Bp/B.

*
of ,95 or better the en-
s
ergy returned is less than 3^ of the input energy and may

be neglected. The input energy may be calculated from the '

dimensions of the hysteresis loop and a resistance found

which will dissipate the same amount of energy during
switching. Dividing this resistance by the square of the
number of input turns, 'to make its application to design

procedures more general, an equivalent resistance per

turns squared, 5q, is shown to be (using Sands' nota-

tion A37)
"^
^o = A(Br»Bg)xl. 26x10 (2)

where A Is^dross sectional area of core in; sq. cm.

Bp is 'residual flux density in gauss
Bg is saturation flux density in gauss
EL^ is driving field in oersteds
T is switching time in sec. jH',-.

L is mean flux path length in cm.

Substituting the previously listed core characteristics,
after making the necessary units conversions,
^
R«= .Q76(192Qf2Q0Q)xl. 26x10"
° .65x5x16-^x^.25
« 0.51 ohms per turns squared.

Choosing the ratio of unwanted to wanted flux transfer,

^12 » ^° ^® ^/^ ^^^ assuming the forward resistance of the

18
diodes (lN34A*s) to be about 100 ohms, the value of the

series resistance, R-j_, was found from the relationship

N.

where Nc/Ny is the turns ratio of input to output

windings
IL, is the forward resistance of the diodes
Rl is the series resistor^

Substituting in (3),

1 r Ljc 100
1 2 100+Ri
and Ri « 300 ohms.

Now the number o'f turns required on the input v/inding can

be determined from:

N^^Q = Rl*Rp « 300-I-100 = 400 ohms (4)

2
Nc = 400 = 783 turns squared

Nc = 28 turns on input winding (5)

N-- 2Nc - 56 = 60 turns on output (6)

I
winding,
-wi
r\r\Tnrr-

3« Logical Circuit Design

The design of the logical circuits was, in general,

less straightforward and well defined than that of the

shift register. The bases for the design were the ele-

mentary logical operations defined by the truth tables

contained in the summary of binary logic presented in

Appendix I,
It has been shown /5j that three basic require-

ments are necessary to an all-core logical system, namely,

1, storage or delay, 2. amplification, and 3» two of

19
the three logical operations AND, OH, and NOT, That the

first two requirements are implicitly satisfied by proper

operation ,of the shift register may best be shov/n by con-

sidering the particular mode of operation of the register

which was used for test and demonstration purposes, de-

,1-

scribed later in Chapter VII, in which a single "1" is

cycled continuously through the register.

Cores lend themselves well to use as OR gates since

any one of two or more inputs can set a core to saturation.
The OR circuit used was identical to an ordinary shift

register stage except that an additional 28-turn input

winding was provided as indicated in Figure 9«

Either AND or NOT operation could have been chosen
for the second logical operation, but the latter seemed to

be more useful for this application since the logical

equations for addition are most often written in terms of

the input functions and their complements or NOT»s, Also,

direct realization of an AND circuit v/ith cores would be

quite difficult if the inputs are derived directly from

cores and the output must be able to switch the following

core, as has been assumed throughout the system under con-

sideration, A coincident-current core memory is essen-

tially an AND device since an output is desired only from

the core which lies at the intersection of the selected

X and Y lines. Here, however, as in other previously

proposed systems of cores, only a voltage output signal

is desired for use as an input to the following circuit,

20
 Minniok Cl] proposes q one-level AND circuit v/ith
cores, but manipulation of his equations is instructive.

Using his notation and definitions,

2» = i-z defined as inverse z (7)

f2^(il,X2) = ^\^^2 AKD (8)

y®z = l-y»z» defined as inclusive OR (9)

f2(xi,X2) = Xi«K2 .
OR (10)

From these definitions it must follow that

f^lx^jX^) = Xife2 (10)

« 1-X]^«X2' from (9)

* l-fl(xi,X2) from (8)

a fX« (2:1^1X2) from (7)
and thus OR - AND' or AND NOT. This conclusion implic-

itly defines a logical structure other than that presented

in Appendix I and which seems to offer no particular ad-

vantage for present purposes.

Complementation, which corresponds to the logical

NOT, may be accomplished in more than one way. For in-

stance, if a "1" were represented by a positive pulse then

'•T" (NOT 1) might be a negative pulse, and vice versa for

the "0". Complementation in this case might be accomplished

rather easily with a couple of biased cores by properly

arranging the sense of the various v/indings. Unfortunately,

however, this is not the situation encountered here. The

output of the magnetic-core shift register is such that

l" is represented by the presence of a pulse, normally

negative in this system but dependent only on the sense

21
of the output winding, and "0" by the absence of a pulse.

To complement this output the circuit shown in Figure 10(a)

was used with operation to be as indicated in Figure 10(b),

With no signal input, i.e., a "0" to be complemented, the
externally generated clock, or shift, pulse drives "through**
the bias and causes the core to switch from point "a",

where it had been held by the bias current, to point "b"

with a large resultant flux change and a negative output
signal which is the desired ""O". If an input signal is

present, i.e., a "1**. to be complemented, this signal works

against or inhibits the clock pulse, since they arrive

ooincidentally, to such a degree that the net mmf is zero

or so nearly zero that the core remains essentially at

"a", no appreciable flux change occurs, and no output

signal is generated which is the desired **T"#

22
 CHAPTER VI
ADDER DESIGN

To add the output of two registers in binary fashion

it is necessary also to account for any carry which may

have resulted from the previous addition of the next least

significant binary digits. To perform all this simulta-

neously a three-input adder of the type shown in Figure 11

could be rather easily designed directly from the logical

equations of Appendix I, Such an adder was built at the

Naval Ordnance Laboratory, Corona, using DC sources as ex-

perimental inputs through toggle switches and it is re-

ported to have operated satisfactorily with a S/N as high

as 9:1 (on an amplitude, rather than area, basis). To

achieve this result using as inputs the outputs of previous

cores in the system .is quite another matter, however, and

even moreso if the output signal from the adder must itself
be of sufficient magnitude to drive the next core in the

system to saturation, Tv;o possibilities were explored.

First consider asynchronous operation of the adder,

that is, without benefit of shift pulse. This implies

that the input pulses would have to be sufficiently large

not only to set the core, but to shift the output to the

next core as well. Also, since the adder cores must in

some cases change state, unlike the "T" mode of operation,

this vvfill load the driving cores rather heavily, Further-

23
more, consider the relative states of magnetization of each

core of the adder for all possible input conditions as

shown in the table of Figure 12 which may be constructed

directly from the logical equations. The significant out-

puts are encircled. Inspection of this table indicates

that what might be termed four-step operation is required.

If all cores were biased with a steady DC current to a

relative state of "minus two" then a full output, suffi-

cient to set another core to saturation, would be desired

when a core is driven up through the bias with a relative

drive of "three". This same core^ however, is required

under other circumstances to give no output for a driVe of

"two", and, worse still, the output of three such cores

in series must still be negligible. Considering the possi-

ble variations in the shape of the input pulses from the

various cores this seems unreasonable to ask.

The alternative procedure v/as to provide a shift

pulse to each adder core and to operate it in somewhat

the same manner as the NOT cores. In this way the input

signal would have only to inhibit the shift pulse to the

desired degree. This would eliminate the problem of load-

ing the previous cores and at the same time provide an ex-

ternal source capable of supplying the pov/er required to

shift to the following core. The disadvantages to this

scheme are twofold. First, the trouble encountered with

only one inhibiting signal in the NOT cores quickly dis-

courages the practice of piling three such signals, one

24
atop the other as it were, and expecting good discrimi-

nation or S/N, Second, considering that it had been estab-

lished experimentally that approximately 100 turns were

required on the input winding to inhibit properly, this

would mean each adder core must have three 100-turn input

windings, one 20-t\irn bias winding, one 20- turn shift

winding, and one 100-turn output winding. This is just

about twice as many turns as it is possible to thread by

hand through the cores being used. This latter trouble,

incidentally, would have hampered the previous scheme also

and is the best immediate, single reason for not attempt-

ing the three-input adder.

The. decision to proceed with a two-input adder, or

essentially two half -adders, was a costly one in terms of

operating speed.
The logical equations for a half -adder are:

Sun = {A-fB)«(A«B) (11)

Carry = A«B (12)

Inspection of the truth tables of Figure 13 indicates

that the AM) operations can be eliminated by making the

substitution:

A.B = I+l (13)

Expanding the half -adder equations using this substitution,

Sum = (A+B)*(A«B)
= (A+B)«(A4.B)

' (A*B) + (A+B) (U)

25
 Carry « A.B
« A+1

Although these equations appear distended and awkward they

give promise of being more nearly physically realizable than

the others*

The block diagram of a half -adder designed to imple-

ment the preceding equations is shown in Figure 14. Two

half-adders of this sort may be combined with an OR gate

in the manner shown in Figure 15 to form a full adder.

The system proposed by Minnick [l] achieves some

saving in number of cores over that described above by

accomplishing the complementing simultaneously with the OR

operation in a single .core. However, the complexity of the

timing pulse schedule is considerably increased and the

speed of operation would remain the same.

No consideration has been given to the problem of

switching "one-out-of-many" using core matrices since it

was not germane to the system proposed here and since the

procedures have been well established in conjunction with

the magnetic-core miatrix memories previously mentioned

AO.llJ.
I

,S.:-
t^

26
 CHAPTER VII
EXPEHIMENTAL RESULTS

1, Shift Register

Two stages of the shift register were built using

the design values specified in Chapter V, Experiments

showed that these values did not give a satisfactory S/N

so the number of turns on the output winding was increased,

eventually to 100 turns before a really good S/N was ob-

tained. At the seme time the series resistor was opti-

mized at 150 ohms. For these conditions the flux trans-

fer ratio, ^i2» ^^^ calculated from equation (3) to be:

Fip » 28 ^ 100 = .112

'
or a ;:S/N of about 9:1 on an area, or flux, basis, Actu-

ally a S/N of about 20:1 was obtained in operation by driv-

ing the shift windings with a pulse of about 12 NI, ten

;iseo in duration (see Figure 16).

This discrepancy was puzzling at first, but further

research into the literature provided a clue. In operation

of a register somewhat similar to this one, although con-

siderably faster, Sims at MIT found the effective forward

resistance of 1N34A diodes to be about 30 ohms instead of

the 100 ohms assumed fllj • Substituting this value for Rp

in equation (3)

Fto
12 -
=
28^ 30 .
'
28 •= .046
100*1a+156
i^^()il5() ' SOT

27
or a S/N of 21,4 which is in good agreement with the re-

sults of rough graphical integration of the oscilloscope

photograph traced for Figure 16. •

A ten-stage, five-bit register was built and tested

using this design except that the number of turns on the

shift v;inding was increased from 15 to 20 to ease the load

on the current driver. This register was eventually split

into two'-five-stage registers, later designated "A** and **B",

for further testing and experimental purposes.

The test procedure for the shift register fell intq

three categories: first, to determine whether the register

operated correctly under normal circumstances; second, to

determine its storage and attenuation or amplification

characteristics; a;jd third, to investigate the limits of

reliable operation*
The first function was easily satisfied by programming

various sequences of "l*s" and "O's" into the first stage

from the Magnetic Circuit Tester described in Chapter IV

and checking the output with an oscilloscope.

The second type of test was a more exacting one. With

no shift pulses applied, the firs't core v;as set to the "1"

state using an external unidirectional current sourcejl*'

which was then removed. All other cores were storing "OV,
The output of the tenth tlast) stage was then connected to

the input of the first stage and shift pulses were applied

to the shift windings. The "1*', initially stored in the

2B
first stage, was successively propagated dovm the register

and caused to recycle itself indefinitely, "biting its

own tail". No attenuation of the signal nor deterioration

in S/N as a function of time occurred, implying the theo-

retical possibility of building a shift register having

an infinite number of stages.

To determine the limits of reliable operation of

the register, the mode of operation just described was

used while the shift pulses were reduced in duration and

amplitude. In this way the "worst possible" condition,

sometimes specified in computer tests, was achieved since

failure in any stage would cause the single bit being

circulated to be lost. In this way it was found that the

minimum tolerable shift pulse duration was about 5,0 jiseo

and the minimum amplitude about 10,8 NI and each was rela-

tively independent of the other.

It Is interesting to note that failure occurred in

a different way when the pulse amplitude v/as reduced below

its minimum than when the pulse duration was reduced too

far. When the amplitude was reduced below 10.8 NI the sin-
gle "1" being recirculated disappeared. This is felt to

result from the shift pulse being of insufficient magni-

tude to transfer to the next core the energy necessary for

a complete flux change. This loss is then reflected in the

next stage and within a few cycles the cumulative effect

reduces the flux change to that of the noise level and.

29
by definition, the register contains all "0*s",

The effect of reducing the pulse duration below

five jisec was to cause the register to fill with "l»s".

This behavior is explained on the basis that the core

from which the "1" is being shifted does not have time to
complete its flux excursiom along a major loop and hence

comes to rest at a point above -Bp. Further shift pulses

occurring before the re-arrival of the "1** tend to drive

the operating point toward -Bp and each of these minor

excursions can be thought of as transfering some flux to

the following stage. Eventually this flux build-up in

succeeding stages of the circle of operation will amount

to storage of a "1" in every stage. It is to be noted

that at least one "1" must be present in the register for

this chain of events to take place, A register filled

with "O's" will never spontaneously fill with "I's" as the
pulse width is reduced.

This completed the test of the register which v/as,

for the purposes of this project, only a means to an end.

For this reason design refinements which might have been

investigated further had time permitted were ignored.

Further experience has indicated that improvements might

be made in the direction of reducing the shift pulse ampli-

tude, and perhaps duration, by making the turns ratio more

nearly 2:1, the theoretical optimum, and at the same time

increasing the value of the series resistor in each stage.

30
It is doubtful, however, if too much can be accomplished

without some deterioration in S/N and sacrifice in sta-

bility of operation,

2. Logical Circuits
The logical OR gate functioned as predicted and no

modifications were necessary.

The complementing, or logical NOT, circuit showed

an unsatisfactory S/N when first tested and the trouble

was traced to the "T" function.

The shift pulse supplied to the complementing core was

originally made identical v/ith the shift pulse which had

shifted the information to be complemented out of the pre-

ceding core. Since, however, the flux change in the first

core is completed before the shift pulse is removed, and,

in fact, is completed in about the first six ;isec of a ten

jLisec shift pulse, a condition somewhat as shown in Figure

17 results where the shaded area roughly represents the

uncanceled mmf . This leads to an unwanted output for T*

occurring during the latter half of the shift pulse. For
this reason the width of the shift pulse to the comple-

menting core was reduced to about five )isec and was in*»

creased slightly in amplitude over the normal shift pulses

to help overcome the 1.10 NI DC bias. At first the input •

signal amplitude was found to be insufficient to inhibit

the shift pulse which itself had to be great enough v/hen

uninhibited to switch the complementing core and to drive

31
the following core to saturation. This difficulty was

overcome by v/inding 100 turns on the input instead of

the usual 28, This was possible here because the loading

effect on the preceding core is negligible during the sub-

traction of the inmf *js since no traversal of the hysteresis

loop occurs. Because it was difficult to observe the out-

put of such a low impedance circuit directly, the output

was made to set a shift register stage and the output of

this latter core, observed across the normal 150 ohm load,

had a S/N of about 20:1 for the complemented output. It

is quite possible that a gain in s/N occurred in the inter-

mediate core since such a phenomenon v/as observed in the

shift register. Still, the observation of S/N at the but-

put of the next stage seems to be a fair criterion since

this turns out to be the way in which the circuit is used

in the system.

The half -adder of Figure 14 which is shown schemati-

cally in Figure 18 was actually constructed and tested.

Operation was only partly successful in that the upper

branch, or "straight through" part of the circuit, func-

tioned correctly for several stages while the lower, or

complementing, branch ciid not. It was apparent that the

interaction of the various cores on one another was con-

siderable even though isolating diodes had been provided

between all stages and a high- impedance DC bias source

was built to replace the ignition batteries used previously.

32
Further isolation was necessary and, again, the price to

be paid was time and an increased number of components.

Buffer stages, which were normal shift register stages,

were inserted in the half-adder as indicated in Figure 19,

Also shown is the increase in time spent in the half -adder

by a factor o^ three. In an actual computer this would

be a very serious limitation but for the purposes of this

study it was an undesirable but acceptable condition*

33
 CHAPTER VIII

CONCLUSIUNS, RiiCOM^IOATlONS, AM) POSSIBILITIES

1, Conclusions

The investigations reported in this thesis seem to

indicate that an all-core computing system is possible.

The basic circuits for such a system have been designed

and tested. Lack of sufficient current pulse sources,

coupled with lack of time, precluded building and testing

the entire system. However, using only combinations of

circuits which were proven successful, the block diagram

of Figure 20 represents the fulfillment of all the require-'

ments for the basic computer system proposed in Chapter II,

It appears that the proposed system could be operated at

a basic repetition rate of 50 Kc in the logical portion,

i#e,, the adder, and thijs one-third this rate in the shift

register. This implies that the serial addition of n

binary digits could be accomplished in (n-t-2) times 60 ^sec

which compares favorably with many modern nachines.

The basic speed limitation in the system is the time

required in the second half -adder to deterioine the second-

ary carry digit and feed it back through the OR gate to

combine with the partial carry from the first half -adder,

all this is time to add to the partial sum due to the next

most significant digits. To accomplish this the shift

register operates at only one-third the pulse rate of

the adder and various timing delays have been introduced

34
to insure arrival of the information at the proper place

at the proper time. The recirculation of the contents of

the "A" register must also be delayed a time equal to that

spent in the adder.

The entire system, including two ten-bit shift regis-

ters and the adder, uses the following components:

Cores 84
Diodes 158
Resistors 74

The vacuum tube equivalent, using a three-input tube adder,

would require something in the neighborhood of 33 tubes.

The maximum reliable rate of operation of the core

system would be about 15 to 20 Kc, that of a comparable

system using tubes in the range of 100 Kc,

From the power requirements computed in Chapter III,

and assuming ten jusec shift pulses for operation at 16,7 Kc,

the power consumed will be less than

11, 5x10*^x16. 7x10^x84 = 16,1 watts

This does not include whatever pov/er may have been neces-
sary to generate the shift pulses nor any losses in the DC

bias supply. The vacuum tube system would probably draw in

excess of 100 watts.

It appears that compared to its vacuum tube counter-

part this system would be more complex and slov;er but use

less power. The real advantages of the core system, though,

are felt to be its reliability and ruggedness, Qommercially

available magnetic-core shift registers nov/ use one core

35
per bit and one diode per stage. This single improvement

in the shift register alone would reduce the diode count

below 100 and the cores to 64. Further improvements in

design, materials, and techniques may be expected to cor-

respondingly brighten the core picture, all without sacri-

ficing the prime advantages of cores — high reliability

and long life,

2. Recomiaendations

The possibility of improving the shift register de-

sign was discussed briefly in Chapter VII and some general

recommendations were made toward that end.

In the logical circuits improvements would bq desira-

ble to reduce the time spent in the adder and to reduce

the complexity. The first step might be in the direction

of eliminating the buffer stages in the ha^lf -adders and

the second step to eliminate the half -adders altogether

in favor of a three-input or full adder, ^;

The possibility exists that unforseen combinative

difficulties might arise in the actual testing of the

system proposed in Figure 20 should it be constructed in

its entirety. In such a case additional buffer stages

could be inserted as necessary, keeping always in mind the

associated reduction in operating speed. The ability of

a single core to set two cores in a branch circuit has been

experimentally verified.

36
3. Possibilities

Considerable feeling ezists among some engineers that

the future of computers lids largely in machines willing
to sacrifice some speed of operation for reliability. An
example often cited is the fable of The Tortoise and the

Hare. Perhaps a better analogy is that of the very fast

but expensive and tempermental race horse which must be

carefully groomed only to spend a few minutes on the

track at high speed while the ordinary work horse can be

expected to be in top form nearly all the time and to per-

form its duties for long periods without special handling.

The all-magnetic computer may well be the work-horse of

the future.

Other impendi'ng developments use cores in more con-

ventional machines. Designers have in the planning stages

a system to utilize complex, yet highly reliable, switching

circuits to speed computer operation. One method visualizes

a vertical shift»* to any one of a series of magnetic-core

switch lines which may perform such functions as shift

right one place", shift left two places^^, shift to out-

put , etc,

. Further logical, or arithmetic, operations could be

speeded by the use of function tables which might consist

of core matrices whose reading v/indings follow a certain

pattern. For example, consider the possibility of a direct

decimal multiplier, A square core matrix having ten

37
X-lnputs and ten Y-inputs would have one or two cores at
the intersection of each X and Y line. The reading windings

of these cores would be arranged in such a manner as to

give the product of X and Y, For instance, at the inter-

section of the X»7 and Y«4 lines are tv;o cores. Through

one is threaded an output winding connected to the terminal

corresponding to "8", through the other the "carry 2" out-

put winding. Simultaneous half -excitations, of the type

used in coincident-current matrix memories, when applied

to the X=7 and Y=4 inputs would induce output voltages

only in the "8** and "carry 2" lines.

As a further example of the use of function tables,

consider a ten-by-ten matrix having three sets of reading

windings laced as shown in Figure 21, In this case the

matrix would perform the function of comparison of the nu-

merical magnitudes of the inputs, the outputs being "X is

greater than Y" , "X is equal to Y", or "X is less than Y".

If the preceding examples seem to involve a rela-

tively large number* of cores this is no accident. Pre-

liminary investigations of the possibility of incorporating

extensive core logic into a computer have been made by

International Telemeter Corporation, The conclusion was

that cores are practical as a replacement for tubes as

logical elements at pr.esent only v/hen large "swatches" of

logic are to be performed in parallel. The advent of power

transistors, capable of supplying the relatively large

38
driving currents used in core work', is expected to lend

impetus to the use of cores as logical elements in com-

puters*

}»'*

39
 )l^

e =

time

Figure 1, Voltage output from switched core

B B
B,

Bi

H H
f
Bias current

Figure 2, Idealiaed slant Figure 3. Operating condi-

• hysteresis loop tions on slant-
loop core

40
 Delay

Carry
"A" Register

Adder
"B*» Register

Sum

Figure km Proposed magnetic-core arithmetic unit

Input
pulse

Shift pulse

Figure 5» Basic form of one-core-per-bit shift register

Input
pulse

"LpA" shift pulse

LI"B»» shift pulse

Figure 6. Basic form of two-cores-per-bit shift register

41
 B
«2_n
k r r^
*\

)
-Bj

"0"

Shift pulse

Figure ?• Idealized square hysteresis

iQop of ferrite core

"A** shift pulse U IJ~

"B" shift pulse time

Figure 8. Time relationship of "A" and "B" shift pulses

jT"B" input

""
"A" input
J]^
1 r "A-B" output

Shift pulse

Figure 9. Logical OR circuit

42
 DC bias source B

7t

Complemented .JL

Input output DC bias

pulse

U Shift pulse J Shift

1 pulse

Figure 10a. Logical NOT circuit 3

Input "l"

Figure 10b. Operation of

logical NOT
circuit

Sum winding

Figure 11a. Sum output of tbree-lnput adder

Carry winding

Figure lib. Carry output of three-Input adder

43
 Input Relative state of Desired sum
magnetization of output
A B c core #1 #2 #3 #4

(0) 2 2 2

1
1 1
1
if A
2 2 2
1 1
1

1 1 1 _ 1
1 1 2 2 ®12 2
1 1
1 1 1 ©111
2 (D) 2
1

Figure 12. Relationships existing in three-

input adder of Figure 11a.

A B A B A*B A+B A+B

1 1 1
1 1 1
1 1 1
1 1 1 1

Figure 13. Truth table

— AfB
^ A Reg.
NOT ^ OR NOT
A »l
— OR I
^
'
__Jl*B4.A+B
A't-B't-AfB

[
not [
' ^
— Sum
\ B Reg. I
— A^ OR A4.1
NOT I-
A»l
^ Carry
moL
Figure 14. Block diagram of modified half -adder using
only OR and NOT circuits

44
 A Firsb .4.
Second Sum
half- half-
B adder adder

0' 1 1 f

n
\j
f
' '—p- /%T>
UA C»«

Jc'

Figure 15. Block diagram of full adder

T
20 volts

i i^"^'

Figure 16, Tracing of oscilloscope photo

of output pulse at last stage
of shift register showing S/N

^r 10 jisec

^ Input -^ ^^
;• signal ^ Shift pulse

Figure 17» Current pulse conditions in

complementing circuit

45
 1 1

Input from "A" Reg.

NOT ^

Figure 18. Schematic diagram of modified half -adder

){*•

B = Buffer stage

h
U Reg. p— OR - - NOT —B -1

t
1

— NOT -- B -^
i
•

OR — B-- NOT
1
-

^B Reg. — -

OR -- B --NOT —B -
1
— NOT -- B J .

i^ T
X *-
^ '^
K,
" ^
'fc-
3 -
-

Figure 19. Block diagram of buffered half -adder showing

number of clock times spent in passage of a
digit

46
 A B A Recirculation of contents
B of upper register
Letters refer to tining of pulses accordinc to schedule belov;,

1
I
B B D' C D' C D'-'Cd C D C D C B D'C
'
D D'CD D'C
r --fBJC^ B

s<
i£K5l.®-L!LH.BK
Shift registers H^ N — ^ Bl

r Hiii—CD !i!^h-ii^K [jb]--[]b]--[b]—{T[- L? H_JjHj}"1JLH

H-CiH'" Partial carry ;

{nJ-Q SxiEli

I
Secondary .carrj_

Pulse Schedule
Key to Sjiibols

A (Shift) rn] n*^ stoge of shift register

J

B (Shift) n [n] not

'
0' OR
LJ Lj
1

C (Logic) j i
|_|

D (Logic) Bj Buffer (or idler) stage

_j j__. i_J I I i

'I n j-; 1
C« (Comp.) ,

j ! 1 L ri

D' (Comp.) _JLJ1_,: ^l__n i"l T! ^i i

Figure 20. Block diagram of computer arithraetic unit

using magnetic cores

47
 2<Y X=Y

xx> x9r/r:> x>.>^

Y inputs

X>Y

1234 56789 10
Z Inputs

Figure 21. yunction table for comparison of X and Y

J5>r

48
A
B — AND
-

X AM) .OR AND

"•h.

- 0/AB^XB4.iC57
B c

A - AND

Figure S2a

A
I — OR
B
AND

OR
c — AND
A
1 — AND QfU^Ti.
'
Figure 22b

A
AND C(B^iiS)
1 B— . OR c— AND

Figure 22c

A AND »" C(A+B)

OR ,]
B

Figure 22d

Figure 22. Various forms of logical equations

49
 BIBLIOGKAPHY

1, Bozorth, R. M, FERROMAGNETISM, D. Van No strand,

1951

2, Forrester, J. W, DIGITAL IN5'0RI/lA.TI0N STORAGE IN THREE

DI^iENSIONS USING J/iAGNETIC COKES,
Journal of Applied Physics, Vol. 22,
No. 1, pp 44-48, January, 1951

3, Good enough*, J, B, MAGNETIC MATERIALS FOR DIGITAL

and Menyuk, N. COLiPUTER COilPONENTS, Journal of
Applied Physics, Vol. 26, No, 1,
pp 8-18, January, 1955
4, Goodenough, J, B, A THEORY OF DOMAIN CREATION AND COER-
CIVE FORCE IN POLYCRYSTALLINE FERRITES,
Physical Review, Vol. 95, PP 917-932,
August, 1954

5« Guterman, S,, LOGICAL AND CONTROL FUNCTIONS PER-

iCodis, R. D, end FOR^IED Wira RIAGNETIC CORES, Proc.
RuhTnan , S« I.R.E., Vol. 43, No. 3, PP 291-298,
March, 1955

6. Kittel, C. PHYSICAL THEORY OF FERROMAGNETIC

DOIviAINS, Reviews of Modern physics,
Vol, 21, No. 4, PP 541-583, October,
1949

?• Minnick, R. C, MAGNETIC SWITCHING CIRCUITS, Journal

of Applied Physics, Vol. 25, No. 4,
PP 479-485, April, ,1954
8, Naval Ordnance NOL Corona Report 143 for October-
Laboratory, December., 1953, Computing Machine
Corona, Calif, Components Program ^^•

9. Papian, W. N. A COINCIDENT-CURRENT MAGNETIC MEMORY

CELL FOR THE STORAGE OF DIGITAL IN-
FORMATION, Proc. I.R.E., Vol. 4a,
pp 475-478, April, 1952
10* Rajchman, J. A. STATIC MAGNETIC MATRIX MEMORY AND
ITCHING CIRCUITS, RCA Review, Vol.
SV,
13, No. 2, pp 183-201, June, 1952

50
11. Rajchman, J. A. A MYRIABIT MAGNETIC-CORE MATRIX
MEl^ORY, Proc. I.R.E., Vol. 41, No.
10, pp 1407-1421, October, 1953

12. Sands, E. A. THE BEHAVIOR OF RECTANGULAR HYSTERESIS

LOOP I/iAGNETIC MATEiilALS UNDER CURRENT
PULSE CONDITIONS, Proc. I.R.E., Vol.
40, No, 10, pp 1246-1250, October,
1952

13. Sands, E. A. AN ANALYSIS OF 1/IAGNETIC SHIFT REGIS-

TER OPERATION, Proc. I.R.E., Vol.
41, No. 8, pp 993, August, 1953

14. Sims, R. C. AN INVESTIGATION OF MAGNETIC-CORE

STEPPING REGISTERS FOR DIGITAL COM-
PUTERS, Masters Thesis, MIT, 1952

15. Wang, A. MAGNETIC DELAY-LINE STORAGE, Proc,

I.R.E., Vol. 39, pp 401-407, April,
1951

51
 Appendix I

. BINARY LOGIC
I

I. General logical operations

A. OR (logical sum) - An output occurs when either one

or both of two inputs, A and B, are present. This

is symbolically v/ritten as A+B,

B* AND (logical product) - An output occurs only

when both of two inputs, A and B, are present.

This is written A«B.

C. NOT (logical complement) - An output occurs when

its corresponding function is not present at the

input. The output is called the "complement" or

"prime" of the input function and is written (for

an input A) as ][«

II. Truth tables

A. General logical operations

A B A+B A-B A B

1 1
1 1 1
1 1 1
1 1 1 1

B. Two-input adders

A B Sum Carry

1 1
1 1
1 1 1

52
 C. Three-input adders

ABC SUm Carry Sum equation Carry equation

ABC AB(or others)
1 1 aSc AB "
10 1 1^ AB ••

oil 1 ABC BC
10 1 aS^ AB «
10 1 1 ABC AG
110 1 ABC AB
111 1 1 ABC AB It

Discarding the redundancies,

Sum = ABC+a5C4.ABS"4.a12*

Carry = AB4-BC4.CA

D. Logical Identities

A4A = 1 •-

A'A «

(SI) = A*l
(A»B) = A*B

A(A+B) » A-B
A4A»B = A-^B

By using these logical identities of Boolean al-

ge"bra the arithmetic of switching or gating operations

may be expressed in several different ways. The choice in

any particular application usually depends largely upon

the physical or electrical realization of the specified

operation, l,a», how many levels of logic can be tolerated

from timing considerations, how many components must be

used, what sort of load will be imposed on the driving

circuit, etc.

As an illustrative example consider the simple

53
equation

{A+B)C

which is defined by the truth table which follows:

Corresponding term
ABC (A4.B)C for logical equation

ABC
1 ABC
10 ABC
Oil 1 Xbc
10 ABC
10 1 1 AB3
110 ABC
111 1 ABC

The first logical equation results from considering simul-

taneously all three inputs and writing the corresponding
terms of the equation by inspection of the truth table,

complementing the inputs as necessary to give the desired

output upon multiplication. After discarding the redun-
dant terms the result is:

(A+B)C « ABC4.ABC4.Alfc

The multiplication together of the three inputs A, B, and

C , in each term implies some sort of triple coincidence gate

which is generally difficult to achieve physically. Hence

the equations may be manipulated to a more usable form.

For each step a block diagram of the corresponding circuit

is given and the relative complexity, as determined by the

number of gates used, and the number of logical levels are

indicated.

54
 Block Relative Logical
Form of logical equation diagram complexity levels
Figure

(A+B)C = C/AB^ABi-aI/ 22a 5 3

» 6*/'(a*7:)b*aS7 22b 5 4
« c(b+a1) 22c 3 3

« C(A'l-B) 22d 2 2

This final result, as might be expected, is the original

equation.

Jf'*'

55
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