Electronic Circuit Design Lab (6ETC07)

P. R. POTE (PATIL) EDUCATION & WELFARE TRUST’S

GROUP OF INSTITUTIONS,

COLLEGE OF ENGINEERING & MANAGEMENT,

AMRAVATI.

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

ENGINEERING

Year: 2022-23 Semester: Sixth

SUBJECT: CMOS Design

Electronic Circuit Design Lab

 Electronic Circuit Design Lab (6ETC07)

Institute Vision Mission

Mission
 To flourish as a centre of excellence for producing the skilled technocrats
and committed human beings.
Vision

 To create conducive environment for teaching &learning.

 To impart quality education through demanding academic programs.

 To enhance career opportunities by exposure to Industries & recent

technologies.

 To develop professionals with strong ethics and human values for the
betterment of society.

Department of Electronics & Telecommunication Engineering.

Vision
To become a centre of excellence in Electronics & Telecommunication
Engineering to produce quality, self-motivated, creative and ethical engineers.

Mission
 To provide basic and advance knowledge to the students of Electronics &
Telecommunication Engineering.
 To strive towards efficient industry–institute interaction and academic
excellence.
 To inculcate awareness towards societal needs and environmental issues.
 Electronic Circuit Design Lab (6ETC07)

Program Educational Objectives (PEOs)

 To prepare the Engineering graduates to Acquire strong foundation in
engineering, science and technology to innovate and develop
multidisciplinary products.
 Excel in their technical, entrepreneurial and professional career in the
field of Electronics & Telecommunication Engineering.
 Practice the profession with ethics, integrity, leadership and social
responsibilities.
 Electronic Circuit Design Lab (6ETC07)

Department of Electronics & Telecommunication Engineering

Certificate

This is to certify that Mr./Ms…………………………………………………………...

of …...………… Semester of Bachelor of Engineering in ………………………………

Engineering of P. R. Pote (Patil) College of Engineering & Management,

Amravati, has completed the term work satisfactory in subject

……………………. for the academic year 2022- 2023 as prescribed in the

curriculum.

Place………………… PRN No………………

Date………………… Roll No……………………

Dr. R. D. Ghongade
Subject Teacher Head of the Department
 Electronic Circuit Design Lab (6ETC07)

Academic Year: 2022-23 Course: EXTC

Subject & Code: Electronic Circuit Design Lab (6ETC07) Semester: 6th

Name of Faculty:

Name of Student:

PRN No: Roll No:

Sign of
Title of the Date of Date of Assessment Teacher
SN. Page
Practical / Experiment No. Performance Submission Marks (15) and
Remarks
To design layout diagram
1 for CMOS Inverter on silicon
using Microwind.
To design layout diagram
for two input CMOS NAND
2
logic gate on silicon using
Microwind.
To design layout diagram
3 for two input CMOS NOR
logic gates on silicon using
Microwind.
To design layout diagram
4 for D filp-flop using
Microwind.
To write a Verilog program
for basic logic gates to
5
synthesize and simulate
using Xilinx software tool.
To write Verilog code for
implementation for 2*4
6
decoder circuit using Xilinx
software tool.
To write Verilog code for
implementation for 4:1
7
Multiplexer circuit using
Xilinx software tool.
To write Verilog code for
implementation for D flip-
8
flop circuit using Xilinx
software tool.

Signature of Faculty
 Electronic Circuit Design Lab (6ETC07)

GUIDELINES FOR TEACHERS

Teachers shall discuss the following points with students before start of practical of
the subject.

1 Learning Overview: To develop better understanding of importance of the

subject. To know related skills to be developed such as intellectual and
motor skills
2 Know your Laboratory Work: To understand the layout of laboratory,
specifications of equipment / instruments /materials, procedure, working in
groups, planning time etc. also to know total amount of work to be done in
the laboratory.
3 Teacher shall ensure that required equipment is in working condition
before start of each experiment, also keep operating instruction manual
available.
4 Explain prior concepts to the students before starting of each experiment.
5 Evolve student’s activity at the time of conduct of each experiment.
6 While taking reading / observation each student (from batch of 20 students)
shall be given a chance to perform / observe the experiment.
7 Teacher shall assess the performance of students continuously.
8 Teacher is expected to share the skills to be developed in the students.
9 Teacher should ensure that the respective skills are developed in the
students after the completion of the practical exercise.
10 Teacher may provide additional knowledge and skills to the students even
though not covered in the manual but are expected from students by the
industries.
11 Teacher may suggest the students to refer additional related literature of the
technical papers / reference books / Seminar Proceedings, etc.
12 Focus should be given on development of enlisted skills rather than
theoretical / codified knowledge.
13 During assessment teacher is expected to ask questions to the students to tap
their achievements regarding related knowledge and skills.
14 Teacher should give more focus on hands on skills.
 Electronic Circuit Design Lab (6ETC07)

INSTRUCTIONS FOR STUDENTS

Students shall read the points given below for understanding the theoretical
concepts and practical applications.
1 Listen carefully to the lecture given by teacher about importance of subject,
curriculum philosophy, learning structure, skills to be developed,
information about equipment, instruments, procedure, method of continuous
assessment, tentative plan of work in laboratory and total amount of works to
be done in a semester.
2 Student shall undergo study visit of the laboratory for types of equipment,
and material to be used, before performing experiments.
3 Read the write up of each experiment to be performed, a day in advance.
4
Organize the work in the group and make a record of all observations.
5
Understand the purpose of experiment and its practical implications.
6
Student should not hesitate to ask any difficulty faced during conduct of
practical /exercise.
7
Write the answers of the questions allotted by the teacher during practical
hours if possible or afterwards, but immediately.
8 The student shall study all the questions given in the laboratory manual and
practice to write the answers to these questions.
9 Student should develop the habit of pear discussion / group discussion
related to experiments / exercise so that exchanges of knowledge / skills
could take place.
10 Students shall attempt to develop related hands-on-skills and gain
confidence.
11 Student shall focus on development of skills rather than theoretical or
codified knowledge.
12 Student shall insist for the completions of recommended Laboratory Work,
answers to the given question etc.
13 Student shall develop the habit of evolving more ideas, innovations, skills
etc. that included in the scope of the manual.
14 Student shall refer technical magazines, proceedings of the Seminars, refer
website related to the scope of the subjects and update their knowledge and
skills.
15 Student should develop the habit of not depend totally on teachers but to
develop self-learning techniques.
16 Student should develop the habit to interact with the teacher without
hesitation with respect to academic involved.
17 Student should develop habit to submit the practical’s exercise continuously
and progressively on the schedule dates and should get the assessment
done.
18 Student should be well prepared while submitting the write up of the
exercise. This will develop the continuity of the studies and he will not be
overloaded at the end of the term.
 Electronic Circuit Design Lab (6ETC07)

LABORATORY INSTRUCTIONS

 Students must present a valid ID card before entering the computer lab.
 Playing of games on computer in the lab is strictly prohibited.
 Before leaving the lab, users must close all programs positively and keep
the desktop blank.
 Users are strictly prohibited from modifying or deleting any important files
and install any software or settings in the computer
 Based on the prime priority, users may be requested by the lab in-charge,
to leave the workstation any time and the compliance is a must.
 Internet facility is only for educational/ study purpose.
 Silence must be maintained in the lab at all times.
 The lab must be kept clean and tidy at all times.
 If any problem arises, please bring the same to the notice of lab in-charge.
 Lab timing will be as per the academic time table of different classes
 Every user must make an entry while entering in the Computer Lab and
also at the time of exit from the lab.
 Students are not allowed to use personal Pen Drives, CDs, DVDs etc., in a
Computer Lab. Only prescribed official Pen Drives, CDs, DVDs etc. will be
used in the Computer Lab to avoid VIRUS in Computers.
 Users must turn-off the computer before leaving the computer lab.
 In case of theft / destruction of the computers or peripherals, double the
cost of the lost will be charged from the student/user.
 Computer Lab Assistants are available to assist with BASIC computer and
software problems. They are not tutors and will not tell you how to
complete your assignments.
 Unauthorized copying and/or installing of unauthorized software is not
permitted. This may be a violation of copyright laws.
 Electronic Circuit Design Lab (6ETC07)

P. R. Pote (Patil) College of Engineering & Management, Amravati

Department of Electronics & Telecommunication Engineering

Name of the Program: B. E. Engineering Academic Year: 2022-23

Class: 3rd Year Semester: Sixth
Section: --- Course Code: 6ETC07
Course/Subject: Electronic Circuit Design Lab Course Owner:

SN List of Practical(s) / Experiment(s)

1 To design layout diagram for CMOS Inverter on silicon using Microwind.
To design layout diagram for two input CMOS NAND logic gate on silicon using
2
Microwind.
To design layout diagram for two input CMOS NOR logic gates on silicon using
3
Microwind.
4 To design layout diagram for D filp-flop using Microwind.
To write a Verilog program for basic logic gates to synthesize and simulate using
5
Xilinx software tool.
To write Verilog code for implementation for 2*4 decoder circuit using Xilinx
6
software tool.
To write Verilog code for implementation for 4:1 Multiplexer circuit using Xilinx
7
software tool.
To write Verilog code for implementation for D flip-flop circuit using Xilinx
8
software tool.
 Electronic Circuit Design Lab (6ETC07)

Lab Course Outcomes

After successful completion of laboratory course, the students will able to

Outcomes
SN
1. Understand Front & Back end design aspects of simple VLSI Digital circuits
Model digital circuits with Verilog HDL, simulate, synthesize and prototype in
2.
PLDs.
 Electronic Circuit Design Lab (6ETC07)

Assessment Strategy: Rubrics for continuous evaluation in lab session

Allocated
Parameters High Medium Low
Marks
Student Student did not
Student
answered only answer any
answered all
few prelab prelab question
the prelab
questions and and not aware
Prelab test questions and
2 partial know about objective
Objective of the
objective of the of the
experiment.
experiment. experiment
2 1 0
Student Student
Student
performed or performed or
performed or
executed executed
executed
experiment, experiment,
experiment,
obtained obtained
obtained results,
In-Lab results, and results, and
5 and drawn
performance drawn drawn
conclusion
conclusion fully conclusion
below the
as per partially as per
expectation.
expectation. expectation.
5 4-3 2-1
Student
Student
partially
answered the Student did not
answered the
Post lab Viva answer the Post
Post lab Viva
voce questions lab Viva voce
voce questions
and fully questions and
Post lab test and partially
3 confirms the not confirms the
confirms the
understanding understanding of
understanding
of the the experiments.
of the
experiments.
experiments.
3 2-1 0
Records
Records Records
submitted by
submitted by submitted by the
the Student
the Student Student found
found
Lab Record found highly highly
5 moderately
satisfactory dissatisfactory
satisfactory
after evaluation. after evaluation.
after evaluation.
5 4-3 2-1
Total Marks 15 Marks (Continuous Assessment)
 Electronic Circuit Design Lab (6ETC07)

Assessment Strategy: Rubrics use for Internal Examination.

Allocated
Parameters High Medium Low
Marks
Student not
Students able to Student partially
able to conduct
conduct the able to conduct
given
given the given
experiment
Performance 5 experiment with experiment with
with desired
desired output. desired output.
output.
5-4 3-1 0
Student Student answered
Student did not
answered the the Questions
answer the
Viva Voce 5 Questions moderately
Questions.
satisfactorily. satisfactorily.
5-4 3-1 0
Total marks 10 Marks (Internal Examination)

Continues Assessment (15) +Internal Examination (10)

Grand Total Marks
=25 Marks
 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 1

AIM: To design layout diagram for CMOS Inverter on silicon using

Microwind.
LEARNING OBJECTIVE: -

 To simulate CMOS inverter and obtain simulation result.

 To Prepare the Layout of Inverter.

LEARNING OUTCOME:

 Students will able to design different circuit.

SOFTWARE REQUIRED:
SN Name of Software Tool Specification Qty Required
1 Microwind 3.8 ---
2 DSCH

THEORY:
The NMOS transistor and the PMOS transistor form a typical complementary
MOS (CMOS) device. When a low voltage (0 V) is applied at the input, the top
transistor (P-type) is conducting (switch closed) while the bottom transistor
behaves like an open circuit. Therefore, the supply voltage (5 V) appears at the
output. Conversely, when a high voltage (5 V) is applied at the input, the bottom
transistor (N-type) is conducting (switch closed) while the top transistor behaves
like an open circuit. Hence, the output voltage is low (0 V).

CIRCUIT DIAGRAM:

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PROCEDURE:

 Open the DSCH3.1

 Drag the components like pmos, nmos, voltage
source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Open Microwind by double clicking microwind2.
 Create new design by Click on File New.
 Select model file by Click on File Select Foundry and
select the model file.
 Create new text file and type name and save as Verilog file.
 Click on Compile Compile Verilog File. Select the
Verilog text file and
 Click on Generate.
 To Run Simulation Click Simulate Start Simulation.
 View the output waveforms.

SIMULATION MODEL:

MOS LAYOUT:

We use MICROWIND3.1 to draw the MOS layout and simulate its behavior.
Go to the directory in which the software has been copied (By default
MICROWIND3.1). Double-click on the MicroWind3.1 icon. The MICROWIND3.1
display window includes four main windows: the main menu, the layout display
window, the icon menu and the layer palette.

VERILOG CODE:
module cmosInv(in2, out2)
input in2;
output out2;
pmos #(17) pmos(out2,vdd,in2); //1.0u0.12u
nmos #(114) nmos(out2,vss,in2); // 0.48u 0.12u
endmodule

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LAYOUT DESIGN:

RESULTS & ANALYSIS:

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LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 ________ to form integrated circuit VLSI technology uses

2 What is medium scale integration?
3 To design VLSI, _____ architecture is used…
4 What is the high-level representation of VLSI design is ________________
5 What type of simulation model is used to check the timing performance
of a design…?

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Which 'law' describes the exponential growth of integrated circuit

complexity?
2 CMOS inverter has ______ regions of operation.
3 If both the transistors are in saturation, then they act as ________
4 Extract the last column of a matrix a and store it in matrix b.
5 What is the command to find the Scilab current working directory?

CONCLUSION:

ASSESSMENT SCHEME:
Pre-Lab In Lab Post Lab Record Total
Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 4

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 2
AIM: To design layout diagram for two input CMOS NAND logic gate on
silicon using Microwind.

LEARNING OBJECTIVE: -
 To Simulate NAND Gate.

 To Prepare the Layout of NAND Gate.

LEARNING OUTCOME:

 Students will able to design different circuit.

SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Microwind ---
2 DSCH

THEORY:
NAND gate is known as universal gate as any function can be implemented with
it. NAND functionality can be implemented by parallel combination of PMOS and
series combination of NMOS transistor. When any one of the inputs is zero, then
the output will be one and when both the inputs are one the output will be low.
CIRCUIT DIAGRAM:

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 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:
 Open the DSCH3.1
 Drag the components like pmos, nmos, voltage
source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Open Microwind by double clicking microwind2.
 Create new design by Click on File New.
 Select model file by Click on File Select Foundry and
select the model file.
 Create new text file and type name and save as Verilog file.
 Click on Compile Compile Verilog File. Select the
Verilog text file and
 Click on Generate.
 To Run Simulation Click Simulate Start Simulation.
 View the output waveforms.

PROGRAMMING
module cmosNand2(A,B,Nand);
input A,B;
output Nand2;
nmos #(121) nmos(Nand2,w1,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,B); // 2.0u 0.25u
nmos #(107) nmos(w1,vss,B); // 2.0u 0.25u
endmodule

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LAYOUT DESIGN:

RESULTS & ANALYSIS:

Truth Table:

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 Electronic Circuit Design Lab (6ETC07)

LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 Which type of CMOS circuits are good and better?

2 In CMOS fabrication, nMOS and pMOS are integrated in same
substrate?
3 What kind of substrate is provided above the barrier to
dopants?
4 nMOS fabrication process is carried out in ____________
5 The photoresist layer is exposed to ____________

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Which color is used for n-diffusion?

2 P-well is created on __________
3 Which color is used for polysilicon?
4 The CMOS inverter has _____ power dissipation.
5 In CMOS NAND gate, p transistors are connected in

CONCLUSION:

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 Electronic Circuit Design Lab (6ETC07)

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 9

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 3
AIM: To design layout diagram for two input CMOS NOR logic gates on
silicon using Microwind.

LEARNING OBJECTIVE: -
 To Simulate NOR Gate.

 To Prepare the Layout of NOR Gate.

LEARNING OUTCOME:

 Students will able to design different circuit.

SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Microwind 3.1 ---
2 DSCH

THEORY:
NOR gate is known as universal gate as any function can be implemented with it.
NOR functionality can be implemented by parallel combination of NMOS and
series combination of PMOS transistor. When any one of the inputs is one, then
the output will be one and when both the inputs are zero the output will be low.
CIRCUIT DIAGRAM:

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 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:
 Open the DSCH3.1
 Drag the components like pmos, nmos, voltage
source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Open Microwind by double clicking microwind.
 Create new design by Click on File New.
 Select model file by Click on File Select Foundry and
select the model file.
 Create new text file and type name and save as Verilog file.
 Click on Compile Compile Verilog File. Select the
Verilog text file and click on Generate.
 To Run Simulation Click Simulate Start Simulation.
 View the output waveforms.

PROGRAMMING:

module nor2Cmos(B,A,Nor2);

input B,A;

output Nor2;
nmos #(121) nmos(Nor2,vss,A); // 1.0u 0.12u
pmos #(121) pmos(Nor2,w4,B); // 2.0u 0.12u
pmos #(107) pmos(w4,vdd,A); // 2.0u 0.12u
nmos #(121) nmos(Nor2,vss,B); // 1.0u 0.12u
endmodule

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LAYOUT:

RESULTS & ANALYSIS:

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LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 In CMOS logic circuit the n-MOS transistor acts as

2 As die size shrinks, the complexity of making the photomasks
____
3 ______ is used in logic design of VLSI.
4 Which provides higher integration density?

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Which gate is faster?

2 The width of n-diffusion and p-diffusion layer should be?
3 α is used for scaling
4 The basic figures of merit for MOS devices are

CONCLUSION:

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 Electronic Circuit Design Lab (6ETC07)

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 14

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 4
AIM: To design layout diagram for D filp-flop using Microwind.
LEARNING OBJECTIVE: -
 To Simulate NOR Gate.

 To Prepare the Layout of NOR Gate.

LEARNING OUTCOME:

 Students will able to design different circuit.

SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Microwind 6.1.0 ---

THEORY:

D-FF is a sequential flip flop. It is one bit cell and has input as reset clock
and data input. Reset has highest priority whenever RST=1 then FF is reset
when there is a clock event the data input is saved in D-FF and passed on
to the output. Depending upon clock value these are categorized as: a)
positive edge triggered and b) negative edge triggered. Here we use
positive edge triggered.

CIRCUIT DIAGRAM:

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 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:
 Open the DSCH3.1
 Drag the components like pmos, nmos, voltage
source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Open Microwind by double clicking microwind.
 Create new design by Click on File New.
 Select model file by Click on File Select Foundry and
select the model file.
 Create new text file and type name and save as Verilog file.
 Click on Compile Compile Verilog File. Select the
Verilog text file and click on Generate.
 To Run Simulation Click Simulate Start Simulation.
 View the output waveforms.

LAYOUT:

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RESULTS & ANALYSIS:

LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 What should be the spacing between two diffusion layers?

2 Which type of contact cuts are better?
3 Which gives scalable design rules?
4 Area A of a slab can be given as __

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Conducting layer is separated from substrate using __

2 A feature size square has ____
3 Which quantity is slower?
4 The total resistance can be given as ___

CONCLUSION:

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 Electronic Circuit Design Lab (6ETC07)

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 18

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 5
AIM: To write a Verilog program for basic logic gates to synthesize and
simulate using Xilinx software tool.
LEARNING OBJECTIVE: -

 To implement Verilog Code for basic logic gates.

LEARNING OUTCOME:

 Students will able to Describe Verilog hardware description languages

(HDL).
SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Xilinx ISE ---

THEORY:

AND GATE

The AND gate performs logical multiplication which is most commonly

known as the AND junction. The operation of AND gate is such that the output
is high only when all its inputs are high and when any one of the inputs is low
the output is low.
Y=a&b
OR GATE:
The OR gate performs logical addition which is most commonly known as
the OR junction. The operation of OR gate is such that the output is high only
when any one of its input is high and when both the inputs are low the output
is low.
Y=a|b

NOT GATE:
The Inverter performs a basic logic gate function called Inversion or
Complementation. The purpose of an inverter is to change one logic level to

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 Electronic Circuit Design Lab (6ETC07)

opposite level. When a high level is applied to an inverter, the low level will
appear at the output and vice versa.

Y = ~a
NAND GATE:
The term NAND is derived from the complement of AND. It implies the AND
junction with an inverted output. The operation of NAND gate is such that the
output is low only when all its inputs are high and when any one of the inputs
is low the output is high.

Y = ~ (a & b)
NOR GATE:
The term NOR is derived from the complement of OR. It implies the OR
junction with an inverted output. The operation of NOR gate is such that the
output is high only when all its inputs are low and when any one of the inputs
is high the output is low.

Y = (a | b)
EX-OR GATE:
The output is high only when the inputs are at opposite level.

Y=a^b
EX-NOR GATE:
The output is high only when the inputs are at same level.

Y = ~ (a ^ b)

PROCEDURE:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements for Verilog code.
5. Write the functionality of the gates.
6. Verify the truth table using Isim simulator.

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7. Terminate the program.

PRGRAMMING:

Verilog Code for basic logic gates

module logicgates(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
and(c,a,b);
or(d,a,b);
not(e,a);
nand(f,a,b);
xor(g,a,b);
xnor(h,a,b);
endmodule

RESULTS & ANALYSIS:

Thus, the Verilog code for the basic logic gates, simulated using Xilinx
project navigator.

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LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 Expand “VERILOG”
2 What are the different ways of modeling in Verilog?
3 What are the different tools available for simulation?
4 What is meant by universal gate? List them.

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Name two logic primitive gates.

2 What statement is primarily used to describe a design in the
dataflow style?
3 Write the different types of port modes.
4 What are the two main data types in Verilog HDL?

CONCLUSION:

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 22

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 6
AIM: To write Verilog code for implementation for 2*4 decoder circuit
using Xilinx software tool.
LEARNING OBJECTIVE: -

 Understand 2:4 decoder logic verification using Verilog simulation.

LEARNING OUTCOME:

 Students will able to Verify behavioral and RTL models.

SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Xilinx ISE 6.1.0 ---

THEORY:
A decoder is a device which does the reverse operation of an encoder,
undoing the encoding so that the original information can be retrieved. The
same method used to encode is usually just reversed in order to decode. A
combinational circuit converts binary information from n input lines to a
maximum of 2n unique output lines.

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 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:

1. Start the program.

2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements for Verilog code.
5. Write the functionality of the gates.
6. Verify the truth table using Isim simulator.
7. Terminate the program.

PRGRAMMING:

module decodertwoistofour(a,y);
input [ 1:0] a;
output [3:0] y;
reg[3:0]y;
always @ (a)
begin
if (a==2'b00)
y=4'b0001;
else if (a==2'b01)
y=4'b0010;

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 Electronic Circuit Design Lab (6ETC07)

else if (a==2'b10)
y=4'b0100;
else if (a==2'b11)
y=4'b1000;
else
y=4'bzzzz;
end
endmodule

RESULTS & ANALYSIS:

Thus, the Verilog code for the 2:4 decoder, simulated using Xilinx project
navigator.

LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 What is a decoder?
2 What for enable inputs are used in decoder?
3 What are the applications of decoder?

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 What is the key difference between an initial statement and an

always statement?
2 Name two kinds of assignments that you can have in a Verilog
HDL model.
3 What is the difference between wire and reg data type?

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 Electronic Circuit Design Lab (6ETC07)

CONCLUSION:

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 26

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 7
AIM: To write Verilog code for implementation for 4:1 Multiplexer
circuit using Xilinx software tool.
LEARNING OBJECTIVE: -

 Understand 4:1 Multiplexer logic verification using Verilog

simulation.

LEARNING OUTCOME:
 Students will able to Verify behavioral and RTL model for 4:1 Mux.

SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 Xilinx ISE ---

THEORY:
In electronics, a multiplexer (or mux) is a device that selects between
several analog or digital input signals and forwards it to a single output line.
A multiplexer of 2^{n} inputs have n select lines, which are used to select
which input line to send to the output. Multiplexers are mainly used to
increase the amount of data that can be sent over the network within a
certain amount of time and bandwidth. A multiplexer is also called a data
selector. Multiplexers can also be used to implement Boolean functions of
multiple variables.

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 27

 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:

1. Start the program.

2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements for Verilog code.
5. Write the functionality of the gates.
6. Verify the truth table using Isim simulator.
7. Terminate the program.

PROGRAMMING:

# Verilog code for 4:1 Multiplexer.

module fourtoonemux (select,d,q);
input [1:0] select;
input [3:0] d;
output q;
wire q ;
wire [1:0] select;
wire[3:0] d;
assign q= d [select];
endmodule

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 Electronic Circuit Design Lab (6ETC07)

RESULTS & ANALYSIS:

Thus, the Verilog code for the 4:1 MUX, simulated using Xilinx project
navigator.

LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 What is the relationship between input lines and select lines?

2 Why a multiplexer is called a data selector?
3 Mention the applications of multiplexer

LIST OF POST-LABQUESTIONS/MODEL ANSWERS:

1 Differentiate between decoder and demultiplexer.

2 To suspend a simulation, use this system task command.
3 Name the bitwise logical operators

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 Electronic Circuit Design Lab (6ETC07)

CONCLUSION:

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 30

 Electronic Circuit Design Lab (6ETC07)

EXPERIMENT NO. 8
AIM: To write Verilog code for implementation for D flip-flop circuit
using Xilinx software tool.
LEARNING OBJECTIVE: -

 To Understand D-FF logic verification using Verilog simulation.

LEARNING OUTCOME:

 Students will able to Verify behavioral and RTL model for D-FF.
SOFTWARE REQUIRED:

SN Name of Software Tool Specification Qty Required

1 SCILAB 6.1.0 ---

THEORY:

D-FF is a sequential flip flop. It is one bit cell and has input as reset clock and
data input. Reset has highest priority whenever RST=1 then FF is rested
when there is a clock event the data input is saved in D-FF and passed on to
the output. Depending upon clock value these are categorized as: a) positive
edge triggered and b) negative edge triggered. Here we use positive edge
triggered.

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 Electronic Circuit Design Lab (6ETC07)

PROCEDURE:

1. Start the program.

2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements for Verilog code.
5. Write the functionality of the gates.
6. Verify the truth table using Isim simulator.
7. Terminate the program.

PROGRAMMING:

# Verilog code for D flip-flop.

module D_flipflop (D,CLK,Q );
input D,CLK;
Output Q;
reg Q;
always @ (D or CLK)
if (CLK)
Q = D;
endmodule
RESULTS & ANALYSIS:
Thus, the Verilog code for the D-FF, simulated using Xilinx project navigator.

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 Electronic Circuit Design Lab (6ETC07)

LIST OF PRE-LAB QUESTIONS/MODEL ANSWERS:

1 Differentiate between combinational and sequential circuits

2 What is meant by triggering of a flip-flop?
3 What do you mean by clock skew?

LIST OF POST-LAB QUESTIONS:

1 What is master-slave flip-flop?

2 Distinguish between latch and edge triggered flip-flop?
3 What is use of characteristic and excitation table?

CONCLUSION:

ASSESSMENT SCHEME:

Pre-Lab In Lab Post Lab Record Total

Test performance Test (5) (15)
(2) (5) (3)

Signature of Faculty

Department of Electronics & Telecommunication Engineering PRPCEM, Amravati 33