Vxibus Products: Description
Vxibus Products: Description
Description
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Mates with user's PCB to
form a C or B-size module.
ICS's Model VXI-5524A is The quickest way to make a
a low-cost VXI Register In- VXI module.
terface for connecting vir-
tually any kind of a circuit ■
Provides 48 latched I/O
to the VXIbus. The VXI-5524A signals, a VXI expansion
provides 48 digital I/O lines to directly bus, TTL Triggers and VXI
control simple circuits or read back data values, a interrupt capability.
16-bit VXI data expansion bus for more complex Supports virtually any kind
circuitry plus triggers and interrupter capability. of user circuit or function.
Applications include prototyping and short run
VXIbus C and B size modules. ■
3.3V, 5 V tolerant Digital IO
VXI-5524A Interface Board and VXIbus signals
Packaging Concept Easily used with 3.3V circuits
without level conversion.
The VXI-5524A interface is a narrow PC card The user interface also has a two trigger lines
that is located at the VXI bus end of the module. that connect to a selected pair of the VXIbus TTL ■
User configurable model
The user places his components on a separate Trigger Lines. The input trigger can be used to
number, manufacturer ID,
printed circuit board which mates with the VXI- start an event on the user's circuit. The output
version and serial numbers
5524A to make a complete 'B' or 'C'' size assembly. trigger line can be used to drive the VXIbus TTL
Identifies the finished module
The two cards mate together with a right-angle Trigger line and trigger other VXI modules. The
as your product.
96-pin DIN connector and are mechanically held user interface has an interrupt line that can be
together with a metal bracket. pulsed to generate a VXIbus interrupt on a selected ■
Two companion compo-
VXI IRQ line. The VXI-5524A reports three nent boards available for
For quick prototyping, ICS offers a companion bits for 8 interrupt codes as part of the interrupt prototype modules
sea-of-holes board with holes on 0.1 inch centers response word. No need to layout prototype
and a bare copper clad board. ICS also supplies The user interface also includes a 10 MHz boards.
design kits and CAD templates so the user can clock and all seven VXIbus voltages.
layout his own printed circuit board. ■
Module hardware kits
Easy Configurability available for building 1, 2
The VXI-5524A can be enclosed with ICS's or 3-slot wide modules.
All of the VXI-5524A's configurable func-
11434x series VXI Hardware Kits to make a Complete hardware support
tions, such as the manufacturer ID code and
complete 1, 2, or 3-slot wide module. Each VXI for C-size modules.
model number, serial number, etc. are stored in
Hardware Kit includes a blank front panel, side
a nonvolatile EEPROM and are restored when
shields and all the hardware necessary to make VXI-1 Rev 4.0 and VXI-2
the card is reset or powered on. The user sets
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VXI bus
VXI-5524A Block Diagram
Three
A block diagram of the VXI-5524A is 16-bit
48 Data Lines
shown in Figure 1 on the right. It shows the 48 VXI Control, Status Bi-dir
Handshake Lines
bidirectional digital I/O lines, an expansion and ID Registers Latch
bus for driving additional circuits, address VD(15:0)
and strobe lines, VXI triggers, interrupt Expansion Bus
Data Bus
inputs, power and clocks. This selection Xcvr
User's Interface
Xcvr
of signals makes it very easy for the user
to build virtually any kind of a circuit on Address Lines
the mating board. Simple circuits with Address and Strobes
minimal data needs can be driven directly Decoder
from the 48 data lines without any additional
Trigger Bi-directional TTL Trigger Pair
logic. More complex circuits such as data TTLTRG0-7
Selector
converters, FIFOs etc. or circuits that need
additional I/O lines can be attached to the IRQ1-7 IRQ VXI Interrupt and Cause Code Lines
buffered expansion bus. Selector
+5, -5, -2, 12, 24V VXIbus Power and Clocks
Data Lines
Up to 48 data lines can be controlled
by addressing the three bidirectional latches Figure 1 VXI-5524A Block Diagram
on the VXI-5524A. The latch direction is
set by bits in the Control Register. When
configured as outputs, the latches hold data
to drive the user's circuits. The latch outputs
are high current drivers capable of sinking 64 Trigger and IRQ Lines PCB Layout Aids
mA and sourcing 24 mA. When configured
The VXI-5524A's Trigger Selection logic ICS provides drawings and CAD design
as inputs, the latches are open circuit inputs
selects a pair of adjacent VXI TTLTRG lines aids to simplify the design of the user's
with pullups to 3.3 Vdc for inputting data
and routes them to the user's circuit board. mating PC board to the VXI-5524A. The
from TTL, CMOS or contact closures. When
The lower TTLTRG line is an input trigger mating board outline drawing and suggested
more than 48 data lines are needed, additional
to initiate action on the user's circuit. The bill of materials are part of the VXI-5524A's
latches or other circuits can be placed on the
higher TTLTRG line drives a VXIbus TTL Instruction Manual.
user's circuit board and attached to the VXI
data expansion bus. Trigger line to trigger other modules.
PCB design files and CAD templates are
The VXI-5524A's IRQ Selection logic also available on a CD-ROM. These design
The data expansion bus is a 16-bit wide
routes a user interrupt onto one of the 7 aids include the board outline drawings,
bus that buffers the VXI D16 data lines onto
VXIbus IRQ lines. When the user's logic parts library and a prototype schematic. The
the user's circuit board. Handshake lines
pulses the IRQ line, the VXI-5524A latches CAD files are supplied as DXF files and in
include an address select strobe, a write line
a 3-bit cause code for use in the Interrupt ORCAD design format. Both file formats
and a not-ready line to hold the VXI DTACK
Response word and for the VXI-2 Interrupt are compatible with most PC layout and
line while the data is being read.
Status Register. schematic capture systems. The prototype
schematic includes all of the signals on the
Register Addressing
Clock and Power user interface. To complete the design, the
All VXI modules are assigned 64 bytes or user just has to add his components to the
thirty-two 16-bit word addresses in the A16 A clock signal and all VXI voltages are
schematic and route the final design.
address space. The VXI-5524A uses the first routed to the user's interface connector. A
sixteen addresses, 00 hex to 1F hex, for its jumper on the VXI-5524A lets the user se-
Complementary CD-ROMs (Part number
VXI registers and for compliance with the lect the VXI-5524A's 10 MHz oscillator or
123153) are available at no charge to any
new VXI Specification for Extended Register the VXIbus CLK10 signal as the module's
qualified VXI designer or customer. Call
Based Devices. Addresses 3A-3E hex are clock source.
for your copy or email [email protected]
used for the 48 data I/O lines. Addresses, with your name, company name and mail-
20 hex to 38 hex, are encoded on 4 address ing address.
lines for the user's logic so they can be easily
decoded with a '138' type decoder to address
additional devices.
VXI-5524A: Specifications
TABLE 1 TABLE 2
User Interface Signal-Pin Assignments Signal Definitions
A1 Inhibit# B1 Cause1 C1 + 12 V A(1:4) Data Bus address lines for VXI register
A2 Clk10 B2 Cause2 C2 - 12 V addresses 20-3A HEX.
A3 NRdy# B3 Cause3/RST# C3 -2V
A4 Clear# B4 EDR# C4 - 5.2 V Acc_LED# Drives Access LED on user's board.
A5 Strobe# B5 Vcc C5 Vcc
A6 DWrite# B6 Gnd C6 Gnd Cause1 User IRQ cause bit 1 (LSB)
A7 DStb# B7 D15 C7 D7 Cause2 User IRQ cause bit 2
A8 IRQ# B8 D14 C8 D6 Cause3/RST# Dual purpose line. If VXI-5524A reset
A9 TrigOut# B9 D13 C9 D5 jumper is not installed, the line is the
A10 TrigIn# B10 D12 C10 D4 IRQ cause bit 3. If the reset jumper is
A11 A1 B11 D11 C11 D3 installed, the line used to reset the VXI-
A12 A2 B12 D10 C12 D2 5524A board logic.
A13 A3 B13 D9 C13 D1
A14 A4 B14 D8 C14 D0 CH(1:48) Data IO lines. Data direction set in 16
A15 CH48 B15 CH40 C15 CH32 line increments by user configuration.
A16 CH47 B16 CH39 C16 CH31
A17 CH46 B17 CH38 C17 CH30 Clear# Clear strobe to reset user's circuits.
A18 CH45 B18 CH37 C18 CH29
A19 CH44 B19 CH36 C19 CH28 Clk10 10 MHz clock. VXIbus CLK10 or VXI-
A20 CH43 B20 CH35 C20 CH27 5524A 10 MHz oscillator.
A21 CH42 B21 CH34 C21 CH26
A22 CH41 B22 CH33 C22 CH25 D(0:15) VXI Expansion Data Bus, D0 is LSB
A23 CH24 B23 CH16 C23 CH8
A24 CH23 B24 CH15 C24 CH7 DStb# Data Bus transfer strobe. Asserted when
A25 CH22 B25 CH14 C25 CH6 Expansion Bus addressed.
A26 CH21 B26 CH13 C26 CH5
A27 CH20 B27 CH12 C27 CH4 DWrite# Data Bus Write direction line. Asserted
A28 CH19 B28 CH11 C28 CH3 when VXIbus is writing data.
A29 CH18 B29 CH10 C29 CH2
A30 CH17 B30 CH9 C30 CH1
EDR# External Data Ready input for handshak-
A31 Acc_LED# B31 SysFail_LED# C31 + 24 V
ing CH input lines. User sets EDR F/F
A32 Rdy_LED# B32 Fail_LED# C32 - 24 V
when data is ready.
Notes:
Fail_LED# Drives Failed LED on user's board.
1. # indicates low true signal.
Inhibit# Inhibit signal from EDR flip-flop. Digi-
tal inputs should be held steady while
Inhibit# is asserted.