材料工程(二)
Topic 3: 晶圓製造
授課教師: 林義峰
4. Wafer Manufacturing 晶圓製造
A. Why silicon ?
B. Crystal structure and Defects
C. From Sand to Wafer
D. Epitaxial Deposition
4. Wafer Manufacturing A. Why silicon ?
Why Silicon? 名稱 矽
符號 Si
原子序 14
• 豐度高, 便宜
原子量 28.0855
• 二氧化矽非常 發現者 鍾斯、傑可柏、柏塞利爾斯
穩定,強介電質
發現地點 瑞典
,容易在熱氧化
發現日期 1824
過程中成長一
層二氧化矽. 名稱來源 由拉丁字silicis衍生而來，意指火石
• 較大的能隙,操 單晶矽的鍵長度 2.352 Å
作溫度的範圍 固體密度 2.33 g/cm3
較大. 摩爾體積 12.06 cm3
音速 2200 m/sec
電阻係數 100,000 μΩ．cm
反射率 28%
熔點 1414 °C
沸點 2900 °C
4. Wafer Manufacturing 晶圓製造
A. Why silicon ?
B. Crystal structure and Defects
C. From Sand to Wafer
D. Epitaxial Deposition
4. Wafer Manufacturing A. Why silicon ?
Crystal Structures
根據原子在固體材料內部的排列方式，可區分為:
• Amorphous 非晶態
– No repeated structure at all
• Polycrystalline 多晶態 Grain
Boundary
– Some repeated structures Grain
• Single crystal 單晶態
• One repeated structure
4. Wafer Manufacturing
B. Crystal structure and Defects
Unit Cell of Single Crystal Silicon
單晶矽之基本的晶格晶胞(Lattice Cell)
單晶矽的每一個矽原子都會
與四個矽原子鍵結在一起
4. Wafer Manufacturing
B. Crystal structure and Defects
Crystal Planes and Miller Indices
Describe the surface of crystal
1 1 1
( , , )
3 2 1
(2,3,6)
Miller Indices
If the plane intercepts 1/h, 1/k, 1/l on the x, y and z axis
The Miller Indices of the plane is (h, k, l)
4. Wafer Manufacturing
B. Crystal structure and Defects
(100) (110) (111)
[111]
[110]
[100]
4. Wafer Manufacturing
B. Crystal structure and Defects
就積體電路製程而言，<100>及<111>是單晶晶圓中最常用的方向
Crystal Orientations: <100> Crystal Orientations: <111>
z z
(100) (111)
<111> plane
<100> plane (100)
<100> plane
y y
x
x
(100)的晶圓校常用來做 (111)的晶圓通常用來做
MOS的IC晶片 雙載子電晶體或積體電
路的IC晶片
4. Wafer Manufacturing
B. Crystal structure and Defects
就積體電路製程而言，<100>及<111>是單晶晶圓中最常用的方向
Crystal Orientations: <100> Crystal Orientations: <111>
z z
<111>的晶圓通常用
來做雙載子電晶體或
積體電路的IC晶片
<111> plane
(100)
<100> plane
(100)
<100> plane (111)
y
y
x
(100) Orientation Plane x (111) Orientation Plane
Basic lattice cell Silicon atom
因為<111>方向的原
子表面密度較高，故
表面較為堅固且比較
適合高功率的元件
4. Wafer Manufacturing
B. Crystal structure and Defects
Crystal Defects
Basic lattice cell Silicon atom
<100> Wafer Etch Pits <111> Wafer Etch Pits
<100>晶圓上的蝕刻班 <111>晶圓上的蝕刻班
4. Wafer Manufacturing
B. Crystal structure and Defects
Illustration of the Defects
Impurity on substitutional site Silicon Atom
雜質原子在取代位置上
Impurity in
Interstitial Site
Silicon 雜質原子在矽間
Interstitial 隙位置上
矽間隙原子
Vacancy or Schottky Defect Frenkel Defect
空位缺陷 法蘭克缺陷
4. Wafer Manufacturing
B. Crystal structure and Defects
Dislocation Defects
差排（Dislocation defects）是晶格的幾何缺陷，這可能是晶格在進行提拉製
程時所造成的，在晶圓製造過程中，差排與過度的機械應力有關：
(1). 不均勻的加熱或冷卻步驟
(2). 掺雜物擴散到晶格內部
(3). 薄膜沉積所造成
晶圓表面上的缺陷會造成電子的散射而導致電阻的增加並影響元件性能，降
低積體電路晶片的生產良率。
4. Wafer Manufacturing 晶圓製造
A. Why silicon ?
B. Crystal structure and Defects
C. From Sand to Wafer
D. Epitaxial Deposition
4. Wafer Manufacturing C. From Sand to Wafer
From Sand to Wafer Grain
Boundary
Grain
砂
變 • Quartz sand: silicon dioxide 二氧化矽
矽 • Sand to metallic grade silicon (MGS) 冶金級矽
矽 • React MGS powder with HCl to form TCS SiHCl3
的
純 • Purify TCS by vaporization and condensation
化 • React TCS to H2 to form polysilicon (EGS) 電子級矽材料
拉晶 • Melt EGS and pull single crystal ingot 矽材料提拉成為單晶晶圓
晶 • Cut end, polish side, and make notch or flat 邊緣圓滑化處理
圓 • Saw ingot into wafers 晶圓切片處理
加
• Edge rounding, lap, wet etch, and CMP 晶圓平坦化處理
工
• Laser scribe
• Epitaxy deposition 磊晶成長(在單晶基片上生長一層薄的單晶層)
4. Wafer Manufacturing C. From Sand to Wafer
From Sand to Silicon Sand to metallic grade silicon (MGS)
砂
• Quartz sand: silicon dioxide 二氧化矽
變
矽 • Sand to metallic grade silicon (MGS) 冶金級矽
Heat (2000° C)
SiO2 + C Si + CO2
Sand Carbon MGS Carbon Dioxide
還原劑 冶金級矽
98~99%
4. Wafer Manufacturing C. From Sand to Wafer
From Sand to Wafer Grain
Boundary
Grain
砂
變 • Quartz sand: silicon dioxide 二氧化矽
矽 • Sand to metallic grade silicon (MGS) 冶金級矽 多晶態
矽 • React MGS powder with HCl to form TCS SiHCl3, 三氯矽烷
的
純 • Purify TCS by vaporization and condensation
化 • React TCS to H2 to form polysilicon (EGS) 電子級矽材料
拉晶 • Melt EGS and pull single crystal ingot 矽材料提拉成為單晶晶圓
晶 • Cut end, polish side, and make notch or flat 邊緣圓滑化處理
圓 • Saw ingot into wafers 晶圓切片處理
加
• Edge rounding, lap, wet etch, and CMP 晶圓平坦化處理
工
• Laser scribe
• Epitaxy deposition 磊晶成長(在單晶基片上生長一層薄的單晶層)
4. Wafer Manufacturing C. From Sand to Wafer
矽 • React MGS powder with HCl to form TCS SiHCl3
Silicon Purification I 的
純
• Purify TCS by vaporization and condensation
化 • React TCS to H2 to form polysilicon (EGS) 電子級矽材料
Heat (300 ° C)
冶金級矽
Si + 3HCl SiHCl3 + H2
MGS Hydrochloride TCS Hydrogen
Hydrochloride Reactor,
300 C
Si + HCl Silicon
MGS
TCS Powder
Condenser
Filters
Purify TCS by vaporization and condensation
Pure TCS with
Purifier
99.9999999%
4. Wafer Manufacturing C. From Sand to Wafer
Polysilicon Deposition, EGS
矽 • React MGS powder with HCl to form TCS SiHCl3
的
純
• Purify TCS by vaporization and condensation
化 • React TCS to H2 to form polysilicon (EGS) 電子級矽材料
React TCS to H2 to form polysilicon (EGS)
Heat (1100 ° C)
Grain
Boundary
SiHCl3 + H2 Si + 3HCl Grain
TCS Hydrogen EGS Hydrochloride
電子級矽材料
Silicon Purification II
Process
Chamber EGS
H2
H2 and TCS
Liquid
TCS TCS+H2EGS+HCl
Carrier gas
bubbles Electronic Grade Silicon
4. Wafer Manufacturing C. From Sand to Wafer
From Sand to Wafer
砂
變 • Quartz sand: silicon dioxide 二氧化矽
矽 • Sand to metallic grade silicon (MGS) 冶金級矽
矽 • React MGS powder with HCl to form TCS SiHCl3
的
純 • Purify TCS by vaporization and condensation
化 • React TCS to H2 to form polysilicon (EGS) 電子級矽材料
拉晶 • Melt EGS and pull single crystal ingot 矽材料提拉成為單晶晶圓
Grain
Boundary
拉晶
Grain
多晶態 單晶態
4. Wafer Manufacturing C. From Sand to Wafer
Crystal Pulling: CZ method Melt EGS and pull single crystal ingot
Czochralski Method, CZ 種晶晶體
查克洛斯基法
Single Crystal Silicon Seed
Quartz Crucible Single Crystal
石英坩鍋
silicon Ingot 單晶矽晶棒
Molten Silicon Heating Coils
1415 °C 電阻式加熱器
Graphite Crucible EGS
石墨坩鍋
矽晶體的直徑能夠藉由溫度及提拉的速度來控制。使用矽單晶晶
棒來做為晶體提拉的種晶，利用提拉速度來控制晶體的直徑。
4. Wafer Manufacturing C. From Sand to Wafer
CZ Crystal Pullers
4. Wafer Manufacturing C. From Sand to Wafer
CZ Crystal Pulling
4. Wafer Manufacturing C. From Sand to Wafer
Crystal Pulling: FZ method 懸浮帶區法
多晶矽 融熔矽
棒
加熱線圈移動
加熱線
圈
單晶矽
種晶
4. Wafer Manufacturing C. From Sand to Wafer
CZ method v.s. FZ method
• 查克洛斯基法是較常用的方法
– 價格便宜
– 較大的晶圓尺寸 (直徑300 mm )
– 晶體碎片和多晶態矽再利用
• 懸浮帶區法
– 純度較高(不用坩堝)
– 價格較高, 晶圓尺寸較小 (150 mm)
– 有差排的晶體
4. Wafer Manufacturing C. From Sand to Wafer
From Sand to Wafer
拉晶 • Melt EGS and pull single crystal ingot 矽材料提拉成為單晶晶圓
晶 • Cut end, polish side, and make notch or flat 邊緣圓滑化處理
圓 • Saw ingot into wafers 晶圓切片處理
加
• Edge rounding, lap, wet etch, and CMP 晶圓平坦化處理
工
• Laser scribe
• Epitaxy deposition 磊晶成長(在單晶基片上生長一層薄的單晶層)
4. Wafer Manufacturing C. From Sand to Wafer
Ingot Polishing, Flat, or Notch
Wafer Sawing 晶圓切片處理
刻痕方向 冷卻液
Orientation Coolant
Notch
晶體晶棒
Crystal Ingot
鋸刀
Saw Blade Ingot
Movement
晶棒移動
Diamond Coating
鑽石薄層
刻痕 不能振動
平邊
Flat, 150 mm and Notch, 200 mm
smaller and larger
定晶圓方向
4. Wafer Manufacturing C. From Sand to Wafer
Parameters of Silicon Wafer
Wafer Size (mm) Thickness (mm) Area (cm 2) Weight (grams)
50.8 (2 in) 279 20.26 1.32
76.2 (3in) 381 45.61 4.05
100 525 78.65 9.67
125 625 112.72 17.87
150 675 176.72 27.82
200 725 314.16 52,98
300 775 706.21 127.62
4. Wafer Manufacturing C. From Sand to Wafer
Wafer Edge Rounding 邊緣圓滑化處理
Wafer movement
Wafer
Wafer Before Edge Rounding
Wafer After Edge Rounding
4. Wafer Manufacturing C. From Sand to Wafer
Wafer Lapping 表面研磨(粗磨)
• Rough polished 研磨漿: 氧化鋁微粒懸浮在甘油中
• conventional, abrasive, slurry-lapping
• To remove majority of surface damage
• To create a flat surface
Wet Etch 溼式蝕刻
• Remove defects from wafer surface
• 4:1:3 mixture of HNO3 (79 wt% in H2O), HF (49 wt% in H2O), and
pure CH3COOH.
• HNO3: Si→SiO2
• HF: SiO2 etching
4. Wafer Manufacturing C. From Sand to Wafer
Chemical Mechanical Polishing • 100 Å SiO2
化學機械研磨 particle in NaOH
Pressure solution
Slurry
Wafer Holder
Wafer
Polishing Pad
4. Wafer Manufacturing C. From Sand to Wafer
200 mm Wafer Thickness and Surface Roughness Changes
After Wafer Sawing
晶圓切片後 914 mm
76 mm
After Edge Rounding 914 mm
邊緣圓滑化處理
12.5 mm
After Lapping 814 mm
表面研磨(粗磨)
<2.5 mm
After Etch 750 mm
溼式蝕刻 幾乎是零缺陷的表面
Virtually Defect Free
After CMP 725 mm
化學機械研磨
4. Wafer Manufacturing 晶圓製造
A. Why silicon ?
B. Crystal structure and Defects
C. From Sand to Wafer
D. Epitaxial Deposition
磊晶成長(在單晶基片上生長一層薄的單晶層)
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxy Grow 磊晶成長(在單晶基片上生長一層薄的單晶層)
•Epitaxial layer is a single crystal layer on a single crystal substrate.
Epitaxy: Purpose
• 雙載子電晶體的載體層
– 當維持在高集崩潰電壓時，降低集極電阻.
– 僅磊晶層.
• 因為比晶圓晶體有較低的氧碳濃度，可增強動態隨機
記憶體(DRAM)和互補型金氧半電晶體積體電路
(CMOS IC)的性能
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxy Application, Bipolar Transistor
射極 基極 集極
Al•Cu•Si
SiO2
n+ p n+
p+ p+
N型磊晶層
電子流
n+ 深埋層
P型晶片
• 雙載子電晶體的載體層
– 當維持在高集崩潰電壓時，降低集極電阻.
– 僅磊晶層.
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxy Application: CMOS
金屬 1, Al•Cu
W
BPSG
STI n+ n+ USG p+ p+
P型井區 N型井區
P型磊晶矽
P型晶圓
• 因為比晶圓晶體有較低的氧碳濃度，可增強動態隨機
記憶體(DRAM)和互補型金氧半電晶體積體電路
(CMOS IC)的性能
4. Wafer Manufacturing D. Epitaxial Deposition
Gas Phase Epitaxy 氣相磊晶
• There are two methods for growing epitaxy silicon layers on
silicon wafers –
(1) CVD epitaxy process 化學氣相沉積磊晶製程
(2) the molecular beam eiptaxy process 分子束磊晶製程
Silicon Source Gases Dopant Source Gases
Silane SiH4 Diborane B2H6
Phosphine PH3
Dichlorosilane DCS SiH2Cl2
Arsine AsH3
Trichlorosilane TCS SiHCl3
N-type
Tetrachlorosilane SiCl4
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxy Growth Process DCS Epitaxy Grow, Arsenic Doping
磊晶成長步驟
•T>700oC: Epitaxy Si
•550oC<T<650oC: Poly Si
•T<550oC: Amorphous Si
Schematic of DCS Epi Grow and SiH2Cl2
Arsenic Doping Process AsH3
H2
HCl
Si AsH3
As H N-type
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Silicon Growth Rate Trends
氣相成核
產生大量粒子 1300 1200 1100 1000 900 800 700
1.0
Growth Rate, micron/min
0.5 Transition Temperature
SiH4
0.2 Mass transport
limited
0.1 SiHCl3
0.05
Surface reaction limited
0.02 溫度敏感 SiH2Cl2
0.01
0.7 0.8 0.9 1.0 1.1
1000/T(K)
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Hardware 磊晶的硬體設備
批式生產
Barrel Reactor 桶狀式反應器
Radiation
Heating
Coils Wafers
優點:
- 有良好的磊晶均勻性
缺點:
- 無法在高溫情形下操作
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Hardware 磊晶的硬體設備
批式生產
Vertical Reactor Horizontal Reactor
Heating Coils
Wafers
Wafers
Reactants
Heating Reactants
Coils Reactants and
byproducts
Reactants and
byproducts
優點: 優點:
- 有良好的磊晶均勻性 - 簡單、便宜
缺點: 缺點:
- 機械複雜性大 - 均勻性不佳
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Hardware 磊晶的硬體設備
Single Wafer Reactor
加熱燈管
幅射線 Heat Heating Lamps
Radiation
Wafer 晶圓
Reactants
反應物 反應物與副產品
Reactants &
byproducts
Susceptor Quartz Quartz 石英視窗
Lift Window
Fingers
•Sealed chamber, hydrogen ambient •Large wafer size (to 300 mm)
•Capable for multiple chambers on a mainframe •Better uniformity control
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Process
•氫氣沖洗清潔, 溫度升高 去除微粒、表面缺陷
•磊晶薄膜成長
•氫氣沖洗, 停止加熱
•晶圓卸載和再裝載
•用氯化氫清潔反應室
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Process
Hydrogen Purge
• 大部分氮氣做為沖洗的氣體
• 氮相當穩定且豐度高
• 超過攝氏1000 C, 氮可以和矽反應
• 氮化矽在晶圓表面會影響磊晶矽沉積製程
• 因此氫氣被用來吹除淨化磊晶反應室
• 藉由與晶圓表面的污染物形成氣態的氫化
物來清潔晶圓表面
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Process
Defects in Epitaxy Layer
表面成核造成的推疊錯誤 由基片推疊錯誤造成的缺陷
Stacking Fault from Stacking Fault form
Surface Nucleation Substrate Stacking Fault
差排 雜質微粒
Dislocation Impurity Particle
尖凸物
Hillock
Epi Layer
Substrate
4. Wafer Manufacturing D. Epitaxial Deposition
Epitaxial Process
Future Trends
• 大晶圓尺寸
• 單晶圓磊晶成長
• 降低磊晶成長的溫度
• 超高真空(UHV, 到 10-9 torr)
• 選擇性磊晶
