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dkkeyanDigital Principles and System
Design
(Second Year B.E/B.Tech Students)
As per the Syllabus & Regulation (KNCET – UGR2020)
(CSE & IT)
EDITED AND COMPILED BY
Mr. A. Suresh Kumar, M.E.,
Assistant Professor
Mrs. R. Deebika, M.E.,
Assistant Professor
Mrs. S. Revathi, M.E.,
Assistant Professor
Kongunadu College of Engineering and Technology, (Autonomous)
Thottiam, Tiruchirappalli
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ISBN : 978-93-90967-82-7
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PREFACE
It gives us a great sense of satisfaction in bringing out the book titled “DIGITAL
PRINCIPLES AND SYSTEM DESIGN” for THIRD SEMESTER B.E / B.Tech students. This
book was prepared to cater to the needs of II YEAR Engineering Students.
This book is divided into five units, covering the topics such as Boolean Algebra and Logic
Gates, Combinational Logic, Synchronous Sequential Logic, Asynchronous Sequential Logic,
Memory and Programmable Logic. It covers the entire syllabus.
The central core of the book is easy, with clear steps and practical applications. The main
concept for the preparation of this book is totally based on the learning capacity of budding
Engineering students from different levels.
Each and every topic in this book is approached with different dimensions, diagrams and
analysis in a lucid manner.
We are glad to receive all your suggestions, comments to enrich the quality of the material
to this mail id [email protected].
ACKNOWLEDGEMENT
We are very much grateful to our Chairman Dr.PSK.R.Periaswamy, Kongunadu
Educational Institutions for his valuable encouragement to write this book.
We sincerely thank our Principal Dr.R.Asokan, Kongunadu College of Engineering and
Technology(Autonomous) for having faith on bringing out this book.
We would like to thank Dr.M.Dharmalingam, Professor & Head, Department of Electronics
and Communication Engineering, Kongunadu College of Engineering and
Technology(Autonomous) for his immense help to bring this book in a short time period.
We thank all the faculty members, friends and family members for providing unconditional
support for bringing out this book on time.
We would welcome suggestions and review comments to improve the book.
SYLLABUS
20EC304 DIGITAL PRINCIPLES SYSTEM DESIGN
OBJECTIVES:
The Student should be made to:
Understand the Digital fundamentals, Boolean algebra and its applications in digital
systems
Familiarize with the design of various combinational digital circuits using logic gates
Introduce the analysis and design procedures for synchronous and asynchronous sequential
circuits
Explain the various semiconductor memories and related technology
Introduce the electronic circuits involved in the making of logic gates.
UNIT I - BOOLEAN ALGEBRA AND LOGIC GATES 9
Number Systems – Decimal, Binary, Octal, Hexadecimal, radix conversion ,1's and
2's complements, Codes – Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems
& Postulates, Logic gates, Universal gates, Sum of products and product of sums, Minterms and
Maxterms, Karnaugh map Minimization
UNIT II - COMBINATIONAL LOGIC 9
Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry
look ahead Adder, BCD Adder, Binary Multiplier, Multiplexer, Magnitude Comparator, Decoder,
Encoder, Priority Encoder – Parity checker & Generator, Introduction to HDL – HDL Models of
Combinational circuits.
UNIT III - SYNCHRONOUS SEQUENTIAL LOGIC 9
Latches, Flip flops – SR, JK, T, D– operation and excitation tables, Triggering of FF,
Analysis and design of clocked sequential circuits – Design - Moore/Mealy models, state
minimization, state assignment, circuit implementation – Design of Counters- Ripple Counters,
Synchronous Counter, Ring Counters, Shift registers, Universal Shift Register- HDL Models of
Sequential Circuits.
UNIT - IV ASYNCHRONOUS SEQUENTIAL LOGIC 9
Stable and Unstable states, output specifications, cycles and races, state reduction, race free
assignments, Hazards, Essential Hazards, Pulse mode sequential circuits, Design of Hazard free
circuits.
UNIT V - MEMORY AND PROGRAMMABLE LOGIC 9
Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static
and dynamic RAM - Programmable Logic Devices – Programmable Logic Array (PLA) -
Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) . Implementation
of combinational logic circuits using PLA, PAL.
TOTAL: 45 PERIODS
OUTCOMES:
On successful completion of this course, the students will be able to,
Simplify digital electronics in the present contemporary world
Design various combinational digital circuits using logic gates
Analysis and design procedures for synchronous and asynchronous sequential circuits
Implement the semiconductor memories and related technology
Demonstrate the electronic circuits involved in the design of logic gates
TEXT BOOK:
1. Morris.M R. Mano, Michael D. Ciletti, "Digital Design: With an Introduction to the Verilog
HDL, VHDL, and SystemVerilo", 6th Edition, Pearson Education, 2018.
REFERENCES:
1. Kharate.G.K, Digital Electronics, Oxford University Press, 2010
2. John F.Wakerly, Digital Design Principles and practices, Fifth Edition, Pearson education,
2017
3. Charles H.Roth Jr, Larry L.Kinney, Fundamentals of Logic design, Sixth Edition,
CENGAGE learning, 2013
CONTENTS
UNIT I – BOOLEAN ALGEBRA AND LOGIC GATES
1.1 Introduction 1.1
1.2 DecimalNumberSystem 1.1
1.3 BinaryNumberSystem 1.1
1.4 OctalNumberSystem 1.2
1.5 HexadecimalNumberSystem 1.2
1.6 NumberBaseConversions 1.3
1.7 Complements 1.12
1.8 SignedBinaryNumbers 1.20
1.9 Binary Arithmetic 1.22
1.10 OtherNumberSystems 1.28
1.11 BinaryCodes 1.28
1.12 ErrorDetectionCodes 1.33
1.13 Alphanumericcode 1.35
1.14 BooleanPostulatesandLaws 1.37
1.15 DeMorgan’sTheorems 1.44
1.16 BooleanRulesforSimplification 1.46
1.17 MinimizationofBooleanExpressions 1.50
1.18 Duality 1.56
1.19 BooleanFunctions 1.58
1.20 ProductofSums(POS)Method 1.59
1.21 SumofProducts(SOP)Method 1.61
1.22 Minterms 1.63
1.23 Maxterms 1.64
1.24 Canonicalform 1.65
1.25 Conversionbetweencanonicalforms 1.71
1.26 KarnaughMaps 1.72
1.27 TabulationMethod(Quine-McCluskeyMethod) 1.98
1.28 BasicLogicGates 1.114
1.29 OtherLogicGates 1.115
1.30 GateConversions 1.118
1.31 DigitalICS 1.120
1.32 UniversalGates 1.121
UNIT II – COMBINATIONAL LOGIC
2.1 Introduction 2.1
2.2 DesignProcedure 2.1
2.3 HalfAdder 2.4
2.4 FullAdder 2.5
2.5 HalfSubtractor 2.8
2.6 FullSubtractor 2.9
2.7 ParallelBinaryAdders 2.12
2.8 ParallelSubtractor 2.13
2.9 BinaryAdder/Subtractor 2.14
2.10 SerialAdder 2.15
2.11 SerialSubtractor 2.17
2.12 SerialAdder/Subtractor 2.17
2.13 BinaryMultiplier 2.18
2.14 CarryLookAheadAdder 2.20
2.15 BCDAdder 2.23
2.16 MagnitudeComparator 2.26
2.17 ParityGeneratorandChecker 2.29
2.18 CodeConverters 2.31
2.19 Decoders 2.39
2.20 Encoders 2.43
2.21 Multiplexers 2.47
2.22 Demultiplexers 2.51
2.23 ImplementationsofCombinationalLogic 2.53
2.24 IntroductiontoHardwareDescriptionLanguage 2.59
2.25 HDLBasedDesignFlow 2.61
2.26 VHDLBuildingBlocks 2.63
2.27 Library 2.72
2.28 TypesandConstants 2.72
2.29 PredefinedTypes 2.73
2.30 User-DefinedTypes 2.74
2.31 SequentialStatements 2.75
2.32 ChallengesinHDL 2.78
2.33 HDLforCombinationalCircuits 2.79
UNIT III – SYNCHRONOUS SEQUENTIAL LOGIC
3.1 Introduction 3.1
3.2 ClassificationofLogicCircuits 3.2
3.3 Flip-flops 3.2
3.4 SRFliflop 3.3
3.5 ClockedSRFlipflop 3.5
3.6 Triggeringofflipflops 3.6
3.7 DFlipflop 3.8
3.8 JKFlipflop 3.9
3.9 TFlipflop 3.11
3.10 MasterSlaveJKFlipflop 3.11
3.11 ExcitationTable 3.12
3.12 RealizationofOneFlipflopusingotherFlipflops 3.15
3.13 Classificationofsynchronoussequentialcircuits 3.19
3.14 StateEquation 3.20
3.15 StateTable 3.20
3.16 StateDiagram 3.20
3.17 AnalysisofSynchronousSequentialCircuits 3.21
3.18 StateMinimization 3.31
3.19 StateAssignment 3.34
3.20 DesignofSynchronousSequentialCircuits 3.35
3.21 ASMChart 3.43
3.22 ShiftRegisters 3.46
3.23 Counters 3.54
3.24 SynchronousCounters 3.58
3.25 Modulus-NCounter 3.64
3.26 ShiftRegisterCounters 3.65
3.27 DesignofCounters 3.68
3.28 Up/DownRippleCounter 3.89
3.29 HDLforSequentialLogicCircuits 3.91
UNIT IV–ASYNCHRONOUS SEQUENTIAL LOGIC
4.1 Introduction 4.1
4.2 TypesofAsynchronousSequentialCircuits 4.1
4.3 TransitionTable 4.2
4.4 FlowTable 4.2
4.5 PrimitiveFlowTable 4.3
4.6 AnalysisofFundamentalModeCircuits 4.3
4.7 AnalysisofPulseModeCircuits 4.7
4.8 Races 4.12
4.9 Cycles 4.14
4.10 RaceFreeStateAssignment 4.14
4.11 MinimizationofPrimitiveFlowTable 4.18
4.12 DesignofFundamentalModeAsynchronousCircuits 4.22
4.13 DesignofPulseModeAsynchronousCircuits 4.29
4.14 Hazards 4.36
4.15 DesignofHazardFreeCircuits 4.37
UNITV–MEMORY AND PROGRAMMABLE LOGIC
5.1 Introduction 5.1
5.2 MemoryUnit 5.1
5.3 WriteOperation 5.2
5.4 ReadOperation 5.3
5.5 ClassificationofMemories 5.3
5.6 RAMOrganization 5.5
5.7 StaticRAMCell 5.6
5.8 BipolarRAMCell 5.7
5.9 MOSFETRAMCell 5.8
5.10 DynamicRAMCell 5.9
5.11 ROM 5.12
5.12 ROMCell 5.12
5.13 ROMOrganization 5.14
5.14 PROM 5.15
5.15 EPROM 5.17
5.16 UVEPROM 5.18
5.17 EEPROM 5.18
5.18 MemoryCycles 5.19
5.19 MemoryDecoding 5.20
5.20 MemoryExpansion 5.22
5.21 AdvantagesofRAM 5.25
5.22 AdvantagesofROM 5.25
5.23 DisadvantagesofROM 5.25
5.24 ComparisonBetweenRAM/ROM 5.26
5.25 ComparisonBetweenSRAM/DRAM 5.26
5.26 ComparisonofTypesofMemories 5.26
5.27 ImplementationofCombinationalLogicCircuits 5.27
5.28 ProgrammableLogicDevices 5.29
5.29 ClassificationofPLDS 5.30
5.30 ProgrammableROM 5.32
5.31 ProgrammableLogicArray 5.34
5.32 ImplementationofCombinationalUsingPLA 5.36
5.33 ProgrammableArrayLogic 5.46
5.34 ImplementationofCombinational 5.47
5.35 FieldProgrammableGateArrays 5.52
5.36 Comparison Between PROM, PLA and PAL 5.54
5.37 EAPROM 5.54
Boolean Algebra and Logic Gates 1.1
UNIT I
BOOLEAN ALGEBRA AND LOGIC GATES
1.1 INTRODUCTION
The number systems are used quite frequently in the field of digital electronics and computers.
Number systems of a given radix or base provide the means of quantifying information for processing
by digital systems. There are several number systems but the following are the important ones in the
field of digital electronics:
Decimal number system Binary number system
Octal number system Hexadecimal number system
1.2 DECIMAL NUMBER SYSTEM
The decimal number system has 10 numerals or symbols. These symbols are 0, 1, 2, 3, 4, 5, 6, 7,
8 and 9. The decimal system is also called the base-10 system because it has 10 digits. The position
weights in decimal number system is shown in Figure 1.1.
103 102 101 100 101 102 103 104
Fig. 1.1: Position weights in binary number system
For example, the decimal number 183 represents one hundred, eight tens and three ones. Any
number has two parts, one part is integer part and the other part is fractional part. The decimal point
is used to separate the integer and fractional parts of the number. The number 8265.14 is equal to,
( ) ( ) ( ) ( ) ( ) ( )
1.3 BINARY NUMBER SYSTEM
The binary number system is a base 2 number system. This number system has two digits 0 and 1.
These digits are called BITS. The position of a 1 or 0 in a binary number indicates its weight or value
within the number. The weights in a binary number are based in powers of two. The position weights
in the binary number system is given in Figure 1.2.
23 22 21 20 21 22 23 24
Fig. 1.2: Position weights in binary number system
The bit at the left most position is called Most-Significant Bit (MSB) and the bit at the right most
position is called Least-Significant Bit (LSB).
MSB LSB
1 1 0 1 1 1 0 0
1.2 Digital Principles and System Design
1.4 OCTAL NUMBER SYSTEM
The octal number system is a base 8 number system. It has eight digits 0, 1, 2, 3, 4, 5, 6 and 7.
Beyond 7, this number system as 10, 11, 12, ... and so on. The position weights in an octal number
system is shown in Figure 1.3.
83 82 81 80 81 82 83
Fig. 1.3: Position weights in an octal number system
1.5 HEXA DECIMAL NUMBER SYSTEM
The hexa decimal number system has a base (radix) of sixteen. It is composed of 16 digits, 0 to 9
and alphabetic characters A, B, C, D, E and F. Hexa decimal numbers are widely used in computer
and microprocessor applications. Most digital systems process binary data in groups that are multiples
of four bits, making the hexadecimal number very convenient. The digit position in a hexadecimal
number system has weights as shown in Figure 1.4.
163 162 161 160 161 162 163
Fig. 1.4: Position Weights in Hexa decimal number
Hexa decimal, Binary and Octal numbers corresponding decimal numbers are given in Table 1.1.
Table 1.1: Number Systems
Decimal Hexa Decimal Binary Octal
0 0 0000 0
1 1 0001 1
2 2 0010 2
3 3 0011 3
4 4 0100 4
5 5 0101 5
6 6 0110 6
7 7 0111 7
8 8 1000 10
9 9 1001 11
10 A 1010 12
11 B 1011 13
12 C 1100 14
13 D 1101 15
14 E 1110 16
15 F 1111 17
Boolean Algebra and Logic Gates 1.3
1.6 NUMBER BASE CONVERSIONS
Man uses decimal number system while computer uses binary number system. Therefore it is
necessary to convert decimal number into its equivalent binary number while feeding the number into
the computer. While the computer displaying the result, it is necessary to convert binary number into
its equivalent decimal number. When the result is in a large quantity of binary numbers of many bits,
like 110011001100001111100, it is inconvenient. Therefore hexa decimal and octal numbers are used
as a short hand means of expressing large binary numbers. The following possible conversions can be
performed in digital systems:
Binary
Decimal Hexa decimal
Octal
Decimal
Binary Hexadecimal
Octal
Binary
Octal Decimal
Hexadecimal
Binary
Hexadecimal Decimal
Octal
1.6.1 Decimal to Binary Conversion
Decimal-to-Binary conversion can be done by using repeated division by 2 for integers.
Example 1.1: 1510 = ?2
2 15
2 71
2 31
11 1510 = 11112
Example 1.2: ?
2 108
2 54 0
2 27 0
2 13 1
2 61
2 30
11 10810 = 11011002
1.4 Digital Principles and System Design
Example 1.3: 0. 8 51 0 = ?2
0.85 2 = 1.7 = 0.7 with a carry of 1
0.7 2 = 1.4 = 0.4 with a carry of 1
0.4 2 = 0.8 = 0.8 with a carry of 0
0.8 2 = 1.6 = 0.6 with a carry of 1
0.6 2 = 1.2 = 0.2 with a carry of 1
0.2 2 = 0.4 = 0.4 with a carry of 0
0.8510 = 0.1101102 (approximate)
Example 1.4: 0. 312510 =?2
0.3125 2 = 0.625 = 0.625 with a carry of 0
0.625 2 = 1.25 = 0.25 with a carry of 1
0.25 2 = 0.50 = 0.50 with a carry of 0
0.50 2 = 1.00 = 0.00 with a carry of 1
0.312510 = 0.01012
Example 1.5: 0.62510 = ?2
0.625 2 = 1.25 = 0.25 with a carry of 1
0.25 2 = 0.50 = 0.50 with a carry of 0
0.50 2 = 1.00 = 0.00 with a carry of 1
0.62510 = 1012
1.6.2 Decimal-to-Hexa Decimal Conversion
The decimal to hexadecimal conversion is explained with the following examples:
Example 1.6: 247910 = ?16
16 2479
16 154 15 (F)
9 10 (A) 247910 9AF16
Example 1.7: 350710 = ?16
16 3507
16 219 3
13 11 (B) 350710 = DB316
Boolean Algebra and Logic Gates 1.5
Example 1.8: 0.6210 = ?16
0.62 16 = 9.92 = 0.92 with a carry of 9
0.92 16 = 14.72 = 0.72 with a carry of 14(E)
0.72 16 = 11.52 = 0.52 with a carry of 11(B)
0.52 16 = 8.32 = 0.32 with a carry of 8
0.6210 = 0.9EB816
Example 1.9: 4019.25710 = ?16
16 4019
16 251 3
15 11 (B) 401910 = FB316
0.257 16 = 4.112 = 0.112 with a carry of 4
0.112 16 = 1.792 = 0.792 with a carry of 1
0.792 16 = 12.672 = 0.672 with a carry of 12(C)
0.672 16 = 10.752 = 0.752 with a carry of 10(A)
4019.25710 = FB3.41CA16
1.6.3 Decimal-to-Octal conversion
The decimal to octal conversion can be done by using repeated division by 8.
Example 1.10: 15310 = ?8
8 153
8 19 1
23 15310 = 2318
Example 1.11: 2 6 51 0 = ?8
8 265
8 33 1
41 2 6 51 0 = 4 1 18
Example 1.12: 0 . 5 51 0 =?8
0.55 8 = 4.4 = 0.4 with a carry of 4
0.4 8 = 3.2 = 0.2 with a carry of 3
0.2 8 = 1.6 = 0.6 with a carry of 1
0.6 8 = 4.8 = 0.8 with a carry of 4
0.8 8 = 6.4 = 0.4 with a carry of 6
0.5510 = 0.431468 (approximate)
1.6 Digital Principles and System Design
Example 1.13: 2479.6410 = ?8
8 2497
8 312 1
8 39 0
47 247910 = 47018
0.64 8 = 5.12 = 0.12 with a carry of 5
0.12 8 = 0.96 = 0.96 with a carry of 0
0.96 8 = 7.68 = 0.68 with a carry of 7
0.68 8 = 5.44 = 0.44 with a carry of 5
2497.6410 = 4701.50758
1.6.4 Binary-to-Decimal Conversion
The positional weight for the binary number system and decimal equivalents are given in
Figure 1.5.
16 8 4 2 1 0.5 0.25 0.125 0.0625 0.03125
24 23 22 21 20 2-1 2-2 2-3 2-4 2-5
Fig. 1.5: Positional weight and decimal equivalents
Example 1.14: 1110112 = ?10
( ) ( ) ( ) ( 0 ) +( ) +( )
= 32 + 16 + 8 + 0 + 2 + 1 = 5910
Example 1.15: 0.11012 = ?10
( ) ( ) ( 0 ) ( 1 )
= 0.5 + 0.25 + 0 + 0.0625 = 0.812510
Example 1.16: 10010.0112 = ?10
( ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 1 ) ( 1 )
=( 1 6+0+0+2+0 )×( 0+0 . 2 5+0 . 1 2 5 )=1 8 . 3 7 51 0
Example 1.17: 01010110.01102 = ?10
( 0 ) ( 1 ) ( 0 ) ( 1 ) +( 0 ) ( 1 ) +( 1 ) +( 0 ) ( 0 )
+( 1 ) + ( 1 ) + ( 0 )
=( 0+6 4+0+1 6+0+4+2+0 )×( 0+0 . 2 5+0 . 1 2 5+0 ) = 86.37510
Boolean Algebra and Logic Gates 1.7
1.6.5 Binary-to-Hexa Decimal Conversion
The binary to hexadecimal conversion is explained with the following examples:
Example 1.18: 1111010101102 = ?16
1111
0101
0110
F 5 6
(111101010110)2 = (F56)16
Example 1.19: 11111100002 = ?16
0011 1111
0000
3 F 0
(1111110000)2 = (3F0)16
Example 1.20: 11101000110101102 = ?16
1110 1000 1101 0110
E 8 D 6
= (E8D6)16
Example 1.21: 0.101101102 = ?16
1011 0110
B 6
(0.10110110)2 = (0.B6)16
Example 1.22: (10111011.1111001)2 = (?)16
1011
1011
1111
0010
B B F 2
= B B F 2 1 6
Example 1.23: (10110001101011.1101101)2 = ?16
0010
1100
0110
1011
1101
1010
2 C 6 B D A
(2C6B DA)16
1.8 Digital Principles and System Design
1.6.6 Binary-to-Octal Conversion
The binary to octal conversion is performed by forming a 3 bit binary group and converting each
3 bit binary to its octal equivalent.
Example 1.24: (10101111)2 = ?8
010
101
111
2 5 7 (10101111)2 = (257)8
Example 1.25: (0.0110111)2 = ?8
011
011
100
3 3 1 (0.110111)2 = (0.331)8
Example 1.26: (1011011.01101)2 = ?8
001 011 011
011 010
1 3 3 3 2 (1011011.01101)2 = (133.32)8
Example 1.27: (1010011.00101)2 = ?8
001
010
011 001
010
1 2 3 1 2 (1010011.00101)2 = (123.12)8
1.6.7 Octal-to-Binary Conversion
The octal number is converted into binary number by a group of 3 bits
Example 1.28: (3574)8 = ?2
3 5 7 4
011 101 111 100 (3574)8 = (11101111100)2
Example 1.29: (0.7460)8 = ?2
7 4 6 0
111 100 110 000 (0.7460)8 = (0.111100110)2
Example 1.30: (34.321)8 = ?2
3 4 3 2 1
011 100 011 010 001 (34.321)8 = (11100.011010001)2
Boolean Algebra and Logic Gates 1.9
1.6.8 Octal-to-Decimal Conversion
The positional weight for the octal number system and their decimal equivalents are given in
Figure 1.6.
512 64 8 1 0.125 0.015625 0.00195
83 82 81 80 81 82 83
Fig. 1.6: Positional weight and decimal equivalent of octal number system
Example 1.31: 4658 = ?10
( ) +( 6 ) +( 5 )
( ) + ( 6 ) + ( 5 )
= 256 + 48 + 5
= 309 (465)8 = (309)10
Example 1.32: 0.7318 = ?10
( 7 ) +( 3 ) +( 1 )
( 7 0. 1 25 )+( 30 . 01 56 25 )+( 10 . 00 19 5)
= 0.92382510 (0.731)8 = (0.923825)10
Example 1.33: 326.2168 = ?10
( 3 ) +( 2 ) +( 6 ) ( 2 ) +( 1 ) +( 6 )
(3)+(2) +
= 214.2773437510
326.216 8 214.2773437510
1.6.9 Octal-to-Hexa Decimal Conversion
Example 1.34: 3278 = ?16
3 2 7
Octal to Binary
011 010 111
0000 1101 0111
Binary to Hex 0 D 7
1.10 Digital Principles and System Design
(327)8 (D7)16
Example 1.35: 6158 = ?16
6 1 5
Octal to Binary
110 001 101
Binary to Hex 0001 1000 1101
1 8 D
(615)8 ( 1 8 D )1 6
Example 1.36: 1024.1028 = ?16
1 0 2 4 1 0 2
Octal to Binary
001 000 010 100 001 000 010
Binary to Hex 0010 0001 0100 0010 0001 0000
2 1 4 2 1 0
(1024.102)8 = (214.210)16
1.6.10 Hexadecimal-to-Binary Conversion
The hexadecimal-to-binary conversion is explained with following examples:
Example 1.37: 30616 = ?2
3 0 6
0011 0000 0110 (306)16 = (1100000110)2
Example 1.38: 9 A F F1 6 = ? 2
9 A F F
1001 1010 1111 1111 ( 9 A F F)1 6 = (100110101111.1111)2
Example 1.39: 7 A F 4 B B 1 6 = ? 2
7 A F 4 B B
0111 1010 1111 0100 1011 1011
1
( 7 A F 4 B B)1 6 = (111101011110100.10111011)2
Boolean Algebra and Logic Gates 1.11
1.6.11 Hexa Decimal-to-Decimal Conversion
The positional weight for the hexadecimal number system and their decimal equivalents are given
in Figure 1.7.
4096 256 16 1 0.0625 0.0039 0.00024
163 162 161 160 161 162 163
Fig. 1.7: Positional weight and decimal equivalent of Hex
Example 1.40: 2 F 5 91 6 =?1 0
( 2 ) +( F ) +( 5 ) ( 9 )
( 2 ) +( 1 5 ) + ( 5 ) ( 5 ) +9
= 1212110 ( 2 F 5 9)1 6 = (12121)10
Example 1.41: A B C D1 6 =?1 0
( A ) +( B ) +( C ) ( D )
( 1 0 ) +( 1 1 ) + ( 1 2 ) ( 1 3)
= 40960 + 2816 + 192 + 13
= 4398110 ( A B C D )1 6 = (43981)10
Example 1.42: F 8 E 61 6 =?1 0
( 1 5 ) +( 8 ) +( 1 4 ) ( 6 ) ( 3 ) +( 9 )
= ( 6 1 4 4 0 ) ( 0 . 1 8 7 5+0 . 0 3 5 2 )
= 63718.222710 ( F 8 E 6 )1 6 = (63718.2227)10
1.6.12 Hexa Decimal-to-Octal Conversion
Convert the given hexadecimal number into its equivalent 4 bit binary number and regroup the
bits in 3 bit group. Then 3 bit binary number is converted into octal number.
Example 1.43: 2 5 B1 6 =?8
2 5 B
0010 0101 1011
Binary 001 001 011 0111
Octal 1 1 3 3
( 2 5 B)16 =( 1 1 3 3 )8
1.12 Digital Principles and System Design
Example 1.44: A 2 4 61 6 =?8
A 2 4 6
1010 0010 0100 0110
Binary
001
010
001 001 000 110
Octal 1 2 1 1 0 6
(A246)16 =(121106)8
Example 1.45: 5 C 2 . 3 91 6 =?8
5 C 2 3 9
0101 1100 0010 0011 1001
Binary 010 111 000
010 001 110 010
Octal 2 7 0 2 1 6 2
( 5 C 2 . 3 9 )1 6 =( 2 7 0 2 . 1 6 2 )8
1.7 COMPLEMENTS
Complements are used in digital computers for simplifying the subtraction operation and for
logical manipulation. There are two types of complements:
r’s complement
(r 1)’s complement
For binary numbers, r(base) = 2
2’s complement
1’s complement
For decimal numbers, r(base) = 10
10’s complement
9’s complement
1.7.1 1’s Complement
The 1’s complement of a binary number is the number that results when we complement each bit.
If the binary number is,
A A A A
The 1’s complement is
A A A A
Boolean Algebra and Logic Gates 1.13
Therefore, the 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s.
The following are some examples:
The 1’s complement of 10110001 is 01001110
The 1’s complement of 1111 is 0000
1.7.2 2’s Complement
The 2’s complement is the binary number that results when we add 1 to the 1’s complement. i.e.,
2’s complement = 1’s complement + 1
If the binary number is 1101
1’s complement 0010
1(+)
2’s complement 0011
1
Some other examples of 2’s complements:
Binary Number 1’s Complement 2’s Complement
1000 0001 0111 1110 0111 1111
1111 1001 0000 0110 0000 0111
1.7.3 1’s Complement Subtraction
Subtraction of binary numbers using 1’s complement method allows subtraction only by addition.
To subtract a smaller number from a large number (X Y), the 1’s complement method as follows:
Obtain the 1’s complement of the smaller number (Y)
Add this to the large number (X)
Remove the carry and add it to the result. This carry is called ‘end- around-carry’.
Example 1.46: X Y
X , Y
1’s complement of Y = 0101
Solution: X = 1110
1’s complement of Y = 0101 (+)
Sum = 1 0011
End-around carry = 1 (+)
X Y = 0100
1.14 Digital Principles and System Design
Example 1.47: (X Y) = 9 3 = 6
X = 1001
1’s complement of Y = 1100 (+)
Sum = 1 0101
End-around carry = 1 (+)
XY= 0110
Subtraction of a large number (X) from a smaller (Y), the 1’s complement method as follows:
Obtain the 1’s complement of the larger number (X).
Add this to the smaller number (Y).
The answer is the 1’s complement of the result and is opposite in sign. There is no carry.
Example 1.48: Y X = 10 14 = 4
X = 1110
1’s complement of X = 0001
Y = 1010
Solution: Y = 1010
1’s complement of X = 0001 (+)
Sum = 1011
1’s complement of result (1011) is 0100 and is opposite sign. i.e., 0100.
Example 1.49: Y X = 3 9 = 6
X = 1001
1’s complement of X = 0110
Y = 0011
Solution: Y = 0011
1’s complement of X = 0110 (+)
Sum = 1001
1’s complement of result (1001) is 0110 and is opposite sign.
i.e., 0110.
1.7.4 2’s Complement Subtraction
The subtraction of a small number from a large number by the 2’s complement method is as
follows:
Boolean Algebra and Logic Gates 1.15
(i) Determine the 2’s complement of the smaller number
(ii) Add this is to the larger number
(iii) Omit the carry.
Example 1.50: X Y = 14 10 = 4
X = 1110
Y = 1010
1’s complement of Y = 0101
1 (+)
2’s complement of Y = 0110
Solution: X = 1110
2’s complement of Y = 0110 (+)
1 0100
The carry (1) is discarded. Therefore the result is (0100).
Example 1.51: X Y = 1010100 1000011
1’s complement of Y = 0111100
1 (+)
2’s complement of Y = 0111101
Solution: X = 1010100
2’s complement of Y = 0111101 (+)
1 0010001
Ans: X Y = 0010001
The subtraction of a larger number from a smaller number is as follows:
Determine the 2’s complement of the larger number.
Add 2’s complement to the smaller number.
There is no carry. The result is in 2’s complement form and is negative.
To get the true answer, take 2’s complement of the result and change the sign.
Example 1.52: Y X = 10 14 = 4
Y = 1010
X = 1110
1’s complement of X = 0001
1 (+)
2’s complement of X = 0010
Solution: Y = 1010
2’s complement of X = 0010 (+)
1100
Y X = (2’s complement of 1100)
1.16 Digital Principles and System Design
1’s complement of 1100 = 0011
1
2’s complement of 1100 = 0100
Therefore the true answer is 0100
Example 1.53: (Y X) = 9 10 = 1
Y = 1001
X = 1010
1’s complement of X = 0101
1 (+)
2’s complement of X = 0110
Solution: Y = 1001
2’s complement of X = 0110 (+)
1111
(Y X)= (2’s complement of 1111)
1’s complement of 1111 = 0000
1 (+)
2’s complement of 1111 = 0001
Y X = 0001
1.7.5 Comparison of 1’s and 2’s complements
The 1’s complement can be easily obtained using an inverter. The 2’s complement is obtained as
adding ‘1’ to the 1’s complement.
The 2’s complement system requires only one arithmetic operation, but the 1’s complement
system requires two arithmetic operations.
The 1’s complement is used in logical manipulation for inversion operation; the 2’s complement
is used only for arithmetic applications.
1.7.6 9’s Complement
The 9’s complement of a decimal number is found by subtracting each digit in the number from 9.
The examples of 9’s complement are:
(i) 9’s complement of 71 is, 99
17
82
(ii) 9’s complement of 444 is, 999
444 ()
555
Boolean Algebra and Logic Gates 1.17
(iii) 9’s complement of 1542701 is, 9999999
1542701
8457298
1.7.7 10’s Complement
The 10’s complement of a decimal number that results add 1 to its 9’s complement.
(i) 10’s complement of 71 is, 99
17 ()
82
1 (+)
83
(ii) 10’s complement of 444 is, 999
444 ()
555
1 (+)
556
(iii) 10’s complement of 1542701 is, 9999999
1542701 ()
8457298
1 (+)
8457299
1.7.8 9’s Complement Subtraction
The 9’s complement subtraction method is same as the 1’s complement subtraction method. The
9’s complement method for subtraction a smaller number from a larger number is as follows:
Determine the 9’s complement of the smaller number
Add this is to the larger number
Remove the carry and add it to the result
Example 1.54: 98 18 = 80
9’s complement of 18, 99 18 = 81
98
81 (+)
Carry (1) 79
1 (+)
80
1.18 Digital Principles and System Design
Example 1.55: 55 10 = 45
9’s complement of 10 is, 99 10 = 89
55
89 (+)
Carry (1) 44
1 (+)
45
Subtraction of a larger number from a smaller one by the 9’s complement method is as follows:
Determine the 9’s complement of the larger number.
Add this is to the smaller number.
The answer is the 1’s complement of the true result and is opposite in sign.
Example 1.56: 15 67 = 52
9’s complement of 67 is, 99 67 = 32
15
32 (+)
47
True result = (1’s complement of 47)
i.e., (99 47) = 52
Example 1.57: 265 347 = 082
9’s complement of 347 is, 999 347 = 652
265
652 (+)
917
True result = (1’s complement of 917)
= (999 917)
= (082)
1.7.9 10’s Complement Subtraction
Subtraction of a smaller number from a larger number by the 10’s complement method is as
follows:
Determine the 10’s complement of the smaller number.
Add this is to the larger number.
The carry is discarded.
Boolean Algebra and Logic Gates 1.19
Example 1.58: 25 15 = 10
1’s complement of 15 = 99 15 = 84
2’s complement of 15 = 84 + 1 = 85
25
85 (+)
(1) 10 Ans: 10
Example 1.59: 786 - 412 = 374
1’s complement of 412 999
412
587
1 (+)
2’s complement of 412 588
786
588 (+)
Carry (1) 374 Ans: 374
The 10’s complement method for subtraction of a larger number from a smaller number is as
follows:
Determine the 10’s complement of larger number.
Add this to the smaller number.
The result is in 10’s complement form and is negative.
To get an answer in true form, take the 10’s complement and change the sign.
Example 1.60: 31 57 = 26
9’s complement of 57 99
57 ()
42
1 (+)
10’s complement of 57 43
31
43 (+)
74
Result = (10’s complement of 74)
9’s complement of 74 is 99
74 ()
25
10’s complement of 74 is 25 + 1 = 26. 31 57 = 26.
1.20 Digital Principles and System Design
Example 1.61: 265 347 = 082
9’s complement of 347 999
347 ()
652
1 (+)
9’s complement of 347 653
265
653 (+)
918
Result = (10’s complement of 918)
9’s complement of 918 999
918 ()
81
1 (+)
10’s complement of 918 82 265 347 = 82.
NOTE: The same proceudre is used to find the solution for subtraction with 7’s complement, 8’s
complement, 15’s complement and 16’s complement.
1.8 SIGNED BINARY NUMBERS
Digital systems must be able to handle both positive and negative numbers. In ordinary arithmetic,
a positive number is indicated by a ‘+’ sign and a negative number is indicated by a ‘’ sign. But in
binary numbers, the left most bit (sign bit) denotes the sign.
0 is used for the +ve sign and 1 is used for the ve sign. Therefore 001, 111 are coded as 1001,
1111. These numbers contain a sign bit followed by magnitude bits. Numbers in this form are called
signed binary numbers.
When a signed binary number is represented in sign-magnitude form, the left-most bit is the sign
bit and the remaining bits are the magnitude bits. For example + 32 is expressed as an 8 bit signed
binary number using the sign-magnitude form as,
0 0100000
Sign bit Magnitude bits
32 is represented as 10100000
Thus in the sign-magnitude form, a negative number has the same magnitude bits as the
corresponding positive number, but the sign bit is ‘1’ rather than ‘0’.
Some other examples are:
(i) 18 10010010 (ii) 97 11100001
+ 18 00010010 + 97 01100001
Boolean Algebra and Logic Gates 1.21
The sign-magnitude for the decimal numbers ( 15 to + 15) are represented in Table 1.2.
In the 1’s complement form of signed binary numbers, a negative number is the 1’s complement
of the corresponding positive number.
For example, 8 is represented as 10001000
Signed 1’s complement 11110111 (1’s complement of + 8)
In the 2’s complement form, a negative number is the 2’s complement of the corresponding positive
number. Signed 2’s complement of 8 is,
11110111
1 (+)
11111000 (2’s complement of + 8)
Range of signed numbers
For 8 bit numbers,
Unsigned numbers range = 0 to 2n 1
= 0 to 255
Signed numbers range = (2n 1) to + (2n 1 1)
= 128 to + 127
16 bit signed numbers range = 32768 to + 32767
Table 1.2: Sign-Magnitude Numbers
Decimal Sign Decimal Sign
Magnitude Magnitude
+ 15 01111 15 11111
+ 14 01110 14 11110
+ 13 01101 13 11101
+ 12 01100 12 11100
+ 11 01011 11 11011
+ 10 01010 10 11010
+ 9 01001 9 11001
+ 8 01000 8 11000
+ 7 00111 7 10111
+ 6 00110 6 10110
+ 5 00101 5 10101
+ 4 00100 4 10100
+ 3 00011 3 10011
+ 2 00010 2 10010
+ 1 00001 1 10001
+ 0 00000 0 10000
1.22 Digital Principles and System Design
1.9 BINARY ARITHMETIC
1.9.1 Binary Addition
A+ B Sum Carry
0+0 0 0
0+1 1 0
1+0 1 0
1+1 0 1
The examples for binary additon are given below:
Example 1.62:
0011
1010 (+)
1101
Example 1.63:
0101 0111
0011 0101 (+)
1000 1100
Example 1.64
57.5 + 0.3125 = 57.8125
111001.1000
000000.0101 (+)
111001.1101
Example 1.65
31.75 + 19.25 = 51.00
011111.110
010011.010 (+)
110011.000
Example 1.66
101.01 + 110 + 10.1 = ?
101.01
110.00
1011.01
10.10
1101.11
Boolean Algebra and Logic Gates 1.23
Example 1.67
101101 + 1110 + 110 = ?
101101
1110
110
1000001
Note: 1 + 1= 10
1 + 1+ 1 = 11
1 + 1 + 1 + 1 = 100
1.9.2 Binary Subtraction
AB Difference Borrow
00 0 0
01 1 1
10 1 0
11 0 0
Example 1.68: 1011
0101 ()
0110
Example 1.69: 111.01
100.10 ()
010.11
Example 1.70: 10101.001
01110.110 ()
00110.011
Note: For binary subtraction, use 1’s complement and 2’s complement methods also.
1.9.3 Binary Multiplication
The four basic rules for multiplying bits are as follows:
0 0=0
0 1=0
1 0=0
1 1=1
1.24 Digital Principles and System Design
Example 1.71: 110
101
110
000
110
11110
Example 1.72: 110.1 10.1
110.1
10.1
1101
0000
1101
10000.01
1.9.4 Binary Division
Example 1.73: 110 111
10
11 110
11
000 110 11 = 10
Example 1.74: 110 10
11
10 110
10
10
10
00 110 10 = 11
1
1.9.5 Addition with signed numbers
There are 4 cases that can occur when two signed binary numbers are added.
Both numbers are +ve
+ve number with magnitude larger than ve number
ve with magnitude larger than +ve number
Both numbers are ve
1. Addition of two positive numbers yields a positive number
6 00000110
13 (+) 00001101
19 00010011
Boolean Algebra and Logic Gates 1.25
2. Addition of a positive number and a smaller negative number yields a positive number,
+ 13 00001101
6 (+) 11111010
+7 (1) 00000111
discard carry
3. Addition of a positive number and a larger negative number yields a negative number in 2’s
complement
+ 6 00000110
13 (+) 11110011
17 (1) 11111001
discard carry The sum is negative and therefore 2’s complement form.
4. Addition of two negative numbers yields a negative number in 2’s complement
6 11111010
13 (+) 11110011
19 11101101
The sum is negative and therefore in 2’s complement form.
Example 1.75: Perform each of the following computations using signed, 8 bit words in 1’s complement
and 2’s complement binary arithmetic. (Dec. 2005)
1. (+95)10 + (63)10
2. (+42)10 + (87)10
3. (13)10 + (59)10
4. (+38)10 + (38 )10
5. (105 )10 + (120 )10
1. (+95)10 + (63 )10 .
In signed binary number, the left most bit is the sign bit and the remaining bits are the magnitude
bits.
(+63 )10 = 0 0111 111
(63 )10 = 1 01111111
sign magnitude
1’s complement of (63)10 = 1 1000000
2’s complement of (63)10 = 1 1000001
1.26 Digital Principles and System Design
1’s complement arithmetic
(+95)10 + (63)10
(+95)10 0101 1111
1
(63)10 1100 0000
1 0001 1111
+ 1
0010 0000 = +32
2’s complement arithmetic
(+95) + (63)
0101 1111
1100 0001
0010 0000 = +32
2. (+42)10 + (87 )10
(+87)10 = 0 1010111
(87)10 = 1 1010111
1’s complement of ()10 = 1 0101000
2’s complement of (7)10 = 1 0101001
1’s complement arithmetic
(+42 )10 + (87 )10
0010 1010
1010 1000
1101 0010
1’s complement of result is 1 0101101 = 45
2’s complement arithmetic
00101010
10101001
11010011 = 45
Since the two’s complement of 1101 0011 is (0010 1100 + 1 = 0010 1101) (+45)10, 1101 0011 is
(45)10.
3. (13)10 + (59)10
(+13) 0 000 1101
(13) 1 000 1101
(+59) 0 0111 011
(59) 1 0111011
Boolean Algebra and Logic Gates 1.27
1’s complement arithmetic
(13)10 + (59 )10
Sign
1’s complement of (13)10 = 1 111 0010
1’s complement of (59)10 = 1 1000100
1 1 0110110
+1
1 01100111
1’s complement of result is 1 1001000 = 72
2’s complement arithmetic
2’s complement of (13) = 1 111 0011
2’s complement of (59) = 1 100 0101
1 011 1000 = 72
Since 2’s complement of result is
01001000 = +72, 10111000 = 72.
4. (+38)10 + (38)10
(+38) = 0 0100110
(38) = 1 0100110
1’s complement of (38) = 1 1011001
2’s complement of (38) = 1 1011010
1’s complement arithmetic
0 0100110
1 1011001
1 1111111
1’s complement of result is 1 000000 = 0
2’s complement arithmetic
0 0100110
1 1011010
0 0000000 = 0
5. (105)10 + (120)10
(+105) = 0 1101001
(105) = 1 1101001
(+120) = 0 1111000
(120) = 1 1111000
1.28 Digital Principles and System Design
1’s complement arithmetic
(105) + (120)
1’s complement of (105) = 1 0010110
1’s complement of (120) = 1 0000111
1 0 0011101
+1
0 10011110 = 30
2’s complement arithmetic
2’s complement of (105) = 1 0010111
2’s complement of (120) = 1 0001000
0 0 011111 = 31
Error occurs due to overflow.
1.10 OTHER NUMBER SYSTEMS
Table 1.3 shows the some positional number system and their possible symbols.
Table 1.3: Number Systems
Number System Base Possible Symbols
Binary 2 0, 1
Ternary 3 0, 1, 2
Quarternary 4 0, 1, 2, 3
Quinary 5 0, 1, 2, 3, 4
Octal 8 0, 1, 2, 3, 4, 5, 6, 7
Decimal 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
Duodecimal 12 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B
Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
1.11 BINARY CODES
The digital data is represented, stored and transmitted as groups of binary bits. The group of bits
is called as binary code. The binary code represent numbers, alphabets, special characters and control
functions. The codes are classified as,
Weighted codes
Non-weighted codes
Error detecting and correcting codes
Alphanumeric codes
Boolean Algebra and Logic Gates 1.29
Codes
Weighted codes Non-weighted Alphanumeric Error detecting
Codes Codes and correcting codes
Excess-3 Gray Parity Hamming
BCD 5421 2421 84 74 ASCII EBCDIC Hollerith
(8421)
1.11.1 Weighted Codes
Weighted binary codes obey their positional weighting principles. Each digit position of a number
represents a specific weight. The bits are multiplied by the weights and the sum of these weighted bits
give the equivalent decimal value.
8421 code is the binary-coded-decimal (BCD) code. The other 4 bit weighted binary codes are:
5421, 2421, 8 4 , 74 etc. The examples for 5 bit code are 84621, 51111 and 63210 code. The
example for 7 bit code is biquinary (5043210) code.
1. BCD (8421) Code
The binary-coded-decimal (BCD) uses the binary number system to specify the decimal numbers
0 to 9. It has 4 bits. It is called 8 4 2 1 code, i.e., bit 3 has weight 8(23), bit 2 has weight 4(22), bit
1 has weight 2(21) and bit 0 has weight 1(20). Table 1.4 shows the 8421 BCD code used to represent
the decimal digits.
Table 1.4: BCD Code
Decimal Digit BCD Code
8 4 2 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0001 0000
11 0001 0001
12 0001 0010
1.30 Digital Principles and System Design
2. Other 4 bit codes: Table 1.5 shows the 4 bit binary codes for the decimal digits 0 to 9.
Table 1.5: Binary Codes
Decimal 5421 2421 84 74
0 0000 0000 0000 0000
1 0001 0001 0111 0111
2 0010 0010 0110 0110
3 0011 0011 0101 0101
4 0100 0100 0100 0100
5 1000 1011 1011 1010
6 1001 1100 1010 1001
7 1010 1101 1001 1000
8 1011 1110 1000 1111
9 1100 1111 1111 1110
Representation of decimal digit 7 in 5421 code:
() ( 0 ) () ( 0 )
Representation of decimal digit 5 in 2421 code:
() ( 0 ) () ( 1)
Representation of decimal digit 2 in 8 4 code:
( 0 ) ( 1) ( ) ( 0 )
Representation of decimal digit 1 in 7 4 code:
( 0 ) ( 1) ( ) ( 1)
The some other weighted 4 bit binary codes are:
3321 Code
4221 Code
5221 Code
5311 Code
6311 Code
7421 Code
1.11.2 Non Weighted Codes
Non-weighted codes are codes that are not positionally weighted, i.e, each position within a binary
number is not assigned a fixed value. The non-weighted codes are:
Excess-3 (XS 3) Code
Gray Code
(i) Excess-3 Codes: The excess-3 code is a modified form of binary number. It is obtained by
simply adding ‘3’ to a decimal number. For example, to encode the decimal number ‘4’ into an
excess 3 code, first add 3. i.e., 4 + 3 = 7. Then it is encoded into binary code 0111. Table 1.6
Boolean Algebra and Logic Gates 1.31
shows excess-3 codes to represent decimal numbers. XS 3 code is also called as reflective
code.
Table 1.6: Excess-3 Codes
Decimal BCD Code XS 3 Code
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100
10 0001 0000 0100 0011
11 0001 0001 0100 0100
12 0001 0010 0100 0101
(ii) Gray Codes: In gray code, numbers differ from any adjacent number by a single bit. For example,
in going from decimal 3 to 4, the Gray-code number changes from 0010 to 0110. Every number
differs by only 1 bit from the preceding number. It is also called as unit-distance code or reflected
code. Table 1.7 shows the gray code representation.
Table 1.7: Gray Codes
Decimal Binary Code Gray Code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
1.32 Digital Principles and System Design
(iii) Binary-to-Gray Code Conversion: The binary-to-gray code conversion is achieved using
following rules:
The most significant bit (MSB) in the Gray code is the same as the corresponding MSB in the
binary number.
Going from left to right, perform an EX-OR operation between the adjacent pair of binary code
bits to get the next Gray code bit.
Example 1.76: Convert the binary number 1001 to Gray code,
Binary : 1 0 0 1
Gray : 1 1 0 1
Gray Code : 1101
Example 1.77: Convert the binary (10110)2 to its gray code.
Binary : 1 0 1 1 0
Gray : 1 1 1 0 1
Gray Code : 11101
Let the binary number is represented as B, B , B ,. . . , BN and gray code is G, G , G ,. . . , GN then
G B
G B B
G B B
.
.
.
G N B N BN
(iv) Gray-to-Binary Code Conversion: The gray-to-binary code conversion is achieved using
following rules:
The MSB in the binary code is the same as the corresponding bit in the gray code.
To obtain the next binary digit, perform an EX-OR operation between the bit just written down
and the next gray code bit.
Example 1.78: Convert the Gray code 1000 to binary
Gray : 1 0 0 0
Binary : 1 1 1 1
Binary Number : 1 1 1 1
Boolean Algebra and Logic Gates 1.33
Example 1.79: Convert the gray code 10101111 to binary
Gray : 1 0 1 10 1 1 1
Binary : 1 1 0 0 1 0 1 0
Binary number is 11001010
1.12 ERROR DETECTION CODES
1.12.1 Parity Bit
In any electronic system involving the transfer of data (in the form of binary digits) then data
transmission errors are possible. Any external noise introduced in the physical communication medium
may change some of the bits from 0 to 1 or 1 to 0. The purpose of an error-detection code is to detect
such bit-reversal errors. The method of Parity is widely used as a method of error detection.
A parity bit is an extra bit included with a message to make the total number of 1’s transmitted
either odd or even.
Even Parity: The value of the parity bit is set such that the total number of 1’s in the data word is
even.
Example : 11001 which has an odd number of 1's. The new total group is thus 110011.
11110 which has an even number of 1's. The new total group is thus 111100.
Odd Parity: The value of the parity bit is set such that the total number of 1's in the data word is odd.
Example: 11001 which has an odd number of 1’s. The new total group is thus 110010.
11110 which has an even number of 1’s. The new total group is thus 111101.
A message of 4 bits and a parity bit are shown in Table 1.8.
Error-Detection
Let an even parity bit is generated in the sending end for each message transmission. The message,
together with the parity bit is transmitted to its destination. The parity of the received data is checked
in the receiving end. If the parity of the received information is not even, it means that atleast one bit
has changed value during the transmission. This method detects 1, 3 or any odd combination of errors
in each message that is transmitted. An even combination of errors is undetected.
1.12.2 2-out of-5 Code
2-out of-5 code is used for error detection in communications work. It utilizes five bits to represent
the ten decimal digits, so it is a form of BCD code. Each code word has exactly two 1’s, a convention
that facilitates decoding and provides for better error detection than the single-parity-bit method. If
more or less than two 1’s appear, an error is detected.
1.34 Digital Principles and System Design
Table 1.8: Parity Bit
ODD Parity EVEN Parity
Message P Message P
0000 1 0000 0
0001 0 0001 1
0010 0 0010 1
0011 1 0011 0
0100 0 0100 1
0101 1 0101 0
0110 1 0110 0
0111 0 0111 1
1000 0 1000 1
1001 1 1001 0
1010 1 1010 0
1011 0 1011 1
1100 1 1100 0
1101 0 1101 1
1110 0 1110 1
1111 1 1111 0
1.12.3 63210 Code
This is a BCD code. Like 2-out of-5 code, it is also characterized by having exactly two 1’s in
each 5 bit groups.
1.12.4 50 - 43210 Code
This code is also called as Biquinary (two five) code. It is used in counters and is composed of
a 2 bit group and a 5 bit group, each with a single 1. Its weights are 50 43210. The 2 bit group,
having weights of five and zero, indicates whether the number represented is less than, equal to, or
greater than 5. The 5 bit group indicates the count above or below 5.
During transmission of signals from one location to another, an error may occur. One or more bits
may change value. A circuit in the receiving side can detect the presence of more or less than two 1’s
and if the received combination of bits does not agree with the allowable combination, an error is
detected.
1.12.5 Ring Counter Code
This code has ten bits, one for each decimal digit, and a single 1 makes error detection possible.
It is easy to decode but wastes bit and requires more circuitry to implement than the 4 bit or 5 bit
codes. Its weights are 9876543210. It is used in shift registers and ring counters.
Boolean Algebra and Logic Gates 1.35
Table 1.9 shows these error detection codes.
Table 1.9: Error Detection Codes
Decimal 2-out of-5 63210 50 43210 9876543210
0 00011 00110 01 00001 0000000001
1 00101 00011 01 00010 0000000010
2 00110 00101 01 00100 0000000100
3 01001 01001 01 01000 0000001000
4 01010 01010 01 10000 0000010000
5 01100 01100 10 00001 0000100000
6 10001 10001 10 00010 0001000000
7 10010 10010 10 00100 0010000000
8 10100 10100 10 01000 0100000000
9 11000 11000 10 10000 1000000000
1.13 ALPHANUMERIC CODES
Alphanumeric codes are used to represent numbers, letters and other special features using binary
bits. The alphanumeric codes are encoding the following:
Decimal digits (0 9)
Alphabetic characters (A to Z and a to z)
Mathematical symbols (like, +, =, < , >)
Special control characters (like, ESC, NUL, ACK)
The alphanumeric codes are,
ASCII Code,
EBCDIC Code,
Hollerith Code.
1.13.1 ASCII Code
ASCII [American Standard Code for Information Interchange] is a 7 bit code, which is used to
represent numbers, letters, characters and other special computer control functions. ASCII is pronouced
as “as-kee”.
ASCII is 7 bit code, therefore it has 27 = 128 characters.
Upper case alphabets = 26
Lower case alphabets = 26
Decimal digits (0 9) = 10
Special symbols = 33
Control characters = 33
Total = 128
The ASCII characters, ASCII values in binary, decimal and hexadecimal are shown in Appendix 1.
1.36 Digital Principles and System Design
1.13.2 EBCDIC Code
EBCDIC [Extended Binary Coded Decimal Interchange Code] is an 8-bit code, pronounced as
“eb-see-disk”. It differs from ASCII code only in its code grouping for the different alphanumeric
characters.
EBCDIC has 28 = 256 characters, in which 117 are unassigned. The remaining 139 characters are
as follows:
Upper case alphabets = 26
Lower case alphabets = 26
Decimal digits (0 9) = 10
Special symbols= 27
Control characters = 50
Total = 139
The control characters are placed in between 0000 0000 and 0011 1111 and the alphanumeric
codes and symbols are placed in between 0100 0000 and 1111 1111.
1.13.3 Hollerith Code
The Hollerith Code is the alphanumeric code used in punched cards. Each card has 80 columns
and 12 rows. The rows are numbered 0 through 9, 11 and 12. The columns are numbered 1 through 80,
each one containing one character. Each character is uniquely identified by the rows punched in that
column.
Thus far, we can express a decimal 8 as follows:
Decimal 8
Binary 1000
Octal 10
Hexadecimal 8
BCD 1000
XS 3 1011
Gray 1100
Biquinary 10 01000
ASCII 0011 1000
EBCDIC 1111 1000
Hollerith 8
Example 1.80:
Consider a decimal number 14 and write the equivalent for this in Binary, BCD, 2421, Gray and
Excess 3 codes. (Dec. 2005)
Boolean Algebra and Logic Gates 1.37
Solution:
Binary 1110
BCD 0001 0100
2421 0001 0100
Gray 1001
XS 3 0001 0111
1.14 BOOLEAN POSTULATES AND LAWS
1.14.1 Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed for this purpose
an algebraic system now called Boolean Algebra.
In 1938 C.E. Shannon introduced a two-valued Boolean Algebra called Switching Algebra, in
which he demonstrated that the properties of bistable electrical switching circuits can be represented
by this algebra.
For the formal definition of Boolean Algebra, we shall employ the postulates formulated by E.V.
Huntington in 1904.
1.14.2 Postulates or Axioms
The Postulates or Axioms of Boolean Algebra are a set of logical expressions that we accept
without proof and upon which we can build a set of useful theorem. Actually the axioms are nothing
more than the definitions of 3 basic logic operations: AND, OR and INVERT.
Postulate 1 0.0 = 0 Postulate 6 0 + 1 = 1
Postulate 2 0.1 = 0 Postulate 7 1 + 0 = 1
Postulate 3 1.0 = 0 Postulate 8 1 + 1 = 1
Postulate 4 1.1 = 1 Postulate 9 = 0
Postulate 5 0 + 0 = 0 Postulate 10 = 1
1.14.3 Theorems of Boolean Algebra
The Commutative Properties
The Associative Properties
The Idempotent Properties
The Identity Properties
The Null Properties
The Distributive Properties
The Negation Properties
1.38 Digital Principles and System Design
The Double Negation Properties
The Absorption Properties and
De Morgan’s Theorems
(i) Commutative Properties
Theorem 1a : AB = BA
1b : A + B = B + A
Theorem 1a: AB = BA
“A AND B” is the same as ‘B AND A’ ; in effect, it makes no difference which input of an AND
gate is connected to A and which is connected to B. The truth tables are identical.
A B AB B A BA
0 0 0 0 0 0
0 1 0 = 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1
Table 1.10(a)
Theorem 1b : A + B = B + A
“A OR B” is same as “B OR A”
A B A+B B A B+A
0 0 0 0 0 0
0 1 1 = 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1
Table 1.10(b)
The commulative properties can be extended to any number of variables:
A+B+C=B+A+C ABCD = BACD
A+C=C+A BADC = ABDC
B+A+C=B+C+A
(ii) The Associative Properties
Theorem 2a: (AB)C = A(BC)
2b: (A + B) + C = A + (B + C)
Theorem 2a : (AB)C = A(BC)
A AND B ANDed with C is same as A ANDed with B AND C
Boolean Algebra and Logic Gates 1.39
A B C AB (AB)C A B C BC A(BC)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 = 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1
Fig. 1.8: Associative Law
Note that (AB)C = A(BC) = ABC
Theorem 2b: (A + B) + C = A + (B + C)
A OR B ORed with C is some as A ORed with B OR C
A B C A+B (A+B) + C A B C B+C A+(B+C)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 1 1 = 1 0 0 0 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1
Fig. 1.9: Associative Law
1.40 Digital Principles and System Design
Note that, (A + B) + C = A + (B + C) = A + B + C
The associative properties can be extended to any number variables:
A(BCD) = (AB)(CD) = (ABC)D = ABCD
A + (B + C + D) = (A + B) + (C + D) = (A + B + C) + D
=A+B+C+D
(iii) The Idempotent Properties
Theorem 3a : AA = A
Theorem 3b : A + A = A
AA= A A+A=A
If A = 0, then AA = 0.0 = 0 = A If A = 0, then A+A = 0 + 0 = 0 = A
If A = 1, then AA = 1.1 = 1 = A If A = 1, then A+A = 1+1 = 1 = A
Note: A A A = A
A+A+A=A
(iv) Identity Properties
Theorem 4a : A 1 = A
Theorem 4b : A + 1 = 1
A 1= A A+1=1
If A = 0, then A . A If A = 0, then A
If A = 1, then A . A If A = 1, then A
Note: 1 A = A
1+A=1
AB+C AB C
A B C D
Boolean Algebra and Logic Gates 1.41
(v) The Null Properties
Theorem 5a: A
Theorem 5b: A A
A 0 =0
If A = 0, then A .
If A = 1, then A .
A 0=A
If A = 0, then A A
If A = 1, then A A
Note:
A B C D
AB C D ABC D
(vi) The Distributive Property
Theorem 6: A B C A B A C A AB
B
A AB+BC
B
C A(B+C) A
B+C
C AC
Fig. 1.10: Distributive Law
A B C (B + C) A(B + C) A B C AB AC AB + AC
0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 = 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1
1 1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1
A B C A B C AB AC AB AC
1.42 Digital Principles and System Design
A B C D E A B C A B D E
A B C D A B C A B D
AC BC ADBD
Note: The distributive property is often used in reverse called as factoring.
A B A C A B C
X Y W X Y Z X Y W Z
(vii) The Negative Properties
Theorem 7a : AA
Theorem 7b : A A
If A , . If A ,
If A , . If A ,
Note: A B C A B C
(viii) The Double Negation Property
Theorem 8 : A A
If A , A , A A
If A , A , A A
Note: A + BC = A + BC.
(ix) The Absorption Properties
Theorem 9a: A + AB = A
Theorem 9b: A(A + B) = A
Theorem 9c: A AB A B
9a) A + AB = A Example
A B A A A A BC D A
Boolean Algebra and Logic Gates 1.43
9b) A(A + B) = A
AA AB A AB A X Y X Y W Y Z X Y
9c) A+ AB = A+ B
A AB A A B AB A A B A B
A A A B X Y X Y Z
= A B =X+Y+Z
=A+B
Bubbled AND Gate
A
A A
Y Y
B
B
B
AND gate with inverted inputs Bubbled AND gate - Truth Table
Y AB A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Fig. 1.11: Bubbled AND gate
Bubbled OR Gate
A
A A
Y B Y
B
B
OR gate with inverted inputs Bubbled OR gate
Y A B Bubbled OR gate Truth Table
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Fig. 1.12 : Bubbled OR gate
1.44 Digital Principles and System Design
1.15 DE MORGAN’S THEOREMS
Theorem (1) : A B A B
Theorem (2) : A B A B
De Morgan’s First Theorem
AB A B
“The complement of a product equals the sum of the complements.”
A NAND gate performs the same operation as a bubbled OR gate.
A A
AB = A+B
B B
NAND Bubbled OR
A B AB AB A B A B A B
0 0 0 1 0 0 1 1 1
0 1 0 1 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 0 0 0
Fig. 1.13: De Morgan’s Theorem 1
De Morgan’s Second Theorem
A B AB
“The complement of sum equals the product of the complements”.
A NOR gate performs the same operation as Bubbled AND gate
A
A AB
A+B = B
B
NOR Bubbled AND
A B A+ B AB A B A B AB
0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0
Fig. 1.14: De Morgan’s Theorem 2
Boolean Algebra and Logic Gates 1.45
Note: A B A B ; A B A B
De Morgan’s two theorems can be regarded as a single theorem by observing the following rule:
“Change the logic operation covered by the inversion bar, remove the inversion bar, and complement
each variable that was originally covered by the bar.”
(i) A B C A B C and A B C A BC
(ii) AB A B A B
(iii) A B C A B C A B C
(iv) AB C A B C A B C
(v) A B CD E A B CD E
= A B CD E
= A B C D E
= A B C D E
(vi) A B C B C A B C B C
= ABC BC
= A BC B C
= AB C BB C B CC
= AB C
= AB C
The Boolean theorems are given in Table 1.11.
1.46 Digital Principles and System Design
TABLE 1.11: Boolean Theorems
1. Commutative 1a AB = BA 1b A+B=B+A
2. Associative 2a (AB)C = A(BC) 2b (A + B) + C =
A + (B + C)
3. Idempotent 3a AA = A 3b A+A=A
4. Identity 4a A A 4b A+1=1
5. Null 5a A 5b A+0=A
6. Distributive 6 A(B + C) = AB + AC
7. Negation 7a AA 7b A A
8. Double Negation 8 A A
9. Absorption 9a A + AB = A 9b A(A + B) = A
9c A AB A B
10. De Morgan A B A B A B A B
1.16 BOOLEAN RULES FOR SIMPLIFICATION
Boolean algebra finds its most practical use in the simplification of logic circuits. To translate a
logic circuit’s function into symbolic (Boolean) form, and apply certain algebraic rules to the resulting
equation to reduce the number of terms and/or arithmetic operations, the simplified equation may be
translated back into circuit form a logic circuit performing the same function with fewer components.
If equivalent function may be achieved with fewer component, the result will be increased reliability
and decreased cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this section for use in reducing
expressions to their simplest forms. The identities and properties already reviewed in this chapter are
very useful in Boolean simplification, and for the most part bear similarity to many identities and
properties of “normal” algebra. However, the rules shown in this section are all unique to Boolean
mathematics.
Rule 1:
A + AB = A
Boolean Algebra and Logic Gates 1.47
A (Same)
A
A
A+AB
A
AB
B
Fig. 1.15: Logic diagram for A + AB = A
This rule may be proven symbolically by factoring an “A” out of the two terms, then applying the
rules of A + 1 = 1 and 1A = A to achieve the final result:
A + AB
Factoring A out of both terms
A(1 + B)
Applying identity B + 1 = 1
A(1)
Applying identity 1A = A
A
Rule 2: (Dec. 2005)
A AB A B
A A
A
A+AB
B
AB
(same)
A+B
Fig. 1.16: Logic diagram for A + AB = A + B
1.48 Digital Principles and System Design
A AB
Applying the previous rule to expand A term A + AB = A
A A B AB
Factoring B out of 2nd and 3rd terms
A B A A
Applying negation A A
A + B(1)
Applying identity 1B = B
A+B
Rule 3:
(A + B) (A + C) = A + BC
Fig. 1.17 : Logic diagram (A + B) (A + C) = A + BC
And, the corresponding proof:
(A + B) (A + C)
Distributing terms
AA + AC + AB + BC
Applying identity AA = A
A + AC + AB + BC
Applying rule A + AB = A to the A + AC term
A + AB + BC
Applying rule A + AB = A to the A + AB term
A + BC
Boolean Algebra and Logic Gates 1.49
Example 1.81: Simplify the expression AB + BC(B + C)
Fig. 1.18: Logic diagram
AB + BC(B + C)
Distributing terms
AB + BBC + BCC
Applying identity AA = A to 2nd and 3rd terms
AB + BC + BC
Applying identity A + A = A to 2nd and 3rd terms
AB + BC
Factoring B out of terms
B(A + C)
The final expression, B(A + C), is much simpler than the original, yet performs the same function.
The truth tables for these two expressions should be identical.
Fig. 1.19 : Simplified function diagram
1.50 Digital Principles and System Design
1.17 MINIMIZATION OF BOOLEAN EXPRESSIONS
Example 1.82: W = ABC + CAB + BAC
= ABC + ABC + ABC (Theorem 1a)
= ABC + ABC (Theorem 3b)
= ABC
Example 1.83: X A B C A BC
A B C C (Theorem 6)
= A B (Theorem 7b)
= AB (Theorem 4a)
Example 1.84: W X XY Z XY Z
= X XY Z X XY Z
= Y Z Y Z
=0+0
=0
Example 1.85: Z A BC ABC ABC ABC
AB C C AB C A BC (Theorem 6)
AB AC B B (Theorem 7b)
AB AC
AB AC (Theorem 4a)
Example 1.86: W X X X X X X X X
X X X X X X X X X X X X X (Theorem 6)
X X X X X X X X X (Theorem 7a, 3a)
X X X X X X X X X
X X X X X X X
X X X (Theorem 7b)
X X X
Boolean Algebra and Logic Gates 1.51
X X X (Theorem 7b)
X (Theorem 4b)
=1
Example 1.87: A W X Y W X WY W XY W X X Y
W X Y W X W X Y WY W XYW X W XY X Y
W Y W X X W X W YY WW XY X W X X YY (Theorem 7a)
W Y W W X W XY X W X X (Theorem 5a)
=0+0+0+0 (Theorem 3b)
=0
Example 1.88: Y = ABC + AB + A
= A(BC + B + 1) (Theorem 4b)
= A (Theorem 4a)
= A
Example 1.89: W X Y YZ X
X Y X YZ (Theorem 1a)
XY (Theorem 9a)
Example 1.90: W A BC
A B C (De Morgan’s Theorem 10b)
= ABC
Example 1.91: W A B C D
A B C D (Theorem 10a)
A B C D (Theorem 10a, 10b)
= A + B + CD
Example 1.92: W AC D C A B
A C D C A B (Theorem 10a, 10b)
AC D C A B
A CD C AB (Theorem 8)
1.52 Digital Principles and System Design
A AB C CD (Theorem 1b)
=A+B + C+ D (Theorem 9c)
Example 1.93: W A B C A B
A BC A B
AB C A B
Example 1.94: Y A A B A B C A B C D
= A(1 + B + BC + BCD)
A A
Example 1.95: W A A A B A A B C A A B C D
A A A B C A B C D
A A A A
=AAAA=A
Example 1.96: A A
A A A A A
A A A A A A A
A A A A A A A
A A A A A A A A A A
A A A A
Example 1.97: Y A B A B
AA AB B A B B
AB A B B
A A B B
B B B B B.
Boolean Algebra and Logic Gates 1.53
Example 1.98: Y ABC ABC ABC A BC
AB AB AB A B C
AB B AB B C
A A C
A A C
C C .
Example 1.99: Y = AB + A(B + C) + B(B + C)
= AB + AB + AC + BB + BC
= AB + AB + AC + B + BC (BB = B)
= AB + AC + B + BC (AB + AB = AB)
= AB + AC + B (B + BC = B)
= AC + B (B + BA = B)
Example 1.100: Y AB C B D AB C
ABC ABB D AB C
ABC A D AB C BB
ABC AB C A D
ABC AB C
ABC C ABC
ABC ABC (CC = C)
BC A A BC A A
BC
Example 1.101: Y AB C ABC AB C ABC A B C
B C A A A BC ABC ABC
BC AB C C ABC A A
1.54 Digital Principles and System Design
B C AB ABC C C
B C B A AC
B C B A C A AC A C
B C AB BC
Example 1.102: Y A B A C ABC
AB AC ABC
A B A C ABC
AA AC AB BC ABC
A AC AB BC ABC AA A
A AC AB BC AB ABC AB
A AB BC A AC A C A
A BC A AB A B A
Example 1.103: Y A B A C A B C A B C
A B AC A BC A B A BC C
A B AC A B C C A AC B B A A C
A B A C A BC C C C
A B A C A BC
A B A C BC A A B A B
A A B C C B
A B C B
A C B B
=1
Example 1.104: Y A B A B
A A A B A B B B
AB AB B B A A
AB AB B B B B
A A B A A
B
Boolean Algebra and Logic Gates 1.55
Example 1.105: Y A B A B C B B C
= AB + AB + AC + BB + BC
= AB + AB + AC + B + BC (BB = B)
= AB + AC + B + BC (AB + AB = AB)
= AB + AC + B (B + BC = B)
= AB + B + AC
= B + AC (AB + B = B)
Example 1.106: Y A B A C A BC
A B A C A B C
A B A C A BC
A A AC A B BC A BC
A BC A C A B A BC A A A
A BC AC A B A B ABC AB C A B
A BC A B A AC A C A
A BC A A B A B A
Example 1.107: Y = ABC.D
ABC D
A BC D
A BC D
AC BC D
Example 1.108: Simplify the following Boolean expression to a minimum number of literals:
(i) AC ABC AC (Dec 2011)
A C ABC AC (Theorem 10)
A AC C ABC (Theorem 9C)
A C C AB
A AB C C
ABCC
1.56 Digital Principles and System Design
A 1 B
1 B 1
(ii) XYZ XY XYZ (iii) XY YZ XYZ
y xz x xz
xy z y yx
y xz x z xy z y x
xy yz xz
y xxz
xy yz zx
y 1 z
= y(1)
=y
(iv) AB ABD ABD A C D ABC (v) BD BCD ABCD
AB AB AC D B
B D DC A B C D
B D C AB AC AD
A A CD BC
BD BC AB AC AD
A ACD ABC
AC BD
1.18 DUALITY
The dual is formed by replacing
AND with OR
OR with AND
0 with 1
1 with 0 in a Boolean expression.
Boolean Algebra and Logic Gates 1.57
The variables and components are left unchanged. This rule for forming the dual as,
D
f X ,X , . . . ,X N ,, , , f X ,X ,. . .,X N , , , ,
If F A B C A B C , then the dual expression is F D A B C A B C
Table 1.12 lists the postulates and theorems related to duality theorem.
TABLE 1.12: Duality Theorem
Expression Dual
X+0=X X X
X X X X
X+X=X X X X
X X
X Y Y X X Y Y X
X Y Z X Y Z X Y Z X Y Z
X Y Z X Y X Z X Y Z X Y X Z
X Y X Y X Y X Y
X + XY = X X(X + Y) = X
Proof:
1. X+X=X X X X
X X X X X X XX
X X X X XX X X
XXX X X X
X X
= X =X
2. X X
X X
X X X
X X
XX
=1
3. A B C D E F A B C D E F
A BC DE F ABCDE F
A B C D E F
1.58 Digital Principles and System Design
1.19 BOOLEAN FUNCTIONS
A Boolean function is an expression formed with binary variables, the two binary operators OR
and AND, the unary operator NOT, parentheses and an equal sign. For a given value of the variables,
the function can be either 0 or 1.
Consider, for example, the Boolean function
F x yz
F if x , y and z
F1 = 0 ; otherwise
Boolean function also be represented in a Truth Table. To represent a function in a truth table, we
need a list of the 2n combinations of 1’s and 0’s of the ‘n’ binary variables and a column showing the
combinations for which the function is equal to 1 or 0.
TABLE 1.13 : Boolean Functions
X Y Z F1 = X Y Z F2 = X +Y Z F3 = X Y Z F4 = X Y X Z
X Y Z +X Y
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
When X = 1, Y=1, Z=1
F
F .
F . . . . .
F . .
A Boolean function may be transformed from an algebraic expression into a logic diagram
composed of AND, OR and NOT gates
(a) F1 = X Y Z
Boolean Algebra and Logic Gates 1.59
(b) F2 = X +Y Z
(c) F3 = X Y Z + X Y Z + XY
(d) F4 = XY + X Z
Fig. 1.20 : Implementation of Boolean functions with gates
To implement a Boolean function with a less number of gates we have to minimize literals and the
number of terms. Usually, literals (Boolean variables in complemented or uncomplemented form)
and terms are arranged in one of the two standard forms of switching equations:
Sum of Product form (SOP)
Product of Sum form (POS)
1.20 PRODUCT-OF-SUMS METHODS
The logical product of those fundamental sums that produce output 0’s in the truth table. The
corresponding logic circuit is an OR-AND circuit or the equivalent NOR-NOR circuit.
1.60 Digital Principles and System Design
TABLE 1.14 : POS table
A B C Y
0 0 0 0 A BC
0 0 1 1
0 1 0 1
0 1 1 0 A B C
1 0 0 1
1 0 1 1
1 1 0 0 A B C
1 1 1 1
Y = 0, when A = 0, B = 1 and C = 1 . So this particular combination makes the output of an OR
gate equal to 0, when B and C . Thus A + B C is on sum term. Similarly other two sum terms
are A + B + C and A B C . Thus the standard product of sum form is,
F A B C A B C A B C
Figure 1.21 Shows the OR-AND logic circuit and Figure 1.22 shows the NOR-NOR logic circuit
for this expression.
A
B
C
A
B Y
C
A
B
C
Fig. 1.21: OR-AND circuit
A A B B C C
Fig. 1.22: NOR-NOR circuit
Boolean Algebra and Logic Gates 1.61
1.21 SUM-OF-PRODUCTS METHOD
The logical sum of those fundamental products that produce output 1's in the truth table. The
corresponding logic circuit is an AND-OR circuit or the equivalent NAND-NAND circuit.
For example, F A BC A B C A BC , is a standard sum of products of A, B and C are the only
variables pertaining to the logic. Note that this expression is not in simplest form because we can
write,
F A BC A B C ABC
A C B B A BC
A C A BC
This simplified expression is a sum of products; but not a standard sum of products.
The logic expression corresponding to a given truth table can be written in a standard sum-of-
products form of writing one product term for each input combination that produces an output of 1.
These product terms are ORed together to create the standard sum of products.
TABLE 1.15 : SOP table
A B C F
0 0 0 0
0 0 1 1 A BC
0 1 0 0
0 1 1 0
1 0 0 1 A BC
1 0 1 1 A BC
1 1 0 0
1 1 1 0
We note that F is 1 when A = 0, B = 0 and C = 1 , so this particular combination makes the output
of an AND gate equal to 1 when A and B roman and C are all equal to 1. Thus A B C is one product
term. Similarly other two product terms are A B C and A B C . Thus the standard sum-of-products
form is,
F A BC A BC A BC
1.62 Digital Principles and System Design
Consider the truth table given in Table 1.16.
TABLE 1.16: Design Truth Table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 A BC
1 0 0 0
1 0 1 1 A BC
1 1 0 1 A BC
1 1 1 1 ABC
Y A BC A BC A BC A B C
Figure 1.23 shows the AND-OR logic circuit and Figure 1.24 shows the NAND-NAND circuit
for the expression.
A ABC
B
C
A
B
C ABC
A Y
B
C ABC
A
B
C ABC
Fig. 1.23: AND-OR circuit
Fig. 1.24: NAND-NAND circuit
Boolean Algebra and Logic Gates 1.63
Example 1.109: Suppose a truth table has a low output for the first three input conditions: 000, 001
and 010. If all other outputs are high, what is the product-of-sum (POS) form?
Solution: Y A B C A B C A B C
Example 1.110: Suppose a 3 variable truth table has a high output for these input conditions: 000,
010, 100 and 110. What is the sum-of-product (SOP) form?
Solution: Y A BC A BC A BC A BC
Example 1.111: Convert the Boolean expressions to SOP form.
(a) AB + B(CD + EF) = AB + BCD + BEF
(b) (A + B) (B + C + D) = AB + AC + AD + BB + BC + BD
(c) A B C A BC
= (A + B) C
= AC + BC
1.22 MINTERMS
The ‘n’ variables forming an AND term, with each variable being primed or unprimed, provide 2n
possible combinations, called Minterms or Standard Products.
Consider two binary variables x and y combined with an AND operation. Since each variable may
appear in either form, there are 4 possible combinations:
x y,xy,x y and x y
Each of these four AND terms represents one of the distinct areas in the Venn diagram and is
called a Minterm.
x y
xy xy xy
xy
Fig. 1.25 : Venn Diagram for two variables
The 2n difference minterms may be determined by a method similar to one shown in Table 1.17
for 3 variables. The binary numbers from 0 to 2n 1 are listed under the ‘n’ variables. Each Minterm
1.64 Digital Principles and System Design
is obtained from an AND term of the ‘n’ variables, with each variable being primed, if the corresponding
bit of the binary number is a ‘0’ and unprimed if a ‘1’.
Symbol for Minterm Mj
TABLE 1.17 : Minterms and Maxterms
Minterms Maxterms
X Y Z Term Symbol Term Symbol
0 0 0 xyz m0 x y z M0
0 0 1 xyz m1 x y z M1
0 1 0 xyz m2 x y z M
0 1 1 xyz m x y z M
1 0 0 xyz m x y z M
1 0 1 xyz m x y z M
1 1 0 xyz m x y z M
1 1 1 xyz m x y z M
1.23 MAXTERMS
The ‘n’ variables forming an OR term, with each variable being primed or unprimed, provide in 2n
possible combinations, called Maxterms or Standard sums.
The eight maxterms for 3 variables, together with their symbolic designation are listed in Table.
Each maxterm is obtained from an OR term of the ‘n’ variables, with each variable being unprimed if
the corresponding bit is a 0 and primed if a 1.
Each Maxterm is the complement of its corresponding Minterm and Vice versa.
A Boolean function may be expressed algebraically from truth table (Table 1.18) by forming a
minterm for each combination of the variables that produces a 1 in the function and then taking the
OR of all those terms for example the function f 1 in the table is determined by expressing the
combinations 001, 100 and 111 as x y z , x y z and x y z.
f x y z x y z x y z m m m
f x y z x y z x yz x y z m m m m
“Any Boolean function can be expressed as a sum of Minterms (by ‘SUM’ is meant the ORing of
terms)”.
Boolean Algebra and Logic Gates 1.65
The complement of f1 is
f x y z x y z xy z x yz x yz
TABLE 1.18 : Truth Table for f 1 and f 2
Function Function
x y z
f1 f2
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The complement of f gives the function f ,
= x y z x y z xy z x yz x y z
f x y z x y z x y z x y z x y z
M M M M M
Similarly, it is possible to read the expression for f2 from the table,
f x y z x y z x y z x y z
M M M M
“Any Boolean function can be expressed as a product of Maxterms (by ‘product’ is the meant of
ANDing of terms).”
1.24 CANONICAL FORM
Boolean functions expressed as a sum of minterms m or product of maxterms ( π M) are said
to be in canonical forms.
1.24.1 Sum of Minterms
The sum of minterms of a Boolean function is obtained in two ways:
from truth table from algebraic expression.
The following example clarifies these procedure:
Example 1.112: Express the Boolean function F A BC in a sum of minterms.
Method 1: The truth table for the function F A BC is shown in Table 1.19.
1.66 Digital Principles and System Design
TABLE 1.19 : Truth table for F = A + BC
A B C B BC F A BC
0 0 0 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 1 0 0 1
The combination of variables that produces ‘1’ in the function are the minterms and then taking
the OR of all these minterms is the sum of minterms.
F(A , B , C) m m m m m
m , ,, ,
Method 2: Explaining the expression into a sum of AND terms. Each term is then inspected to see if
it contains all the variables. If it misses one or more variables, it is ANDed with an expression such as
x x , where x is one of the missing variables.
The Boolean function, F A BC
The function has three variables. The first term A is missing two variables and the second term
B C is missing one variable. Therefore, the first term
A A B B
AB AB
This is still missing one variable, therefore
A A B C C AB C C
A B C A BC A BC A BC
The second term, BC BC A A
= ABC A BC
Combining all terms, we obtain,
F A BC
A BC A BC A BC A BC A BC A BC
A BC A BC ABC A BC A BC
A BC A BC A BC A BC A BC
m m m m m
Canonical form, F(A, B, C) m , ,, ,
Boolean Algebra and Logic Gates 1.67
1.24.2 Product of Maxterms
The product of maxterms of a Boolean function is obtained
from truth table from expression
Example 1.113: Express the Boolean function F X Y X Z in a product of maxterm form.
Method 1:
TABLE 1.20 : Truth table for F = X Y + X Z
X Y Z XY XZ F = X Y + XZ
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 0 0
0 1 1 0 1 1
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 1 0 1
1 1 1 1 0 1
Form a maxterm for each combination of the variables that produces a 0 in the function and then
form the AND of all those maxterms. Therefore the product of Maxterms,
F M M M M
F X ,Y ,Z π M , , ,
or π , , ,
Method 2: Expanding the expression into a product of OR terms using the distributive law, X + YZ
= (X + Y) (X + Z) . Each term is then inspected to see if it contains all the variables. If it misses one
or more variables, it is ORed with an expression such as xx , where x is one of the missing variables.
F X Y XZ
X Y X X Y Z
X X Y X X Z Y Z
X Y X Z Y Z
The function has 3 variables: X, Y and Z. Each OR term is missing one variable; therefore,
I term, X Y X Y Z Z X Y Z X Y Z
II term, X Y X Y YY X Y Z X Y Z
III term, Y Z Y Z X X X Y Z X Y Z
1.68 Digital Principles and System Design
Combining all the terms and removing those that appear more than once, we finally obtain:
F X Y Z X Y Z X Y Z X Y Z
M M M M
π M , , ,
F(X, Y, Z) = π (0, 2, 4, 5)
Example 1.114: Express the Boolean function
F A B C B C D A B C D in canonical POS form.
Solution: The first term is missing variable ‘D’
A B C A B C DD A B C D A B C D
The second term is missing variable ‘A’
B C D B C D AA A B C D A B C D
The third term is already in standard form.
The canonical form, F A B C D A B C D
A B C D A B C D A B C D
Example 1.115: Convert the Boolean function into canonical SOP form,
F ABC A B A BC D
Solution: First term is missing variable ‘D’.
AB C A B C D D A B C D A B C
Second term is missing two variables C and D.
A B AB C C ABC A BC
then, A B C A B C D D A B C D A B C D A B CD A B C D
Third term is already in standard form,
F ABC D A BCD A BC D A BC D A BCD A BC D A BC D
Example 1.116: Obtain the canonical sum of product (SOP) from the function,
F=A+B
Soluton: F = A + B
= A B B B A A
Boolean Algebra and Logic Gates 1.69
A B A B A B AB
A B A B AB
Example 1.117: Obtain the canonical SOP of the function F = AB + ACD .
Solution: First term is missing two variables C and D
A B A B C C D D
A B C A BC D D
A B C D A B C D A BCD A BC D
Second term is missing one variable ‘B’
A C D A C D B B
A B C D ABC D
Canonical form,
F A B C D A B C D A BC D A BC D ABC D
Example 1.118: Obtain the canonical SOP of the function,
F = A + BC
Solution: F A B B C C B C A A
A B A B C C A B C AB C
A B C A BC A BC ABC A BC A B C
A B C A BC A BC ABC A B C
This result can be checked with the truth table.
TABLE 1.21 : Truth Table for F = A + BC
A B C BC F = A + BC
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1 AB C
1 0 0 0 1 ABC
1 0 1 0 1 ABC
1 1 0 0 1 A BC
1 1 1 1 1 ABC
1.70 Digital Principles and System Design
F A B C A BC A BC A BC A B C
m , , , ,
Example 1.119: Obtain the canonical POS form F A B B C
Solution: The first term has a missing variable ‘C’
A B A B C C A B C A B C
The second term has a missing variable ‘A’
B C B C A A A B C A B C
Canonical form is F A B C A B C A B C A B C
Example 1.120: Express the function F A BC in
(a) Canonical SOP and (b) Canonical POS form
Solution: Canonical SOP form:
F A BC
A B B C C BC A A
A B AB C C A BC A BC
A BC A BC A BC ABC A BC A BC
A B C A BC A BC ABC A BC
m m m m m
F , , , ,
Canonical POS form:
F A BC
A B A C
A B CC A C BB
A B C A B C A B C A B C
A B C A B C A B C
M M M
F π , ,
Boolean Algebra and Logic Gates 1.71
1.25 CONVERSION BETWEEN CANONICAL FORMS
The binary values of the product terms in given canonical SOP expression are not present in the
equivalent canonical POS expression. Therefore to convert from canonical SOP to canonical POS,
the following steps are taken:
Step 1: Evaluate each product term in the SOP expression. i.e., determine the binary numbers that
represent the product terms.
Step 2: Determine all of the binary numbers not included in the evaluation of step 1.
Step 3: Write the equivalent sum term for each binary number from step 2 and express in POS form.
Using a similar procedure, we can convert POS to SOP form.
Example 1.121: Convert the following SOP expression to an equivalent POS expression:
A BC A BC A B C A BC A B C
Solution:
Step 1: The evaluation is: 000 + 010 + 011 + 101 + 111
Step 2: Since there are 3 variables, 23 = 8 possible combinations are possible. The SOP expression
contains 5 of these combinations, so the POS must contain other 3 combinations, which are 001, 100
and 110.
Step 3: POS expression is, A B C A B C A B C
Method 2: The conversion between canonical forms can be done by another method:
The complement of a function expressed as the sum of minterms equals the sum of minterms
missing from the original function. This is because the original function is expressed by those minterms
that make the function equal to 1, whereas its complement as a 1 for those minterms that the function
is a 0. As an example consider the function,
F A, B, C A B C A B C A B C A B C A B C
, , , ,
This has a complement that can be expressed as
F , , m m m
The complement of F, F is obtained by De Morgan’s theorem,
F m m m
m m m
M M M
π M , ,
π , ,
mj M j
1.72 Digital Principles and System Design
Example 1.122: Convert the canonical SOP into canonical POS F(A , B , C) = , , , .
Solution: F , , ,
F , , ,
m m m m
By DeMorgan’s theorem,
F m m m m
m m m m
M M M M
π , , ,
Using this complementary relationship, find logical function in terms of maxterms. For example,
for a 4 variable if
F , , , , , , ,
then the complement is F π M , , , , , , , .
1.26 KARNAUGH MAPS
A Karnaugh map is a graphical representation of a truth table that can be used to reduce a logic
circuit to its simpliest terms. The size of the Karnaugh map depends on the amount of inputs that are
listed in the truth table. An example of a three variable Karnaugh Map is shown below:
AB AB AB AB
C ABC ABC ABC ABC
C ABC ABC ABC ABC
The terms withing a Karnaugh Map are obtained by combining the row and column boolean
expression that are shown at the top and left margins of the Karnaugh Map. Each combined term
within the Karnaugh Map corresponds to a single line of inputs in a truth table. Terms that have a line
over them corresponds to a low or zero input. Terms without any marking corresponds to a high or 1
input.
1.26.1 Constructing a Karnaugh Map
(1) Two variable maps:
A B Y B B B B
0 0 0 A 0 0 A AB AB
0 1 0 A 1 1 A AB AB
1 0 1
1 1 1
Boolean Algebra and Logic Gates 1.73
(2) Three variable maps:
A B C Y C C
0 0 0 0 AB 0 0
0 0 1 0 AB 1 0
0 1 0 1 AB 1 1
0 1 1 0 AB 0 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
(3) Four variable maps:
A B C D Y CD CD CD CD
0 0 0 0 0 AB 0 1 0 0
0 0 0 1 1 AB 0 0 1 1
0 0 1 0 0 AB 0 0 0 1
0 0 1 1 0 AB 0 0 0 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 1 1 0 1
Pairs, Quads and Octets
Pairs
Pair eliminates are variable and its complements.
Pair of 1's horizontally and vertially adjacent.
CD CD CD CD
AB 0 0 0 0
AB 0 0 0 0 Y A B C D A B CD
AB 0 0 1 1 A B C D D
AB 0 0 0 0 = ABC
1.74 Digital Principles and System Design
CD CD CD CD
AB 0 0 0 0
AB 0 0 0 0 Y A B CD A BCD
AB 0 0 0 1 A CD B B
AB 0 0 0 1 A CD
Quads: A quad is a group of four 1’s that are horizontally or vertially adjacent
CD CD CD CD A BC D ABC D A B C D A B C D
AB 0 0 0 0 A B C D D A BC D D
AB 0 0 0 0 A B C A BC
AB 1 1 1 1 A B C C
AB 0 0 0 0 = AB
CD CD CD CD
AB 0 0 0 0 A B C D A B C D ABC D ABC D
AB 0 0 0 0 A B C D D A BC D D
AB 0 0 1 1 A C B B
AB 0 0 1 1 = AC
Octet: An octet is a group of eight 1’s.
An octet eliminates three variables and their complements.
CD CD CD CD Y A BC D A BC D A B C D A BCD
AB 0 0 0 0 ABC D ABC D ABC D ABC D
AB 0 0 0 0 A B C D D A BC D D
AB 1 1 1 1 A B C D D A B C D D
AB 1 1 1 1 A B C C A B C C
A B A B = A B B = A
Boolean Algebra and Logic Gates 1.75
1.26.2 Karnaugh Map Simplifications
Encircle octets first, the quads second and the pairs last.
C D CD CD C D
AB 0 1 1 1
AB 0 0 0 1 Y AC C D A B D
AB 1 1 0 1
AB 1 1 0 1
Overlapping Groups: It is possible to use the same 1 more than once.
C D CD CD C D
AB 0 0 0 0
AB 0 1 0 0 Y A BC D
AB 1 1 1 1
AB 1 1 1 1
It is valid to encircle the 1’s as shown below. But the isolated 1 results in a more complicated
equation.
C D CD CD C D
AB 0 0 0 0
AB 0 1 0 0 Y A A BC D
AB 1 1 1 1
AB 1 1 1 1
Rolling the map
CD CD CD CD CD CD CD CD
AB 0 0 0 0 AB 0 0 0 0
AB 1 0 0 1 AB 1 0 0 1
AB 1 0 0 1 AB 1 0 0 1
AB 0 0 0 0 AB 0 0 0 0
Visualize the picking up the karnaugh map and rolling it so that the left side touches the right
side. By doing so, the two pairs can be realised as Quad.
The quad has the equation,
Y BD
1.76 Digital Principles and System Design
Proof: To show whether the rolling is valid or not.
Y BC D B C D
B D C C B D
Rolling and Overlapping: It is possible to overlap and roll the map to get large groups.
CD CD CD CD CD CD CD CD
AB 1 1 0 0 AB 1 1 0 0
AB 1 1 0 1 AB 1 1 0 1
AB 1 1 0 1 AB 1 1 0 1
AB 1 1 0 0 AB 1 1 0 0
Y C B C D Y C B D
CD CD CD CD CD CD CD CD
AB 1 1 0 1 AB 1 1 0 1
AB 1 1 0 1 AB 1 1 0 1
AB 1 1 0 0 AB 1 1 0 0
AB 1 1 0 1 AB 1 1 0 1
Y C ABC D AC D Y C AD A B D
CD CD CD CD
AB 1 1 0 1
AB 1 1 0 1
AB 1 1 0 0
AB 1 1 0 1
Y C AD BC D
Eliminating Redundant Groups
Redundant group is a group whose 1’s are already used by other groups. The redundant group is
eliminated as shown in Figure 1.26 (b).
Boolean Algebra and Logic Gates 1.77
CD CD CD CD CD CD CD CD
AB 0 0 1 0 AB 0 0 1 0
AB 1 1 1 0 AB 1 1 1 0
AB 0 1 1 1 AB 0 1 1 1
AB 0 1 0 0 AB 0 1 0 0
Fig. 1.26 (a) Fig. 1.26 (b)
1.26.3 Don’t Care Condition
In some digital system, certain output conditions never occur during normal operation. Therefore
corresponding output never appears. Since the output never appears it is indicated by an ‘X’ in the
truth table.
CD CD CD CD CD CD CD CD
AB 0 0 0 0 AB 0 0 0 0
AB 0 0 1 0 AB 0 0 0 0
AB X X X X AB X X X X
AB 0 0 X X AB X X X X
Y BCD Y AD
Solution:
1. Given the truth table, draw a Karnaugh map with other 0’s, 1’s and don’t cares.
2. Enclose the actual 1’s on the Karnaugh map in the largest groups you can find by treating the
don’t cares as 1’s.
3. After the actual 1’s have been included in groups, disregard the remaining don’t cares by
visualizing them as 0’s.
Example:
CD CD CD CD
AB 1 0 0 0
AB 0 0 0 0
AB X X X X
AB X X X X
Y A BC D
Here don’t cares are of no help. The best way is, encircle the isolated 1, while treating don’t cares
as 0’s.
1.78 Digital Principles and System Design
1.26.4 Reducing Karnaugh Maps
The rules for reducing Karnaugh Maps are as follows:
All of the 1’s in the Karnaugh Map are called minterms.
The 1’s can be reduced in groups of 2, 4 and 8.
Minterms that are next to each other horizontally or vertically, can be grouped together.
Minterms that have been grouped in a Karnaugh Map, can be reduced to the boolean terms that
are common with all the terms in the group.
Minterms that cannot be grouped together, cannot be reduced.
Use a minterm for grouping more than once.
All 1’s must be accounted for.
Example 1.123: Determine the Karnaugh Map and reduced boolean equation for the truth table
shown in Table 1.22.
TABLE 1.22 : Truth Table
C B A OUTPUT
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
Without reduction the Boolean Equation for the above truth table is:
Y A BC A BC A BC A BC A BC
Each minterm corresponds to an instance in the truth table when the output is high. The Karnaugh
Map for the above truth table, with the allowed groupings are shown below:
AB AB AB AB
C 1 0 0 0
C 1 1 1 1
The map shows two groupings that cover each minterm. Each of these groupings will reduce to
one term.
The two terms that are grouped together A B C reduces to A B C . This is because A and B are
common to both terms.
The four terms A B C and A B C and A BC and A B C that are grouped together reduces to C .
This is because C is the only input common to all four terms.
Boolean Algebra and Logic Gates 1.79
Therefore the boolean equation
Y A BC A BC A BC A BC A BC reduces to
Y AB C
1.26.5 Simplification of Sum of Product Expression
The procedure to simplify the SOP expression using K-map as follows:
Plot the K-map and enter the 1’s in those cells corresponding to the combinations for which
function value is 1.
Check the K-map for adjacent 1's and encircle those 1’s which are not adjacent to any other 1's.
Check for those 1's which are adjacent to only one other 1 and encircle such pairs.
A group must contain either 1,2,4,8 or 16 ones (1's), which are all powers of two.
Combine any pairs necessary to include any 1's that have not yet been grouped.
Form the simplified expression by summing product terms of all the groups.
The minterms for variable and standard product terms and represented by 2 varibale K map, 3
variable K-map and 4 variable K-map are shown in Figurre 1.27.
B
0 1 A 0 1
0 0 1 0 AB AB
1 2 3 1 AB AB
(a) Two Variable Map
C
0 1 AB 0 1
00 0 1 00 ABC ABC
01 2 3 01 ABC AB C
01 6 7 11 A BC ABC
10 4 5 10 ABC ABC
(b) Three Variable Map
CD
00 01 11 10 AB 00 01 11 10
00 0 1 3 2 00 A BCD A BCD A BC D A BCD
01 4 5 7 6 01 A BCD A BCD AB CD AB CD
11 12 13 15 14 11 A BC D A BCD ABCD A B CD
10 8 9 11 10 10 A BC D A BC D A BC D A BCD
(c) 4 Variable Map
Fig.1.27: Representation of functions in the Map
1.80 Digital Principles and System Design
Example 1.124: Simplify the following SOP expression on a Karnaugh Map.
A BC A BC A BC A B C
Solution: The expression is evaluated as follows:
A BC A BC A BC A B C
001 010 110 111
C
AB 0 1
00 1
01 1
11 1 1
10
F BC A B A BC
Example 1.125: Simplify the SOP by using K-map
Y = m (0,1,3,7)
AB C 0 1
00 1 1
01 1
11 1
10
Y A B BC
Example 1.126: Simplify the expression Y m m m m
Solution:
C
AB 0 1
00
01 1
11 1 1
10 1
Y BC AC
Boolean Algebra and Logic Gates 1.81
Example 1.127: Simplify the Boolean expression using K map F AC A B A BC B C .
Solution: The given expression is not a standard SOP form. First convert this non-standard SOP to
standard SOP and then simplify the expression using K-map.
AC AC B B AB C A BC
A B AB C C AB C A BC
B C B C A A AB C A BC
F AC A B A BC B C
A B C A BC A B C A BC A BC A B C A BC
A BC A BC ABC A BC A B C
C
AB 0 1
00 1
01 1 1
11 1
10 1
F C A B
Example 1.128: Use a K map to minimize the following SOP expression:
F A BC D A BC D A BC D A BC D
A BC D A BC D A BC D A BC D A BCD A BC D
Solution:
CD
AB 00 01 11 10
00 1 1 1
01 1 1
11 1 1
10 1 1 1
F D BC
1.82 Digital Principles and System Design
Example: 1.129: Simplify the expression
F = m(0,2,4,5,6,7,8,10,11,12,14,15)
Solution:
CD
AB 00 01 11 10
00 1 1
0 1 3 2
01 1 1 1 1
4 5 7 6
11 1 1 1
12 13 15 14
10 1 1 1
8 9 11 10
F D AB A C
Example 1.130: Simplify the expression using K-map
F m m m m m m m
CD
AB 00 01 11 10
00 1
0 1 3 2
01 1
4 5 7 6
11 1 1 1
12 13 15 14
10 1 1
8 9 11 10
F AC D A BC A C D A BC
Example 1.131: Simplify the following SOP expression on a K-map
BC A B A BC A BC D A BCD A BC D
Boolean Algebra and Logic Gates 1.83
Solution: The SOP expression is obviously not in standard form because each product term does not
have 4 variables. The first and second term are both missing 2 variables, the third term is missing one
variable and the rest of the terms are standard. First expand the terms by including all combinations of
the missing variables numerically as follows:
BC AB + A BC + A BC D + A BCD + A BC D
1100 10 1 0 0001 1011
0000 1000
1101
0001 1001
1000 1010
1001 1011
Repeated terms are cancelled under the rule A + A = A, therefore,
F A BC D A BC D A BC D A BC D
A BC D A BC D A BC D A BC D
(0, 1, 8, 9 10, 11, 12, 13)
CD
00 01 11 10
AB
00 1 1
0 1 3 2
01
4 5 7 6
11 1 1
12 13 15 14
10 1 1 1 1
8 9 11 10
F A B AC A BC
Example 1.132: Simplify using K-map
F(A, B, C, D) m (7,8,9) + d(10,11,12,13,14,15)
1.84 Digital Principles and System Design
Solution:
CD
00 01 11 10
AB
00
0 1 3 2
01 1
4 5 7 6
11 X X X X
12 13 15 14
10 1 1 X X
8 9 11 10
F = A + BCD
Note: Without don’t cares, F A BC A B C D
With don’t cares, F = A + BCD
Therefore, it is clear that, the advantage of using don’t care terms is to get the simplest expression.
Example 1.133: Simplify using K-map
F(A, B, C, D) m (1,3,7,11,15) + d(0,2,5)
Solution:
CD
00 01 11 10
AB
00 X 1 1 X
0 1 3 2
01 X 1
4 5 7 6
11 1
12 13 15 14
10 1
8 9 11 10
F ABC D
(or)
Boolean Algebra and Logic Gates 1.85
CD
00 01 11 10
AB
00 X 1 1 X
0 1 3 2 F AD C D
01 X 1 F A B C D (or)
4 5 7 6 AD C D
11 1
12 13 15 14
10 1
8 9 11 10
Example 1.134: Using the K-Map method, simplify the following Boolean function
F m (0,2,3,6,7) + d (8, 10, 11, 15) (April 2005)
Solution:
CD 00 01 11 10
AB
00 1 1 1
0 1 3 2
01 1 1
4 5 7 6
11 X
12 13 15 14
10 X X X
8 9 11 10
F AC B D
Example: Simplify the following Boolean function F using Karnaugh map method.
1.86 Digital Principles and System Design
Example 1.135: F A, B,C, D 1, 4,5,6,12,14,15 (Dec 2011)
CD
AB 00 01 11 10
00 1
0 1 3 2
01 1 1 1
4 5 7 6
11 1 1 1
12 13 15 14
10
8 9 11 10
F A, B,C, D BD ACD ABC
Example 1.136: F A, B,C, D 0,1, 2, 4,5,7,11,15 (Dec 2011)
CD
AB 00 01 11 10
00 1 1 1
0 1 3 2
01 1 1 1
4 5 7 6
11 1
12 13 15 14
10 1
8 9 11 10
F A, B,C, D AC ABD ACD ABD
Example 1.137: F A, B,C, D 2,3,10,11,12,13,14,15 (Dec 2011)
Boolean Algebra and Logic Gates 1.87
CD
AB 00 01 11 10
00 1 1
0 1 3 2
01
4 5 7 6
11 1 1 1 1
12 13 15 14
1 1
10
8 9 11 10
F A, B,C, D AB BC
Example 1.138: F A, B,C, D 0, 2, 4,5,6, 7,8,10,13,15 (Dec 2011)
CD
AB 00 01 11 10
00 1 1
0 1 3 2
01 1 1 1 1
4 5 7 6
11 1 1
12 13 15 14
10 1 1
8 9 11 10
F A, B,C, D AB BD BD
Example 1.139: Implement the switching function. (May 2012)
F x , y, z m 1, 2,3, 4,5,7 with NAND gates.
1.88 Digital Principles and System Design
z
xy 0 1
00 1
0 1
01 1 1
4 5
11 1
12 13
10 1 1
8 9
F z xy xy
z z
x x
xy
y z . xy . xy
y y z xy x y
xy
Example 1.140: f A, B,C m 0,1,3,7 d 2,5 (May 2013)
Boolean Algebra and Logic Gates 1.89
z
xy 00 01
00 1
0 1
01 1 1
2 3
11 1
6 7
10 1 X
4 5
f C AB
Example 1.141: F(w, x, y, z) = m(0, 7, 8, 9, 10, 12) + d(2, 5, 13) (May 2013)
CD
AB 00 01 11 10
00 1 X
0 1 3 2
01 X 1
4 5 7 6
11 1 X
12 13 15 14
10 1 1 1
8 9 11 10
F wy xz wx
1.26.6 Simplification of Product of Sum expression
To simplify a POS expression, for each maxterm in the expression in, a ‘0’ has to be entered in the
corresponding cells and groups must be formed with ‘0’ cells, instead of 1 cells to get he minterm
(SOP) expression. The simplified term corresponding to each group can be obtained by the OR operation
of the variables that are same for all cells of that group. Here, a variable corresponding to ‘0’ has to
be represented in an uncomplemented form.
1.90 Digital Principles and System Design
Example 1.142: Simplify, the POS expression using K map method.
F π (0, 1, 4, 5, 6, 8, 9, 12, 13, 14)
Solution: CD
AB 00 01 11 10
00 0 0
0 1 3 2
01 0 0 0
4 5 7 6
11 0 0 0
12 13 15 14
10 0 0
8 9 11 10
F C B D
Example 1.143: Simplify the POS expression
F π (0,6,7,8,12,13, 14,15)
CD
AB 00 01 11 10
00 0
0 1 3 2
01 0 0
4 5 7 6
11 0 0 0 0
12 13 15 14
10 0
8 9 11 10
F A B B C B C D
Boolean Algebra and Logic Gates 1.91
Example 1.144: Simplify the expression
F(A, B, C, D) = π M (4,5,6,7,8,12) . d(1,2,3,9,11,14)
Solution:
CD
00 01 11 10
AB
00 X X X
0 1 3 2
01 0 0 0 0
4 5 7 6
11 0 X
12 13 15 14
10 0 X X
8 9 11 10
F A B A C D
Example 1.145: Simplify the POS expression,
F π M (0,3,4,7,8,10,12,14).d(2,6)
CD
00 01 11 10
AB
00 0 0 X
0 1 3 2
01 0 0 0 X
4 5 7 6
11 0 0
12 13 15 14
10 0 0
8 9 11 10
F D AC
1.92 Digital Principles and System Design
Example 1.146: Determine the minterm sum of product form of the switching function.
F = (0,1,4,5,6,11,14,15,16,17,20,22,30,32,33,36,37,48,49,52,53,59,63) (Dec. 2010)
Solution:
Fill up the K-map with the variable given
F = Function of A, B, C, D E and F
A
0 1
B CE
CD CD
EF 00 01 11 10 EF 00 01 11 10
00 1 1 00 1 1
0 01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 AB CEF 10
CD CD
EF 00 01 11 10 EF 00 01 11 10
00 1 1 00 1 1
1
01 1 1 01 1 1
11 11 1 1
10 1 1 10
AEFD ABCEF
Four 1’s in each box form a group of 16 bits and their reduced function is CE . Therefore
F = (0,1,4,5,6,11,14,15,16,17,20,22,30,32,33,36,37,48,49,52,53,59,63)
F(A, B, C, D, E, F) = CE AEFD ABCEF ABCEF
Boolean Algebra and Logic Gates 1.93
Example 1.147: Minimize the following expression using Karnaugh map.
Y A BCD A BCD ABCD ABCD A BCD. (May 2011)
CD
AB 00 01 11 10
00 0 0 0 1
01 1 1 0 0
11 1 0 0 0
10 0 1 0 0
Y ABC BCD ABCD ABCC
Example 1.148: Simplify the following Boolean function F using Karnaugh map method.
(i) F A, B,C, D 1, 4, 5, 6,12,14 (Dec 2010)
CD
AB CD CD CD CD
AB 1
AB 1 1 1
AB 1 1
AB
F B C D A CD BC D
(ii) F A, B,C, D 0,1, 4, 5, 7,11,15
1.94 Digital Principles and System Design
CD
AB CD CD CD CD
AB 1 1
AB 1 1 1
AB 1
AB 1
F A C ABD AC D
(iii) F A, B,C, D 2, 3,12,13,14,15
CD
AB CD CD CD CD
AB 1 1
AB
AB 1 1 1 1
AB
F AB ABC
(iv) F A, B, C, D 0, 2, 5, 7, 8,10,13,15
CD
AB CD CD CD CD
AB 1 1
AB 1 1
AB 1 1
AB 1 1
F BD B D
Boolean Algebra and Logic Gates 1.95
Example 1.149: Simplify F(A, B, C, D) = (0, 1, 2, 5, 8, 9, 10) in sum of products and
product of sums using K-map. (Dec 2012)
Solution: CD 00 01 11 10
AB
1 1 1
00 0 1 3 2
1
01 4 5 7 6
11 12 13 15 14
1 1 1
10 8 9 11 10
SOP:
F = BD ACD ABC
POS:
CD 00 01 11 10
AB
0 0 0
00
0
01
11
0 0 0
10
POS: F = B D A C D A B C
1.96 Digital Principles and System Design
1.26.7 FIVE VARIABLE MAP
The five-variable map consists of 2 four-variable maps with A, B, C, D and E. Variable A
distinguishes between the two maps, as indicated on the top of the diagram as A = 0 and A = 1.
Minterms 015 belong with A = 0 and minterms 16 31 with A = 1.
A= 0 A= 1
DE DE
BC 00 01 11 10 BC 00 01 11 10
00 0 1 3 2 00 16 17 19 18
01 4 5 7 6 01 20 21 23 22
11 12 13 15 14 11 28 29 31 30
10 8 9 11 10 10 24 25 27 26
Example 1.150
Simplify the Boolean expression:
F ( A, B, C, D, E) = (0, 2, 3, 4, 5, 6, 7, 11, 15, 16, 18, 19, 23, 27, 31)
A= 0 A= 1
DE DE
BC 00 01 11 10 00 01 11 10
BC
00 1 1 1 00 1 1 1
0 1 3 2 16 17 19 18
01 1 1 1 1 01 1
4 5 7 6 20 21 23 22
11 1 11 1
12 13 15 14 28 29 31 30
10 1 10
1
8 9 11 10 24 25 27 26
F DE A B C B C E
In DE and B C E terms, A is not included because the adjacent squares belong to both A = 0 and
A = 1.
In A B C term, it is necessary to include A because all the squares are associated with A = 0.
F DE A B C B C E
Boolean Algebra and Logic Gates 1.97
Example 1.151: Simplify the Boolean function
F ( A, B, C, D, E) = ( 0, 1, 4, 5, 16, 17, 21, 25, 29)
DE A= 0 A=1
DE
BC 00 01 11 10 00 01 11 10
BC
00 1 1 00 1 1
0 1 3 2 16 17 19 18
01 1 1 01 1
4 5 7 6 20 21 23 22
11 11 1
12 13 15 14 28 29 31 30
10 10 1
8 9 11 10 24 25 27 26
F A D E ADE BCD
Example 1.152: Find the minimal sum of product form for the following switching function:
f ( x1 , x2 , x3 , x4 , x5) = m ( 2, 3, 6,7, 11, 12, 13,14, 15, 23, 28, 29, 30,31) (May 2006)
x4x5 x1 = 0 x4x5 x1 = 1
x2x3 00 01 11 10 x2x3 00 01 11 10
00 1 1 00
0 1 3 2 16 17 19 18
01 1 1 01 1
4 5 7 6 20 21 23 22
11 1 1 1 1 11 1 1 1 1
12 13 15 14 28 29 31 30
10 1 10
8 9 11 10 24 25 27 26
F x2 x3 x1 x4 x5 x1 x 2 x4 x1 x3 x4 x5
1.98 Digital Principles and System Design
Example 1.153: Find the minimal sum of product expression for the following switching function:
f ( x1 , x2 , x3 , x4 , x5) = m ( 1, 2, 3, 6, 8, 9, 14, 17, 24, 25, 26, 27, 30, 31) + d(4, 5)
(May 2006)
x4x5 x1 = 0 x4x5 x1= 1
x2x3 00 01 11 10 x2x3 00 01 11 10
00 1 1 1 00 1
0 1 3 2 16 17 19 18
01 X X 1 01
4 5 7 6 20 21 23 22
11 1 11 1 1
12 13 15 14 28 29 31 30
10 1 1 10 1 1 1 1
8 9 11 10 24 25 27 26
F x2 x3 x 4 x3 x 4 x5 x1 x2 x4 x1 x 2 x3 x4 x1 x3 x4 x5
1.27 TABULATION METHOD (QUINE-McCLUSKEY METHOD)
The K map method of minimization of logic functions is convenient as long as the number of
variables does not exceed 4 or 5. When the number of variable increases, K map become very difficult.
To avoid this difficult, Quine-McCluskey or Tabulation method can be used. This method is developed
by Quine and McCluskey. The procedure for simplification of Boolean function by Quine- McCluskey
method is as follows:
Each minterm should be expressed by its binary representation.
Arrange the minterms based on the number of 1’s
Compare each binary number from one group to other and if they differ only one bit position,
put dash () mark and copy the remaining term. Please tick () mark after each comparison.
Apply the same process described in step 3 for the resultant column and these cycles have to be
continued unitl no new list can be found (i.e., no further elimination of literals)
List the unchecked (unticked) implicant and form prime implicant chart.
Prime implicant chart
The prime implicants should be represented in rows and each minterm of the function in a
column.
Boolean Algebra and Logic Gates 1.99
The cross (X) mark should be placed in each row to show the comparison of minterms that make
the prime implicants.
Search for single X column and select prime implicants corresponding to that dot by putting the
star (*) mark in front of it.
Prime implicants that cover minterms with a single cross in their column are called essential
prime implicants.
Write the simplified expression using prime implicants.
Example 1.154: Simplify the Boolean function by using tabulation method
F(A,B,C,D) m (0,2,3,6,7,8,10,12,13)
Solution: The minterms are represented in the binary form as shown in Table 1.23(a)
Table 1.23(a) Binary representation of minterms
Minterm Binary equivalent
0 0 0 0 0
2 0 0 1 0
3 0 0 1 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
12 1 1 0 0
13 1 1 0 1
The above binary representation are grouped into a number of sections in terms of the number of
1's as shown in Table 1.23(b)
Table 1.23(b) Group of minterms for different number of 1's
Number of 1's Minterm A B C D
0 0 0 0 0 0
1 2 0 0 1 0
8 1 0 0 0
3 0 0 1 1
2 6 0 1 1 0
10 1 0 1 0
12 1 1 0 0
3 7 0 1 1 1
13 1 1 0 1
1.100 Digital Principles and System Design
Any two number in these groups which differ from each other by only variable can be chosen and
combined, to get 2 cell combination as shown in Table 1.23(c).
Table 1.23(c) 2-cell combination
Combination A B C D
(0,2) 0 0 0
(0,8) 0 0 0
(2,3) 0 0 1
(2,6) 0 1 0
(2,10) 0 1 0
(8,10) 1 0 0
(8,12) 1 0 0
(3,7) 0 1 1
(6,7) 0 1 1
(12,13) 1 1 0
Table 1.23(d) 4 cell combination
Combination A B C D
(0,2,8,10) 0 0
(2,3,6,7) 0 1
From the 2-cell combinations, are variable and a dash () in the same position can be combined to
form 4-cell combination as shown in Table 1.23(d).
The cells (0,2) and (8,10) from the same 4 cell combination as the cells (0,8) and (2,10). The order
in which the cells are placed in a combination does not have any effect. Thus the (0,2,8,10) combination
may be given as (0,8,2,10)
i.e., (0,2,8,10) = (0,8,2,10)
(2,3,6,7) = (2,6,3,7)
Using Table 1.28(c) and (d) the prime implicants table can be as shwon in Table 1.23(e).
Table 1.23(e) Prime Implicant Table
Minterms
Prime Implicants
0 2 3 6 7 8 10 12 13
(8, 12)
(12,13)*
(0,2,8,10)*
(2,3,6,7)*
Boolean Algebra and Logic Gates 1.101
The columns having only one cross (X) mark correspond to essential prime implicants. A tick
mark put against every column which has only one cross mark. A star (*) mark is placed against every
essential prime implicant. The sum of the prime implicants gives the function in its minimal SOP
form. Therefore, F = (1 1 0 ) + ( 0 0) + (0 1 )
F A, B, C , D A B C B D AC
Example 1.155: Find the minimal SOP for the given function using Quine-McCluskey method
F m (0,1,2,8,10,11,14,15) (April 2005)
Solution: Binary representation of minterms
Minterms Binary equivalent
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
8 1 0 0 0
10 1 0 1 0
11 1 0 1 1
14 1 1 1 0
15 1 1 1 1
Group of minterms for different number of 1's:
Number of 1's Minterm A B C D
0 0 0 0 0 0
1 1 0 0 0 1
2 0 0 1 0
8 1 0 0 0
2 10 1 0 1 0
3 11 1 0 1 1
14 1 1 1 0
4 15 1 1 1 1
2 cell combination 4 cell combination
Combination A B C D Combination A B C D
(0,1) 0 0 0 (0,2,8,10) 0 0
(0,2) 0 0 0 (10,11,14,15) 1 1
(0,8) 0 0 0
(2,10) 0 1 0
(8,10) 1 0 0
(10,11) 1 0 1
(10,14) 1 1 0
(11,15) 1 1 1
(14,15) 1 1 1
1.102 Digital Principles and System Design
Here (0,2,8,10) = (0,8,2,10), (10,11,14,15) = (10,14,11,15)
Prime Implicants Table
Prime Minterms
Implicants 0 1 2 8 10 11 14 15
(0,1)*
(0,2,8,10)*
(10,11,14,15)*
F = [(0 0 0 ) + ( 0 0) + (1 1 )]
F A BC B D AC
Example 1.156: Simplify the following function using tabulation method
F(A,B,C,D) = m (1,2,3,5,9,12,14,15) + d (4,8,11)
1) (Dec 2005)
Solution: The don’t care conditions are used to find the prime implicants; but it is not compulsory to
include don’t care term in the final expression.
Binary representation of minterms
Minterms Binary equivalent
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
5 0 1 0 1
9 1 0 0 1
12 1 1 0 0
14 1 1 1 0
15 1 1 1 1
d4 0 1 0 0
d8 1 0 0 0
d11 1 0 1 1
Boolean Algebra and Logic Gates 1.103
Group of minterms for difference number of 1's:
Number of 1's Minterm A B C D
1 1 0 0 0 1
2 0 0 1 0
d4 0 1 0 0
d8 1 0 0 0
2 3 0 0 1 1
5 0 1 0 1
9 1 0 0 1
12 1 1 0 0
3 d11 1 0 1 1
14 1 1 1 0
4 15 1 1 1 1
2-cell combinations 4-cell combinations
Combination A B C D Combination A B C D
(1,3) 0 0 1 (1,3,9,11) 0 1
(1,5) 0 0 1
(1,9) 0 0 1
(2,3) 0 0 1
(4,5) 0 1 0
(4,12) 1 0 0
(8,9) 1 0 0
(3,11) 0 1 1
(9,11) 1 0 1
(12,14) 1 1 0
(11,15) 1 1 1
(14,15) 1 1 1
1.104 Digital Principles and System Design
Prime Implicant Table
Prime implicant A B C D
(1,5) 0 0 1
(2,3) 0 0 1
(4,5) 0 1 0
(4,12) 1 0 0
(8,9) 1 0 0
(8,12) 1 0 0
(12,14) 1 1 0
(11,15) 1 1 1
(14,15) 1 1 1
(1,3,9,11) 0 1
Select the minimum number of prime implicants which must cover all the minterms, except don’t
care minterms:
Prime Implicants m1 m2 m3 d4 m5 d8 m9 d11 m12 m14 m15
(1,5)*
(2,3)*
(4,5)
(4,12)
(8,9)
(8,12)
(12,14)*
(11,15)
(14,15)*
(1,3,9,11)*
Only m2 column has single cross (X) mark and hence the prime implicant corresponding to it
(2,3) is included in the final expression.
m1 column has 2 cross marks. We can include the prime implicants which has more minterms -
(1,3,9,11).
Columns d4, d8 and d11 are don’t cares.
m5 is not included yet, therefore prime implicants (1,5) is included in the final expression.
m12 is not included yet, therefore prime implicant (12,14) is included.
m15 also can be included in the final expression by including prime implicant (14,15)
Boolean Algebra and Logic Gates 1.105
The final expression is,
F = (0 0 1) + ( 0 0 1 ) + (1 1 0 ) + (1 1 1 ) + ( 0 1)
AC D A BC A B D A B C B D
Example 1.157: Simplify the given function
F = (A,B,C,D) = m (2,3,7,9,11,13) + d (1, 10, 15)
Solution: The don’t cares are treated like required minterms when finding the prime implicants.
Minterm Binary Representation
d1 0001
2 0010
3 0011
7 0111
9 1001
d10 1010
11 1011
13 1101
d15 1111
Group of minterms for different number of 1's:
Number of 1's Minterm A B C D
1 0 0 0 1
1
2 0 0 1 0
3 0 0 1 1
2
9 1 0 0 1
10 1 0 1 0
7 0 1 1 1
3
11 1 0 1 1
13 1 1 0 1
4 15 1 1 1 1
1.106 Digital Principles and System Design
2-cell combination 4-cell combination
Combination A B C D Combination A B C D
(1,3) 0 0 1 (1,3,9,11) 0 1
(1,9) 0 0 1 (2,3,10,11) 0 1
(2,3) 0 0 1 (3,7,11,15) 1 1
(2,10) 0 1 0 (9,11,13,15) 1 1
(3,7) 0 1 1
(3,11) 0 1 1
(9,11) 1 0 1
(9,13) 1 0 1
(10,11) 1 0 1
(7,15) 1 1 1
(11,15) 1 1 1
(13,15) 1 1 1
The don’t care columns are omitted when forming prime implicants table
Prime implicants 2 3 7 9 11 13
(1,3,9,11)
(2,3,10,11)*
(3,7,11,15)*
(9,11,13,15)*
F = ( 0 1 ) + ( 1 1) + (1 1)
= B C + CD + AD
Boolean Algebra and Logic Gates 1.107
Example 1.158: Simplify the following 5 vairiable expression using Mccluskey method.
F = m(0, 1, 9, 15, 24, 29, 30) + d(8, 11, 31) (Dec 2010)
Solution:
(1) (2) (3)
0 0000 0, 1 (1) 0, 1, 8, 9
1 0001 0, 8 (8)
8 1000 1, 9(8)
9 01001 8, 9(1)
24 11000 8, 24(16)
11 1011 9, 11(2)
15 01111 11, 15(4)
29 11101 15, 31(16)
30 11110 30, 31(1)
31 11111
Prime implicant table
0 1 9 15 24 29 30
0, 1, 8, 9
8, 24
9, 11
11, 15
15, 31
29, 31
30, 31
1.108 Digital Principles and System Design
Answer:
A’C’D’ + BC’D’E’ + A’BDE + ABCE + ABCD
Or
A’C’D’ + BC’D’E’ + BCDE + ABCE + ABCD
Example 1.159: Minimize the expression using Quine McCluskey (Tabulation) method
Y A BCD A BCD ABCD ABCD ABCD ABCD (May 2012)
CD CD CD CD
1
CD 00 01 11 10
AB
1 1
AB 00 0 1 3 2
1
1
AB 01 4 5 7 6
1 1
AB 11 12 13 15 14
1
AB 10 8 9 11 10
Given, F(A, B, C, D) = {0, 2, 5, 9, 12, 13}
Min term Binary equivalent
0 0 0 0 0
2 0 0 1 0
5 0 1 0 1
9 1 0 0 1
12 1 1 0 0
13 1 1 0 1
Boolean Algebra and Logic Gates 1.109
Number of 1’s Minterms A B C D
0 0 0 0 0 0
1 2 0 0 1 0
2 5 0 1 0 1
9 1 0 0 1
12 1 1 0 0
3 13 1 1 0 1
2 – cell combination
Combination A B C D
(0, 2) 0 0 0
(5, 13) 1 0 1
(9, 13) 1 0 1
(12, 13) 1 1 0
Prime implicants 0 2 5 9 12 13
(0, 2)
(5, 13)
(9, 13)
(12, 13)
F = A’B’D’ + BC’D + AC’D + ABC’
Example 1.160: Simplify the Boolean function using Quine McCluskey method:
F(A, B, C, D, E, F) = m(0, 5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44, 46, 55,
56, 57, 60, 61) (May 2013)
1.110 Digital Principles and System Design
Solution:
Minterms Binary equivalent
0 0 0 0 0 0 0
5 0 0 0 1 0 1
7 0 0 0 1 1 1
8 0 0 1 0 0 0
9 0 0 1 0 0 1
12 0 0 1 1 0 0
13 0 0 1 1 0 1
23 0 1 0 1 1 1
24 0 1 1 0 0 0
25 0 1 1 0 0 1
28 0 1 1 1 0 0
29 0 1 1 1 0 1
37 1 0 0 1 0 1
40 1 0 1 0 0 0
42 1 0 1 0 1 0
44 1 0 1 1 0 0
46 1 0 1 1 1 0
55 1 1 0 1 1 1
56 1 1 1 0 0 0
57 1 1 1 0 0 1
60 1 1 1 1 0 0
61 1 1 1 1 0 1
Group of mintrems for different number of 1’s
Number of 1’s Minterms A B C D E F
0 0 0 0 0 0 0 0
1 8 0 0 1 0 0 0
2 5 0 0 0 1 0 1
9 0 0 1 0 0 1
Boolean Algebra and Logic Gates 1.111
12 0 0 1 1 0 0
24 0 1 1 0 0 0
40 1 0 1 0 0 0
3 7 0 0 0 1 1 1
13 0 0 1 1 0 1
25 0 1 1 0 0 1
28 0 1 1 1 0 0
37 1 0 0 1 0 1
42 1 0 1 0 1 0
44 1 0 1 1 0 0
56 1 1 1 0 0 0
4 23 0 1 0 1 1 1
29 0 1 1 1 0 1
46 1 0 1 1 1 0
57 1 1 1 0 0 1
60 1 1 1 1 0 0
5 55 1 1 0 1 1 1
61 1 1 1 1 0 1
2-Cell Combination
Combination A B C D E F
(0, 8) 0 0 0 0 0
(8, 9) 0 0 1 0 0
(8, 12) 0 0 1 0 0
(8, 24) 0 1 0 0 0
(8, 40) 0 1 0 0 0
(5, 7) 0 0 0 1 1
(5, 13) 0 0 1 0 1
(5, 37) 0 0 1 0 1
(9, 13) 0 0 1 0 1
(9, 25) 0 1 0 0 1
(12, 13) 0 0 1 1 0
(12, 28) 0 1 1 0 0
1.112 Digital Principles and System Design
(24, 25) 0 1 1 0 0
(24, 28) 0 1 1 0 0
(24, 56) 1 1 0 0 0
(40, 42) 1 0 1 0 0
(40, 44) 1 0 1 0 0
(40, 56) 1 1 0 0 0
(7, 23) 0 0 1 1 1
(13, 29) 0 1 1 0 1
(25, 29) 0 1 1 0 1
(25, 57) 1 1 0 0 1
(28, 29) 0 1 1 1 0
(28, 60) 1 1 1 0 0
(42, 46) 1 0 1 1 0
(44, 46) 1 0 1 1 0
(44, 60) 1 1 1 0 0
(56, 57) 1 1 1 0 0
(56, 60) 1 1 1 0 0
(23, 55) 1 0 1 1 1
(29, 61) 1 1 1 0 1
(57, 61) 1 1 1 0 1
(60, 61) 1 1 1 1 0
4 Cell Combination
Combination A B C D E F
(9, 13, 25, 29) 0 0 0 1
(12, 13, 28, 29) 0 1 1 0
(24, 25, 28, 29) 0 1 1 0
(24, 25, 56, 57) 1 1 0 0
(24, 28, 44, 60) 1 1 0 0
(24, 28, 56, 60) 1 1 0 0
(40, 42, 44, 46) 1 0 1 0
(25, 29, 57, 61) 1 1 0 1
(28, 29, 60, 61) 1 1 1 0
Boolean Algebra and Logic Gates 1.113
Prime Implicant Table
0 5 7 8 9 12 13 23 24 25 28 29 37 40 42 44 46 55 56 57 60 61
(0, 8)
(8, 9)
(8, 12)
(8, 24)
(8, 40)
(5, 7)
(5, 13)
(5, 37)
(40, 56)
(7, 23)
(23, 55)
(9, 13, 25, 29)
(12, 13, 28, 29)
(24, 25, 28, 29)
(24, 25, 56, 57)
(24, 28, 44, 60)
(24, 28, 56, 60)
(40, 42, 44, 46)
(25, 29, 57, 61)
(28, 29, 60, 61)
* *
F(A, B, C, D, E, F) = (00 000) + (00101) + (101 0)
F(A, B, C, D, E, F) = ABDEF BCDEF ABCF
1.114 Digital Principles and System Design
1.28 BASIC LOGIC GATES
There are three basic logic gates each of which performs a basic logic function, they are called
NOT, AND and OR. All other logic functions can ultimately be derived from combinations of these
three. For each of three basic logic gates a summary is given including the logic symbol, the
corresponding truth table and the Boolean expression.
1.28.1 The NOT gate
The NOT gate is unique in that it only has one input. The logic symbol of NOT gate is shown in
Figure 1.28.
Fig. 1.28: Logic Symbol
The input to the NOT gate A is inverted i.e., the binary input state of 0 gives an output of 1 and
the binary input state of 1 gives an output of 0.
A is known as “NOT A” or alternatively as the complement of A.
The truth table for the NOT gate appears as below:
TRUTH TABLE
A A
0 1
1 0
1.28.2 The AND gate
The AND gates has two or more inputs. The output from the AND gate is 1 if and only if all of the
inputs are 1, otherwise the output from the gate is 0. The AND gate is drawn as shown in Figure 1.29.
Fig. 1.29 : Logic Symbol
The output from the AND gate is written as A . B
The truth table for a two-input AND gate is given below:
Boolean Algebra and Logic Gates 1.115
TRUTH TABLE
A B A B
0 0 0
0 1 0
1 0 0
1 1 1
1.28.3 The OR gate
The OR gate has two or more inputs. The output from the B
A+B
OR gate is 1 if any of the inputs is 1. The gate output is 0 if and A
only if all inputs are 0. The OR gate is drawn as shown in
Figure 1.30. Fig. 1.30 : Logic Symbol
The output from the OR gate is written as A + B.
The truth table for a two-input OR gate is given below:
TRUTH TABLE
A B A+ B
0 0 0
0 1 1
1 0 1
1 1 1
1.29 OTHER LOGIC GATES
The three basic logic gates can be combined to provide more complex logical functions. Four
important logical functions are described here, namely NAND, NOR, XOR and XNOR. In each case
a summary is given including the logic symbol for that function, the corresponding truth table and
the Boolean expression.
1.29.1 The NAND gate
The NAND gate has two or more inputs. The output from
the NAND gate is 0 if and only if all of the inputs are 1
otherwise the output is 1. Therefore the output from the NAND
gate is the NOT of A AND B (also known as the complement Fig. 1.31: Logic Symbol
or inversion of A B ). The NAND gate is shown in Figuree
1.31 where the small circle immediately to the right of the gate
on the output line is known as an invert bubble.
1.116 Digital Principles and System Design
The output from the NAND gate is written as A B . The Boolean expression A B reads as “A
NAND B”. The truth table for a two-input NAND gate is given below:
TRUTH TABLE
A B A B
0 0 1
0 1 1
1 0 1
1 1 0
1.29.2 The NOR gate
The NOR gate has two or more inputs. The output from A
the NOR gate is 1 if and only if all of the inputs are 0, otherwise A+B
B
the output is 0. This output behaviour is the NOT of A OR B.
The NOR gate is drawn as shown in Figure 1.32. Fig. 1.32: NOR-Logic Symbol
The output from the NOR gate is written as A+B which reads “A NOR B”.
The truth table for a two-input NOR gate is given below:
TRUTH TABLE
A B A B
0 0 1
0 1 0
1 0 0
1 1 0
1.29.3 The Exclusive-OR (XOR) gate
The exclusive-OR or XOR gate has two or more inputs. For a two-input XOR the output is similar
to that from the OR gate except it is 0 when the both inputs are 1. This cannot be extended to XOR
gates comprising 3 or more inputs however.
In general, an XOR gate gives an output value of 1 when
A
there are an odd number of 1’s on the inputs to the gate. The B
truth table for a 3-input XOR gate below illustrates this point.
Fig. 1.33 : XOR-Logic Symbol
The XOR gate is drawn as shown in Figure 1.33.
The output from the XOR gate is written as A B which reads “A XOR B”.
Boolean Algebra and Logic Gates 1.117
The truth table for a two-input XOR gate looks like
TRUTH TABLE
A B A B
0 0 0
0 1 1
1 0 1
1 1 0
Y = A B = AB AB
For a 3-input XOR gate with inputs A, B and C the truth table is given by
A B C A B C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
1.29.4 The Exclusive-NOR (XNOR) gate
The exclusive-NOR or XNOR gate has two or more inputs. The output is equivalent to inverting
the output from the exclusive-OR gate described above. Therefore an equivalent circuit would comprise
an XOR gate, the output of which feeds into the input of a NOT gate.
In general, an XNOR gate gives an output value of 1 when there are an even number of 1’s on the
inputs to the gate. The truth table for a 3-input XNOR gate below illustrates this point.
The XNOR gate is drawn using the same symbol as the XOR gate with an invert bubble on the
output line as is illustrate in Figure 1.34.
A
B
Fig. 1.34 : Logic Symbol
1.118 Digital Principles and System Design
The output from the XNOR gate is written as A B which reads “A XNOR B”.
Y A B
AB AB
AB AB
A B A B
Y AB A B
The truth table for a two-input XNOR gate looks like
TRUTH TABLE
A B A B
0 0 1
0 1 0
1 0 0
1 1 1
For a 3-input XNOR gate with inputs A, B and C the truth table is given by
A B C A B C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
1.30 GATE CONVERSIONS
Any logic gate can be replaced by sets of other interconnected logic gates. Therefore any digital
design can be implemented with a small number of logic gate types. The gate conversion circuits are
shown in Figure 1.35.
Boolean Algebra and Logic Gates 1.119
Fig. 1.35 : Gate Conversions
1.120 Digital Principles and System Design
1.31 DIGITAL ICs
1.31.1 14 Pin DIP 14 13 12 11 10 9 8
vcc
The 14 Pin DIP (Dual-in-line package) was one of the first
types of Integrated Circuits (IC’s) developed. The term dual- DUAL-IN-LINE
in-line package comes from the two parallel sets of pins that PACKAGE
are situated across each other on the IC. The typical layout of
GND
a 14 pin DIP is shown in Figure 1.36.
1 2 3 4 5 6 7
Fig. 1.36 : 14 Pin Dip
The pins are normally number counterclockwise with pin # 1 falling under the notch. For most
IC’s pin 7 is GND and pin 14 is Vcc. In order to utilize this IC, pin 14 must be connected to a supply
voltage (usually 5V) and pin 7 must grounded. Then the various gates within the IC may be used for
analysis.
1.31.2 74X04 Hex Inverter
14 13 12 11 10 9 8
The 74X04 is a hex inverter. The 04 is the number that
v cc
determines the chip type. It is a hex inverter because it contains
6 inverters on a single IC. The X is in place of specific features
that the IC may contain. The most commonly listed special 7404
feature is the 74LS04, where LS stands for Low Power Shottky
GND
Transistors. The pin-out for the 74X04 is shown in
Figure 1.37. 1 2 3 4 5 6 7
Fig. 1.37 : 7404 IC
1.31.3 74X08 Quad AND Gate 14 13 12 11 10 9 8
v cc
The 74X08 contains 4 AND gates. The 08 is the number
that determines the chip type. It is called a quad AND gate
because it contains 4 AND gates on a single IC. The pin-out 7408
for the 74X08 is shown in Figure 1.38.
GND
1 2 3 4 5 6 7
Fig. 1.38 : IC 7408
1.31.4 74X32 Quad OR Gate
The 74X32 contains 4 OR gates. The 32 is the number that determines the chip type. It is called a
quad OR gate because it contains 4 OR gates on a single IC. The pinout for the 74X32 is shown in
Figure 1.39.
Boolean Algebra and Logic Gates 1.121
14 13 12 11 10 9 8
v cc
7432
GND
1 2 3 4 5 6 7
Fig. 1.39 : IC 7432
14 13 12 11 10 9 8
v cc
1.31.5 74X00 Quad NAND Gate
The 74X00 contains 4 NAND gates. The 00 is the number
that determines the chip type. It is called a quad NAND gate 7400
because it contains 4 NAND gates on a single IC. The pin-out
GND
for the 74X00 is shown in Figure 1.40.
1 2 3 4 5 6 7
Fig. 1.40 : IC 7400
1.32 UNIVERSAL GATES
1.32.1 NAND GATE AS A UNIVERSAL GATE
The NAND gate is said to be a universal gate because any digital system can be implemented with
it. The implementation of AND, OR and NOT operations with NAND gates is shown in
Figure 1.41 and EX-OR operations with NAND gates is shown in Figure 1.42.
Fig. 1.41 : Implementation of basic gates using NAND
1.122 Digital Principles and System Design
Exclusive OR with NAND
Fig. 1.42 : Implementation of EX-OR gate
1.32.2 NOR GATE AS A UNIVERSAL GATE
The NOR gate is called a universal gate because combinations of it can be used to accomplish all
the basic functions. The implementation of basic gates using NOR gate is shown in Figure 1.43.
A A+A=A A NOT A
NOR
A A
NOR
A
A+B=AB AND AB
B
B
NOR
B
A+B A
A OR A+B
NOR NOR A+B B
B
Fig. 1.43 : Implementation of Basic gates using NOR
1.33 IMPLEMENTATION OF LOGIC FUNCTIONS USING GATES
If the operation of the circuit is defined by a logic function, a logic circuit can be implemented
directly from that function. For example, suppose we need a circuit that is defined by X = ABC. Then
we immediately know that all that is needed is a 3 input AND gate. If we need a circuit that is defined
by X = A + B , we will use a two input OR gate with an inverter on one of the inputs B . The same
reasoning used for these examples for these simple cases can be extended to more complex logic
circuits.
1.123 Digital Electronics
TWO MARK QUESTIONS
1.Define binary logic?
Binary logic consists of binary variables and logical operations. The variables areDesignated by
the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1
and 0. There are three basic logic operations:AND, OR, and NOT.
2.Convert (634) 8 to binary
634
110 011 100
Ans = 110011100
3.Convert (9B2 - 1A) H to its decimal equivalent.
N = 9 x 16 2 + B x 16 1 + 2 x 16 0 + 1 x 16 -1 + A (10) x 16 -2
= 2304 + 176 + 2 + 0.0625 + 0.039
= 2482.1 10
4.State the different classification of binary codes?
1. Weighted codes
2. Non - weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error Detecting and correcting codes.
5.Convert 0.640625 decimal number to its octal equivalent.
0.640625 x 8 = 5.125
0.125 x 8 = 1.0
= 0.640 625 10 = (0.51) 8
Digital Fundamentals 1.124
6.Convert 0.1289062 decimal number to its hex equivalent
0.1289062 x 16 = 2.0625
0.0625 x 16 = 1.0
= 0.21 16
7.Convert 22.64 to hexadecimal number.
16 22 -6
16 1 -1
0.64 x 16 = 10.24
0.24 x 16 = 3.84
0.84 x 16 = 13.44
.44 x 16 = 7.04
Ans = (16. A 3 D 7) 16
8.State the steps involved in Gray to binary conversion?
The MSB of the binary number is the same as the MSB of the gray code number.So Write it down.
To obtain the next binary digit, perform an exclusive operation between the bit just written down
and the next gray code bit. Writedown the result
9.What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are commutative property, associative Property and
distributive property.
10State the associative property of boolean algebra.
The associative property of Boolean algebra states that the OR ing of severalvariables results in
the same regardless of the grouping of the variables. The associativeproperty is stated as follows:
A+ (B+C) = (A+B) +C
1.125 Digital Electronics
11.Where the digital systems are used?
Digital systems are used extensively in computation and data processing, control systems,
Communications and measurements. Since digital systems are capable of greater accuracy and
reliability than analog systems, many tasks formerly done by analog are now being performed
digitally.
12.What is the difference between analog and digital systems?
In a digital system the physical quantities or signals can assume only discrete values, while in
analog systems the physical quantities or signals vary continuously over a specified range.
13.What is a binary number system and Why are binary numbers used in digital systems?
The number system with base (or radix) two is known as the binary number system. Only two
symbols are used to represent the numbers in the system and these are 0 and 1.The outputs of the
switching devices used in digital systems assume only two different values. Hence it is natural to
use binary numbers internally in digital systems.
14.What is the difference between binary code and BCD?
Binary: Any distinct element can be represented by a binary code.
No limitation for the minimum or maximum number of elements required for coding the element.
BCD: Only a decimal digit can be represented.
It is a four bit representation.
15. What is an Excess3 code?
The excess3 code is a non weighted code which is obtained from the 8-4-2-1 code by adding
3(0011) to each of the codes.
16. What is a gray code and mention its advantages.
A gray code is a non weighted code which has the property that the codes for successive decimal
digits differ in exactly one bit.
The gray code is used in applications where the normal sequence of binary numbers may produce
an error during the transition from one number to the next.
17. What is meant by non-weighted codes?
Each bit has no positional value i). Excess-3 code ii).Gray code iii).Five bit BCD
Digital Fundamentals 1.126
18. List the names of universal gates. Why it is named so?
NAND and NOR gates are universal gates. Because a combination of NAND gates or a
combination of NOR gates can be used to perform functions of any of the basic logic gates
19.Explain the procedure for BCD addition?
In BCD addition of two numbers involve following rules:-
1. Maximum value of the sum for two digits = 9 (max digit 1) + 9 (max digit 2) + 1 (previous
addition carry) = 19
2. If sum of two BCD digits is less than or equal to 9 (1001) without carry then the result is a
correct BCD number.
3. If sum of two BCD digits is greater than or equal to 10 (1010) the result is in-correct BCD
number. Perform steps 4 for correct BCD sum.
4. Add 6 (0110) to the result.
20.Explain the procedure for excess-3 code?
Excess-3 code is an example of unweighted code. Excess-3 equivalent of a decimal number is
obtained by adding 3 and then converting it to a binary format. For instance to find excess-3
representation of decimal number 4, first 3 is added to 4 to get 7 and then binary equivalent of 7
i.e. 0111 forms the excess-3 equivalent.
21.what do you understand by self complementing code?
A binary code is self complementary if complement of any code word is again a code .in self
completing codes 9's complement of a number can be obtained by interchanging 0's and 1's.
22.why the Gray code is called as reflected binary code?
This is a variable weighted code and is cyclic. This means that it is arranged so that every
transition from one value to the next value involves only one bit change. The gray code is
sometimes referred to as reflected binary, because the first eight values compare with those of
the last 8 values, but in reverse order.
23. What is meant by non-weighted codes?
Each bit has no positional value i). Excess-3 code ii).Gray code iii).Five bit BCD
1.127 Digital Electronics
24. What is the feature of gray code? What are its applications
The advantage of gray code also called reflected code over pure binary numbers is that a number
in gray code changes by only one bit as it proceeds from one number to the next. A typical
application of the reflected code occurs when the analog data are represented by a continuous
change of a shaft position. The shaft is portioned into segments and each segment is assigned a
number. If adjacent segment are made to correspond to adjacent reflected-code numbers,
ambiguity is reduced when detection is sensed in the line that separates any two segments.
So in 3-bit code, error may occur due to one bit position, other two bit positions of adjacent
sectors are always same and hence there is no possibility of error. Thus in 3-bit code, probability
of error is reduced to 66 % and in 4-bit code it is reduced upto 25%.
25. Which if the following is the hexadecimal equivalent of (2598.675)10
2598/16 = Q = 162, R = 6 = (6)16
162/16 = Q = 10, R = 2 = (2)16
10/16 = Q = 0, R = 10 = (A)16
0.675 × 16 = 10.8
0.8 × 16 = 12.8
0.8 × 16 = 12.8
0.8 × 16 = 12.8
10 = A, 12 = C
(2598.675)10 = (A26.ACCC)16
Digital Fundamentals 1.128
MCQ QUESTIONS
1. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Answer: a. (11.375)10
2. Binary equivalent of (45.312)8 is
a) (100101.011001010)2
b) (000100.011001111)2
c) (1000111.01111010)2
d) (100101.011110010)2
Answer: a. (100101.011001010)2
3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the
number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer: b. Multiplying
4. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Answer: a. MSB
1.129 Digital Electronics
5. The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Answer: c. (FF)16
6. Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
c) 101110
d) 1001000
Answer: d. 1001000
7. On multiplication of (10.10) and (01.01), we get
a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
Answer: c. 011.0010
8. Divide the binary number (011010000) by (0101) and find the quotient
a) 100011
b) 101001
c) 110010
d) 010001
Answer: b. 101001
Digital Fundamentals 1.130
9. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Answer: c. 00110101
10. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
Answer: a. A + AB = A
11. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Answer: a. (AB)’ = A’ + B’
12. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer: a. SOP
1.131 Digital Electronics
13. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
Answer: b. AB + AB’ + A’B
14. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix
of
squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
Answer: a. Venn Diagram
15. There are ______ cells in a 4-variable K-map.
a) 12
b) 16
c) 18
d) 8
Answer: b. 16
16. The prime implicant which has at least one element that is not present in any other implicant
is known as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
Digital Fundamentals 1.132
d) Prime Complement
Answer: a. Essential Prime Implicant
17. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
Answer: c. K-maps
18. It should be kept in mind that don’t care terms should be used along with the terms that are
present in ___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
Answer: a. Minterms
19. These logic gates are widely used in _______________ design and therefore are available in
IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
Answer: b. Digital
20. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
1.133 Digital Electronics
c) A = 0, B = 0
d) A = 0, B’ = 1
Answer: c. A = 0, B = 0
21. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
Answer: d. OR
22. The code where all successive numbers differ from their preceding number by single bit is
__________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Answer: d. Gray
23. The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0
Answer: a. A
24. The systematic reduction of logic circuits is accomplished by:
a) Symbolic reduction
b) TTL logic
Digital Fundamentals 1.134
c) Using Boolean algebra
d) Using a truth table
Answer: c. Using Boolean algebra
25. Each “1” entry in a K-map square represents:
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Answer: a. A HIGH for each input truth table condition that produces a HIGH output
26. Looping on a K-map always results in the elimination of __________
a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
Answer: c. Variables within the loop that appear in both complemented and
uncomplemented form
27. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’
Answer: a. 1
28. Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
1.135 Digital Electronics
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Answer: b. (A + B’)(C’ + D)
29. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Answer: d. 10100
30. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Answer: b
Digital Fundamentals 1.136
REVIEW QUESTIONS
1. State and prove the postulates, theorems of Boolean algebra.
2. Use QM method to simply the Boolean expression (x1,x2,x3,x4,x5)=
∑(0,1,4,5,16,17,21,25,29)
3. Reduce the Boolean function using tabulation method and implement using
universal gates F(A,B,C,D,E,F) = ∑m(6,9,13,18,19,25,27,29,41,45,57,61)
4. State and prove the demogans theorem
5. Find a Min SOP and Min POS for F = b’c’d + bcd +acd’ + a’b’c +a’bc’d
6. Using the K-Map find the MSB form of F = ∑m(0-3, 12-15) + ∑d(7,11)
7. Implement y= (A+C)(A+D’)(A+B+C’) using NOR gates only
8. Using the K-Map simplify the expression Y(A,B,C,D)
m1+m3+m5+m7+m8+m9+m0+m2+m10+m12+m13Indicate the prime
implicants, essential and Non essential prime implicants. Draw the logic circuit
using AND -OR-INVERT gates and also Using NAND gates
9. Simplify the Boolean function F = (1,3,5,6,7,10,14,15) and realize the NAND
gate only
10. Explain in detail about universal gates
11. i) Reduce the following Boolean
expression using K- map technique. F (W,
X, Y, Z) = ∑m (0, 7, 8, 9, 10, 12) + ∑d (2,
5)
12. Simplify the following using tabulation method
F (A, B, C, D) = ∑m (1, 2, 3, 5, 9, 12, 14, 15) + ∑d (4, 8, 11)
Combinational Logic 2.1
UNIT 2
COMBINATIONAL LOGIC
2.1 INTRODUCTION
A combinational circuit consists of logic gates
whose outputs at any time are determined directly
from the present combination of input without
regard to previous inputs. A combination circuit 1 1
consists of input variables, logic gates and output 2 2
variables. The logic gates accept signals from the Combinational
Input Logic Output
inputs and generate signals to the outputs. This variables Circuit variables
process transforms binary information from the
given input data to the required output data. A n m
block diagram of a combinational circuit is shown
in Figure 2.1. It accepts ‘n’ binary input variables Fig. 2.1 : Block diagram of a
combinational circuit
and generate ‘m’ output variables depending on
the logical combination of gates.
The possible representations for a combinational logic function:
A truth table
An algebraic sum of minterms, the canonical sum
A minterm list using the notation
An algebraic product of maxterms, the canonical product
A maxterm list using the notation.
2.2 DESIGN PROCEDURE
Any combinational circuit can be designed by following the design procedure given below:
From the given word description of the problem, identify the number of input variables and
required output.
The variables input and output variables are assigned letter symbols.
Draw a truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
Obtain the Boolean expression for each output using either algebraic or K-map method.
Obtain the logic diagram.
In practical design method, some constraints are considered:
Minimum number of gates.
2.2 Digital Principles and System Design
Minimum number of inputs to a gate.
Minimum propagation time of the signal through the circuit.
Minimum number of interconnections.
Limitations of the driving capabilities of each gate.
Example 2.1: Design a combination logic circuit with three input variables that will produce a logic
1 output when more than one input variables are logic 1.
Solution: Number of Input variables = 3
Number of Output variables = 1
Let assign the letter symbols A, B and C to three input variables and assign ‘Y’ to one output
variable. The relationship between input variables and output variable is tabulated in truth table as
given in Table 2.1.
TABLE 2.1: Truth Table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Using K map method, find the Boolean expression for Y.
BC
00 01 11 10
A
0 0 0 1 0
1 0 1 1 1
Y = AB + AC + BC
Combinational Logic 2.3
Draw the logic diagram for Y = AB + AC + BC.
Fig. 2.2: Logic diagram
Example 2.2: Design a combinational logic circuit that has four inputs and one output. The output is
high if both inputs A and B are high or both inputs C and D are high.
Solution: The relationship between input variables (A, B, C, D) and output variable (Y) is tabulated as
shown in Table 2.2.
TABLE 2.2 : Truth Table
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
2.4 Digital Principles and System Design
Using K map obtain the Boolean expression for output variable Y
CD
AB 00 01 11 10
00 0 0 1 0
01 0 0 1 0
11 1 1 1 1
10 0 0 1 0 Y = AB + CD
Draw the logic diagram for Y = AB + CD.
Fig. 2.3 : Logic diagram
2.3 HALF ADDER
“The half adder accepts two binary digits on its inputs and produces two binary digits on its
outputs, a sum and a carry bit.”
Figure 2.4(a) shows the logic symbol of a half-adder and Figure 2.4(b) shows the truth table for
the half-adder.
Inputs Outputs
A Sum
A B S Cout
0 0 0 0
Half
Adder 0 1 1 0
B Carry 1 0 1 0
1 0 0 1
(a) Logic symbol (b) Truth Table
Fig. 2.4: Half adder
Combinational Logic 2.5
The half adder follows the basic rules for addition:
0+0=0
0+1=1
1+0=1
1 + 1 = 10
By using K-map, determine the expression for output variables (sum and carry out)
B B
0 1 0 1
A A
0 0 1 0 0 0
1 1 0 1 0 1
Sum = AB AB Carry = Cout = AB
=A B
The output carry is produced with an AND gate with A and B on the inputs and the output sum is
produced with an EX-OR gate as shown in Figure 2.5.
A
S
B
Cout
Fig. 2.5: Half adder logic diagram
2.4 FULL ADDER
“The full adder accepts three inputs-two input bits and input carry and generates sum output and
output carry.”
A half adder has only two inputs and there is no provision to add a carry coming from the lower
order bits when multi addition is performed. For this purpose a full adder is used. A full adder has 3
inputs A, B, Cin and two outputs Sum (s) and carry out (Cout). Figure 2.6(a) shows the logic
symbol and Figure 2.6(b) shows the truth table for full adder.
A Sum
Full
B
adder
Cin Cout
Fig. 2.6(a): Logic symbol
2.6 Digital Principles and System Design
INPUTS OUTPUTS
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Fig. 2.6(b): Truth Table
By using K-map simplification, determine the expression for output variables S and Cout.
(i) Expression for Carry
BCin
A 00 01 11 10
0 1
1 1 1 1
Cout ACin AB BCin
(ii) Expression for Sum
BCin
A 00 01 11 10
0 1 1
1 1 1
S A B Cin A B C in A B C in A B C in ABCin
A B Cin BC in A B C in BCin
A B Cin A B Cin
Let X = B Cin , then S = AX AX
=A X
Replacing X with B Cin, then
S = A B Cin
Cout = ACin + AB + BCin
Combinational Logic 2.7
The logic diagram is constructed by logic gates as shown in Figure 2.7.
A
B Sum
Cin
AB
BCin
Cout
ACin
Fig. 2.7 : Full adder logic diagram
2.4.1 Implementation of full adder using Half adders
The full adder can also be implemented with two half-adders and one OR gate as shown in Figure 2.8.
For a half adder, Sum = A B
Cout = AB
For a full adder, Sum = A B Cin
Cout AB ACin BCin
AB ACin BCin A A
AB ACin ABCin ABCin
AB 1 Cin ACin ABCin
AB ACin ABCin
AB ACin B B ABCin
AB ABCin ABCin ABCin
AB 1 Cin ABCin ABCin
AB ABCin ABCin
AB Cin AB AB
AB Cin A B
2.8 Digital Principles and System Design
Using these expressions draw the logic diagram for full adder.
A
B Sum
Cin
Fig. 2.8: Implementation of full adder
Notice in Figure 2.8, there are two half adders, connected as shown in the block diagram Figure
2.9, with their output carries ORed.
Half adder Half adder
A S S
B Cout Cout
Cin
AB
Fig. 2.9 : Implementation of full adder with half adders
2.5 HALF SUBTRACTOR
A half subtractor is a combinational circuit that subtracts two bits and produces their difference.
It also has an output to specify if a 1 has been borrowed. Let us designate minuend bit as A and the
subtrahend bit as B. The result of operation A B = D and the borrow is Bout. Figure 2.10(a) shows the
logic symbol of a half subtractor and Figure 2.10(b) shows the truth table for the half-subtractor.
Inputs Outputs
A B D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
(a) Logic symbol (b) Truth table
Fig. 2.10 : Half subtractor
Combinational Logic 2.9
The half subtractor follows the basic rules for subtraction:
00=0
0 1 = 1 with 1 borrow
10=1
11=0
By using K-map, determine the expression for output variables, Difference (D) and Borrow out (Bout).
B B
A 0 1 A 0 1
0 0 1 0 0 1
1 1 0 1 0 0 A
D
B
D AB AB Bout AB
A B
The difference output (D) is produced with
an EX-OR gate and the borrow output (Bout) is
produced with an AND gate with A and B as Bout
shown in Figure 2.11.
Fig. 2.11: Half subtractor
2.6 FULL SUBTRACTOR
“The full subtractor accepts three inputs minuend, subtrahend and borrow from the previous
stage and generates difference output and borrow output.”
The full subtractor has 3 inputs-Minuend (A), Subtrahend (B) and borrow from the previous stage
(Bin) and two outputs-difference (D) and borrow out (Bout). Figure 2.12(a) shows the logic symbol
and Figure 2.12(b) shows the truth table for full subtractor.
Inputs Outputs
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
(a) Logic symbol (b) Truth Table
Fig. 2.12 : Full Subtractor
2.10 Digital Principles and System Design
K-map Simplification
(i) Expression for ‘D’:
BBin
A 00 01 11 10
0 0 1 0 1
1 1 0 1 0
D A B Bin A B B in A B B in ABBin
(ii) Expression for Borrow (Bout)
BBin
A 00 01 11 10
0 0 1 1 1
1 1 0 1 0
Bout AB ABin BBin
The Boolean function for D is simplified as,
D A B Bin A B B in ABBin ABB in
Bin A B AB B in AB A B
Bin A B Bin A B
Bin Bin A B A B
Bin A B
The logic diagram of full subtractor is constructed by logic gates is shown in Figure 2.13.
A
B D
Bin
ABin
AB Bout
BBin
Fig. 2.13 : Full subtractor-logic diagram
Combinational Logic 2.11
2.6.1 Implementation of Full Subtractor using Half Subtractor
A full subtractor can also be implemented with two half subtractors and one OR gate as shown in
Figure 2.14.
For a half subtractor, D A B
Bout A B
For a full subtractor, D A B Bin
Bout AB ABin BBin
AB ABin B B BBin
AB ABBin A B Bin BBin
AB 1 Bin A BBin BBin
AB BBin A BBin
AB BBin A A A BBin
AB ABBin ABBin A B Bin
AB 1 Bin ABBin A B Bin
AB ABBin A B Bin
AB Bin AB AB
Bout A B Bin A B
Using these expressions, draw the logic diagram for full subtractor as given below:
A
B
Bin
AB
Fig. 2.14 : Implementation of full subtractor
2.12 Digital Principles and System Design
Notice in Figure 2.14, there are two half subtractors connected as shown in the block diagram
Figure 2.15, with their output borrows ORed.
Fig. 2.15 : Implementation of full subtractor using half subtractors
2.7 PARALLEL BINARY ADDERS
A single full adder is capable of adding two 1 bit numbers and an input carry. To add binary
numbers with more than one bit, additional full-adders are required. In order to add two binary numbers,
a full adder is required for each bit in the number. Thus for two-bit numbers, we need two full-adders.
Similarly for the addition of four-bit numbers, we need four full-adders and so on.
A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary numbers
in parallel. It consists of full-adders connected in a chain, with the output carry from each full-adder
connected to the input carry of the next full-adder in the chain. The least significant bits (LSB) of the
two binary numbers being added go into the right most full adder whereas the higher order bits are
applied as shown to the successive higher-order adders. The most significant bits (MSB) of the two
binary numbers are applied to the left-most full-adder. The block diagram of 4 bit parallel adder is
shown in Figure 2.16.
Fig. 2.16 : 4 bit Parallel Adder
Combinational Logic 2.13
The input carry is labelled as C0 and the output carry is labelled as C4.
There are several parallel adders that are available as ICs. Table 2.3 shows the most commonly
used 4 bit parallel adders. In the IC package, a 4 bit parallel adder consisting 4 terminals for the
augend bits, 4 terminals for addend bits, 4 terminals for the sum bits and 2 terminals for the input and
output carries. The logic symbol of a 4 bit parallel adder is shown in Figure 2.17.
TABLE 2.3: IC 4 Bit Parallel Adder
Family IC
TTL 7483A
LSTTL 4LS83A
CMOS 74HC283
Fig. 2.17 : Logic symbol of a 4-bit parallel adder
8 bit Parallel adder: In order to accomplish addition of large binary numbers, two or more IC adders
can be connected together, i.e., cascaded. Figure 2.18. Shows two 74LS83A adders connected to add
two 8 bit numbers, A7 A6 A5 A4 A3 A2 A1 A0 and B7 B6 B5 B4 B3 B2 B1 B0.
Fig. 2.18 : Cascading of two 74L383A
2.8 PARALLEL SUBTRACTOR
The subtraction of binary numbers can be done here by means of 2’s complement method. The 2’s
complement can be obtained by taking the 1’s complement and adding 1 to the least significant pair of
bits. In the parallel subtractor, the 1’s complement can be implemented with inverters added with
each data input B and a one can be added to the sum through the input carry as shown in Figure 2.19.
2.14 Digital Principles and System Design
Fig. 2.19 : 4 Bit Parallel Subtractor
2.9 BINARY ADDER/SUBTRACTOR
The 4 bit binary adder/subtractor circuit is shown in Figure 2.20. It performs the operations of
both addition and subtraction. It has two 4 bit input A0 A1 A2 A3 and B0 B1 B2 B3. The ADD /SUB line
is the control line, connected with input carry C0 of the least significant bit of the full adder, is used to
perform the operations of addition and subtraction.
The addition and subtraction operations can be combined into one circuit with one common
binary adder. This is done by including an EX-OR gate with each full- adder. When ADD /SUB = 0,
the circuit is an adder and when ADD /SUB = 1, the circuit is a subtractor. Each EX-OR gate receives
input ADD /SUB and one of the inputs of B.
ADDER
When ADD /SUB = 0, the operation is B 0 = 0. The full-adder receives the value of B and the
input carry C0 = 0. Thus the circuit performs the addition operation, A + B.
SUBTRACTOR
When ADD /SUB = 1, the operation is B 1 B . The full adder receives the value of B and the
input carry C0 = 1. The B inputs are all complemented and a 1 is added through the input carry (C0).
Thus the circuit performs the subtraction operation, i.e.,
A + (2’s complement of B) = A B.
Combinational Logic 2.15
B3 A3 B2 A2 B1 A1 B0 A0
ADD/SUB
Full Full Full Full
C4 Adder C3 Adder C2 Adder C1 Adder C0
S3 S2 S1 S0
Fig. 2.20 : 4 Bit Adder/Subtractor
2.10 SERIAL ADDER
In the serial adder, the addition operation is done by bit-by-bit. The serial adder requires simpler
circuit than a parallel adder. The speed of operation of serial adder is lower than the parallel adder.
The operation of serial adder as follows:
Two shift registers A and B are used to store the numbers to be added serially. A single full adder
is used to add one pair of bits at a time along with the carry. The D-flipflop is used to store the carry
output of the full adder, so that it can be added to the next significant position of the numbers in the
registers. The contents of the shift registers shift from left to right and their outputs starting from A0
and B0 are fed into a single full adder along with the output of the D-flipflop upon application of each
clock pulse. The sum output of the full adder is fed to MSB bit (S3) of the sum register. For each
succeeding clock pulse, the contents of the both shift registers are shifted once to the right and new
carry bit are transferred to sum register and D- flipflop respectively. This process continues untill all
the pairs of bits are added. The diagram of a serial adder is shown in Figure 2.21 and a four bit serial
adder is shown in Figure 2.22.
Ai Si
Full
Bi Adder
Cin Cout
DELAY
Fig. 2.21 : Serial Adder
2.16 Digital Principles and System Design
Sum/Difference
Register
Fig. 2.22 : 4 Bit Serial Adder
Example 2.3: Solve (0111) + (0010) using serial adder.
Let, A3 A2 A1 A0 = 0 1 1 1
B3 B2 B1 B0 = 0 0 1 0
C0 = Cin = 0
(i) Before the first clock pulse occurs, as the inputs to the full adders are A0 = 1, B0 = 0 and Cin = 0.
The full adder outputs will be S = 1, Cout = 0.
(ii) When the first clock pulse occurs, the value in the A and B registers shift from left to right by
one bit. In addition, the sum (S) is transferred to S3 of the sum register and the Cout is transferred
to D-flipflop, whose output becomes 0, which is the carry input (Cin) of the full adder.
(iii) Now A0 = 1, B0 = 1 and Cin = 0 and therefore, S = 0 and Cout = 1. When the second clock pulse
occurs, A, B and Sum registers again shift right; S = 0 is transferred to S3 and Cout = 1 is transferred
to the D-flipflop.
(iv) Now A0 = 1, B0 = 0, Cin = 1 and therefore S = 0, Cout = 1. When the third clock pulse occurs, A,
B and Sum registers shift right; S = 0 is transferred to S3 and Cout = 1 is transferred to D-flipflop.
(v) New A0 = 0, B0 = 0, Cin = 1 and therefore S = 1, Cout = 0. When the fourth clock pulse occurs, A,
B and Sum registers shift right; S = 1 is transferred to S3 and Cout = 0 is transferred to D-flipflop.
At the end of the fourth clock pulse, the result will be available in the sum register as 1001 and
Cout is 0.
Result: 0111 + 0010 = 1001
Combinational Logic 2.17
2.11 SERIAL SUBTRACTOR
A serial subtractor can be obtained by converting the serial adder by
(i) feeding the output B , into the full adder instead of B.
(ii) initially setting the D-flipflop to 1 instead of 0.
(iii) difference register instead of sum register.
The remaining circuitry is the same as serial adder.
The serial subtractor using 2’s complement subtraction method. The subtrahend is stored in the
‘B’ register and the minuend is stored in ‘A’ register. The subtrahend is converted into 1’s complement
number by adding a NOT gate with B register and get 2’s complement number by adding 1 through
Cin. The 2’s complement of subtrahend is added to the minuned by the full adder and the result is
stored in the difference register.
2.12 SERIAL ADDER/SUBTRACTOR
The four bit serial adder/subtractor is shown in Figure 2.23. When ADD /SUB = 0, the
uncomplemented B3 B2 B1 B0 will be applied to the full adder. The D-flipflop is initially cleared by
applying a low pulse at CLR input and the circuit function as a 4-bit serial adder. When ADD /SUB=1,
the complemented output of B register B3 B 2 B1 B 0 will be applied to the full adder. The D-flipflop
is set to 1 so as to get the 2’s complement of the subtrahend by applying a low pulse at PR input and
thus the circuit function as a 4-bit serial subtractor.
Sum/Difference
Register
Fig. 2.23: 4 Bit Serial Adder/Subtractor
2.18 Digital Principles and System Design
2.13 BINARY MULTIPLIER
Multiplication operation can be carried out by (i) Multipliers using partial product addition and
shifting and (ii) Parallel multipliers.
Multiplier using Shift Method
To understand the multiplication process using shift method, consider the multiplication of two
4-bit binary numbers 1010 and 1011, as an example.
1010 Multiplicand
x 1011 Multiplier
1010 Partial product 1
1010 Partial product 2
0000 Partial product 3
1010 Partial product 4
1101110
From the above multiplication process, one can easily understand that if the multiplier bit is 1,
then the multiplicand is simply copied as a partial product; if the multiplier bit is 0, then the partial
product is 0. Whenever a partial product is obtained, it is shifted one bit to the left of the previous
partial product. This process is continued until all the multiplier bits are checked, and then the
partial products are added to this multiplication process, i.e. multiplication by partial product addi-
tion and shifting, can be implemented using the block diagram shown in figure.
In the shown figure, the 4-bit multiplier is stored in register Y (Y3Y2Y1Y0); the 4-bit
multiplicand is stored in register M (M3M2M1M0), and the X register (X4X3X2X1X0) is initially cleared
to 00000. Here, to perform multiplication, the least significant bit of the multiplier bit (Y0) is checked
whether it is 0 or 1. If Y0 = 1, the number in the multiplicand register (M) is added with the least
significant 4-bits of X register (X3X2X1X0;X4 is to store carry in addition process) and the combined
X and Y register is shifted to the right by 1 bit. If Y0 = 0, the combined X and Y register is shifted to
the right by 1 bit without performing any addition. This process has to be repeated four times to
perform 4-bit multiplication. Now, the multiplication result (R7R6R5R4R3R2R1R0) will be available
in X and Y registers (X3X2X1X0Y3Y2Y1Y0).
Combinational Logic 2.19
Fig.2.24: 4-bit binary multiplier using shift method
Parallel Multiplier
The 4-bit multiplier using shift method requires 4 cycles of addition and shifting operations, but
it requires only a single 4-bit parallel adder. The speed of multiplication process can be increased
considerably in parallel multiplier at the extra cost of increased hardware. The circuit diagram for a
4-bit parallel mutliplier is shown in figure.
Fig.2.25:4-bit parallel multiplier
2.20 Digital Principles and System Design
It requires three 4-bit parallel binary adders and 16 numbers of 2-input AND gates. Here, each group
of 4 AND gates is used to obtain partial products while 4-bit parallel adders are used to add the
partial products. Since the generation of partial products and their additions are performed
in parallel in the group of AND gates and 4-bit adders respectively, the multiplication result
(P7P6P5P4P3P2P1P0) will be available at the output immediately after the propagation delay in the
multiplier circuit.
The operation of the parallel multiplier can be understood in a better manner from the
symbolic form of binary multiplication process shown in figure.
Fig.2.26: Symbolic form of binary multiplication process
2.14 CARRY LOOK AHEAD ADDER
In parallel adder, all the bits of the augend and the addend are available for computation at the
same time. The carry output of each full-adder stage is connected to the carry input of the next higher-
order stage. Since each bit of the sum output depends on the value of the input carry, time delay
occurs in the addition process. This time delay is called as carry propagation delay.
Combinational Logic 2.21
For example, addition of two numbers (0011 + 0101) gives the result as 1000. Addition of the
LSB position produces a carry into the second position. This carry when added to the bits of the
second position, produces a carry into the third position. This carry when added to the bits of the third
position, produces a carry into the last position. The sum bit generated in the last position (MSB)
depends on the carry that was generated by the addition in the previous positions. i.e., the adder will
not produce correct result until LSB carry has propagated through the intermediate full-adders. This
represents a time delay that depends on the propagation delay produced in an each full-adder. For
example if each full adder is considered to have a propagation delay of 30 ns, then S3 will not react its
correct value until 90 ns after LSB carry is generated. Therefore total time required to perform addition
is 90 + 30 = 120 ns.
The method of speeding up this process by eliminating inter stage carry delay is called look
ahead-carry addition. This method utilizes logic gates to look at the lower order bits of the augend
and addend to see if a higher-order carry to be generated. It uses two functions: carry generate and
carry propagate.
Carry generate, Gi = Ai Bi
Carry propagate, Pi = Ai Bi
Sum, Si = Pi Ci
= Ai Bi Ci
Carry, Ci+1 = Gi + Pi Ci
The structure of one stage of a carry look ahead adder is shown in Figure 2.27.
Ai
Bi
Ci
Ai–1
A0
Carry
Lookahead
Bi–1
Logic Cout
B0
C0
Fig. 2.27 : Structure of one stage of a carry look ahead adder
2.22 Digital Principles and System Design
Gi (carry generate) generates carry if both Ai and Bi are 1 regardless of the input carry.
Pi (carry propagate) propagates carries if atleast one of its addend bits is 1. The carry output of a
stage can now be written in terms of the generate and propagate signals:
Ci+1 = Gi + Pi Ci
To eliminate carry ripple, expand the Ci term for each stage and multiply out to obtain a 2-level
AND-OR expression. Using this technique, we can obtain the following carry equations for the first
four adder stages are obtained.
C1
C2 = G1 + P1 C1
C3 = G2 + P2 C2 = G2 + P2 (G1 + P1 C1)
= G2 + P2 G1 + P2 P1 C1
C4 = G3 + P3 C3 = G3 + P3 (G2 + P2 G1 + P2 P1 C1)
= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 C1
From these equations, it can be seen that C4 does not have to wait for C3 and C2 to propagate.
Infact, C4 is propagated at the same time as C2 and C3. Figure 2.28shows the implementation of carry
equations for C2, C3 and C4 using AND-OR logic.
C4
P3
G3
C3
P2
G2
P1
C2
G1
C1
Fig. 2.28 : Logic diagram of a look ahead carry generator
Combinational Logic 2.23
2.15 BCD ADDER
The BCD adder is used to add two BCD digits and produces a sum in BCD digit. We know that,
BCD number means 0 to 9 (10 digits) and are represented in the binary form 0000 to 1001.
BCD numbers cannot be greater than 9 and 10 is represented in BCD as 0001 0000. In BCD
addition, the sum is greater than 9(1001), we obtain a non-valid BCD representation. The addition of
binary 6(0110) to the binary sum converts it to the correct BCD representation and also produces an
output carry as required.
Let us consider BCD addition of 5 and 10,
5 0101
10 1010 (+)
15 1111
1
1111 is an invalid BCD number. It can be corrected by the addition of 6(0110) to the invalid BCD
number.
15 1111
1
6 0110 (+)
0001 0101 15 (BCD)
Thus we can summarize the BCD addition procedure as follows:
1. Add two BCD numbers using ordinary binary addition.
2. If the result is equal to or less than 9, no correction is needed. The sum is in correct BCD form.
3. If the result is greater than 9 or if a carry is generated from the result, the result is invalid and the
correction is needed.
4. To correct the invalid sum add 6(0110) to the result. If a carry results from this addition, add it
to the next higher order BCD digit.
Implementation of BCD adder using logic circuit as follows:
4-bit binary adder for initial addition.
Logic circuit to detect sum greater than 9.
Second 4-bit binary adder to add 6(0110) to the result if result is greater than 9 or carry is 1.
The logic circuit to detect result greater than 9 can be determined by simplifying the boolean
expression of given Table 2.4.
2.24 Digital Principles and System Design
TABLE 2.4: Truth Table
Inputs Output
S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Draw the K-map for the above truth table and find out the expression
S1 S0
S3 S2 00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 1 1 1 1
10 0 0 1 1
Y = S3 S2 + S3 S1
Combinational Logic 2.25
This Binary to BCD correction expression is shown in Figure 2.29.
Fig. 2.29 : Binary to BCD Correction
In first binary adder, two BCD numbers together with input carry are added. When the result is
equal to zero (i.e., result 9 or Cout = 0), nothing is added to the result. When the result is one
(i.e., result 9 or Cout = 1) binary 0110 is added to the result through second binary adder. The Cout
generated by second adder can be ignored, since it supplies information already available at the
output carry terminal. The single digit BCD adder is shown in Figure 2.30. Multiple digit BCD
adders can be constructed by cascading as many single digit adders as needed. The BCD carry-out
from each stage would be connected to the carry-in of the next higher order stage.
Fig. 2.30 : Single Digit BCD Adder
2.26 Digital Principles and System Design
2.16 MAGNITUDE COMPARATOR
A magnitude comparator is a combinational circuit that compares the magnitude of two numbers
A and B and generates one of the following outputs:
A=B
A<B
A> B .
The block diagram of n-bit magnitude comparator is shown in Figure 2.31.
Fig. 2.31 : Block diagram of n-bit magnitude comparator
To implement the magnitude comparator, the EX-NOR gates and AND gates are used. The EX-
NOR gate is used to find whether the two binary digits are equal or not, and the AND gates are used
to find whether a binary digit is less than or greater than another binary digit as shown in Figure 2.32.
Figure 2.33shows a single bit magnitude comparator.
A
1
B
A0 = B0
A0 > B0 A0 < B0
(A0 = 1, B0 = 0) (A0 = 0, B0 = 1)
Fig. 2.32 : Comparator Operation
Combinational Logic 2.27
A0
B0 A0>B0
A0
A0
B0 A0=B0
B0
B0
A0 A0<B0
Fig. 2.33: Single bit magnitude comparator
The same principle can be extended to an n-bit magnitude comparator. The design of a 2 bit
magnitude comparator is as follows:
The truth table for 2 bit comparator is given in Table 2.5.
TABLE 2.5 : Comparator Truth Table
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
2.28 Digital Principles and System Design
For A > B For A < B
B1B0 B1B0
00 01 11 10 00 01 11 10
A1A0 A1A0
00 0 0 0 0 00 0 1 1 1
01 1 0 0 0 01 0 0 1 1
11 1 1 0 1 11 0 0 0 0
10 1 1 0 0 10 0 0 1 0
A0 B1 B 0 A1 B1 A1 A0 B 0 A0 B1 B0 A1 B1 A1 A0 B0
B1B0 For A = B
A1A0 00 01 11 10
00 1 0 0 0
01 0 1 0 0
11 0 0 1 0
10 0 0 0 1
A1 A 0 B 1 B 0 A1 A0 B 1 B 0 A1 A0 B1 B 0 A1 A 0 B1 B 0
A1 B1 A0 B 0 A0 B0 A1 B1 A0 B0 A0 B 0
A1 B1 A1 B1 A0 B 0 A0 B0 A1 B1 A0 B0
The expressions for determining whether,
A B is A0 B1 B 0 A1 B1 A1 A0 B 0
A B is A0 B1 B0 A1 B1 A1 A0 B0
A B is, A
1 B1 A0 B0
Combinational Logic 2.29
The implementation of 2 bit magnitude comparator using EX-NOR and AND gates using the
above expressions is shown in Figure 2.34.
Fig. 2.34 : 2-bit Magnitude comparator
2.17 PARITY GENERATOR AND CHECKER
A parity bit is used for the purpose of detecting errors during transmission of binary information.
A parity bit is an extra bit included with a binary message to make the number of 1s either odd or
even. The message including the parity bit is transmitted and then checked at the receiving end for
errors. An error is detected if the checked parity does not correspond with the one transmitted. The
circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that
checks the parity bit in the transmitter is called a parity generator and the circuit that checks the parity
in the receiver is called a parity checker.
Even parity means an ‘n’ bit input has an even number of 1s. For example, 110101 has even
parity because it contains four 1s.
Odd parity means an ‘n’ bit input has an odd number of 1s. For example, 110100 has odd parity
because it contains three 1s.
2.30 Digital Principles and System Design
2.17.1 Parity Checker
Exclusive-OR gates are used for checking the parity of a binary number because they produce an
output 1 when the input has an odd number of 1s. Therefore, an even parity input to an EX-OR gate
produces a low output, while an odd parity input produces a high output. Remember the truth table for
EX-OR gate as given below:
Inputs Outputs
0 0 0
0 1 1
1 0 1
1 1 0
Figure 2.35shows a 4 bit parity checker. The output is 1 when the number of 1s in the inputs is
odd and output is 0 when the number of 1s in the inputs is even. For example, when 1001 is the input
given to the 4 bit parity generator, the output is 0, because the number has two 1s.
Fig. 2.35: 4 bit parity checker
Figure 2.36shows a 16 input EX-OR gate. A 16 bit number drives the input. The EX-OR gate
produces an output 1 because the input (1010101010101000) has odd parity.
1 0 10 1 0 1 01 01 0 1 00 0
output = 1
Fig. 2.36: 16 bit parity checker
2.17.2 Parity Generator
Figure 2.34 shows the odd-parity generator. Let the 8 bit binary number,
X7 X6 X5 X4 X3 X2 X1 X0 = 0100 0001
Then the number has even parity, which means the EX-OR gate produces an output of 0. Because
of the inverter X8 = 1 and the final 9-bit output is,
1 0100 0001
Combinational Logic 2.31
This 9 bit output has odd parity.
Suppose the input is 0110 0001. Now it has odd parity. The EX-OR produces an output 1. But the
inverter produces a 0 (X8= 0), so that the final 9 bit output is,
0 0100 0001.
Again the final output has odd parity,
Thus odd-parity generator produces a 9 bit output number with odd parity. If the 8 bit input has
even parity, a 1 comes out of the inverter to produce a final output with odd parity. If the 8 bit input
has odd parity, a 0 comes out of the inverter and the final 9 bit output again has odd parity.
To get even parity generator delete the inverter in the circuit shown in Figure 2.37 .
9 bit number with odd parity
Fig. 2.37 : Odd-parity generator
2.18 CODE CONVERTERS
A code converter is a logic circuit that changes data presented in one type of binary code to
another type of binary code. Now we will discuss about some code converters.
2.18.1 Binary to BCD Converter
Table 2.6 shows the binary codes and corresponding BCD codes.
2.32 Digital Principles and System Design
TABLE 2.6 : Truth Table for Binary to BCD converter
Binary Code BCD code
D C B A B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1
For B0 For B1
BA BA
DC 00 01 11 10 DC 00 01 11 10
00 0 1 1 0 00 0 0 1 1
01 0 1 1 0 01 0 0 1 1
11 0 1 1 0 11 1 1 0 0
10 0 1 1 0 10 0 0 0 0
B0 = A B1 = DC B DB
For B2 For B3
BA BA
DC 00 01 11 10 DC 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 1 1 1 1 01 0 0 0 0
11 0 0 1 1 11 0 0 0 0
10 0 0 0 0 10 1 1 0 0
B2 = DC CB B3 DC B
Combinational Logic 2.33
For B4
B0 A
BA B1 DC B DB
00 01 11 10
DC
B2 DC CB
00 0 0 0 0
B3 DC B
01 0 0 0 0
B4 DC DB
11 1 1 1 1
10 0 0 1 1
B4 = DC + DB
Logic Diagram
Fig. 2.38: Binary to BCD converter
2.18.2 BCD to Excess 3 Converter
Excess-3 code is a modified form of a BCD number. The Excess-3 code can be derived from the
natural BCD code by adding 3 to each coded number. The truth table for BCD to excess 3 code
converter is shown in Table 2.7.
2.34 Digital Principles and System Design
TABLE 2.7 : Truth Table for BCD to Excess 3 converter
Decimal B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
K-map Simplification
B1B0 For E3 B1B0 For E2
00 01 11 10
B3B2 00 01 11 10 B3B2
00 0 0 0 0 00 0 1 1 1
01 0 1 1 1 01 1 0 0 0
11 X X X X 11 X X X X
10 1 1 X X 10 0 1 X X
E3 B3 B2 B0 B1 E2 B2 B1 B 0 B 2 B0 B1
For E1 For E0
B1B0 B1B0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 1 0 1 0 00 1 0 0 1
01 1 0 1 0 01 1 0 0 1
11 X X X X 11 X X X X
10 1 0 X X 10 1 0 X X
E1 B1 B 0 B1 B0 B1 B0 E0 B 0 E3 B3 B2 B0 B1
E2 B2 B1 B 0 B2 B0 B1
E1 B1 B0
E0 B 0
Combinational Logic 2.35
BCD code BCD code
B3 B2 B1 B0
Excess-3 code
E0
E1
E2
E3
Fig. 2.39: BCD to Excess-3 code converter
2.18.3 Binary to Gray Code Converter
The Gray code is often used in digital systems because it has the advantage that only one bit in the
numerical representation changes between successive numbers. Table 2.8 shows decimal and Binary
codes and corresponding Gray code.
TABLE 2.8
Binary code Gray code
Decimal
D C B A G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
2.36 Digital Principles and System Design
K-map Simplification
For G0 For G1
BA BA
DC 00 01 11 10 DC 00 01 11 10
00 0 1 0 1 00 0 0 1 1
01 0 1 0 1 01 1 1 0 0
11 0 1 0 1 11 1 1 0 0
10 0 1 0 1 10 0 0 1 1
G0 BA B A G1 C B CB
BA CB
For G2 For G3
BA BA
DC 00 01 11 10 00 01 11 10
DC
00 0 0 0 0 00 0 0 0 0
01 1 1 1 1 01 0 0 0 0
11 0 0 0 0 11 1 1 1 1
10 1 1 1 1 10 1 1 1 1
G2 DC DC D C G3=D G0 B A
Logic Diagram G1 C B
G2 D C
Binary Code Gray Code
G3 D
A G0
B G1
C G2
D G3
Fig. 2.40 : Binary to gray code converter
Combinational Logic 2.37
2.18.4 Gray Code to Binary Code Converter
Table 2.9 shows the truth table for gray code to binary code converter.
TABLE 2.9 : Truth Table for gray code to binary code converter
Gray code Binary code
G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-map Simplification
For A For B
G1G0
G1G0
G3 G2 00 01 11 10
G3 G2 00 01 11 10
00 0 1 0 1 00 0 0 1 1
01 1 0 1 0 01 1 1 0 0
11 0 1 0 1 11 0 0 1 1
10 1 0 1 0 10 1 1 0 0
2.38 Digital Principles and System Design
A G 3G2 G3 G 2 G1 G 0 G 3 G 2 G3G2 G1G0 G 3G2 G3 G 2 G1G0 G3 G 2 G3G2 G1 G 0
G3 G2 G1 G 0 G3 G2 G1G0 G3 G2 G1G0 G3 G2 G1 G 0
G3 G2 G1 G 0 G1G0 G3 G2 G1G0 G1 G 0
G3 G2 G2 G0 G3 G2 G1 G0
G3 G2 G1 G0 G3 G2 G1 G0
G3 G2 G1 G0 A G3 G2 G1 G0
B G 3 G 2 G3G2 G1 G 3G2 G3 G 2 G1 B G3 G2 G1
G3 G2 G1 G3 G2 G1 C G3 G2
D G3
G3 G2 G1 G3 G2 G1 G3 G2 G1
For C For D
G1 G0 G1G0
G3 G2 00 01 11 10 G3 G2 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 1 1 1 1 01 0 0 0 0
11 0 0 0 0 11 1 1 1 1
10 1 1 1 1 10 1 1 1 1
C G 3G2 G3 G 2 G3 G2 D G3
Logic Diagram
Gray Code Binary Code
G0
A
G1
B
G2
C
G3 D
Fig. 2.41 : Gray code to binary code converter
Combinational Logic 2.39
2.19 DECODERS
Decoder is a digital device that converts coded information into another code or non-coded form.
It is a multi-input multi-output logic circuit. The number of outputs is greater than the number of
inputs (n : 2n). The encoded information is presented as ‘n’ inputs producing 2n possible outputs as
shown in Figure 2.42.
If the number of inputs and outputs are equal in a digital system, then it can be called as code
converters. (BCD to XS-3 code, Binary to BCD code, Gray to Binary Code converters, etc.)
n DECODER 2n
data outputs
inputs
Fig. 2.42: Decoder
2.19.1 Binary Decoder
A binary decoder has ‘n’ bit binary input and a one activated output out of 2n outputs. A binary
decoder is used when it is necessary to activate exactly one of 2n outputs based on an n-bit input value.
Figure 2.43shows 2 to 4 line decoder. 2 inputs are decoded into 4 outputs, each output representing
one of the minterms of the 2 input variables. The Table 2.10 shows the truth table for 2 to 4 line
decoder.
Fig. 2.43: 2 to 4 line decoder
2.40 Digital Principles and System Design
TABLE 2.10: Truth Table
Inputs Outputs
X Y D0D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2.19.2 3-to-8 line Decoder
A 3-to-8 line decoder has three inputs (x, y, z) and eight outputs (D0D7). Based on the 3 inputs
one of the 8 outputs is selected.
The logic diagram of 3-to-8 line decoder is shown in Figure 2.44 and the truth table of this
decoder is given in Table 2.11. The three inputs are decoded into eight outputs, each output representing
one of the minterms of the 3-input variables. This decoder is used for binary-to-octal conversion. The
input variables may represent a binary number and the outputs will represent the eight digits in the
octal number system. The output variables are mutually exclusive because only one output can be
equal to 1 at any one time. The output line whose value is equal to 1 represents the minterm equivalent
of the binary number presently available in the input lines.
TABLE 2.11: Truth Table
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Combinational Logic 2.41
Fig. 2.44: 3-to-8 line decoder
2.19.3 1-of-16 Decoder
The 1-of-16 decoder is shown in Figure 2.45. The 4 inputs ABCD are the control bits. It has 16
output lines and only 1 of the 16 output lines is high. For instance, when ABCD = 0001, only the Y1
AND gate has all inputs high, therefore only the Y1 output is high. If ABCD = 0100, only the Y4 AND
gate has all input high, therefore only the Y4 output goes high. This circuit is also known as 4-to-16
line decoder.
2.42 Digital Principles and System Design
Fig. 2.45: 1-of-16 [4-to-16 line] Decoder
2.19.4 BCD-to-Decimal Decoder
The Figure 2.46shows a 1-of-10-decoder because only one of the 10 output lines is high. For
example, when ABCD = 0011, only the Y3 AND gate has all high inputs, therefore only the Y3 output
is high. If ABCD changes to 1000, only the Y8 AND gate has all high inputs, therefore only the Y8
output goes high. The ABCD possibilities are from 0000 to 1001 (9). The high output always equals
the decimal equivalent of the input BCD digit. For this reason, this circuit is also called a BCD-to-
Decimal converter.
Combinational Logic 2.43
Fig. 2.46: BCD-to-Decimal Decoder
2.20 ENCODERS
An encoder is a digital circuit that performs the inverse operation of a decoder. It is a combinational
logic circuit, that output logic circuit, that output lines generate the binary code corresponding to the
input value.
It has 2n input lines and ‘n’ output lines. The octal-to-binary encoder has 8(23) inputs, one for each
of the octal digits and three (n = 3) outputs that generate the corresponding binary number. It is
assumed that only one input has a value of 1 at any given time; otherwise the circuit has no meaning.
2.20.1 Octal-to-Binary encoder
The octal-to-binary encoder truth table is given in Table 2.12. The encoder can be implemented
with OR gates whose inputs are determined directly from the truth table. Output z is equal to 1 when
the input octal digit is 1 or 3 or 5 or 7. Output y is 1 for octal digits 2, 3, 6 or 7 and output x is 1 for
digits 4, 5, 6 or 7. These conditions can be expressed by the following output Boolean functions:
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
2.44 Digital Principles and System Design
The octal-to-binary encoder is implemented for these Boolean functions using OR gates. The
octal-to-binary encoder is shown in Figure 2.47.
TABLE 2.12 : Truth Table
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Fig. 2.47: Octal-to-Binary Encoder
2.20.2 Priority Encoder
A priority encoder is an encoder circuit that includes the priority function. The operation of the priority
encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence. The truth table of a 4 input priority encoder is given in Table 2.13.
Input D3 has the highest priority. When D3 = 1, the output XY = 11. D2 has the next priority level.
If D2 = 1, D3 = 0, the output xy = 10, regardless of the values of the other two lower priority inputs.
The output for D1 is generated only if higher-priority inputs are 0 and so on down the priority level.
Combinational Logic 2.45
The output V (Valid-output indicator) = 1 only when one or more inputs are equal to 1. V = 0, if all
inputs are 0 and the other two outputs (X and Y) of the circuit are not used.
TABLE 2.13 : Truth Table of a Priority Encodes
Inputs Outputs
D0 D1 D2 D3 X Y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
Although the Table 2.13 has only five rows, when each don’t care condition is replaced first by
0 and then by 1, we obtain all 16 possible input combinations. For example the third row in the table
with X100 represents minterms 0100 and 1100. The don’t care condition is replaced by 0 and 1 as
shown in Table 2.14.
TABLE 2.14: Modified Truth Table
Inputs Outputs
D0 D1 D2 D3 X Y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
0 1 0 0
1 1 0 0 0 1 1
0 0 1 0
0 1 1 0
1 0 1 0 1 0 1
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1 1 1 1
1 0 1 1
1 1 0 1
1 1 1 1
2.46 Digital Principles and System Design
For x For y
D2D3 D2D3
00 01 11 10 00 01 11 10
D2D1 D0D1
00 X 1 1 1 00 X 1 1 0
01 0 1 1 1 01 1 1 1 0
11 0 1 1 1 11 1 1 1 0
10 0 1 1 1 10 0 1 1 0
x = D2 + D3 y = D3 + D1 D 2
For V
D2 D3
D0 D1 00 01 11 10
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1
V = D0 + D1 + D2 + D3
The simplified Boolean expressions for the priority encoder are obtained from the K-maps as
follows:
x = D2 + D3
y = D3 + D1 D 2
v = D0 + D1 + D2 + D3
The priority encoder is implemented in Figure 2.48 according to the above Boolean functions.
Combinational Logic 2.47
Fig. 2.48: 4 input priority encoder
2.21 MULTIPLEXERS
‘m’ control signals
Multiplex means “many into one”. A multiplexer is
a combinational circuit with many inputs but only one
output. By applying control signals, we can steer any
input to the output. It has ‘n’ input signals, ‘m’ control
signals and 1 output signal. Multiplexer is called as data ‘n’ input MUX 1 output
selector or because the output bit depends on the input signals signal
data bit that is selected. The block diagram of multiplexer
is shown in Figure 2.49.
Fig. 2.49
2.21.1 4-to-1 Line Multiplexer
A 4-to-1 line multiplexer has four (n) input lines, two (m) select lines and one output line. The
selection (control) lines decide the number of input lines. If the number of ‘n’ input lines is equal to
2m, then ‘m’ select lines are required to select one of the ‘n’ input lines.
The logic symbol of a 4-to-1 multiplexer is shown in Figure 2.50. If has 4 input lines (I0 to I3), two
select lines (S0, S1) and a single output line. The function table of 4-to-1 multiplexer is shown in Table
2.15.
2.48 Digital Principles and System Design
Fig. 2.50: Logic Symbol
TABLE 2.15 : Function Table
Select Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
1. Y = I0 iff S1 = 0 , S0 = 0
Y = I 0 S 1 S 0 I 0 11 I 0
2. Y = I1 iff S1 = 0, S0 = 1
Y = I1 S 1 S0 I1 , when S1S0 = 01
3. Y = I2 iff S1 = 1 , S0 = 0
Y = I 2 S1 S 0 I 2 when S1S0 = 10
4. Y = I3 iff S1 = S0 = 1
Y = I3S1S0 = I3 when S1S0 = 11
1
The final expression for the data output,
Y = I 0 S 1 S 0 I1 S 1S0 I 2 S1 S 0 I 3 S1S0
Using this expression, the 4-to-1 multiplexer can be implemented using gates as shown in
Figure 2.51.
Combinational Logic 2.49
Fig. 2.51: Logic Diagram of 4-to-1 Multiplexer
2.21.2 16-to-1 Multiplexer
The 16-to-1 multiplexer has 16 data input lines (D0D15), a single output line (Y) and 4 select lines
(A, B, C, D) to select one of the 16 input lines. The truth table for a 16-to-1 multiplexer is shown in
Table 2.16.
For example, when ABCD = 0000, the upper AND gate is enabled while all other AND gates are
disabled. Therefore data bit D0 is transmitted to the output.
Y = D0
If D0 = 0, Y = 0
D0 = 1, Y = 1 i.e., Y depends only on the value of D0
When ABCD = 1111, Y = D15.
Thus the control bits (A, B, C, D) determines which of the input data bits is transmitted to the output.
Figure 2.52 shows the logic diagram of 16-to-1 multiplexer.
TABLE 2.16 : Truth Table of 16-to-1 MUX
Enable Select Inputs Output
E S3 S2 S1 S0 Y
0 0 0 0 0 D0
0 0 0 0 1 D1
0 0 0 1 0 D2
0 0 0 1 1 D3
0 0 1 0 0 D4
0 0 1 0 1 D5
2.50 Digital Principles and System Design
0 0 1 1 0 D6
0 0 1 1 1 D7
0 1 0 0 0 D8
0 1 0 0 1 D9
0 1 0 1 0 D10
0 1 0 1 1 D11
0 1 1 0 0 D12
0 1 1 0 1 D13
0 1 1 1 0 D14
0 1 1 1 1 D15
1 X X X X 1
Fig. 2.52: Logic diagram of 16-to-1 multiplexer
Combinational Logic 2.51
We can implement a 16-to-1 multiplexer using two 8-to-1 multiplexer as shown in Figure 2.53.
To select one of the 16 inputs, 4 select lines (S3S2S1S0) are required. Among the 4 select lines
(S2 S1S0) are connected with 3 select inputs of both 4 to 1 multiplexers. S3 is connected directly to
E (Enable) input of MUX1 and it is connected through an NOT gate to E input of MUX2. Therefore,
when S3 = 0, MUX1 is selected and the inputs (D0 to D7) are multiplexed to the output and MUX2 is
disabled. When S3 = 1, the MUX 1 is disabled while MUX 2 is enabled and the inputs (D8 to D15) are
multiplexed to the output.
Fig. 2.53: 16-to-1 Multiplexer using IC 74151
2.22 DEMULTIPLEXERS
Demultiplex means “one into many”. A demultiplexer is a combinational logic circuit with one
input and many outputs. By applying control signal, we can steer the input signal to one of the output
lines. Figure 2.54 shows the block diagram of demultiplexer. It has 1 input signal, ‘m’ control signals
and ‘n’ output signals.
2.52 Digital Principles and System Design
‘m’ control signals
1 input ‘n’ output
DEMUX
signals signal
Fig. 2.54: Block diagram of demultiplexer
The select inputs (Control Signals) determine to which output the data input will be connected.
As the serial data is changed to parallel data, i.e., the input caused to appear on one of the ‘n’ output
lines, the demultiplexer is called data distributor or serial-to-parallel converter.
2.22.1 1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), 4 outputs (Y0Y1Y2Y3) and two select lines (S1S0).
The truth table of the 1 to 4 demultiplexer is shown in Table 2.17.
When S1S0 = 00, the data input is connected to output Y0.
Y0 S 1 S 0 D D
When S1S0 = 01, the data input is connected to output Y1
Y1 S 1S0 D D
When S1S0 = 10 , the data input is connected to output Y2
Y2 S1 S 0 D D
When S1S0 = 11, the data input is connected to output Y3
Y3 = S1S0D = D
Using these expressions, a 1-to-4 demultiplexer is implemented using AND gates as shown in
Figure 2.55.
TABLE 2.17 : Truth Table
Data Input Select Inputs Outputs
D S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0
Combinational Logic 2.53
(a) Logic Symbol
(b) Logic Diagram
Fig. 2.55: 1 to 4 multiplexer
2.23 IMPLEMENTATION OF COMBINATIONAL LOGIC USING
MULTIPLEXER
Procedure
1. List the inputs of the multiplexer.
2. List under them all the given minterms in two rows. The first half of the minterms associated
with A and the second half with the A.
3. The given function is implemented by circling the minterms of the function and applying the
following rules to find the values for the inputs of the multiplexer:
(i) If the two minterms in a column are not circled, apply 0 to the corresponding multiplexer
input.
(ii) If the two minterms in a column are circled, apply 1 to the corresponding multiplexer
input.
(iii) If the bottom minterm is circled and the top is not circled, apply A to the corresponding
multiplexer input.
(iv) If the top minterm is circled and the bottom is not circled, apply A to the corresponding
multiplexer input.
2.54 Digital Principles and System Design
4. Draw the multiplexer implementation diagram.
Example 2.4: Implement the following function using a multiplexer.
F(A, B, C) = (1, 3, 5, 6)
Solution
Variables, n = 3 (A, B, C)
Select lines = n 1 = 2 (S1, S0)
2n 1 to 1 MUX. i.e., 22 to 1 4 to 1 MUX
Input lines = 2n 1 = 22 = 4 (I0, I1, I2 , I3)
Implementation Table
I0 I1 I2 I3
A 0 1 2 3
A 4 5 6 7
0 1 A A
I0 = 0, I1 = 1, I2 = A, I3 = A
Multiplexer Implementation
Fig. 2.56: 4 to 1 multiplexer
Combinational Logic 2.55
Example 2.5: Implement the following function with a multiplexer.
F(A, B, C, D) = (0, 1, 3, 4, 8, 9, 15)
Solution: Variables, n = 4 (A, B, C, D)
Select lines, n 1 = 3 (S2, S1, S0)
Input lines, 2n 1 = 23 = 8 (I0I7)
2n 1 to 1 MUX = 23 to 1 8 to 1 MUX
Use B, C and D variables as selection lines.
Implementation Table
I0 I1 I2 I3 I4 I5 I6 I7
A 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 A A 0 0 A
Multiplexer Implementation
Fig. 2.57: 8 to 1 multiplexer
2.56 Digital Principles and System Design
Example 2.6: Implement the following Boolean function using 8 : 1 MUX.
F A, B,C, D ABD ACD BCD ACD (Dec. 2010)
Solution:
F A, B,C, D ABD ACD BCD ACD
ABD C C ACD B B BCD A A AD CD
ABDC ABDC ACDB ACDB BCDA BCDA ABD ABD CDA CDA
ABDC ABDC ABCD ABCD ABCD ABCD ABCD ABCD
ABCD ABCD ABCD ABCD ABCD ABCD
=[6, 4, 15, 11, 11, 3, 7, 5, 3, 1, 13, 9, 5, 1]
= [1, 3, 4, 5, 6, 7, 9, 11, 13, 15]
Implement table: [Use B, C, D as selection live]
I0 I0 I0 I0 I0 I0 I0 I0
0 1 2 3 4 5 6 7
A
A 8 9 10 11 12 13 14 15
0 1 0 1 A 1 A 1
MUX Implementation
0 I0
1
I1
I2
I3
y=F
A I4 8 to 1
I5 MUX
I6
I7
S2 S1 S0
B
C
D
Combinational Logic
2.57 Example 2.7: Design a combinational logic using a suitable multiplexer to realize the
following Boolean expression. A D B C B C D .
CD CD CD CD
CD
AB 00 01 11 10
AB 00
0 1 3 2
01 1
AB
4 5 7 6
11 1
AB
12 13 15 14
10 1
AB 8 9 11 10
F(A, B, C, D) = (4, 10, 12)
Variables n = 4(A, B, C, D)
Select lines n - 1 = 4 - 1 = 3 (S2, S1, S0)
Input lines, 2n-1 = 23 = 8 (I0 - I7)
2n-1 to 1MUX = 23 to 1 = 8 to 1 MUX
Use B, C, D variables as selection lines.
Implenetation Table:
I0 I0 I0 I0 I0 I0 I0 I0
0 1 2 3 4 5 6 7
A
A 8 9 10 11 12 13 14 15
0 0 A 0 1 0 0 0
2.58 Digital Principles and System Design
Multiplexer Implementation
0 I0
I1
I2 8 to 1
A
I3 MUX F
y
1 I4
I5
I6
I7
S2 S1 S0
B
C
D
Example 2.8: Implement F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15) using 8 1 multiplexer.
Solution
Implenetation Table:
D0 D1 D2 D3 D4 D5 D6 D0
0 1 2 3 4 5 6 7
A
A 8 9 10 11 12 13 14 15
0 A 0 1 1 D D D
Multiplexer Implementation
0 D0
D1
D2
D3 8 to 1
1 y=F
D4 MUX
D5
D6
A D7
S2 S1 S0
B
C
D
Combinational Logic 2.59
HARDWARE DESCRIPTION LANGUAGE
2.24 INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE (HDL)
The complexity of digital designs has increased drastically with the advent of the smaller geometry
semi-conductor process technology. This increase has made enormous demands on the industry, giving
rise to Hardware Description Languages (HDL) which responded with the HDL-based design process,
methodology and design tools. HDL not only manages the increased complexity, but it also allows a
shorter design cycle.
HDL is a powerful language with numerous language constructs that are capable of describing
very complex behaviour. The characteristics of an ideal HDL are:
Supports multiple level of abstraction (gates to systems)
Concise
Describes functional blocks and their interconnections
Wall suited for synthesis and verification
2.24.1 Types of HDLS
There are manyd ifferent systems for modeling and simulating hardware.
Verilog
VHDL
Super log
System C
L-language and M-language (Mentor)
Aida (IBM/HaL)
and many others
2.24.2 Major HDLS
Two major HDLS are Verilog and VHDL. These both are programming languages. They are text-
based, easier to create a design over schematic entry/capture. VHDL and Verilog both enjoy widespread
use and share the logic synthesis market roughly 50/50.
Verilog has its synthetic roots in ‘C’ and is in some respects an easier language to learna nd use,
which VHDL is more like ADA (U.S. Department of DecenseSponsored Software programming
language) and hase more features that support large project development.
2.60 Digital Principles and System Design
2.24.3 Verilog HDL
Verilog HDL is invented by Philip Moorbyin in 1984 at Gate way Design Automation. It enables
specification of a digital system at a rang eof levels of abstraction: switches, gates, RTL and higher. It was
initially developed in conjunction with the Verilog simulator. The verilog-based synthesis tool is
introduced by Synopsys in 1987. In 1989, Gateway Design Automation is bought by Cadence Design
Systems. Verilog was placed in public domain as Open Verilog International (OVI), IEEE 1364.
2.24.4 VHDL
VHDL is an international IEEE standard specification language (IEEE 1076-1993) for describing
digital hardware used by industry worldwide. VHDL stands for “VHSIC Hardware Description
Language”. VHSIC stands for “Very High Speed Integrated Circuit”. VHDL enables hardware modeling
from the gat eto system level. It provides a mechanism for digital design and reversable design
documentation.
In the mid 1980s, the U.S. Department of Defence (DOD) and the IEEE sponsored the
development of VHDL.
In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to
develop VHDL.
In August 1985, the final version of the language under government contract was released:
VHDL Version 7.2.
In December 1987, VHDL became IEEE standard 1076-1987 and in 1988 an ANSI standard.
In September 1993, VHDL was restandardized to clarify and enhance the language.
VHDL has been accepted as a Draft International Standard by the IEC.
2.24.5 Features of VHDL
Designs may be decomposed hierarchically.
Behavioural specifications can use either an algorithm or an actual hardware structure to define
an element’s operation.
Each design element has both a well-defined interface (for connecting it to other elements) and
a precise behavioural specification (for simulating it).
Concurrency, timing and clocking can all be modeled.
The logical operation and timing behaviour of a design can be simulated.
VHDL handles asynchronous and synchronous sequential circuit structures.
Thus VHDL started out as a documentation and modeling language, allowing the behaviour of
digital-system designs to be precisely specified and simulated.
Combinational Logic 2.61
2.24.6 Advantages of HDLS
The VHDL and Verilog have the following advantages:
They are IEEE standards.
They are supports from government and the industry.
The HDL texts provide high portability among platforms and design tools.
They have the flexibility to model very complex systems down to very primitive circuits.
They facilitate design reuse.
They allow the technology and foundry independence.
The documentations can be built-in.
Combining with the synthesis, a new design methodology is emerged which reduces design
cycle and costs.
2.25 HDL BASED DESIGN FLOW
The several steps in a HDL based design process or design flow is shown in Figure 2.58.
Fig. 2.58: HDL based design flow
2.62 Digital Principles and System Design
2.25.1 Block diagram
A block diagram is an informal pictorial description of the system’s major functional modules and
their basic interconnections. A block diagram shows the inputs, outputs, functional modules, internal
data paths and important control signals of a system. Large logic designs, like software programs are
usually hierarchical and VHDL gives a good framework for defining modules and their interfaces.
2.25.2 Coding
The next step is the actual writing of VHDL code for modules, their interfaces and their internal
details. Since VHDL is a text based language, VHDL text editor is used for this part of the job. VHDL
text editors include features like automatic highlighting of VHDL keywords, automatic indenting,
built-in templates for frequently used program structures and built-in syntax checking and one- click
access to the compiler.
2.25.3 Compiler
A VHDL compiler analyzes code for syntax errors and also checks it for compatibility with other
modules on which it relies. It also creates the internal information that is needed for a simulator to
process the design.
2.25.4 Simulator
A VHDL simulator allows to define and apply inputs to the design and to observe its outputs,
without even having to build the physical circuit.
2.25.5 Verification
Actually, simulation is just one piece of a larger step called verification. It is satisfying to watch
the simulated circuit produce simulated outputs, but the purpose of simulation is larger-it is to verify
that the circuit works as desired. The two dimensions to verification are:
Functional Verification
Timing Verification.
In functional verification, we study the circuit’s logical operation independent of timing
considerations: gate delays and other timing parameters are considered to be zero.
In timing vertification, we study the circuit’s operation including estimated delays and we verify
that the setup, hold and other timing requirements for sequential devices like flip-flops are met.
2.25.6 Synthesis
Synthesis means converting the VHDL description into a set of primitives or components that can
be assembled in the target technology. For example, with programmable logic devices (PLD) the
synthesis tool may generate two-level sum- of-products equations. With application-specific ICs(ASIC),
it may generate a list of gates and a netlist that specifies how they should be interconnected.
Combinational Logic 2.63
The designer may help the synthesis tool by specifying certain technology- specific constraints, such
as maximum number of logic levels or the strength of logic buffers to use.
2.25.7 Fitting
A fitting tool or fitter maps the synthesized primitives or components onto available device
resources. For a PLD, this may mean assigning equations to available AND-OR elements. For an
ASIC, this may mean laying down individual gates in a pattern and finding ways to connect them
within the physical constraints of the ASIC die; this is called the place and routes process.
2.26 VHDL BUILDING BLOCKS
2.26.1 Entity
A VHDL entity is a declaration of a module’s inputs and outputs. All designs are expressed in
terms of entities. The uppermost level of the design is the top- level entity. If the design is hierarchical,
then the top-level description will have lower-level descriptions contained in it. These lower-level
descriptions will be lower-level entities contained in the top-level entity description.
A VHDL entity specifies the name of the entity, the ports of the entity and entity-related information.
The syntax of a VHDL entity declaration is,
entity entity-name is
port (signal-names : mode signal-type;
signal-names : mode signal-type;
.....
signal-names : mode signal-type);
end entity-name;
entity-name: A user-selected identifier to name the entity.
signal-names: A comma-separated list of one or more user-selected identifiers to name external-
interface signals.
mode: Modes (in, out, inout, buffer) are specifying the signal direction.
signal type: A built-in or user-defined signal type (bit, integer, real, etc.)
An entity example is,
entity mux is
port (a , b , c , d : in bit ;
S0 , S1 : in bit ;
x , : out bit) ;
end mux ;
2.64 Digital Principles and System Design
The entity describes the interface to the outside world. It specifies the number of parts, the direction
of the ports and the types of the ports.
The name of the entity is mux. The entity has 7 ports in the port clause. 6 ports are of mode ‘in’
and one port is of mode ‘out’. The four data input ports (a, b, c, d) are of type ‘bit’. The two multiplexer
select inputs. (S0, S1) are also of type ‘bit’. The output port is of type ‘bit’.
2.26.2 Architecture
All entities that can be simulated have an architecture description. The architecture describes the
behaviour of the entity. A single entity can have multiple architectures. One architecture might be
behavioural while another might be a structural description of the design. The syntax of a VHDL
architecture definition is,
architecture architecturename of entityname is
type declarations
signal declarations
constant declarations
function definitions
procedures definitions
begin
concurrent-statement
....
concurrent-statement
end architecture-name ;
An architecture for the counter device is,
architecture data flow of mux is
signal select : integer;
begin
select < = 0 WHEN S0 = 0 AND S1 = 0 ELSE
1 WHEN S0 = 1 AND S1 = 0 ELSE
2 WHEN S0 = 0 AND S1 = 1 ELSE
3;
condition
x < = a AFTER 0.5 NS WHEN select = 0 ELSE
b AFTER 0.5 NS WHEN select = 1 ELSE
c AFTER 0.5 NS WHEN select = 2 ELSE
d AFTER 0.5 NS ;
end data flow;
Combinational Logic 2.65
In this example,
architecture name = dataflow
entity name = mux
The architecture ‘dataflow’ describes the underlying functionality of the entity ‘mux’ and contains
the statements that model the behaviour of the entity.
2.26.3 Configuration
A configuration statement is used to bind a component instance to an entity- architecture pair. A
configuration can be considered like a parts list for a design. It describes which behaviour to be used
for each entity, much like a parts list that describes which part to use for each part in the design. The
syntax of configuration declaration is,
Configuration configuration_name of entity_name is
for architecture_name
for instance_name : entity_name use entity
library_name . entity_name
(architecture_name) ;
end for;
for instance_name : entity_name use configuration
library_name . configuration_name ;
end for;
end for;
end configuration_name ;
2.26.4 Package
A VHDL package is a file containing definitions of objects that can be used in other programs.
The kind of objects that can be put into a package include signal, type, constant, function, procedure
and component declarations.
The primary purpose of a package is to encapsulate elements that can be shared among two or
more design units. A package is a common storage area used to hold data to be shared among a
number of entities. Declaring data inside of a package allows the data to be referenced by other
entities; thus the data can be shared.
2.66 Digital Principles and System Design
A package consits of two parts:
package declaration
package body.
(a) Package Declaration
It defines the interface for the package, much the same way that the entity defines the interface for
a model. The package declaration section can contain the following declarations:
Subprogram declaration
Type, subtype declaration
File declaration
Alias declaration
Constant declaration
Deferred constant declaration
Component declaration
Attribute declaration
Signal declaration
Use clause declaration
(b) Package Body
The main purpose of the package body is to define the values for deferred constants and specify
the subprogram bodies for any subprogram declarations from the package declaration. The package
body contain the following declarations:
Subprogram declaration
Type, subtype declaration
Constant declaration
File declaration
Alias declaration
Subprogram body
Use clause
Syntax of a VHDL Package Declaration
Package package-name is
— declare some stuff
end package;
Combinational Logic 2.67
Syntax of a VHDL Package Body:
package body package_name is
— put subprogram bodies here
end package_name ;
2.26.5 Driver
It is a source on a singal. If a signal is driven by two sources, then when both sources are active,
the signal will have two drivers. VHDL has a unique way of handling multiply driven signals. Multiply
driven signals are very useful for modeling a data bus, a bi-directional bus, and so on. A multiply
driven signal has many drivers. The values of all of the drivers are resolved together to create a single
value for the signal.
Drivers are created by signal assignment statements.
Consider the following architecture:
architecture test of test is
begin
a < = b after 20 ns;
a < = c after 30 ns;
end test ;
Signal ‘a’ is being driven from two sources, ‘b’ and ‘c’. Each concurrent signal assignment statement
creates a driver for signal ‘a’. The first stagement creates a driver that contains the value of signal ‘b’
delayed by 20 nanoseconds. The second statement creates a driver that contains the value of signal
‘C’ delayed by 30 nanoseconds.
2.26.6 Attribute
An attribute is data that are attached to VHDL objects or predefined data about VHDL objects.
Predefined attributes are the data that can be obtained from blocks, signals and types or subtypes. The
data obtained falls into one of the following categories:
Value kind A simple value is returned.
Function kind A function call is performed to return a value.
Signal kind A new signal is created whose value is derived from another signal.
Type kind A type mark is returned.
Range kind A range value is returned.
VHDL user defined attributes are a mechanism for attaching data to VHDL objects. The data
2.68 Digital Principles and System Design
attached can be used during simulation. Data such as the disk file name of the model, loading
information, driving capability, resistance, capacitance, physical location and So on can be attached
to objects. The user-defined attributes can be assigned to the following list of objects:
Entity Type and subtype
Architecture Constant
Configuration Signal
Procedure Variable
Function Component
Package Label
Table 2.18 lists predefined attributes with examples.
TABLE 2.18 : Predefined Attributes
Attribute Explanation Examples
T’BASE Returns the base type of NATURAL’BASE returns
datatype it is attached to INTEGER
T’LEFT Returns left value specified INTEGER’LEFT is-2147483647
in type declaration BIT’LEFT is ‘0’
T’RIGHT Returns right value INTEGER’ RIGHT is 2147483647
specified in type declaration BIT’RIGHT is ‘1’
T’HIGH Returns largest value TYPE bits is 255 downto 0
specified in declaration bits’HIGH is 255
T’LOW Returns smallest value TYPE bits is 255 downto 0
specified in declaration bits’LOW is 0
T’POS(X) Returns position number of TYPE color IS (red, green,
argument in type (first) blue, orange);
position is 0) color’POS (green) is 1
T’VAL(X) Returns value in type at TYPE color IS (red, green,
specified position number blue, orange);
color’VAL (2) is blue
T’SUCC(X) Returns the successor TYPE color is (red,
to the value passed in green, blue, orange)
color’SUCC (green) is
blue
T’PRED (X) Returns the predecessor to TYPE color IS (red, green,
the value passed in blue, orange); color’
PRED (blue) is green
Combinational Logic 2.69
Attribute Explanation Examples
T’LEFTOP(X) Returns the value to the left TYPE color IS (red, green,
of the value passed in blue, orange);
color’LEFTOF (green) is red
T’RIGHTOP(X) Returns the value to the TYPE color IS (red, green,
right of the value passed in blue, orange);
color’RIGHTOP (blue) is
orange
A’LEFT (N) Returns left array bound a_type’LEFT(1) is a 0
of selected index range a_type’LEFT (2) is 7
A’RIGHT(N) Returns right array bound a_type’RIGHT (1) is 3
of selected index range a_type’ RIGHT (2) is 0
A’RIGHT (N) Returns largest array a_type’HIGH (1) is 3
bound value of selected a_type’HIGH (2) is 7
index range
A’LOW (N) Returns smallest array a_type LOW(1) is 0
bound value of selected a_type’LOW(2) is 0
index range
A’RANGE (N) Returns selected index a_type‘RANGE (1) is 0
TO 3
a_ type’RANGE (2) is 7
DOWNTO 0
A’REVERSE_
RANGE (N) Returns selected index a_type’REVERSE_Range (1)
range reversed is 3
DOWNTO 0
a_type’REVERSE_RANGE (2)
is 0 TO 7
A’LENGTH (N) Returns size of selected a_type’LENGTH (1) is 4
index range a_type’LENGTH (2) is 8
S’DELAYED (T) Creates a new signal clock’DELAYED (10 ns)
delayed by T
S’QUIET (T) Creates a new signal that reset’QUIET (5 ns)
is true when signal S has had
no transactions for time T;
otherwise, false
2.70 Digital Principles and System Design
Attribute Explanation Examples
S’STABLE (T) Creates a new signal clock’STABLE (1 ns)
that is true when signal
S has no events
for time T; otherwise, false
S’TRANSA- Creates a signal of type BIT load TRANSACTION
CTION that toggles for every
transaction on signal S
S’EVENT Returns true when an clock’EVENT
event has occurred for signal
S is delta
S’ACTIVE Returns true when a load’ACTIVE
transaction has occurred for
signal S is delta
S’LAST_EVENT Returns the elapsed time data’LAST_EVENT
since the last eventon signal S
S’LAST_ACTIVE Returns the elapsed time since clock ‘ Last_Active
the last transaction on signal S
S’LAST_VALUE Returns the previously data’LAST_VALUE
assigned value of signal S
2.26.7 Generic
A generic is a general mechanism that passes information to an entity. For instance, if an entity is
a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into
the entity with generics. The syntax of a VHDL generic declaration within an entity declaration is,
entity entity-name is
generic (constant-names : constant-type ;
.....
constant-names : constant-type);
Port (signal-names : mode signal-type ;
.....
signal-names : mode signal-type) ;
end entity-name;
Combinational Logic 2.71
The following is an example of an entity for an AND gate that has 3 generics associated with it
entity and is
generic (rise, fall : time; load : integer);
port (a , b : in bit;
c : out bit);
end and
This entity allows to pass in a values for the rise and fall delays, as well as the loading device that
has on its output.
2.26.8 Process
A process is a collection of “sequential” statements that executes in parallel with other concurrent
statements and other processes. A VHDL process statement can be used anywhere that a concurrent
statement can be used. The syntax of a VHDL process statement is given below:
Process (signal-names , signal-name , . . . . . , signal-name)
type declarations
variable declarations
constant declarations
function definitions
procedure definitions
begin
sequential-statement
.....
sequential-statement
end process;
A process statement has a declaration section and a statement part. In the declaration section,
types, variables, constants, subprograms and so on can be cleared. The statement part contains only
sequential statements. Sequential statements consist of CASE statements, IF THEN ELSE statements,
LOOP statements and so on.
2.26.9 Bus
In VHDL, a bus is a special kind of signal that may have its drivers turned off.
2.72 Digital Principles and System Design
2.27 LIBRARY
A VHDL ‘library’ is a place where the VHDL compiler stores information about a particular
design project, including intermediate files that are used in the analysis, simulation and synthesis of
the design. The designer can specify the name of a library using a ‘library clause’ at the beginning of
the design file. For example, the IEEE library is specified as,
Library ieee ;
A design can use a package by including a ‘use clause’ at the beginning of the design file. For
example, to use all of the definitions in the IEEE standard 1164 package, we can specify as
use ieee . std_logic_1164 . all ;
where, ‘ieee’ is the name of a library
‘std_logic_1164’ is the file name, contains the desired definitions ‘all’ talls the compiler to use all
of the definitions in this file.
Instead of ‘all’, we can write the name of a particular object to use just its definition, for example,
use ieee . std_logic_1164 . std_ulogic
2.28 TYPES AND CONSTANTS
All signals, variables and constants in a VHDL program must have an associated “type”. The type
specifies the set or range of values that the object can take on and there is also typically a set of
operators (add, AND, etc.) associated with a given type.
SIGNAL, which represents interconnection wires that connect component instantiation ports
together.
VARIABLE, which is used for local storage of temporary data, visible only inside a process.
CONSTANT, which names specific values.
Signal signal-name : signal-type [: = initial-value];
Example:
Signal VCC : std_logic : = ‘1’ ;
Signal ground : std_logic : = ‘0’ ;
Variable variable-name : variable-type ;
Example:
Variable state : std_logic ;
Variable delay : time ;
Combinational Logic 2.73
Constant constant_name : type_name : = value ;
Example:
Constant PI : real : = 3.1414 ;
Constant Bus_SIZE : integer : = 32 ;
2.29 PREDEFINED TYPES
VHDL has a few predefined types listed in Table 2.19. Type ‘integer’ is defined as the range of
integers ( 231 + 1 through + 231 + 1)
Type ‘boolean’ has two values true and false
Built-in operators for the integer and boolean types are listed in Table 2.20.
TABLE 2.19 : Predefined Types
bit real
bit_vector severity_real
boolean string
character time
integer
TABLE 2.20: Predefined Operators
integer operators boolean operators
+ addition and AND
subtraction or OR
* multiplication nand NAND
/ division nor NOR
mod modulo division xor Exclusive OR
rem modulo remainder xnor Exclusive NOR
abs absolute value not Complement
** exponentiation
2.74 Digital Principles and System Design
2.30 USER-DEFINED TYPES
(i) type:
type type-name is (value-list) ;
Example:
type color is (red , yellow , blue) ;
type traffic_light_state is (reset , stop , wait , go) ;
(ii) subtype:
subtype declarations are used to define subsets of a type.
subtype subtype-name is type-name start to end ;
Example:
subtype fourval_logic is std_logic range ‘X’ to ‘Z’
subtype eightval is integer range 0 to 7 ;
(iii) std-logic type
The IEEE 1164 STD_LOGIC type is actually defined as a subtype of an unresolved type,
STD_ULOGIC. In VHDL, an unresolved type s used for any signal that may be driven in two or more
processes. The definition of VHDL STD_LOGIC type is given as,
type STD_ULOGIC is (‘U’ — Uninitialized
‘X’ — Forcing unknown
‘O’ — Forcing 0
‘I’ — Forcing 1
‘Z’ — High Impedance
‘W’ — Weak unknown
‘L’ — Weak 0
‘H’ — Weak 1
‘’ — Don’t care
);
subtype STD_LOGIC is resolved STD_ULOGIC;
(iv) Array type
An array is an ordered set of elements of the same type, where each element is selected by an
array.
Combinational Logic 2.75
Syntax
type type_name is array (start to end) of element_type ;
type type_name is array (start downto end) of element_type ;
Examples
type monthly_count is array (1 to 12) of integer;
type byte is array (7 downto 0) of STD_LOGIC;
2.31 SEQUENTIAL STATEMENTS
The sequential statements exist inside the boundaries of a process statement as well as in
subprograms. The sequential statements are:
IF
CASE
LOOP
EXIT
ASSERT
WAIT
(i) IF Statement
The IF statement starts with the keyword ‘IF’ and ends with the keywords ‘END IF’. There are
also two optional clauses: ELSIF and ELSE. The ESLIF (if-then- else) clause is repeatable-more than
one ELSIF clause is allowed; but the ELSE clause is optional and only one is allowed. The syntax of
IF statement is,
if statement : : =
if condition then
sequence of statements
[ elsif condition then
sequence of statements
[else
sequence of statements]
end if;
2.76 Digital Principles and System Design
Example
1. If (X < 10) then
a : = b;
end if;
2. If (day = Sunday) then
weekend : = TRUE;
elsif (day = Saturday) then
weekend : = TRUE;
else
weekday : = TRUE;
end if;
(ii) CASE Statement
The CASE statement is used whenever a single expression value can be used to select between a
number of actions. The syntax of a VHDL CASE statement is,
Case expression is
when choices = > sequential-statements
...
when choices = > sequential-statements
end case;
This statement evaluates the given expression, finds a matching value in one of the choices, and
executes the corresponding sequential-statements. One or more sequential statements can be written
for each set of choices. The choices may take the form of a single value or of multiple values separated
by vertical bars (1). Prime-number-detector architecture using CASE statement is shown below:
architecture prime 8_arch of prime is
begin
process(N)
begin
case CONV_INTEGER (N) is
when 1 = > F < = ‘1’ ;
when 2 = > F < = ‘1’ ;
when 3 | 5 | 7 | 11 | 13 = > F < = ‘1’ ;
when others = > F < = ‘0’;
end case;
end process;
end prime 8_arch;
Combinational Logic 2.77
(iii) Loop Statement
The Loop Statement is used whenever an operation needs to be repeated. Loop statements are
used when powerful iteration capability is needed to implement a model. Following is the syntax of
Loop statement:
loop
sequential-statement
.....
sequential-statement
end loop;
Example
for I in 1 to 10 loop
I_squared (I): <$E=> I * I;
end loop;
(iv) EXIT Statement
The EXIT statement allows to exit or jump out of a Loop Statement currently in execution. This
causes execution to halt at the location of the EXIT Statement. Execution continues at the statement
following the Loop Statement.
exit;
exit when a < = b ;
exit loop_label when X = Z;
(v) ASSERT Statement
The ASSERT statement checks the value of a boolean expression for true or false. If the value is
true, the statement does nothing. If the value is false, the ASSERT statement outputs a user-specified
text string to the standard output to the terminal
assert_statement : : =
assert condition
[REPORT expression]
[SEVERITY expression];
2.78 Digital Principles and System Design
(vi) WAIT Statement
WAIT statement is used to suspend a process for a specified time period. It is used for specifying
clock inputs to synthesis tools. The options available to the WAIT Statement are:
WAIT ON signal changes
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time
process
begin
XT < = ‘0’ ; YT < = ‘0’ ;
wait for 10 ns;
end process;
2.32 CHALLENGES in HDL
HDL is new and different from other traditional programming languages. Traditional programming
languages execute sequentially. In general, they are written so that a conclusion may be reached. HDL
models hardware which is concurrent in nature. It provides timing concepts and hardware implications.
Because of this, a person with both software and hardware background can learn HDL much easier
than a person who only knows either software or hardware.
A person who have more software than hardware experience find their challenges in the following
areas:
Process concurrency.
Sequential statements regions and Concurrent statements regions.
Hardware implication with schematic and simulation waveform.
Timing concepts.
Mixing other program languages with VHDL.
A person who have more hardware than software experience find their challenges in the following
areas:
VHDL syntax.
Writing VHDL to imply hardware.
Sequential statements regions and concurrent statements regions.
Taking advantages of VHDL constructs.
Software concepts such as subprograms, packages, libraries and configurations.
Combinational Logic 2.79
2.33 HDL FOR COMBINATIONAL CIRCUITS
2.33.1 3 input OR gate
The HDL program for 3 input OR gate is given below. The 3 inputs of the gate are X, Y, Z and one
output D. This program uses a simple concurrent assignment statement to describe the functionality
of the OR gate.
A
B D
C
Fig. 2.59: 3 input OR gate
library IEEE;
use IEEE . Std_logic_1164 . all;
entity or 3 1S
port (X, Y, Z : in STD_LOGIC;
D : out STD_LOGIC);
end or 3;
architecture Synth of or 3 is
begin
D < = X or Y or Z;
end Synth:
2.33.2 3 INPUT XOR GATE
A
Y
B
Fig. 2.60: 3 input XOR
3 input exclusive OR gate is shown in Figure 2.60.
2.80 Digital Principles and System Design
The VHDL program for a 3-input XOR gate is,
library IEEE;
use IEEE . Std_logic_1664 . all;
entity x or 1 is
port (
A, B, C : in STD_LOGIC;
Y : out STD_LOGIC
);
end xor 1;
architecture xor 1 of xor 1 is
begin
Y < = A xor B xor C;
end xor1;
2.33.3 2-input XNOR gate
A
Y
B
Fig. 2.61: 2-input XNOR
The VHDL program for 2-input XNOR gate using the built-in ‘xnor’ operator is given below. The
‘xnor’ operator can be overloaded to work with any types. In this example two STD_LOGIC type
values are XNOR’ed together to form the final result.
library IEEE;
use IEEE . STD_logic_1164 . all;
entity xnor2 is
generic (delay : time);
port (A, B : in STD_LOGIC;
Y : out STD_LOGIC);
end entity xnor2;
architecture better of xnor2 is
begin
Y < = A xnor B after delay;
end architecture better;
Combinational Logic 2.81
2.33.4 Decoder
There are several ways to approach the design of decoders in VHDL. The most primitive approach
would be two write a structural equivalent of a decoder logic circuit. Figure 2.62 shows the inputs
and outputs of 2-to-4 decoder and Figure 2.63 shows the gate-levelcircuit. The input code word I0, I1
represents an integer in the range 0 3 [00, 01, 10, 11]. The output code word Y3, Y2, Y1, Y0 has Yi
equal to 1 if and only if the input code word is the binary representation of ‘i’ and the enable input EN
is 1. If EN = 0, all of the outputs are 0. The VHDL structural program for 2-to-4 decoder is given
below. The components ‘and’ and ‘inv’ are assumed to already exist in the target technology.
I0 Y0
I1 2-to-4 Y1
Decoder
EN Y2
Y3
Fig. 2.62: 2 to 4 decoder
I0
Y0
Y1
I1
Y2
Y3
EN
Fig. 2.63: Decoder gate circuit
2.82 Digital Principles and System Design
library IEEE;
use IEEE . std_logic_1164 . all;
entity V2to4dec is
port (I0, I1, EN : in STD_LOGIC;
Y0, Y1, Y2, Y3 : ut STD_LOGIC);
end V2to4dec;
architecture V2to4dec_S of V2to4dec is
signal NOTIO, NOTI1 : STD_LOGIC;
component inv port (I: in STD_LOGIC; 0 : out STD_LOGIC); endcomponent;
component and port (I0, I1, I2 : in STD_LOGIC; 0 : out
STD_LOGIC); end component;
begin
u1 : inv port map (I0, NOTI0);
u2 : inv port map (I1, NOTI1);
u3 : and port map (NOTI0, NOTI1, EN, Y0);
u4 : and port map (I0, NOTI1, EN, Y1);
u5 : and port map (NOTI0, I1, EN, Y2);
u6 : and port map (I0, I1, EN, Y3);
end V2to4dec_S;
2.33.5 MULTIPLEXER
The logic symbol of 4-to-1 multiplexer is shown in Figure 2.64 and the logic diagram is shown in
Figure 2.65. The input lines are I0, I1, I2 and I3. The select lines are S0 and S1. The one output line is Y. The
truth table of 4-to-1 multiplexer is given in Table 3.10. The boolean function of 4-to-1 multiplexer is,
Y I 0 S1 S0 I1 S1S0 I 2 S1 S0 I 3 S1S0
Table: 3.10 Truth Table
Select Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
Fig. 2.64: Logic Symbol 1 1 I3
Combinational Logic 2.83
I0
I1
I2
Fig. 3.65: Logic diagram of 4-to-1 Multiplexer
The VHDL program for 4-to-1 multiplexer (8 bit) is given below:
Library IEEE;
use IEEE . Std_logic_1164 . all;
entity mux is
port (
S : in STD_LOGIC_VECTOR (1 downto 0); — Select inputs
I0, I1, I2, I3 : in STD_LOGIC_VECTOR (1 to 8); — Data bus
inputs
Y : out STD_LOGIC_VECTOR (1 to 8) — Data bus output
);
end mux;
architecture better of mux is
begin
with S select Y < =
I0 when “00”,
I1 when “01”,
I2 when “10”,
I3 when “11”,
(others ‘u’) when others; — 8 bit vector of ‘u’
end better;
2.84 Digital Principles and System Design
2.33.6 Parity Checker
We have already discussed that error-detecting codes use an extra bit, called a parity bit, to detect
errors in the transmission and storage of data. In an even parity code, the parity bit is chosen so that
the total number of 1 bit in a code word is even. The 74280 is a 9-bit parity generator/checker. Both
even and odd parity enable inputs and parity outputs are available for generating or checking parity
on 8 bits. Figure 2.66 shows the logic diagram for 9 bit parity generator/checker (74280).
I0
I1
I2
I3
I4
I5
I6
I7
I8
Fig. 2.66: 9-bit Parity Generator/Checker
The behavioural VHDL program for a 9-input parity checker is given below:
Library IEEE;
use IEEE . Std_logic_1164 . all;
entity parity is
port (I : in STD_LOGIC_VECTOR (1 to 9);
EVEN, ODD : out STD_LOGIC );
architecture parity 1 of parity is
begin
process (I)
variable p : STD_LOGIC;
begin
p : = I(1)
for j in 2 to 9 loop
if I(j) = ‘1’ then p : = not p ; end if;
end loop;
ODD < = p ;
EVEN < = not p ;
end process;
end parity 1;
Combinational Logic 2.85
2.33.7 Comparator
The 8 bit comparator receives two 9bit numbers A and B as inputs and the outputs are A = B and
A > B. The logic symbol of 8-bit comparator (74682) is shown in Figure 2.67. The top half of the
circuit checks the two 8 bit numbers for equality. The bottom half of the circuit compares the two
input 8 bit numbers and asserts A > B if [A7 A0] > [B7 B0 ] . The 74682 does not provide less than
(A < B) output. However, any desired condition, including and can be obtained as shown in
Figure 2.68.
VHDL has comparison operators for all of its built-in types. Equality (=) and inequality (/=)
operators apply to equal size and structure and the operands are compared component by component.
The other comparison operators (> , < > = , < = ) apply only to integer types, enumerated types (such
as STD_LOGIC) and one dimensional arrays of integer type. The VHDL program that produces all of
the comparison outputs for comparing two 8bit unsigned integers is given.
INPUT A INPUT B
Fig. 2.67: 8 bit comparator
Fig. 2.68: 8-bit comparator’s other outputs
2.86 Digital Principles and System Design
library IEEE;
use IEEE . Std_logic_1164 . all
entity compare is
port (
A, B : in STD_LOGIC_VECTOR (7 downto 0);
EQ, NE, GT, GE, LT, LE : out STD_LOGIC
);
end compare;
architecture compare 1 of compare is
begin
process (A, B)
begin
EQ < = ‘0’ ; NE < = ‘0’ ; GT < = ‘0’ ;
GE < = ‘0’ ; LT < = ‘0’ ; LE < = ‘0’ ;
if A = B then EQ < = ‘1’ ; end if;
if A/ = B then NE < = ‘1’ ; end if;
if A > B then NE < = ‘1’; end if;
if A > = B then GE < = ‘1’; end if;
if A < B then LT < = ‘1’; end if;
if A < = B then LE < = ‘1’; end if;
end process
end compare 1;
2.33.8 Binary Adder-Subtractor
The addition and subtraction operations combined into one circuit is called as binary adder-
subtractor. This is done by including an XOR gates with each full adder. The mode input M controls
the operation of the circuit. When M = 0, the circuit is an adder and when M = 1, the circuit becomes
a subtractor. Each XOR gate receives input M and one of the inputs of B(B0 B3). When M = 0, B
0 = B. The full adders receive the value of B, the input carry is 0 and the circuit performs addition
operation (A + B), when M = 1, B 1 = B and Cin 0 = 1. The B inputs are all complemented
Combinational Logic 2.87
and 1 is added through the input carry. The circuit performs the operation A + (2’s complement of B)
i.e., A B. The logic diagram of 4 bit binary adder-subtractor is shwon in Figure 2.69 and the logic
symbol is shown in Figure 2.70.
B3 B2 B1 B0
A3 A2 A1 A0
M
C4 Full C3 Full C2 Full C1 Full C0
Adder Adder Adder Adder
S3 S2 S1 S0
Fig. 2.69: 4 bit adder/subtractor
Fig. 2.70: 74283 logic symbol
The IEEE_std_logi_arith package defines two new array types, SIGNED and UNSIGNED, and a
set of comparison functions for operands of type INTEGER, SIGNED or UNSIGNED. The package
also defines addition and subtraction operations for the same kind of operands as well as STD_LOGIC
and STD_ULOGIC for 1-bit operands.
The VHDL program for 8 bit adder-subtractor is given here.
S = 9 bit result of addition of A & B
2.88 Digital Principles and System Design
T = 9 bit result of A + C
U = 8 bit result of C + SIGNED (D)
V = 9 bit result of C UNSIGNED (D)
Library IEEE;
use IEEE . Std_logic_1164 . all;
use IEEE . Std_logic_orith . all;
entity addsub is
port (
A, B : in UNSIGNED (7 downto 0);
C : in SIGNED (7 downto 0);
D : in STD_LOGIC_VECTOR (7 downto 0);
S : out UNSIGNED (8 downto 0);
T : out SIGNED (8 downto 0);
U : out SIGNED (7 downto 0);
V : out STD_LOGIC-VECTOR (8 downto 0)
);
end addsub;
architecture adds of addsub is
begin
S < = (‘0’ & A) + (‘0’ & B);
T<=A+ C
U < = C + SIGNED (D);
V < = C UNSIGNED (D);
end adds;
2.89 Digital Principles and System Design
TWO MARK QUESTIONS
1. Define a combinational logic circuit.
When logic gates are connected together to produce a certain specified combinations of input
variables, with no storage involved, the resulting circuit is called ‘combinational logic circuit’.
2. Define half adder and full adder.
1) Half adder: The logic circuit which performs the arithmetic sum of two bits is called a half
adder.
2) Full adder: The logic circuit which performs the arithmetic sum of 3 bits (bit 1: input 1, bit
2: input 2, bit 3: carry from the previous addition) is called a full adder.
3. Define half subtractor and full subtractor.
1) Half subtractor: It is a combinational circuit that subtracts two bits and produces their
difference and borrow.
2) Full subtractor: It is a combinational circuit that performs a subtraction, between 2 bits. It
also takes into account borrow of the lower significant stage.
4. Suggest a solution to overcome the limitation on the speed of an adder.
It is possible to increase speed of adder by eliminating inter-stage carry delay. This method
utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-
order carry is to be generated.
5. What do you mean by comparator? OR Write a short note on 1-bit comparator?
It is a special combinational circuit designed primarily to compare the relative magnitudes of
two binary numbers. An n-bit comparator receives two n-bit numbers, A and B, outputs are A
> B, A= B and A< B. As per the magnitudes of the two numbers, one of the outputs will be
high.
Combinational Logic 2.90
6. What do you mean by encoder?
An encoder is a digital circuit that performs the inverse operation of a decoder. Encoder has 2"
(or fewer) input lines and n output lines. Encoder has enable inputs to activate encoded outputs.
7. What is decoder?
A decoder is a multiple input, multiple-output logic circuit which converts coded inputs into
coded outputs, where the input and output codes are different. In a binary decoder n-inputs
produce 2n outputs. Usually, a decoder is provided with enable inputs to activate decoded
output.
8. What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n outputs lines.
9. What will be the maximum number of outputs for a decoder with a 6-bit data word?
26=64
10. What is a data selector? or what is multiplexer? or Why is MUX called as data detector?
• Multiplexer is a digital switch. Particularly, it has 2" input lines and n selection lines whose bit
combinations determine which input line is selected and routed onto available only single
output line.
• Hence, multiplexer is a selector of one out of several data sources available at its input lines,
to connect it to output line. Simply it is a 'many into one' device and also called 'data selector'.
11. Draw the schematic of half adder logic.
2.91 Digital Principles and System Design
12. Define look ahead carry addition.
The method of speeding up the process of parallel adder by eliminating inter stage carry delay
is called look ahead-carry addition. This method utilizes logic gates to look at the lower-order
bits of the augend and addend to see if a higher-order carry is to be generated. It uses two
functions: carry generate and carry propagate.
13. Distinguish between a decoder and demultiplexer.
Decoder Demultiplexer
Decoder is a many input to many Demultiplexer is a one input to many outputs
outputs device. device.
The selection of specific output line is controlled
There are no selection lines.
by the value of selection lines.
14. Draw 1:8 demultiplexer using two 1:4 demultiplexer.
15. Define the term priority encoder.
A priority encoder is an encoder circuit in which if two or more inputs are equal to 1 at the
same time, the input having the highest priority will take precedence.
Combinational Logic 2.92
16. Compare the serial and parallel adder.
Serial adder Parallel adder
Uses shift register Uses registers with parallel load capacity
Number of full adder circuit equal to the number
Requires only one full adder circuit
of bits in the binary number
It is a sequential circuit Purely a combinational circuit
Time required depends on number of
Time required does not depend on number of bits
bits
17. Write down the truth table of a full subtractor.
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
18. Draw the circuit for 2-to-1 line multiplexer.
2.9 Digital Principles and System Design
19. Implement the function G=∑m(0,3) using a 2x4 decoder.
20. What is meant by propagation delay?
In parallel adders, sum and carry outputs of any stage cannot be produced until the input carry
occurs. This time delay in the addition process is called carry propagation delay. This delay
increases with the number of bits to be added in the adder circuit.
21. What is the need for a code converter?
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes for different digital systems. It is
sometimes necessary to use the output of one system as the input to another. A conversion circuit
must be inserted between the two systems if each uses different codes for the same information.
Thus a code converter is a circuit that makes the two systems compatible even though each uses
a different binary code.
22.What are the steps to design a combinational logic circuit?
(1) The problem is stated
(2) The number of available input variables and required output variables is determined
(3) The input and output variables are assigned letter symbols
(4) The truth table that defines the required relationships between inputs and outputs is derived
(5) The simplified Boolean function for each output is obtained
(6) The logic diagram is drawn
Combinational Logic 2.94
23. Compare decoder and Demultiplexer.
The Decoder is a combinational circuit that converts binary information from „n‟ input lines to a
maximum of 2n unique output lines. A Demultiplexer (data distributor) is a combinational circuit
that receives the information on a single line and transmits this information on one of 2n possible
output lines. A decoder with enable input can function as a Demultiplexer.
2.95 Digital Principles and System Design
MCQ QUESTIONS
1. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input gives single output
Answer: a. The input will be distributed to one of the outputs
2. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b. Single input, multiple outputs
3. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Answer: a.2
4. In a multiplexer the output depends on its ____________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b. Select inputs
Combinational Logic 2.96
5. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a. IC 74154
6. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
Answer: c. 4 inputs
7. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
Answer: d. Multiplexer
8. A combinational circuit is one in which the output depends on the ____________
a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output
Answer: a. Input combination at the time
2.97 Digital Principles and System Design
9. Which combinational circuit is renowned for selecting a single input from multiple inputs &
directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) Demultiplexer
Answer: a. Data Selector
10. How many inputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 10
d) 16
Answer: c. 10
11. How is an encoder different from a decoder?
a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of a decoder is a binary code for N-of-1 output
Answer: a. The output of an encoder is a binary code for 1-of-N input
12. Can an encoder be called as multiplexer?
a) No
b) Yes
c) Sometimes
d) Never
Answer: b. Yes
13. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
Combinational Logic 2.98
b) The lower value
c) Neither of the inputs
d) Both of the inputs
Answer: a. The higher value
14. How many inputs are required for a 1-of-16 decoder?
a) 2
b) 16
c) 8
d) 4
Answer: d. 4
15. A code converter is a logic circuit that _____________
a) Inverts the given input
b) Converts into decimal number
c) Converts data of one type into another type
d) Converts to octal
Answer: c. Converts data of one type into another type
16. Convert binary number into gray code: 100101.
a) 101101
b) 001110
c) 110111
d) 111001
Answer: c. 110111
17. One that is not the outcome of magnitude comparator is ____________
a) a > b
b) a – b
2.99 Digital Principles and System Design
c) a < b
d) a = b
Answer: b.a-b
18. In magnitude comparator, if two numbers are not equal then binary variable will be
a) 0
b) 1
c) A
d) B
Answer: a.0
19. Which one is a basic comparator?
a) XOR
b) XNOR
c) AND
d) NAND
Answer: a. XOR
20. The number of (2 to 4) Decoders required to implement (4 to 16) Decoder is
a) 6
b) 4
c) 5
d) 7
Answer: b.4
21. Which of the following is correct for full adders?
a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
Answer: d. In a parallel full adder, the first stage may be a half adder
Combinational Logic 2.100
22. In what aspect, HDLs differ from other computer programming languages?
a) No aspect; both are same
b) HDLs describe hardware rather than executing a program on a computer
c) HDLs describe software and not hardware
d) Other computer programming languages have more complexity
Answer: b. HDLs describe hardware rather than executing a program on a computer
23. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c. A XOR B
24. Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c. Accept a carry bit from a previous stage
25. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b.2,1,2
2.101 Digital Principles and System Design
26. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Answer: b. Borrow
27. What does minuend and subtrahend denotes in a subtractor?
a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Answer: c. Its inputs
28. Procedure for the design of combinational circuits are:
A. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Answer: c .A,B,E,C,D
Combinational Logic 2.102
29. The design of an ALU is based on ____________
a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
Answer: b. Combinational logic
30. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Answer: b. Two half subtractors and an OR gate
31. The simplified expression of full adder carry is ____________
a)c=xy+xz+yz
b)c=xy+xz
c)c=xy+yz
d)c=x+y+z
Answer: a. c = xy+xz+yz
32. A magnitude comparator is defined as a digital comparator which has
a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) No output terminal
Answer: c. Three output terminals
2.103 Digital Principles and System Design
REVIEW QUESTIONS
1. Distinguish between a half-adder and a full-adder.
2. Distinguish between a half-subtractor and a full-subtractor.
3. Realize a half-adder using (a) only NAND gates and (b) only NOR gates.
4. Realize a half-subtractor using (a) only NAND gates and (b) only NOR gates.
5. Realize a full-adder using (a) only NAND gates and (b) only NOR gates.
6. Realize a full-subtractor using (a) only NAND gates and (b) only NOR gates.
7. Distinguish between a serial adder and a parallel adder.
8. With the help of a block diagram explain the working of a serial adder.
9. Give the implementation of a 4-bit ripple adder using half-adder(s)/full-adder(s).
10. Realize a look-ahead-carry adder.
11. With the help of a logic diagram explain a parallel adder/subtractor using 2's complement
system.
12. Explain the working of a BCD adder.
13. Realize a single bit comparator.
14. Realize a 2-bit comparator.
15. Realize a 4-bit comparator.
16. Write notes on code converters.
17. Write notes on parity bit generators.
18. Distinguish between an encoder and a decoder.
19. With the help of a logic diagram and a truth table, explain an octal-to-binary encoder.
20. With the help of a gate level logic diagram and a truth table, explain a decimal -to-BCD
encoder.
21. Explain a keyboard encoder using diode matrix.
22. With the help of a logic diagram and a truth table, explain a 3-line to 8-line decoder.
23. With the help of a logic diagram and a truth table, explain a BCD-to-decimal decoder.
24. Write notes on BCD-to-7 segment decoders.
25. Distinguish between a multiplexer and a demultiplexer.
26. Discuss a few applications of multiplexers.
Combinational Logic 2.104
27. With the help of logic diagram and function table explain (a) a 4-input multiplexer and (b)
an 8-input multiplexer.
28. Explain how a 4-variable function can be realized using an 8:1 mux.
29. Show an arrangement to obtain a 16-input multiplexer from two 8-input multiplexers.
30. With the help of a logic diagram and truth table explain (a) a 1-line to 4-line demultiplexer
and (b) a 1-line to 8-line demultiplexer.
Synchronous Sequential Logic 3.1
UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC
3.1 INTRODUCTION
In combinational logic circuits, the outputs
at any instant of time depend only on the
input signals present at that time as shown in
Figure 3.1.
Fig. 3.1: Combinational Circuit
The logic circuits whose outputs at any instant of time depend not only on the present inputs but
also on the past outputs are called sequential logic circuits. Figure 3.2 shows the block diagram of
sequential logic circuit.
Fig. 3.2: Sequential Circuit-Block Diagram
The comparison between combinational and sequential circuits is given in Table 3.1.
TABLE 3.1 : Comparison between combinational and sequential circuits
Combinational Circuits Sequential Circuits
Output depends on the present state Output depends not only on present input
input. but also on the past output.
Faster than sequential circuit. Low speed.
Memory unit is not required. Memory unit is required.
Easy to design. Design is not easy.
1
3.2 Digital Principles and System Design
The rotary channel selected knob on an old-fashioned TV is like a combinational circuit. Its
output selects a channel based only on its current input the position of the knob. The channel-up and
channel-down push buttons on a TV is like a sequential circuit. The channel selection depends on the
past sequence of up/down pushes.
3.2 CLASSIFICATION OF LOGIC CIRCUITS
Logic Circuit
Combinational Sequential
Synchronous Asynchronous
Moore Circuit Mealy Circuit Fundamental Mode Pulse Mode
Fig. 3.3: Classification of Logic Circuits
In the synchronous or clocked sequential circuits, signals can affect the memory elements only at
discrete instants of time. In the asynchronous or unclocked sequential circuits, change in input signals
can affect memory element at any instant of time.
3.3 FLIP-FLOPS
The memory elements used in synchronous sequential circuits
are called flipflops. A flip-flop circuit has two outputs one for the
normal value and another for the complement value of the bit
stored in it. Flip-flops flip from one state to another and then
flop back. They are known as bistable multivibrators.
The output of the flip-flop is either logic 0 (0 volt) or logic
1 (+5 V). The flip-flop output will remain 0 or 1 until the trigger Fig. 3.4: Block Diagram of a Flip-Flop
pulse is given to change the state. This means that it can store
1 bit information. The block diagram of a flip-flop is shown in
Figure 3.4.
The Types of flip-flops are: The Applications of flipflops are:
(i) SR flip-flop (i) Counters
(ii) JK flip-flop (ii) Frequency dividers
(iii) D flip-flop (iii) Shift registers
(iv) T flip-flop (iv) Storage registers
Synchronous Sequential Logic 3.3
3.4 SR FLIP-FLOP
The SR flip-flop has two inputs: S(set) and R(reset) and
two outputs: Q(normal output) and Q (inverted output). The
symbol of SR flip-flop is shown in Figure 3.5. The NOR SR
flip-flop is shown in Figure 3.6. The cross coupled connections
from the output of one NOR gate to the input of the other Fig. 3.5: Symbol of SR flip-flop
NOR gate form a feedback path.
Fig. 3.6: S - R flip-flop
When S = 0 and R = 0, the output, Qn + 1 remains in its present state, Qn.
When S = 0 and R = 1, the flipflop reset to 0.
When S = 1 and R = 0, the flipflop set to 1.
When S = 1 and R = 1, the output of both gates will produce 0. Qn Q n .
The truth table of NOR based SR flip-flop is shown in Table 3.2.
TABLE 3.2: Truth Table of SR flip-flop
Inputs Outputs
S R Qn + 1 Q n+ 1 State
0 0 Qn Qn No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 X X Forbidden
Qn Present State ; Qn + 1 Next State
The SR flip-flop can be also implemented using NAND gates. The inputs of this flip-flop are S
and R .
3.4 Digital Principles and System Design
When S = R = 0, Outputs Qn + 1 = Q n = 1.
When S = 0, R = 1, the flip-flop output Qn + 1 = 1 (set).
When S = 1, R = 0, the flip-flop output Qn + 1 = 0 (reset).
When S = R = 1, the output remains in its prior state.
The NAND based SR flip-flop is shown in Figure 3.7 and the truth table is given in Table 3.3.
S Q
Q
R
Fig. 3.7: NAND based SR flip-flop
TABLE 3.3: Truth Table of S R flipflop
Inputs Outputs
S R Qn + 1 Q n State
0 0 X X Forbidden
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn Qn No change
3.4.1 Characteristic Table and Characteristic Equation
The characteristic table shows the operation of the flip-flop in tabular form. Q is the present state
(Qn) and Qn + 1 stands for next state. The characteristic table of SR flip-flop is shown in Table 3.4.
The characteristic equation is an algebraic expression for the binary information of the characteristic
table. This equation is derived from K-map. This equation specifies the value of the next state as a
function of the present state and the inputs.
Synchronous Sequential Logic 3.5
TABLE 3.4: Characteristic Table
Q S R Qn + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Forbidden
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Forbidden
SR 00 01 11 10
Q
0 X 1
1 1 X 1
Characteristic equation: Qn S QR
3.5 CLOCKED SR FLIP-FLOP
Synchronous circuits change their states only when clock pulses are present. The clocked SR flip-
flop is shown in Figure 3.8. It consists of a basic SR flipflop circuit and two additional NAND gates.
The pulse input acts as an enable signal (EN) for the other two inputs. The outputs of NAND gates 3
and 4 stay at the logic level 1 as long as the clock pulse input remains 0. When the pulse input goes to
1, information from the S or R input is allowed to reach the output.
S S Q
EN
R Q
R
S Q
EN
Q
R
Fig. 3.8 : Clocked S-R flip-flop
3.6 Digital Principles and System Design
The characteristic table and characteristic equation of clocked SR flip-flop are same as the
characteristic table (Table 3.4) and characteristic equation of SR flip-flop. Note that the CP input is
not included in Table 3.4. The table must be interpreted as: Given the present state Q and the inputs
S and R, the application of a single pulse in the EN input causes the flip-flop to go to the next state Qn+1.
3.6 TRIGGERING OF FLIP-FLOPS
The state of a flip-flop is switched by a momentary change in the input signal. This momentary
change is called a trigger and the transition it causes is said to trigger the flip-flop. Clocked flip-flops
are triggered by pulses. A clock pulse starts from an initial value of 0, goes momentarily to 1, and after
a short time, returns to its initial 0 value. Based on the specific interval or point in the clock during or
at which triggering of flip-flop takes place, it can be classified into two different types:
Level triggering,
Edge triggering.
3.6.1 Level Triggering
In Level triggering, the flip-flops are enabled in HIGH (+ve level) or LOW (ve level) level. The
flip-flop action is dependent on the entire period of the pulse.
Positive Level Triggering: If the flip-flop changes its state when the clock is positive, it is called as
positive level triggering.
Negative Level Triggering: If the flip-flop changes its state when the clock is negative, it is called as
negative level triggering.
3.6.2 Edge Triggering
A clock pulse may be either negative or positive. A positive clock source remains at 0 during the
interval between pulses and goes to 1 during the occurrence of a pulse. The pulse goes through two
signal transitions: from 0 to 1 and returns from 1 to 0. The positive transition is defined as the positive
edge and the negative transition is defined as the negative edge. Figure 3.9 (a) shows the positive
pulse and Figure 3.9(b) shows the negative pulse with +ve edge and ve edge.
(a) Positive Pulse (b) Negative Pulse
Fig. 3.9: Edge Triggering
The flip-flop changes its state either at the positive edge or at the negative edge of the clock pulse
and is sensitive to its inputs only at this transition of the clock.
Synchronous Sequential Logic 3.7
To make the flip-flop respond only to a pulse
transition is to use capacitive coupling. An RC
(resistor-capacitor) circuit is inserted in the clock
input of the flipflop. The RC circuit is shown in
Figure 3.10. This circuit generates a spike in
response to a momentary change of input signal.
A positive edge emerges from the RC circuit
with a positive spike and a negative edge emerges
with a negative spike. Edge triggering is achieved Fig. 3.10: RC circuit
by designing the flip-flop to neglect one spike and
trigger on the occurrence of the other spike.
The graphic symbols of level triggered and edge triggered flip-flops are given in Figure 3.11.
(a) Positive level triggered (b) Negative level triggered
SR flipflop SR flipflop
(c) Positive edge triggered SR flipflop d) Negative edge triggered
with active high inputs SR flip flop with active
high inputs
(e) Negative edge triggered with active low inputs
Fig. 3.11 : Graphic Symbols
3.8 Digital Principles and System Design
3.7 D FLIP-FLOP
To eliminate the undesirable condition of the indeterminate state in the RS flip-flop is to ensure
the inputs S and R are never made equal to 1 at the same time. This is done by D flip-flop. The D
(delay) flip-flop has one input called delay input and clock pulse input. The D flip-flop using SR flip-
flop is shown in Figure 3.12(a) and the graphic symbol is shown in Figure 3.12(b).
(a) Using SR flipflop (b) Graphic symbol
Fig. 3.12 : D flip-flop
The truth table of D flip-flop is given in Table 3.5.
TABLE 3.5: Truth Table
Clock Input Output State
D Qn + 1
1 0 0 Reset
1 1 1 Set
0 X Qn No change
3.7.1 Characteristic Table and Characteristic Equation
The characteristic table for the D flip-flop is shown in Table 3.6. It shows that the next state of the
flip-flop is independent of the present state since Qn + 1 is equal to D, whether Q is equal to 0 or 1. This
means that an input pulse will transfer the value of input D into the output of the flipflop independent
of the value of the output before the pulse was applied. The characteristic equation is derived from
K-map.
TABLE 3.6: Characteristic Table
Q D Qn + 1
0 0 0
0 1 1
1 0 0
1 1 1
D
Q 0 1
0 0 1
Characteristic equation: Qn + 1 = D 1 0 1
Synchronous Sequential Logic 3.9
3.8 JK FLIP-FLOP
JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented IC in 1958. JK flipflop has
two inputs J(set) and K(reset). A JK flip-flop can be obtained from the clocked SR flipflop by
augmenting two AND gates as shown in Figure 3.13. The data input J and the output Q are applied
to the first AND gate and its ouput (J Q ) is applied to the S input of SR flipflop. Similarly, the data
input K and the output Q are applied to the second AND gate and its output (KQ) is applied to the R
input of SR flip-flop.
(a) Using SR flipflop (b) Graphic symbol
(c) Logic diagram
Fig. 3.13: JK flip-flop
J=K=0
When J = K = 0, both AND gates are disabled. Therefore clock pulse have no effect, hence the
flip-flop output is same as the previous output.
J = 0, K = 1
When J = 0 and K = 1, AND gate 1 is disabled i.e., S = 0 and R = 1. This condition will reset the
flipflop to 0.
J = 1, K = 0
When J = 1 and K = 0, AND gate 2 is disabled i.e., S = 1 and R = 0. Therefore the flip-flop will set
on the application of a clock pulse.
J=K=1
When J = K = 1, it is possible to set or reset the flip-flop. If Q is high, AND gate 2 passes on a reset
pulse to the next clock. When Q is low, AND gate 1 passes on a set pulse to the next clock. Eitherway, Q
changes to the complement of the last state i.e., toggle. Toggle means to switch to the opposite state.
3.10 Digital Principles and System Design
The truth table of JK flip-flop is given in Table 3.7.
TABLE 3.7: Truth Table
CLK Inputs Output
State
J K Qn + 1
1 0 0 Qn No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q Toggle
3.8.1 Characteristic Table and Characteristic Equation
The characteristic table for the JK flip-flop is shown in Table 3.8. From the Table 3.8, K-map for
the next state transition (Qn + 1) can be drawn and the simplified logic expression which represents the
characteristic equation of JK flip-flop can be found.
TABLE 3.8: Characteristic Table
Q J K Qn + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
JK
00 01 11 10
Q
0 0 0 1 1
1 1 0 0 1
Characteristic equation: Qn J Q K Q
Synchronous Sequential Logic 3.11
3.9 T FLIP-FLOP
The T(Toggle) flipflop is a modification of the JK flipflop. It is obtained from JK flip-flop by
connecting both inputs J and K together, i.e., single input. Regardless of the present state, the flip flop
complements its output when the clock pulse occurs while input T = 1.
When T = 0, Qn + 1 = Qn, i.e., the next state is the same as the present state and no change occurs.
When T = 1, Qn Q n , i.e., the next state is the complement of the present state.
The symbol and truth table of T flip-flop is shown in Figure 3.14.
T Qn + 1 State
0 Qn No change
1 Q Complement
(a) Graphic symbol (b) Truth Table
Fig. 3.14 : T flipflop
The characteristic table is shown in Table 3.9 and characteristic equation is derived using K-map.
TABLE 3.9 : Characteristic table.
Q T Qn + 1
T
0 0 0 Q 0 1
0 1 1
1 0 1 0 0 1
1 1 0
1 1 0
Characteristic Equation: Qn T Q T Q
3.10 MASTER-SLAVE J-K FLIPFLOP
A master-slave flip-flop is constructed using two separate JK flipflops. The first flip-flop is called
the master. It is driven by the positive edge of the clock pulse. The second flip-flop is called the slave.
It is driven by the negative edge of the clock pulse. The logic diagram of a master-slave JK flipflop
is shown in Figure 3.15.
Fig. 3.15 : Logic diagram of Master-slave JK flipflop
3.12 Digital Principles and System Design
When the clock pulse has a positive edge, the master acts according to its J - K inputs, but the
slave does not respond, since it requires a negative edge at the clock input.
When the clock input has a negative edge, the slave flip-flop copies the master outputs. But the
master does not respond since it requires a positive edge at its clock input.
The clocked master-slave J - K flipflop using NAND gates is shown in Figure 3.16.
J Q
CLK
K Q
Master Slave
Fig. 3.16 : Master Slave JK flipflop
3.11 APPLICATION TABLE (or) EXCITATION TABLE
The characteristic table is useful for analysis defining the operation of the flip-flop. It specifies
the next state (Qn + 1) when the inputs and present state are known.
The excitation or application table is useful for design process. It is used to find the flip-flop
input conditions that will cause the required transition, when the present state (Qn) and next state
(Qn + 1) are known.
3.11.1 SR Flipflop
TABLE 3.10 (a) : Characteristic Table TABLE 3.10 (b) : Modified Table
Present Inputs Next Present Next Inputs Inputs
State State State State
Qn S R Qn + 1 Qn Qn + 1 S R S R
0 0 0 0 0 0 0 0
0 0 1 0 0 X
0 0 0 1
0 1 0 1
0 1 1 X 0 1 1 0 1 0
1 0 0 1 1 0 0 1 0 1
1 0 1 0
1 1 0 0
1 1 0 1 X 0
1 1 1 X 1 1 1 0
Synchronous Sequential Logic 3.13
The excitation table for SR flipflop is derived from the characteristic table. Table 3.10(a) shows
the characteristic table of SR flipflop and rearrangement of columns is shown in Table 3.10(b).
Table 3.11 presents the excitation table for SR flipflop. It consists of present state (Qn), next state
(Qn + 1) and a column for each input to show how the required transition is achieved. There are 4
possible transitions from present state to next state. The required input conditions for each of the four
transitions are derived from the information available in the characteristic table. The symbol X denotes
the don’t care condition, it does not matter whether the input is 1 or 0.
TABLE 3.11: Excitation Table
Present Next Inputs
State State
Qn Qn + 1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
3.11.2 J - K flipflop
Table 3.12(a) represents the characteristic table of JK flipflop and Table 3.12(b) represents the
rearrangement of the characteristic table. The required input conditions for each of the four transitions
are derived from the information available in the characteristic table. The excitation table for JK
fliplop is shown in Table 3.13.
TABLE 3.12 (a) : Characteristic Table TABLE 3.12 (b) : Modified Table
Present Inputs Next Present Next Inputs Inputs
State State State State
Qn J K Qn + 1 Qn Qn + 1 J K J K
0 0 0 0 0 0 0 0
0 X
0 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0
1 X
0 1 1 1 0 1 1 1
1 0 0 1 1 0 0 1
X 1
1 0 1 0 1 0 1 1
1 1 0 1 1 1 0 0
X 0
1 1 1 0 1 1 1 0
3.14 Digital Principles and System Design
TABLE 3.13: Excitation Table
Present Next Inputs
State State
Qn Qn + 1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
3.11.3 D flip-flop
The characteristic table and excitation table for the D flipflop are shown in Table 3.14 and Table
3.15 respectively.
Table 3.14: Characteristic Table Table 3.15: Excitation Table
Present Delay Next Present Next Input
State input State State State
Qn D Qn + 1 Qn Qn + 1 D
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 0
1 1 1 1 1 1
3.11.4 T flipflop
The characteristic table and excitation table for the T flipflop are shown in Table 3.16 and Table
3.17 respectively.
TABLE 3.16: Characteristic Table TABLE 3.17: Excitation Table
Present Input Next State Present Next State Input
State State
Qn T Qn + 1 Qn Qn + 1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
Synchronous Sequential Logic 3.15
3.12 REALIZATION OF ONE FLIP-FLOP USING OTHER FLIP-FLOPS
It is possible to implement a flip-flop circuit using any other flip-flop. The realization of one
flipflop using other flipflops is implemented by the use of characteristic tables and excitation tables.
The examples are:
D flipflop using SR flipflop
D flipflop using JK flipflop
D flipflop using T flipflop
T flipflop using SR flipflop
T flipflop using JK flipflop
T flipflop using D flipflop
JK flipflop using SR flipflop
JK flipflop using D flipflop
3.12.1 Realization of D flip-flop using SR flipflop
Write the characteristic table for required flipflop. (D flip-flop)
Write the excitation table for given flipflop. (SR flip-flop)
Determine the expression for the given flip-flop inputs (S and R) by using K-map.
Draw the flip-flop conversion logic diagram to obtain the required flip-flop (D flipflop) by
using the above obtained expression.
TABLE 3.18 : Excitation Table for D flipflop realization using SR flipflop
Required Flip-flop (D) Given Flip-flop (SR)
Present State Input Next State Excitation Inputs
Qn D Qn + 1 S R
0 0 0 0 X
0 1 1 1 0
1 0 0 0 1
1 1 1 X 0
Expression for S Expression for R
D D
Qn 0 1 0 1
Qn
0 0 1 0 X 0
1 0 X 1 1 0
S=D RD
3.16 Digital Principles and System Design
Fig. 3.17: D flip-flop using SR flipflop
3.12.2 Realization of J-K flipflop using SR flipflop
Write the characteristic table for JK flipflop.
Write the excitation table for SR flipflop.
Determine the expression for inputs S and R by using K-map.
Draw the flip-flop conversion diagram.
TABLE 3.19 : Excitation table for JK flipflop realization using SR flipflop
Required flipflop (JK) Given flipflop (SR)
Excitation Inputs
Qn J K Qn + 1 S R
0 0 0 0 0 X
0 0 1 0 0 X
0 1 0 1 1 0
0 1 1 1 1 0
1 0 0 1 X 0
1 0 1 0 0 1
1 1 0 1 X 0
1 1 1 0 0 1
Expression for S Expression for R
JK JK
Qn 00 01 11 10 Qn 00 01 11 10
0 0 0 1 1 0 X X 0 0
1 X 0 0 X 1 0 1 1 0
S J Qn R = KQn
Synchronous Sequential Logic 3.17
Fig. 3.18 : J-K flipflop using SR flipflop
3.12.3 Realization of T flipflop using D flipflop
Write the characteristic table for T flipflop.
Write the excitation table for D flipflop.
Determine the expression for input D using K-map.
Draw the flipflop conversion logic diagram.
TABLE 3.20: Excitation table for realization of T flipflop using D flipflop
Required flipflop (T) Given flipflop (D)
Qn T Qn + 1 Input (D)
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Expression for D
T
0 1
Qn
0 0 1
1 1 0
D TQn TQ n
T Qn
3.18 Digital Principles and System Design
D
T D
Flip-Flop Q
Fig. 3.19: T flipflop using D flipflop
3.12.4 Realization of D flipflop using JK flipflop
Write the characteristic table for D flipflop.
Write the excitation table for JK flipflop.
Determine the expression of inputs J and K using K-map
Draw the flipflop conversion logic diagram.
Table 3.21: Excitation table for realization of D flipflop using JK flipflop
Required flip flop (D) Given flip flop (JK)
Qn D Qn+1 J K
0 0 0 0 X
0 1 1 1 X
1 0 0 X 1
1 1 1 X 0
Expression for J Expression for K
D D
Qn 0 1 Qn 0 1
0 0 1 0 X X
1 X X 1 1 0
J=D K= D
Fig. 3.20: D flipflop using JK flipflop
Synchronous Sequential Logic 3.19
3.13 CLASSIFICATION OF SYNCHRONOUS SEQUENTIAL CIRCUITS
In synchronous or clocked sequential circuits, clocked flip flops are used as memory elements,
which change thier individual states in synchronism with the periodic clock signal. Therefore, the
change in states of flip flops and change in state of the entire circuits occurs at the transition of the
clock signal. The synchronous sequential circuits are represented by two models:
Moore Model
Mealy Model
3.13.1 Moore Model
In the Moore Model, the outputs are a function of the present state of the flip flops only.
The block diagram of Moore model is shown in Figure 3.21. The output depends only on present
state of flip flops, it appears only after the clock pulse is applied, ie., it varies in synchronism with the
clock input.
Fig. 3.21: Moore Model
3.13.2 Mealy Model
In the Mealy model, the outputs are functions of both the present state of the flip flops and inputs.
The block diagram of Mealy model is shown in Figure 3.22.
Outputs
Next
Inputs Memory
State
Decoder Elements
Fig. 3.22 : Block diagram of Mealy Model
3.20 Digital Principles and System Design
3.13.3 Difference between Moore and Mealy Model
Sl.No. Moore Model Mealy Model
1. Its output is a function of Its output is a function of
present state only. present state and present input.
2. It requires more number of It requires less number of
states for implementing same states for implementing same
function function.
3. Input changes do not affect Input changes may affect
the output of the cirucit the output of the circuit.
3.14 STATE EQUATION
It is an algebraic expression that specifies the condition for a flip flop state transition.
Some state equation examples are given below:
A(t+1) = Ax + Bx
B(t+1) = Ax
JA = B + x
KA = BC B C x
3.15 STATE TABLE
The time sequence of inputs, outputs and flip flop states can be enumerated in a state table.
State table consists of 4 sections: Present state, Next state, Input, Output.
The present state section shows the states of flipflops at any given time ‘t’. The next state section
shows the states of the flip flops one clock period later at time (t+1). The input section gives the value
of inputs for each possible present state. The output section gives the value of outputs for each present
state.
3.16 STATE DIAGRAM
State diagram is a graphical representation of a state table.
In the state diagram, a state is represented by a circle and the transition between states is indicated
by directed lines connecting the circles. There is no difference between a state table and a state
diagram except in the manner of representation.
Synchronous Sequential Logic 3.21
3.17 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUIT
The behaviour of a sequential circuit is determined from the inputs, outputs and the state of its flip
flops. The outputs and the next state are both a function of the inputs and the present state. The
analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of
inputs, outputs and internal states. It is also possible to write Boolean expressions that describe the
behaviour of the sequential circuit. A logic diagram is recognized as a synchronous (clocked) sequential
circuit if it includes flip- flops. The flip flops may be of any type and the logic diagram may or may
not include combinational circuit gates.
3.17.1 Analysis of Mealy Model
Example 3.1
A sequential circuit with two ‘D’ flip flops A and B, one input (x); and one output (y). The flip
flop input functions are:
DA = Ax + Bx
DB = Ax
and the circuit output function is,
y = (A + B) x
(a) Draw the logic diagram of the circuit
(b) Tabulate the state table
(c) Draw the state diagram
Solution
Fig. 3.23 : Mealy circuit
3.22 Digital Principles and System Design
Figure 3.23 shows the Mealy synchronous sequential circuit for the given input and output
functions. It consists of two D flip flops A and B, an input x and an output y.
D inputs determine the flipflop’s next state; D = Q(t+1).
Therefore the next-state equations are:
A(t+1) = A(t) x(t) + B(t) x(t)
B(t+1) = B t A t x t
The LHS of equation denotes the next state of the flip flop and the RHS of equation is a Boolean
expression that specifies the present state and input conditions that make the next state equal to 1.
State Table
The state table of the circuit of the circuit is obtained by the following procedure
A circuit with ‘m’ flip flops and ‘n’ inputs needs 2m+n rows in the state table. In this example, m
= 2, n = 1 and 2m+n = 23 = 8 rows are needed. Eight binary combinations from 000 to 111 are
listed under the present state and input columns.
The next state section has m(2) columns, one for each flip flop. The binary values for the next
state are derived directly from the state equations. The next state of flip flop A must satisfy the
state equation, A(t + 1) = Ax + Bx
The next state of flip flop B must satisfy the state equation, B(t + 1) = A x
The output section has as many columns as there are output variables. This example has one
output (y). Therefore one column is needed. Its binary value is derived from the circuit or from
the output equation, y A B x
The state table is given in Table 3.22.
Table 3.22: State Table
Present Input Next State Output
State
A B x A(t+1) = Ax + Bx B(t+1) = A x Y = (A + B) x
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Synchronous Sequential Logic 3.23
The above state is slightly changed with only three sections: present state, next state and output.
The input conditions are enumerated under the next state and output sections. The state table of Table
3.22 is repeated in Table 3.23 using the second form.
Table 3.23: Second form of the state table
Present Next state Output
state
x=0 x=1 x=0 x=1
A B
A B A B y Y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
State Diagram
Fig. 3.24 : State diagram
The state diagram provides the same information as the state table and is obtained directly from
table 3.23. The binary number inside each circle identifies the state of the flip-flops. The directed
lines are labelled with two binary numbers separated by a slash. The input value during the present
state is labelled first and the number after slash gives the output during the present state. For example,
the directed line from state 00 to 01 is labelled 1/0, meaning that when the sequential circuit is in the
present state 00 and the input is 1, the output is 0. A directed line connecting a circle with itself
indicates that no change of state occurs. The state diagram is shown in Figure 3.24.
3.24 Digital Principles and System Design
Example 3.2
Analyze the synchronous Mealy machine in Figure 3.25 in obtain its state diagram.
Fig. 3.25 : Mealy Model
Solution
The given synchronous Mealy machine consists of two D flip flops, one input and one output.
The flip flop input functions are,
D A Y Y x
D B X Y Y
The circuit output function is,
Z Y Y X
State Equations
The next state equation for a D flip flop is,
D = Q(t+1)
Therefore the next-state equations are
Y t YY x
Y t x YY
Synchronous Sequential Logic 3.25
State Table
Table 3.24 : State Table
Present state Input Next State Output
y1 y2 x Y1 t +1 =Y 1Y2 X Y2 t +1 = x+ y1 y2 Z = Y1Y2 x
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1
Table 3.25 : Second form of the state table
Present state Next state Output
x=0 x=1 x=0 x=1
Y1 Y2 Y1 Y2 Y1 Y2 Z Z
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 0
1 1 0 0 0 1 0 1
State Diagram
Fig. 3.26 : State Diagram
3.26 Digital Principles and System Design
3.17.2 Analysis with JK and other flip flops
The next state values of a sequential circuit with D flip flop can be derived directly from the next-
state equations. When other types of flip flops are used, it is necessary to refer the characteristics
table. The next-state values of a sequential circuit that use any other type of flip flop such as JK, SR
or T can be derived by following procedure.
1. Obtain the binary values of each flip flop input function in terms of the present state and input
variables.
2. Use the corresponding flip-flop characteristic table to determine the next state. (Refer Examples
3.3 to 3.5)
3.17.3 Analysis of Moore Model
Example 4.3: A sequential circuit has two JK flip flop A and B. The flip flop input functions are:
JA = B JB = x
K A Bx K B A x
(a) Draw the logic diagram of the circuit
(b) Tabulate the state table
(c) Draw the state diagram
Solution: The output function is not given in the problem. The output of the flip flops may be considered
as the output of the circuit. The logic diagram is shown in Figure 3.27 for the given state equations.
Fig. 3.27 : Sequential circuit with JK flip-flops
State Table
To obtain the next-state values of a sequential circuit with JK flip flops, use the JK flip flop
characteristic table, given in Table 3.26.
Synchronous Sequential Logic 3.27
Table 3.26 : Characteristic Table for J-K flip flop
Q J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Here, Q = A or B and Qn+1 = A(t+1) or B(t+1)
Table 3.27 : State Table
Present Input Flip flop Inputs Next state
state
A B x JA = B KA = B x JB = x KB = A x A(t+1) B(t+1)
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1
Table 3.28 : Second form of the State table
Present State Next State
x=0 x=1
A B A B A B
0 0 0 1 0 0
0 1 1 1 1 0
1 0 1 1 1 0
1 1 0 0 1 1
3.28 Digital Principles and System Design
State Diagram
The state diagram of the Moore Model sequential circuit is shown in Figure 3.28. Since the
circuit has no outputs, the directed lines out of the circles are marked with one binary number only to
designate the value of input x.
Fig. 3.28 : State Diagram
Example 4.4
Derive the state table and state diagram for the given sequential circuit, Figure 3.29.
B B+x
JA A
x
A
x A x
1 KA Y
B
A A+ x B
JB
x B
B
1 KB
CLK
Fig. 3.29 : Sequential Circuit
Solution: Input functions: JA = B + x
KA = 1
JB = A x
KB = 1
Output equation : Y x AB
Synchronous Sequential Logic 3.29
State Table: To obtain the next-state values of a sequential circuit with J-K flip flops, use the JK flip
flop characteristics table given in Table 3.29.
Table 3.29: State Table
Present Input Flip Flop Inputs Next state Output
State
A B x JA = B + x KA = 1 JB = A + x KB = 1 A(t+1) B(t+1) Y = x AB
0 0 0 0 1 1 1 0 1 0
0 0 1 1 1 1 1 1 1 0
0 1 0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 1 0 0 0
Table 3.30: Second form of State Table
Present state Next state Output
x=0 x=1 x=0 x=1
A B A B A B y Y
0 0 0 1 1 1 0 0
0 1 1 0 1 0 0 1
1 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0
State diagram
Fig. 3.30: State diagram
3.30 Digital Principles and System Design
Example 3.5
Analyze the synchronous Moore machine shown in Figure 3.31 to obtain its state diagram.
Fig. 3.31 : Moore Model
Solution: Using the assigned variable Y1 and Y2 for the two JK flip flops, we can write the four
excitation input equations and the single Moore output equation as follows:
JA = Y2x ; KA = Y ; JB = x
KB = x ; Z = y y
State Table:
To obtain the next-state values of a sequential circuit with J-K flip flops, use the JK flip flop
characteristic table given in Table 3.31.
Table 3.31: State Table
Present Input Flip Flop inputs Next State Output
State
y1 y2 x JA = Y2x KA = y JB = x KB= x Y1 (t+1) Y2(t+1) Z = y1 y2
0 0 0 0 1 0 1 0 0 0
0 0 1 0 1 1 0 0 1 0
0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 1 0 0 1
1 0 1 0 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0 1
1 1 1 1 0 1 0 1 1 1
Synchronous Sequential Logic 3.31
Table 3.32 : Second form of state table
Present state Next state Output
x=0 x=1 x=0 x=1
y1 y2 y1 y2 y1 y2 Z Z
0 0 0 0 0 1 0 0
0 1 0 0 1 1 0 0
1 0 0 0 0 1 1 1
1 1 1 0 1 1 1 1
Fig. 3.32 : State diagram
3.17.4 Analysis Procedure
The synchronous sequential circuit analysis procedure is summarized as given below:
Step 1: Assign a state variable to each flip flop in the synchronous sequential logic circuit.
Step 2: Write the excitation input equations for each flip flop and also write the Moore and/or Mealy
output equations.
Step 3: Substitute the excitation input equations into the bistable equations for the flip flops to obtain
the next state output equations.
Step 4: Obtain the state table and reduced form of the state table.
Step 5: Draw the state diagram by using the second form of the state table.
3.18 STATE MINIMIZATION
The state reduction is used to avoid the redundant states in the sequential circuits. The reduction
in redundant states reduce the number of required flip flops and logic gates, thus reducing the cost of
the circuit.
The two states are said to be redundant or equivalent, if every possible set of inputs generate
exactly same output and same next state. When two states are equivalent, one of them can be removed
without altering the input-output relationship.
3.32 Digital Principles and System Design
Since ‘n’ flip flops produced 2n states, a reduction
in the number of states may result in a reduction in
the number of flip flops.
The need for state reduction or state minimization
is explained with one example. In the given state
diagram of Figure 3.33, only the input-output
sequences are important; the internal states are used
merely to provide the required sequences. For this
Fig. 3.33 : State Diagram
reason, the states marked inside the circles are
denoted by letter symbols (a, b, c.....) instead of by
their binary values. The state table of the state
diagram is shown in Table 3.33.
Table 3.33 : State Table
Present State Next State Output
x=0 x=1 x=0 x=1
a b c 0 0
b d e 1 0
c c d 0 1
d a d 0 0
e c d 0 1
From the state Table 3.33, the states c and e generate exactly same next state and same output for
every possible set of inputs. The state c and e go to next states c and d and have outputs of 0 and 1 for
x = 0 and x = 1 respectively. Therefore state e can be removed and replaced by c. The final reduced
state table is given in Table 3.33. The state diagram for the reduced state table consists of only four
states and is shown in Table 3.34.
Table 3.34: Reduced state Table
Present Next State Output
State x = 0 x = 1 x=0 x=1
a b c 0 0
b d c 1 0
c c d 0 1
d a d 0 0
Fig. 3.34: Reduced State Table
Synchronous Sequential Logic 3.33
Example 3.6
Reduce the number of states in the following state table and tabulate the reduced state table.
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 0
e a f 0 1
f g f 0 1
g a f 0 1
Solution
(i) g and e states go to the same next state (a, f) and have same output for both input combinations
(0,1). Therefore states g and e are equivalent and one can be removed; g is replaced by e. Table 3.35
shows the reduced state table 1.
Table 3.35: Reduced state table 1
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
(ii) Now states d and f are equivalent. Both states go to the same next state (e,f) and have same
output (0,1). Therefore one state can be removed; f is replaced by d. The reduced state table-2 is
shown in Table 3.36.
Table 3.36 : Reduced state Table 2
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Thus 7 states are reduced into 5 states.
3.34 Digital Principles and System Design
3.19 STATE ASSIGNMENT
State Assignment is a procedure to minimize the combinational gates in a circuit. State assignment
procedure is assigning binary values to states in such a way as to reduce the cost of the combinational
circuit that drives the flip-flops.
When a sequential circuit is viewed from its external input-output terminals, it may follow a
sequence of internal states. But the binary values of the individual states (state assignment) may be of
no consequence as long as the circuit produces the required sequence of outputs for any given sequence
of inputs.
Two examples of possible binary assignments are shown in Table 3.37 for the five states a,b,c,d
and e. Assignment 1 is a straight binary assignment. Assignment 2 is chosen arbitrarily. Infact there
are 140 different distinct assignment for these states.
Table 3.37 : Two possible Binary state Assignment
State Assignment 1 Assignment 2
a 001 000
b 010 100
c 011 011
d 100 111
e 101 001
Binary Assignment 1 is substituted to Table 3.37 for the letter symbols a,b,c,d and e. The binary
form of the state table is used to derive the combinational circuit part of the sequential circuit. Table
3.38 is the reduced state table with binary assignment 1.
Table 3.38 : Reduced state table with binary assignment 1
Next State Output
Present State
x=0 x=1 x=0 x =1
001 001 010 0 0
010 011 100 0 0
011 001 100 0 0
100 101 100 0 1
101 001 100 0 1
Rules for state assignments
Rule 1: States having the same NEXT STATES for a given
input condition should have assignments which can be grouped
into logically adjacent cells in a K map.
Figure 3.35 (a) shows the example for this rule. There are
4 states whose next state is same (000). Thus state assignments
for these states are 100, 101, 110 and 111, which can be grouped
into logically adjacent cells in a K-map. Fig. 3.35 (a) : Rule 1-Example
Synchronous Sequential Logic 3.35
Rule 2: States that are the NEXT STATES of a single state
should have assignment which can be grouped into logically
adjacent cells in a K-map.
Figure 3.35 (b) shows the example for rule 2. For state
000, there are four next states. These states are assigned as
100, 101, 110 and 111 so that they can be grouped into logically
adjacent cells in a K-map.
Rule 3: Adjacent assignments should be given to states that
Fig. 3.35 (b) : Rule 2-Example
have the same outputs.
3.20 DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS
A synchronous sequential circuit is made up of number of flip flops and combinational gates. The
design of the circuit consists of choosing the flip flops and then finding a combinational gate structure
that together with the flip flops. The number of flip flops is determined from the number of states
needed in the circuit. The combinational circuit is derived from the state table.
Design procedure
1. The given problem is determined with a state diagram
2. From the state diagram, obtain the state table.
3. The number of states may be reduced by state reduction methods, if applicable.
4. Assign binary values to each state (Binary Assignment) if the state table contains letter symbols.
5. Determine the number of flip flops needed and assign a letter symbol (A,B,C ...) to each.
6. Choose the type of flip flop (D,T,JK, SR) to be used.
7. From the state table, derive the circuit excitation and output tables.
8. Using K-map or any other simplification method, derive the circuit output functions and the
flip-flop input functions.
9. Draw the logic diagram.
Fig. 3.36 : Design Procedure
3.36 Digital Principles and System Design
The type of flip flop to be used may be included in the design specifications or may depend on
what is available to the designer. Many digital systems are constructed with JK flip flops because they
are the most versatile available. The selection of flip flops is given as follows:
Flip Flop Application
JK General Applications
D Applications requiring transfer of data
(Ex: Shift Registers)
T Applications involving complementation
(Ex: Binary Counters)
3.20.1 DESIGN WITH J-K FLIP FLOPS
Example 3.7
Design the synchronous sequential circuit specified by the state diagram of Figure 3.37 using J-
K flip flops.
Fig. 3.37 : State Diagram
Solution
The state diagram of Table 3.39 consists of 4 states with binary values already assigned. Since the
directed lines are marked with a single binary digit without a slash, there is one input variable and no
output variables. To represent these four states, two flip flops are needed and designated as A and B.
The input variable is designated as x. Table 3.39 shows the state table for the state diagram.
Table 3.39 : State Table
Present State Next state
x=0 x=1
A B A B A B
0 0 0 0 0 1
0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 1 0 0
Synchronous Sequential Logic 3.37
The present state and input variables are arranged in the form of a truth table in table 3.43. We
have already discussed about the excitation tables in section 3.11. Again the excitation table for JK
flip flop is given in Table 3.40. Using the excitation input values, fill the values of J and K inputs of
flip flop. A(JA and KA) and flip flop B (JB and KB) in the Table 3.41.
Table 3.40: Excitation Table for JK flip flop
Present State Next state Inputs
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Table 3.41: Excitation Table
Inputs of Outputs of
combinational circuit Next combinational circuit
Present Input State
Flip Flop Inputs
State
A B X A(t+1) B(t+1) JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
Flip Flop Input Functions Equations
The flip flop input functions (JA, KA, JB, KB) are derived from excitation table by using K-map
as follows:
Expression for JA Expression for KA
Bx Bx
A 00 01 11 10 A 00 01 11 10
0 1 0 X X X X
1 X, X X X 1 1
J A Bx KA = Bx
3.38 Digital Principles and System Design
Expression for JB Expression for KB
Bx Bx
00 01 11 10 00 01 11 10
A A
0 1 X X 0 X X 1
1 1 X X 1 X X 1
JB = x KB = Ax + A x A x
Logic diagram
Bx
JA A
x
A
Bx A
KA
x
JB B
AX B
B
KB
CLK
Fig. 3.38: Logic diagram with JK flipflop
3.20.2 DESIGN WITH D FLIP FLOPS
Example 3.8
Design the synchronous (clocked) sequential circuit for Mealy state diagram of Figure 3.39 using
D flip flops.
Fig. 3.39 : Mealy State Diagram
Synchronous Sequential Logic 3.39
Solution
Step 1: State Table
Table 3.42: State Table
Present State Next State Output
x=0 x=1 x=0 x=1
A B A B A B Y y
0 0 0 0 0 1 0 1
0 1 1 0 0 1 0 0
1 0 1 0 1 1 0 1
1 1 1 1 0 0 0 0
Step 2: Excitation table for design with D flip flops:
Table 3.43 : Excitation table for D flip flop
Present State Next State Input
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Table 3.44: Excitation table for design with D flip flops
Present State Input Next State Flip Flop Inputs Output
A B x A(t+1) B(t+1) DA DB Y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 0 1 0 0
1 0 1 1 1 1 1 1
1 1 0 1 1 1 1 0
1 1 1 0 0 0 0 0
D = Q(t+1)
Therefore, DA = A(t+1)
DB = B(t+1)
3.40 Digital Principles and System Design
Step 3: K map simplification for flip flop input functions and circuit output function
Expression for DA
Bx
00 01 11 10
A
0 1
1 1 1 1
D A A B B x
Expression for DB
Bx
00 01 11 10
A
0 1 1
1 1 1
DB Ax B x AB x
Expression for y
Bx
00 01 11 10
A
0 1
1 1
Y Bx
Step 4: Logic Diagram
The simplified functions are:
D A AB Bx
D B A x Bx A B x
Y Bx
The logic diagram of sequential circuit with D flip flops is shown in Figure 3.40
Synchronous Sequential Logic 3.41
AB
DA Q A
x A
Bx
Q A
Ax
DB Q B
Bx
B
Q
ABx
CLK
Bx
A
Fig. 3.40 : Logic diagram with D flip flops
3.20.3 DESIGN WITH T FLIP FLOPS
Example 3.9
Design the synchronous sequential circuit for the Moore state diagram of Figure 3.41 using T flip
flops.
Fig. 3.41 : Moore state diagram
Solution
Step 1: State Table: The state table for the given Moore state diagram is shown in Table 3.47.
Table 3.45: State Table
Present State Next State Output
a b 1
b c 1
c d 0
d a 0
3.42 Digital Principles and System Design
Step 2: Binary Assignment
Assign the binary values 00, 01, 11, 10 to the states a, b, c, d respectively. Table 3.46 shows the
state table with binary assignment.
Table 3.46 : State Table with Binary assignment
Present State Next State Output
A B A(t+1) B(t+1) Y
0 0 0 1 1
0 1 1 1 1
1 1 1 0 0
1 0 0 0 0
Step 3: Excitation table for design with T flip flops.
Table 3.47 shows the excitation table for T flip flop and Table 3.48 shows the excitation table for
given problem.
Table 3.47 : Excitation table for T flip flop
Q(T) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Table 3.48 : Excitation Table
Present state Next State Inputs Output
A B A(t+1) B(t+1) TA TB Y
0 0 0 1 0 1 1
0 1 1 1 1 0 1
1 1 1 0 0 1 0
1 0 0 0 1 0 0
Step 4: K-map simplification for flip flop input functions (TA, TB) and output function (Y).
Expression for TA Expression for TB
B B
0 1 0 1
A A
0 0 1 0 1 0
1 1 0 1 0 1
T A AB A B A B T B A B A B A B
Synchronous Sequential Logic 3.43
Expression for Y
B
0 1
A
0 1 1
1 0 0
Y A
Step 5: Logic diagram of Moore sequential circuit with T flip flops.
AB
A
TA
A
Y
TB B
AB
B
B
CLK
Fig. 3.42 : Moore sequential circuit with T flip flops
3.21 ALGORITHM STATE MACHINE (ASM) Chart
A special flow chart that has been developed specifically to define digital hardware algorithms is
called an Algorithmic State Machine (ASM) chart. A state machine is another term for a sequential
circuit, which is the basic structure of a digital system.
The ASM chart resembles a conventional flow chart, but is interpreted differently. A conventional
flow chart describes the sequence of procedural steps and decision paths for an algorithm without
concern for their time relationship. The ASM chart describes the sequence of event as well as timing
relationship between the states of a sequential controller and the events that occur while going from
one state to the next. It is specifically adapted to specify accurately the control sequence and data
processing operations in a digital system, taking into consideration the constraints of digital hardware.
The ASM chart is a special type of flow chart suitable for describing the sequential operations in
a digital system. The chart is composed of three basic elements:
1. a state symbol
2. an input condition symbol (decision symbol)
3. a conditional output symbol
3.44 Digital Principles and System Design
3.21.1 State Symbol
The state symbol is a rectangle with an arrow entering the
top and leaving the bottom. A state name is written to the side
or on top of the box. Inside the box is written a list of
unconditional output(s). If no unconditional output is required,
the box interior is left blank. Figure 3.43 illustrates the ASM
state symbol.
3.21.2 Decision Symbol Fig. 3.43: State symbol
The condition or decision symbol is a diamond or modified diamond. One arrow enters the top
and two leave the sides or a side and the bottom. Written into the decision symbol are the logic
conditions for the decision to be either true or false. The condition(s) can be a single variable or a
Boolean expression. Figure 3.44 shows the decision symbols.
(a) Diamond (b) Modified diamond
Fig. 3.44: Decision symbols
3.21.3 Conditional output symbol
It is a modified elipse, as indicated in Figure 3.45 Output
variables are listed internally to the symbol. There may be a
single variable or multiple variables.
3.21.4 ASM Block Fig. 3.45: Conditional output symbol
An ASM block consists of a state symbol, and/or possibly
a state symbol with decision block(s) and/or conditional output
symbol (s). The block symbols indicate a process involving a
present state, the decisions, and conditional outputs and the
next state.
The Moore sequential circuit model is represented without
conditional output symbols and the Mealy model includes
conditional output symbols.
Fig. 3.46: Simple ASM Block
Synchronous Sequential Logic 3.45
Figure 3.47(a) illustrates a Moore model with an unconditional output in State A. Figure 3.47(b)
shows a Moore/Mealy mix with both unconditional (output variable OUT 1 in State A) and conditional
(Output varibale OUT 2) outputs.
Figure 3.47(b) shows state A, which consists of the state symbol, the decision symbol and the
conditional output symbol. If input variables X Y , then output OUT 2 is active until next state B is
reached. If input variables X Y , the conditional output is inactive and c is the next state. Output
OUT 1 remains active as long as the machine remains in state A. The standard state diagram notation
equivalent of the ASM diagram in Figure 3.47 is shown in Figure 3.48
(a) With decision symbol (b) With decision and conditional output symbol
Fig. 3.47: ASM Blocks
Fig. 3.48: Standard State diagram notation for the ASM block in Fig. 3.47(b)
Each block in the ASM chart describes the state of the system during one clock pulse interval. The
operations within the state and conditional boxes in Figure 3.49 are executed with a common clock
pulse while the system is in state T1. The same clock pusle also transfers the system controller to one
of the next states, T2, T3 or T4 as dictated by the binary values of E and F. The equivalent state diagram
is shown in Figure 3.50.
3.46 Digital Principles and System Design
Fig. 3.49: ASM Block Fig. 3.50: State Diagram equivalent
3.22 SHIFT REGISTERS
3.22.1 Types of Shift Registers
A register is simply a group of flip-flops that can be used to store a binary number. There must be
one flip-flop for each bit in the binary number. For instance, a register used to store an 8-bit binary
number must have eight flip- flops. Naturally the flip-flops must be connected such that the binary
number can be entered (shifted) into the register and possibly shifted out. A group of flip-flops connected
to provide either or both of these functions is called a shift register.
The bits in a binary number (data) can be removed from one place to another in either of two
ways. The first method involves shifting the data 1 bit at a time in a serial fashion, beginning with
either the most significant bit (MSB) or the least significant bit (LSB). This technique is referred to as
serial shifting. The second method involves shifting all the data bits simultaneously and is referred to
as parallel shifiting.
There are two ways to shift data into a register (serial or parallel) and similarly two ways to shift
the data out of the register. This leads to the construction of four basic register types as shown in
Figure 3.51 serial in- serial out, serial in-parallel out, parallel in-serial out, and parallel in- parallel
out. All of these configuration are commercially available as TTL, MSI/LSI circuits. For instance
Serial in-serial out - 54/74LS91, 8 bits
Serial in-parallel out - 54/74164, 8 bits
Parallel in-serial out - 54/74165, 8 bits
Parallel in-parallel out - 54/74194, 4 bits
Parallel in-parallel out - 54/74188, 8 bits
Synchronous Sequential Logic 3.47
(a) Serial in-serial out (b) Serial in-parallel out
(c) Parallel in-serial out (d) Parallel in-parallel out
Fig. 3.51: Shift register types
Data shifting techniques and methods for constructing the four different types of registers are
discussed in the following sections.
3.22.2 Serial-In Serial-Out Shift Register
FF0 FF1 FF2 FF3
Serial Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
input output
1 2 3 4
Serial
Q3 data
CLK output
Fig. 3.52: Serial in/serial out shift register
Figure 3.52 illustrates entry of the four bits 1010 into the register, beginning with the right most
bit. The register is initially clear. The 0 is put onto the data input line, making D = 0 for FF0. When the
first clock pulse is applied, FF0 is reset, thus storing the 0.
Next the second bit, which is a 1, is applied to the data input, making D = 1 for FF0 and D = 0 for
FF1 because the D input of FF1 is connected to the Q0 output. When the second clock pulse occurs,
the 1 on the data input is shifted into FF0, causing FF0 to set; and the 0 that was in FF0 is shifted into
FF1.
3.48 Digital Principles and System Design
The third bit, a 0 is now put onto the data-input line, and a clock pulse is applied. The 0 is entered
into FF0, the 1 stored in FF0 is shifted into FF1, and the 0 stored in FF1 is shifted into FF2.
FF0 FF1 FF2 FF3
Data 0 0 0 0 Data
input D0 Q0 D1 Q1 D2 Q2 D3 Q3 output
1 2 3 4
CLK
FF0 FF1 FF2 FF3
1st data 0 0 0 0
bit = 0 D0 Q0 D1 Q1 D2 Q2 D3 Q3
1 2 3 4 After CLK 1
CLK 1
nd FF0 FF1 FF2 FF3
2 data 1 0 0 0
bit = 1 D0 Q0 D1 Q1 D2 Q2 D3 Q3
1 2 3 4 After CLK 2
CLK 2
rd
FF0 FF1 FF2 FF3
3 data 0 1 0 0
bit = 0 D0 Q0 D1 Q1 D2 Q2 D3 Q3
1 2 3 4 After CLK 3
CLK 3
th
FF0 FF1 FF2 FF3
4 data 1 0 1 0
bit = 1 D0 Q0 D1 Q1 D2 Q2 D3 Q3
1 2 3 4 After CLK 4,
the 4-bit
number is completely
stored in register
CLK 4
Fig. 3.53: Four bits (1010) being entered serially into the register
The last bit, a 1, is now applied to the data input, and a clock pulse is applied. This time the 1 is
entered into FF0, the 0 stored in FF0 is shifted into FF1, the 1 stored in FF1 is shifted into FF2, and
the 0 stored in FF2 is shifted into FF3. This completes the serial entry of the four bits into the shift
register, where they can be stored for any length of time as long as the flip-flops have dc power.
Synchronous Sequential Logic 3.49
To get the data out of the register, the bits must be shifted out serially and taken off the Q3 output
as Figure 3.54 illustrates. After CLK4 in the data-entry operations just described, the right-most bit 0,
appears on the Q3 output. When clock-pulse CLK5 is applied the second bit appears on the Q3 output.
Clock pulse CLK6 shifts the third bit to be output, and CLK7 shifts the fourth bit to the output. Notice
that while the original four bits are being shifted out, more bits can be shifted in. All zeros are shown
being shifted in.
FF0 FF1 FF2 FF3
Data 1 0 1
input Q0 Q1 Q2 Q3 0 1st data bit
D0 D1 D2 D3
1 2 3 4
After CLK 4
register contains
1010
CLK
FF0 FF1 FF2 FF3
0 1 0 1 nd
D0 Q0 D1 Q1 D2 Q2 D3 Q3 2 data bit
1 2 3 4
After CLK 5
register contains
0101
CLK 5
FF0 FF1 FF2 FF3
0 0 1 0 rd
D0 Q0 D1 Q1 D2 Q2 D3 Q3 3 data bit
1 2 3 4
After CLK 6
register contains
0010
CLK 6
FF0 FF1 FF2 FF3
0 0 0 1
D0 Q0 D1 Q1 D2 Q2 D3 Q3 4th data bit
1 2 3 4
After CLK 7
register contains
0001
CLK 7
FF0 FF1 FF2 FF3
0 0 0 0
D0 Q0 D1 Q1 D2 Q2 D3 Q3
1 2 3 4 After CLK 8
register contains
0000
CLK 8
Fig. 3.54 : Four bits (1010) being serially-shifted out of the register and replaced by all zeros.
3.22.3 Serial In Parallel Out shift Register
In this shift register, data bits are entered into the register in the same as serial-in serial-out shift
register. But the output is taken in parallel. Once the data are stored, each bit appears on its respective
output line and all bits are available simultaneously instead of on a bit-by-bit.
3.50 Digital Principles and System Design
Fig. 3.55: Four Bits 1111 being serially entered into shift-right register
Synchronous Sequential Logic 3.51
3.56: A serial-in parallel out shift register
3.22.4 Parallel In Serial Out Shift Register
In this type, the bits are entered in parallel i.e., simultaneously into their respective stages on
parallel lines.
Figure 3.57 illustrates a four-bit parallel in serial out register. There are four input lines XA, XB,
XC, XD for entering data in parallel into the register. SHIFT/ L O A D is the control input which allows
shift or loading data operation of the register. When SHIFT/ L O A D is low, gates G1, G2, G3 are
enabled, allowing each input data bit to be applied to D input of its respective flip-flop. When a clock
pulse is applied, the flip-flops with D = 1, will SET and those with D = 0 will RESET. Thus all four
bits are stored simultaneously.
Fig. 3.57 : Parallel in serial out shift register
When SHIFT/ L O A D is high, gates G1, G2, G3 are disabled and gates G4, G5, G6 are enabled.
This allows the data bits to shift left from one stage to the next. The OR gates at the D-inputs of the
flip-flops allow either the parallel data entry operation or shift operation, depending on which AND
gates are enabled by the level on the SHIFT/ L O A D input.
3.22.5 Parallel in Parallel Out Register
From the third and second type of registers, it is cleared that how to enter the data in parallel i.e.,
all bits simultaneously into the register and how to take data out in parallel from the register. In
3.52 Digital Principles and System Design
parallel in parallel out register, there is simultaneous entry of all data bits and the bits appear on
parallel outputs simultaneously. Figure 3.58 shows this type of register.
Parallel data inputs
X0 X1 X2 X3
FF0 FF1 FF2 FF3
Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3
input
1 2 3 4
Q3
CLK
Q0 Q1 Q2 Q3
Parallel data outputs
Fig. 3.58 : Parallel in parallel out shift register
3.22.6 Universal Shift Registers
A register which is capable of shifting data both to the right and left is called a bi-directional shift
register. A register that can shift in only one direction is called a uni-directional shift register. If the
register has shift and parallel load capabilities, then it is called a shift register with parallel load or
Universal Shift Register.
Shift registers can be used for converting serial data to parallel data, and vice-versa. If a parallel
load capability is added to a shift register, then data entered in parallel can be taken out in serial
fashion by shifting the data stroed in the register.
The functions of shift register are:
1. A clear control to clear the register to 0.
2. A CLK input for clock pulses to synchronise all operations.
3. A shift-right control to enable the shift-right operation and serial input and output lines associated
with the shift right.
4. A shift-left control to enable the shift-left operation and the serial input and output lines associated
with the shift left.
5. A parallel load control to enable a parallel transfer and the n input lines associated with the
parallel transfer.
6. n parallel output lines.
7. A control line that leaves the information in the register unchanged even though clock pulses
are continuously applied.
Synchronous Sequential Logic 3.53
Figure 3.59 illustrates a 4 bit universal shift register. It consists of four D flip-flops and four 4
input multiplexers (MUX). S0 and S1 be the two selection inputs connected to all the four multiplexers.
These two selection inputs are used to select one of the four inputs of each multiplexer. Input 0 in
each MUX is selected when S1 S0 = 00 and input 1 is selected when S1 S0 = 01. Similarly inputs 2 and
3 are selected when S1 S0 = 10 and S1 S0 = 11 respectively. The inputs S1 and S0 control the mode of
operation of the register. When S1 S0 = 00, the persent value of the register is applied to the D inputs
of the flip-flops. This is done by connecting the output of each flip- flop to the 0 input of the respective
multiplexer. The next clock pulse transfers into each flip-flops, the binary value it held previously,
and hence no change of state occurs. When S1 S0 = 01, terminal 1 of the multiplexer inputs has a path
to the D inputs of the flip-flops. This causes a shift-right operation with the lefter serial input transferred
into flip-flop A4. When S1 S0 =10, a shift-left operation results with the right serial input going into
flip-flop A1. Finally when S1 S0 = 11 the binary information on the parallel input liens (I1, I2, I3, and I4)
are transferred into the register simultaneously during the next clock pulse. The function table of bi-
directional shift register with parallel inputs and paralle outputs is shown in Table 3.49
Table 3.49 : Function table
Mode Control
Operation
S1 S0
0 0 No change
0 1 Shift-right
1 0 Shift-left
1 1 Parallel load
Parallel outputs
Q3 Q2 Q1 Q0
FF3 FF2 FF1 FF0
Clear Q Q Q Q
D D D D
CLK
S1 MUX MUX MUX MUX
S0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Serial Input Serial Input
for shift-right for shift-left
I3 I2 I1 I0
Parallel inputs
Fig. 3.59 : 4-bit Uniersal shift register
3.54 Digital Principles and System Design
Bi-direction Shift Register: When mode control M = 1, the AND gates G1 through G4 are enabled
and the data at D8 is shifted to the right when the clock pulses are applied, and thus it acts as a shift-
right register. When M = 0, the AND gates G5 through G8 are enabled allowing the data at D1 to be
shifted to the left, and thus it acts as a shift- left register. M should be changed only when CLK = 0,
otherwise the data stored in the register may be altered. The 4-bit bi-directional shift register is shown
in Figure 3.60.
Shift-right
serial input
Fig. 3.60: 4-bit bi-directional shift register
3.23 COUNTERS
A counter is a sequential circuit consisting a set of flipflops to count the sequence of the input
pulses presented to it in digital form. The number of flipflops used and the way in which they are
connected determine the number of states (called the modulus) and also the specific sequence of
states that the counter goes through during each complete cycle.
Counters are classified into two broad categories according to the way they are clocked:
Asynchronous Synchronous
Asynchronous Counters: In asynchronous (Ripple) counters, the first flip-flop is clocked by the
external clock pulse and then each successive pulse is clocked by the output of the preceding flipflop.
Synchronous Counters: In synchronous counters, the clock input is connected to all the flipflops so
that they are clocked simultaneously.
ASYNCHRONOUS (RIPPLE) COUNTERS
3.23.1 2 Bit Asynchronous Binary Counter
In 2 bit asynchronous binary counter, the clock (CLK) is applied to the clock input of the first
flipflop (FF0) only. The second flipflop, FF1, is triggered by the Q0 output of FF0. Because of the
inherent propagation delay time through a flipflop, a transition of the input clock pulse (CLK) and a
transition of the Q0 output of FFO can never occur at exactly the same time. Therefore, the two
flipflops are never simultaneously triggered, so the counter operation is asynchronous. Figure 3.61
shows a 2 bit asynchronous binary counter.
Synchronous Sequential Logic 3.55
Fig. 3.61: 2 bit asynchronous binary counter
Figure 3.62 shows the timing diagram for 2 bit ripple counter. It illustrates the changes in the
state of the flipflop outputs is response to the clock. The negative-going edge of CLK 1 causes the Q0
output of FFO to go HIGH. It has no effect on FF1 because a negative-going transition must occur to
trigger the flipflop. After the leading edge of CLK 1, Q0 = 1 and Q1 = 0.
The negative-going edge of CLK 2 causes Q0 go LOW, and it triggers FF1, causes Q1 to go HIGH.
After the leading edge of CLK 2, Q0 = 0 and Q = 1.
The negative-going edge of CLK 3 causes Q0 to go HIGH again and it has no effect on FF1. Thus
after the leading edge of CLK 3, Q0 = 1 and Q1 = 1.
The negative-going edge of CLK 4 causes Q0 to go LOW, causing Q1 to go LOW. After the leading
edge of CLK 4, Q0 = 0 and Q1 = 0. The counter has now recycled to its original state.
Since it goes through a binary sequence (00, 01, 10, 11) this counter is a binary counter.
Fig. 3.62: Timing diagram for 2 bit counter
3.23.2 3 Bit Asynchronous Binary Counter
A 3 bit asynchronous binary counter is shown in Figure 3.63. The operation is the same as that of
the 2 bit counter, except that the 3 bit counter has eight states, due to its 3 flipflops. The timing
diagram for 3 bit asynchronous binary counter is shown in Figure 3.64.
3.56 Digital Principles and System Design
Fig. 3.63: 3 bit asynchronous binary counter
Fig. 3.64: Timing diagram
3.23.3 Propagation Delay
Asynchronous counters are commonly referred to as Ripple Counters for the following reason:
The effect of the input clock pulse is first felt by FF0. This effect cannot get to FF1 immediately
because of the propagation delay through FF0. Then there is the propagation delay through FF1
before FF2 can be triggered. Thus the effect of an input clock pulse “ripples” through the counter,
taking same time, due to propagation delays, to reach the last flipflop.
Fig. 3.65: Propagation delays
Figure 3.65 shows the ripple clocking effect for the first four clock pulses, with the propagation
delays indicated. The propagation delay of the first stage is added in the propagation delay of second
stage to decide the transition time for third stage. The cumulative delay of an asynchronous counter is
Synchronous Sequential Logic 3.57
a major disadvantage in many applications because it limits the rate at which the counter clocked and
creates decoding problems.
For example, each flipflop has a propagation delay for 10 ns, total delay time,
tp = 3 10 = 30 ns
The maximum clock frequency,
fmax . M H z.
t p
3.23.4 4 Bit Asynchronous Binary Counter
A 4 bit asynchronous binary counter is shown in Figure 3.66. This counter has 16 states, due to 4
flipflops. The timing diagram is shown in Figure 3.67 for 16 clock pulses.
Fig. 3.66: 4 bit asynchronous counter
Fig. 3.67: Timing diagram
3.23.5 Asynchronous Decade (MOD 10) Counters
The modulus (N) of a counter is the number of unique states that the counter will sequence
through. The maximum possible states (maximum modulus) of a counter is 2n, where ‘n’ is the number
of flipflops in the counter.
3.58 Digital Principles and System Design
Counters can also be designed to have a number of States in their sequence that is less than the
maximum of 2n. The resulting sequence is called a truncated sequence.
One common modulus for counters with truncated sequences is ten, called MOD 10.
Fig. 3.68: Asynchronous Decade Counter
n N
n = 4 = Number of flipflops
Counters with 10 states in their sequence are called decade counters. A decade counter with a
count sequence of zero (0000) through nine (1001) is a BCD decade counter. It must recycle back to
0000 state after the 1001 state. To make the counter recycle after the count of nine (1001) is to decode
count ten (1010) with a NAND gate and connect the output (0) of the NAND gate to the clear (CLR)
inputs of the flipflops as shown in Figure 3.68. The timing diagram of decade counter is shown in
Figure 3.69.
Fig. 3.69: Timing Diagram
3.24 SYNCHRONOUS COUNTERS
The term ‘synchronous’ refers to events that have a fixed time relationship with each other. In
synchronous counter, the clock pulses are applied to all flipflops simultaneously. Hence there is
minimum propagation delay. Table 3.50shows the comparison between synchronous and asynchronous
counters.
Synchronous Sequential Logic 3.59
TABLE 3.50 : Comparison between Synchronous and asynchronous counters
Sl. No. Asynchronous Counters Synchronous Counters
1. All the flipflops are not clocked All the flipflops are clocked simulta-
simultaneously. neously.
2. The delay times of all flip-flops There is minimum propagation delay.
are added. Therefore there is
considerable propagation delay.
3. The maximum frequency depends The maximum frequency does not
on modulus. not depend on modulus.
4. Logic circuit is very simple. Circuit is complex.
5. Minimum number of logic devices The number of logic devices is more
are needed. than ripple counter.
6. Cheaper than synchronous counters. Costlier than ripple counters.
3.24.1 Two Bit Synchronous Counter
In this counter the clock signal is connected in parallel to clock inputs of both the flipflops FF0
and FF1. The output of FF0 (Q0) is connected to J1 and K1 inputs of the second flipflop FF1. Assume
that the counter is initially in the binary 0 states i.e., both flipflops are RESET. When positive edge of
the first clock pulse is applied, FF0 will toggle because J0 = K0 = 1, whereas FF1 output will remains
zero because J1 = K1 = 0. After first clock pulse Q0 = 1 and Q1 = 0.
When the leading edge of CLK 2 occurs, FF0 will toggle and Q0 will go Low. Since FF1 has a
HIGH (Q0 = 1) on its J1 and K1 inputs at the triggering edge of this clock pulse, the flipflop toggles and
Q1 goes HIGH. Thus after CLK2, Q0=0 and Q1=1.
When the positive edge of CLK3 occurs, FF0 again toggles to the SET state (Q0=1) and FF1
remains SET (Q1=0) because its J1 and K1 inputs and both LOW (Q0 = 0). After this triggering edge,
Q0 = 1 and Q1 = 1.
Finally, at the positive edge of CLK4, Q0 and Q1 go LOW because they both have a toggle condition
on their J and K inputs. i.e., Q0 = Q1 = 0. The counter has now recycled to its original state.
Figure 3.70 shows a 2 bit synchronous binary counter and Figure 3.71 shows the timing diagram
for the counter.
3.60 Digital Principles and System Design
Fig. 3.70: 2 Bit synchronous binary counter
Fig. 3.71: Timing Diagram
3.24.2 3 Bit Synchronous Binary Counter
A 3 bit synchronous binary counter is constructed with three JK flipflops and an AND gate as
shwon in Figure 3.72. The output of FF0 (Q0) changes on each clock pulse as the counter progresses
from its original state to its final state and then back to its original state as shown in the timing
diagram of Figure 3.73. To produce this operation, FF0 must be held in the toggle mode by constant
HIGH, on its J0 and K0 inputs.
The output of FF1 (Q1) goes to the opposite state following each time Q0 = 1. This change occurs
at CLK 2, CLK 4, CLK 6 and CLK 8. To produce this operation, Q0 is connected to the J1 and K1
inputs of FF1. When Q0 = 1, and a clock pulse occurs, FF1 is in the toggle mode and therefore changes
state. When Q0 = 0, FF1 remains in in its present state.
Synchronous Sequential Logic 3.61
High
FF0 FF1 Q1 FF2
Q0
J0 J1 J2 Q2
1 2 3
K0 K1 K2
CLK
Fig. 3.72 : 3 bit synchronous binary counter
CLOCK Pulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0
Fig. 3.73: Timing Diagram
3.62 Digital Principles and System Design
Q2 changes state both times, it is preceded by the unique condition in which both Q0 and Q1 are
HIGH. This condition is detected by the AND gate and applied to the J2 and K2 inputs of FF2. Whenever
Q0 = Q1 = 1, the output of the AND gate makes the J2 = K2 = 1 and FF2 toggles on the following clock
pulse. Otherwise the J2 and K2 inputs of FF2 are held LOW by the AND gate input and FF2 does not
change state.
3.24.3 4 Bit Synchronous Binary Counter
In this counter 4 JK flipflops and two AND gates are used as shown in Figure 3.74. The operation
of first 3 flipflops is same as the 3 bit counter. For the fourth stage, flip-flop has to change the state,
when Q0 = Q1 = Q2 = 1. This condition is decoded by 3-input AND gate G2. Therefore, when Q0 = Q1
= Q2 = 1, flipflop FF3 toggles and for all other times it is in no change condition. The timing diagram
for this counter is shown in Figure 3.75. Points where the AND gate outputs are HIGH are indicated
by the shaded areas.
High
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
1 2 3 4
K0 K1 K2 K3
CLK
Fig. 3.74: 4 bit synchronous binary counter
Fig. 3.75: Timing diagram
3.24.4 4 Bit Synchronous Decade Counter
BCD decade counter has a count sequence from 0000 to 1001 (9). After 1001 state it must recycle
back to 0000 state. This counter requires four flipflops and AND/OR logic as shown in Figure 3.76.
The timing diagram for the decade counter is shown in Figure 3.77.
Synchronous Sequential Logic 3.63
J K
J K Q Q
J K Q Q
J K QQQ QQ
High
FF0 FF1 FF2 FF3
J0 Q0 J1 J2 J3
Q1 Q2 Q3
1 2 3 4
Q3
K0 K1 K2 K3
CLK
Fig. 3.76: 4 Bit Synchronous Decade Counter
Fig. 3.77: Timing Diagram
3.24.5 Synchronous UP/DOWN Counter
An up/down counter is a bi-directional counter, capable of progressing in either direction through
a certain sequence. A MOD 8 (3 bit) UP/DOWN counter that advances upward through its sequence
(0, 1, 2, 3, 4, 5, 6, 7) and then can be reversed so that it goes through the sequence in the opposite
direction (7, 6, 5, 4, 3, 2, 1, 0) is an illustration of up/down sequential operation.
To form a parallel (synchronous) UP/DOWN counter, the control input (UP/DOWN) is used to
allow either the normal output or the inverted output of one flipflop to the J and K inputs of the next
flipflop. When UP/DOWN = 1, the MOD 8 counter will count from 000 to 111 and UP/DOWN = 0,
it will count from 111 to 000.
3.64 Digital Principles and System Design
When UP/DOWN = 1, it will enable AND gates 1 and 3 and disable AND gates 2 and 4. This
allows the Q0 and Q1 outputs through the AND gates to the J and K inputs of the following flipflops,
so that the counter counts up as pulses are applied. When UP/DOWN = 0, the reverse action takes
place.
J K Q U P Q D O W N
J K Q Q U P Q Q D O W N
UP
Q1 UP
1
High 3
FF0 FF1 FF2
J0 J1 J2 Q2
Q0 Q1
UP/DOWN 1 2 3
Q0 Q1
K0 K1 K2 Q2
DOWN 2 4
Q0 DOWN
CLK
Fig. 3.78: 3 Bit (MOD 8) UP/DOWN Synchronous Counter
3.25 MODULUS-N-COUNTERS
The counter with ‘n’ flipflops has maximum MOD number 2n. Find the number of flipflops (n)
required for the desired MOD number (N) using the equation,
n N
(i) For example, a 3 bit binary counter is a MOD 8 counter. The basic counter can be modified to
produce MOD numbers less than 2n by allowing the counter to skin those are normally part of counting
sequence.
n=3
N=8
2n = 23 = 8 = N
(ii) MOD 5 Counter:
2n = N
2n = 5
22 = 4 less than N.
23 = 8 > N (5)
3 flipflops are required.
Synchronous Sequential Logic 3.65
(iii) MOD 10 Counter:
n N
, l e s s t h a n N ;
N .
To construct any MOD-N counter, the following method can be used.
1. Find the number of flipflops (n) required for the desired MOD number (N) using the equation,
n N .
2. Connect all the flipflops as a required counter.
3. Find the binary number for N.
4. Connect all flipflop outputs for which Q = 1 when the count is N, as inputs to NAND gate.
5. Connect the NAND gate output to the CLR input of each flipflop.
When the counter reaches Nth state, the output of the NAND gate goes LOW, resetting all flipflops
to 0. Therefore the counter counts from 0 through N 1.
For example, MOD-10 counter reaches state 10 (1010). i.e., QQ QQ The outputs Q
and Q are connected to the NAND gate and the output of NAND gate goes LOW and resetting all
flipflops to zero. Therefore MOD-10 counter counts from 0000 to 1001 and then recycles to the zero
value. The MOD-10 counter circuit is shown in Figure 3.79.
High
FF0 FF1 FF2 FF3
J0 J1 J2 J3
Q0 Q1 Q2 Q3
CLK 1 2 3 4
K0 K1 K2 K3
CLR
Fig. 3.79 : MOD-10 (Decade) Counter
3.26 SHIFT REGISTER COUNTERS
A shift register counter is a basically a shift register with the serial output connected back to the
serial input to produce special sequences. Two of the most common types of shift register counters
are:
(i) Johnson Counter (Shift Counter)
(ii) Ring Counter.
3.66 Digital Principles and System Design
3.26.1 Johnson Counter (Shift Counter)
In a Johnson counter, the complement of the output of the last flipflop is connected back to the D
input of the first flipflop. This feedback arrangement produces a characteristic sequence of states as
shown in Table 3.51 for a 4 bit Johnson counter. The 4 bit sequence has a total of eight states. In
general, a Johnson counter will produce a modulus of 2n, where ‘n’ is the number of stages in the
counter. For example 5 bit Johnson counter has 10 states.
TABLE 3.51 : 4 Bit Johnson Sequence
Clock Pulse Q0 Q1 Q2 Q3
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
0 0 0 0 0
Figure 3.80 shows the circuit of Johnson Counter. The Q output of each stage is connected to the
D input of the next stage. The complement of the output of FF3 Q3 is connected back to the D input
of FF0. The counter fills up with 1s from left to right and then fills up 0s again. The timing diagram of
4-bit Johnson Counter is shown in Figure 3.81.
1 2 3 4
Fig. 3.80: Four-bit- Johnson counter
Fig. 3.81: Timing sequece for a 4-bit Johnson counter
Synchronous Sequential Logic 3.67
3.26.2 Ring Counters
The ring counter utilizes one flipflop for each state in its sequence. It has the advantage that
decoding gates are not required. In case of a 10 bit ring counter, there is a unique output for each
decimal digit.
Figure 3.82 shows the circuit of a ring counter. The output Q0 sets D1 input, Q1 sets D2, Q2 sets D3
and Q3 is fed back to D0. Because of these connections, bit are shifted left one position per positive
clock edge and fed back to the input. All the flipflops are clocked together. When CLR goes low then
back to high, the output is 0000. The first positive clock edge shifts MSB to LSB position and other
bits to one position left so that the output becomes Q = 0010. This process continues on second and
third positive clock edge so that successive outputs are 0100 and 1000. The fourth positive clock edge
starts the cycle all over again and output is 0001. Thus the stored 1 bits follow a circular path (i.e., the
stored 1 bits move left through all flipflops and the final flipflop sends it back to the first flipflop).
This action has given it the name of ring counter. Figure 3.83.
Q0 Q1 Q2
FF0 FF1 FF2 FF3 Q3
D0 Q D1 Q D2 Q D3 Q
CLK 1 2 3 4
Fig. 3.82 : Ring Counter
Fig. 3.83: Timing Diagram
3.68 Digital Principles and System Design
3.27 DESIGN OF COUNTERS
The procedure for design of counters as follows:
Step 1: Specify the counter sequence and draw a state diagram.
Step 2: Derive a next-state table from the state diagram.
Step 3: Make the state assignment and develop a transition table showing the flipflop inputs required.
Step 4: Draw the karnaugh maps for each input of each flipflop.
Step 5: Derive the logic expression for each flipflop input from the K-maps.
Step 6: Implement the expressions with combinational logic and combine with the flipflops to form
the counter.
Example 3.10: Using JK flipflops, design a synchronous counter which counts in the sequence,
000, 001, 010, 011, 100, 101, 110, 111, 000.
Solution:
Step 1: State Diagram
Step 2: State Table
Present State Next State
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000
Synchronous Sequential Logic 3.69
Step 3: Excitation Table for Counter
Excitation Table for JK flipflop:
Q(t) Q(t + 1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Excitation Table for Counter:
Present State Next State Flipflop Inputs
q2 q1 q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Step 4: K-map Simplification
For J2 For K2
Q1Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 1 0 0 X X X X
1 X X X X 1 0 0 1 0
J QQ K QQ
For J1 For K1
Q1Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 1 X X 0 X X 1 0
1 0 1 X X 1 X X 1 0
J Q K Q
3.70 Digital Principles and System Design
For J0 For K0
Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 1 X X 1 0 X 1 1 X
1 0 X X 1 1 X 1 1 X
J Q K Q
Step 5: Circuit Diagram
J K
J Q K Q
J QQ K QQ
Fig.3.84 : Synchronous Counter
Example 3.11: Design a MOD-10 synchronous counter using JK flipflops. Write excitation table and
state table.
Solution n N
n ; 4 flipflops are required.
Step 1: State Diagram
Synchronous Sequential Logic 3.71
Step 2: State Table
Present State Next State
a b
b c
c d
d e
e f
f g
g h
h i
i j
j a
Step 3: Transition Table
Present State Next State
q3 q2 q1 q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
Step 4: Excitation Table
Present State Next State Excitation Inputs
q3 q2 q1 q0 Q3 Q 2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
3.72 Digital Principles and System Design
Step 5: K-map Simplification
For J3 map For K3 map
q1q0 q1q0
q3q2 00 01 11 10 q3q2 00 01 11 10
00 0 0 0 0 00 X X X X
01 0 0 1 0 01 X X X X
11 X X X X 11 X X X X
10 X X X X 10 0 1 X X
J q qq K q
For J2 For K2
q1q0 q1q0
q3q2 00 01 11 10 q3q2 00 01 11 10
00 0 0 1 0 00 X X X X
01 X X X X 01 0 0 1 0
11 X X X X 11 X X X X
10 0 0 X X 10 X X X X
J qq K qq
For J1 For K1
q1q0
q1q0
q3q2 00 01 11 10 q3q2 00 01 11 10
00 0 1 X X 00 X X 1 0
01 0 1 X X 01 X X 1 0
11 X X X X 11 X X X X
10 0 0 X X 10 X X X X
J q q K q
Synchronous Sequential Logic 3.73
For J0 For K0
q1q0 q1q0
q3q2 00 01 11 10 q3q2 00 01 11 10
00 1 X X 1 00 X 1 1 X
01 1 X X 1 01 X 1 1 X
11 X X X X 11 X X X X
10 1 X X X 10 X 1 X X
J K
Step 6: Circuit Diagram J K
J qq K q
J qq K qq
J q qq K q
High
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
1 2 3 4
K0 K1 K2 K3 Q3
CLK
Q0 Q1 Q2 Q3
Fig. 3.85 : MOD 10 Synchronous Counter
Example 3.12: Design a synchronous 3-bit gray code up counter with the help of excitation table.
Solution: Gray code sequence: 000, 001, 011, 010, 110, 111, 101, 100.
Step 1: State Diagram
Fig. 3.86
3.74 Digital Principles and System Design
Step 2: State Table
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
Step 3: Excitation Table
Excitation Table for JK flipflops.
Q(t) Q(t + 1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Present State Next State Excitation Inputs
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 1 1 0 1 X X 0 0 X
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
1 0 1 1 0 0 X 0 0 X X 1
1 0 0 0 0 0 X 1 0 X 0 X
Synchronous Sequential Logic 3.75
Step 4: K-map Simplification
For J2 For K2 For J1
Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
00 0 0 00 X X 00 0 1
01 1 0 01 X X 01 X X
11 X X 11 0 0 11 X X
10 X X 10 1 0 10 0 0
J2 = Q1 Q K2 = Q Q J1 = Q Q0
For K1 For J0 For K0
Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
00 X X 00 1 X 00 X 0
01 0 0 01 X 0 01 1 X
11 0 1 11 1 X 11 X 0
10 X X 10 X 0 10 1 X
K QQ J Q Q Q Q K QQ Q Q
Q Q = Q Q
Step 5: Circuit Diagram
J Q Q K Q Q
J Q Q K QQ
J Q Q K Q Q
FF0 FF1 FF2
J0 Q0 J1 Q1
J2 Q2
1 2 3
K0 Q0 K1 Q1 K2 Q2
CLK
Fig. 3.87 : 3 bit Gray code up counter
3.76 Digital Principles and System Design
Example 3.13: Design a 3 bit (MOD 8) synchronous UP-DOWN counter.
Solution: When UP/DOWN = 1, UP mode, UP/DOWN = 0, DOWN mode.
Step 1: State Diagram
Fig. 3.88
Step 2: State Table
Control input Present State Next State
UP/DOWN
0 a h
0 b a
0 c b
0 d c
0 e d
0 f e
0 g f
0 h g
1 a b
1 b c
1 c d
1 d e
1 e f
1 f g
1 g h
1 h a
Synchronous Sequential Logic 3.77
Step 3: Excitation Table
Control Input Pressure State Next State Excitation Inputs
UP/DOWN (C) Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 1 1 1 1 X 1 X 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
1 1 1 1 1 1 0 X 0 X 0 X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
Step 4: K-map Simplification
For J2 For K2
Q1Q0 Q1Q0
CQ2 00 01 11 10 CQ2 00 01 11 10
00 1 0 0 0 00 X X X X
01 X X X X 01 1 0 0 0
11 X X X X 11 0 0 1 0
10 0 0 1 0 10 X X X X
J C QQ C QQ K C QQ C QQ
3.78 Digital Principles and System Design
For J1 For K1
Q1Q0
Q1Q0
CQ2 00 01 11 10 CQ2 00 01 11 10
00 1 0 X X 00 X X 0 1
01 1 0 X X 01 X X 0 1
11 0 1 X X 11 X X 1 0
10 0 1 X X 10 X X 1 0
J C Q C Q K C Q C Q
For J0 For K0
Q1Q0 Q1Q0
CQ2 00 01 11 10 CQ2 00 01 11 10
00 1 X X 1 00 X 1 1 X
01 1 X X 1 01 X 1 1 X
11 1 X X 1 11 X 1 1 X
10 1 X X 1 10 X 1 1 X
J K
Step 5: Circuit Diagram
C =U P / D O W N
J K
J C Q C Q K C Q C Q
J C QQ C Q Q K C QQ C Q Q
C = UP/DOWN FF0 FF1 FF2
High J0 Q0 J1 Q1 J2 Q2
1 2 3
K0 Q0 K1 Q1 K2 Q2
CLK
Fig. 3.89 : MOD 8 Synchronous UP-DOWN Counter
Synchronous Sequential Logic 3.79
Example 3.14: Design a four state down counter using type T design procedure.
Solution
n N
n = 2 ; Two flipflops are required.
Step 1: State Diagram
Fig. 3.90
Step 2: State Table
Present State Next State
3 0
2 3
1 2
0 1
Step 3: Transition Table
Present State Next State
Q1 Q0 Q1 Q0
1 1 0 0
1 0 1 1
0 1 1 0
0 0 0 1
Step 4: Excitation Table
Excitation Table for Excitation Table for
T flipflop down counter
Q(t) Q(t + 1) T Present State Next State Excitation Inputs
0 0 0 Q1 Q0 Q1 Q0 T1 T0
0 1 1 1 1 0 0 1 1
1 0 1 0 1 1 0 1 1
1 1 0 0 0 0 1 0 1
3.80 Digital Principles and System Design
Step 5: K-map Simplification
Q0 Q0
Q1 0 1 Q1 0 1
0 1 0 0 1 1
1 1 0 1 1 1
T Q T0 = 1
Step 6: Circuit Diagram
Fig. 3.91 : DOWN Counter
Example 3.15: Design a synchronous counter using JK flip-flops to count the following sequence:
“1- 3 - 15 - 5 - 8 - 2 - 0 - 12 - 6 - 9”.
Step 1: State Diagram
0001
1001 0011
1111
0110
1100 0101
0000 1000
0010
Synchronous Sequential Logic 3.81
Step 2: State Table
Present State Next State
0001 0011
0011 1111
1111 0101
0202 1000
1000 0010
0010 0000
0000 1100
1100 0110
0110 1001
1001 0001
Step 3: Excitation Table for JK Flip-Flop
Present State Next State Inputs
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Excitation Table for Counter:
Qn Qn+1 FF Inputs
q3 q2 q1 q0 Q3 Q2 Q1 Q0 J3 J2 J1 J0 K3 K2 K1 K0
0 0 0 1 0 0 1 1 0 0 1 X X X X 0
0 0 1 1 1 1 1 1 1 1 X X X X 0 0
1 1 1 1 0 1 0 1 X X X X 1 0 1 0
0 1 0 1 1 0 0 0 1 X 0 X X 1 X 1
1 0 0 0 0 0 1 0 X 0 1 0 1 X X X
0 0 1 0 0 0 0 0 0 0 X 0 X X 1 X
0 0 0 0 1 1 0 0 1 1 0 0 X X X X
1 1 0 0 0 1 1 0 X X 1 0 1 0 X X
0 1 1 0 1 0 0 1 1 X X 1 X 1 1 X
1 0 0 1 0 0 0 1 X 0 0 X 1 X X 0
3.82 Digital Principles and System Design
Step 4: K - Map simplification
For J3 For K3
Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q 00 01 11 10
2
00 1 0 1 0 00 X X X X
01 X 1 X 1 01 X X X X
11 X X X X 11 1 X 1 X
10 X X X X 10 1 1 X X
J Q Q QQ Q Q K Q
For J2 For K2
Q1Q0
Q1Q0
Q3Q2 00 01 11 10 Q3Q 00 01 11 10
2
00 1 0 1 0 00 X X X X
01 X X X X 01 X 1 X 1
11 X X X X 11 0 X 0 X
10 0 0 X X 10 X X X X
J QQ Q Q Q K Q
For J1 For K1
Q1Q0
Q1Q0
Q3Q2 00 01 11 10 Q3Q 00 01 11 10
2
00 0 1 X X 00 X X 0 1
01 X 0 X X 01 X X X 1
11 1 X X X 11 X X 1 X
10 1 0 X X 10 X X X X
J Q Q Q Q Q Q Q Q K Q Q Q
For J0 For K0
Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10
00 X X X X 00 X 0 0 X
01 X X X X 01 X 1 X X
11 1 X 1 X 11 X X 0 X
10 1 1 X X 10 X 0 X X
J Q K Q Q
Synchronous Sequential Logic 3.83
Step 5: Circuit Diagram
J0 Q0 J1 Q1 J2 Q2 J3 Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3
CLK
3.84 Digital Principles and System Design
Example 3.16: Using D flip flops design a synchronous counter which counts in the sequence, 000,
001, 010, 011, 100, 101, 110, 111, 000.
Solution:
Step 1: State Diagram
000 001
111 010
110 011
101
100
Step 2: State Table
Present state Next state
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000
Step 3: Excitatio table for counter
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Synchronous Sequential Logic 3.85
Excitation table for D flip flop
Present table Next state Flip Flop Inputs
q2 q1 q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
Step 4: K - map simplification
For D2 For D1
Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 1 0 0 0 1 0 1
1 1 1 0 1 1 0 1 0 1
D2 Q2 Q1 Q2 Q0 D1 Q1Q0 Q1 Q0
Q1 Q0
For D0
Q1Q0
Q2 00 01 11 10
0 1 0 0 1
D0 Q0
1 1 0 0 1
3.86 Digital Principles and System Design
Step 5: Circuit Diagram
D0 Q0
D1 Q1 Q 0
D2 Q2 Q1 Q2 Q0
Q2 Q0
D0 Q0 D1 Q1 D2 Q2
Q1 Q0
1 2 3
Q0 Q1 Q2
Q 2 Q1
CLK
Example 3.17: Using RS-FFs design a parallel counter which counts in the sequence.
000, 111, 101, 110, 001, 010, 000, ...
Synchronous Sequential Logic 3.87
Solution:
Excitation table Function Table
Q Q(t+1) S R S R Q Q’
0 0 0 X 0 0 N C
0 1 1 0 0 1 0 1
1 0 0 1 1 0 1 0
1 1 X 0 1 1 Indeterminate
Step 1: State Diagram
000
010
111
001
101
110
Step 2: State Table
Present table Next state Flip Flop Inputs
A B C A(t+1) B(t+1) C(t+1) S1 R1 S2 R2 S3 R3
0 0 0 1 1 1 1 0 1 0 1 0
1 1 1 1 0 1 X 0 0 1 X 0
1 0 1 1 1 0 X 0 1 0 0 1
1 1 0 0 0 1 0 1 0 1 1 0
0 0 1 0 1 0 0 X 1 0 0 1
0 1 0 0 0 0 0 X 0 1 0 X
0 1 1 Don’t care condition
1 0 0
3.88 Digital Principles and System Design
Step 3: K-Map
S1 R1
BC BC
A 00 01 11 10 A 00 01 11 10
0 1 X 0 X X X
1 X X X 1 X 1
S1 B'C ' R1 BC '
S2 R2
BC BC
A 00 01 11 10 A 00 01 11 10
0 1 1 X 0 X 1
1 X 1 1 X 1 1
S2 B' R2 B
S3 R3
BC BC
A 00 01 11 10 A 00 01 11 10
0 1 X 0 1 X X
1 X X 1 1 X 1
S3 B'C ' AB R 3 B'C
Step 4: Circuit Diagram
Synchronous Sequential Logic 3.89
A
S1
B’C’
A’
R1
AB
B
S2
B’
R2
C
S3
C’
R3
CLK
3.28 UP-DOWN RIPPLE COUNTER
The UP-DOWN counter is a combination of the up-counter and the down-counter. As the UP-
DOWN counter has the capability of counting upwards as well as downwards, it is also called
Multimode counter. In an UP-counter, each flip-flop is triggered by the normal output of the preceding
flip-flop; in a DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-
flop. In both the counters, the first flip-flop is triggered by the input pulses.
CUP
VCC
FF0 FF1 FF2 FF3
J0 Q0 1 J1 Q1 3 J2 Q2 5 J3 Q3
CLK
K0 Q0 K1 Q1 K2 Q2 K3 Q3
2 4 6
CDOWN
Fig. 3.92 : Asynchronous 4-bit UP-DOWN counter
Three logic gates per stage are required to switch the individual stages from COUNT-UP to COUNT-
DOWN mode. The logic gates are used to allow either the non-inverted output or the inverted output
of one flip-flop to the clock input of the following flip-flop, depending on the status of the
3.90 Digital Principles and System Design
control inputs. When the CUP line is held at 1 while the CDOWN line is at 0, the lower AND gates (2, 4
and 6) will be disabled and their outputs are zero. So, it will have no effect on the outputs of OR gates.
Also, the upper AND gates (1, 3 and 5) will be enabled, i.e., it will allow QA to pass through the OR
gate and into the clock input of the B flip-flop. Similarly, the QB and QC output will be gated into the
clock input of flip-flops C and D respectively. Thus, as input pulses are applied, the counter will count
up and follow a natural binary counting sequence from 0000 to 1111.
With CUP = 0, CDOWN = 1, the upper AND gates (1, 3 and 5) are disabled and the lower AND gates
(2, 4 and 6) are enabled, allowing Q ,Q and Q , to pass through to the clock inputs of the following
flip-flops. Thus, for this condition, the counter will count down as input pulses are applied.
When the control inputs are both 0 or 1, the counter will not count up or count down because the
clock inputs of B, C and D will be held constant at either 0 or 1. The flip-flop (FF0) will keep toggling
because it is always being clocked. These conditions are not normally used.
TABLE 3.52 : Truth Table of 4-bit up-down counter
COUNT-UP Mode COUNT-DOWN Mode
States QD QC QB QA States QD QC QB QA
0 0 0 0 0 15 1 1 1 1
1 0 0 0 1 14 1 1 1 0
2 0 0 1 0 13 1 1 0 1
3 0 0 1 1 12 1 1 0 0
4 0 1 0 0 11 1 0 1 1
5 0 1 0 1 10 1 0 1 0
6 0 1 1 0 9 1 0 0 1
7 0 1 1 1 8 1 0 0 0
8 1 0 0 0 7 0 1 1 1
9 1 0 0 1 6 0 1 1 0
10 1 0 1 0 5 0 1 0 1
11 1 0 1 1 4 0 1 0 0
12 1 1 0 0 3 0 0 1 1
13 1 1 0 1 2 0 0 1 0
14 1 1 1 0 1 0 0 0 1
15 1 1 1 1 0 0 0 0 0
0 0 0 0 0 15 1 1 1 1
Synchronous Sequential Logic 3.91
3.29 HDL FOR SEQUENTIAL LOGIC CIRCUITS
3.29.1 S-R Latch
S-R latch using NOR gates is one of the sequential logic circuit. Two NOR gates are cross coupled
so that the output of NOR gate 1 is connected to one of the inputs of NOR gate 2 and vice versa. The
latch has two inputs S (set) and R (Reset) and two outputs Q and QN. Figure 3.93 shows the S-R latch
using NOR gates and HDL program for S-R latch is given.
S R Q QN
0 0 Last Q Last QN
0 1 0 1
1 0 1 0
1 1 1 1
Fig. 3.93 : S-R latch
library IEEE;
use IEEE . std_logic_1164 . all;
entity srlatch is
port (S, R : in STD_LOGIC;
Q, QN : buffer STD_LOGIC);
end srlatch
architecture synth of srlatch is
begin
QN < = S nor Q ;
Q < = R nor QN ;
end synth;
3.29.2 D-Latch
Figure 3.94 shows a ‘D’ latch with truth table. The input conditions (00, 11) of SR latch can be
avoided by making them complement of each other. This modified SR latch is known as D-latch. The
control input of a ‘D’ latch labeled as C or CLK or ENABLE (EN). The behavioural program in
VHDL for D latch is given below:
3.92 Digital Principles and System Design
C D Q QN
1 0 0 1
1 1 1 0
0 X last Q last QN
Fig. 3.94 : D-latch
library IEEE;
use IEEE . Std_logic_1164 . all;
entity dlatch is
port (C, D : in STD_LOGIC;
Q, QN : buffer STD_LOGIC);
end dlatch;
architecture behave of dlatch is
begin
process (C, D, Q)
begin
if (C = ‘1’) then Q < = D ; }> end if;
QN < = not Q;
end process;
end behave;
3.29.3 D flip-flop
CLK D Q
0 0
1 1
0 X last Q
Fig. 3.95 : ‘D’ flipflop
Synchronous Sequential Logic 3.93
A positive edge triggered D flip-flop combines a pair of D-latches to create a circuit that samples
its D-input and changes its Q and QN outputs only at the rising edge of a controlling CLK signal. The
D-flipflop shown in Figure 3.95 has asynchronous inputs that may be used to force the flip-flop to a
particular state independent of CLK and D-inputs. These inputs labeled PR(Preset) and CLR(Clear).
The VHDL program for a positive edge triggered D-flipflop is,
library IEEE;
use IEEE . Std_logic_1164 . all;
entity Dff is
port (CLK, CLR, D, PR : in STD_Logic;
Q, QN : out STD_LOGIC);
end Vff;
architecture behave of Dff is
begin
process (CLK, CLR)
begin
if CLR = ‘1’ then Q < = ‘0’ ; QN < = ‘1’;
elsif CLK event and CLK = ‘1’ then Q < = D ; QN < = not D ;
end if;
end process;
end behave;
3.29.4 SHIFT REGISTER
The bi-directional shift register allows shifting of data either to the left or to the right side. It can
be implemented by using logic gates that enables the transfer of data from one stage to the next stage
to the right or to the left, depending on the level of a control line. Figure 3.96 shows a 4-bit bi-
directional shift register. The RIGHT/LEFT is the control input signal which allows data shifting
either towards right or towards left. If RIGHT/LEFT = 1, the shifting of data towards right. If RIGHT/
LEFT = 0, the shifting of data towards left.
When RIGHT/LEFT = 1, gates G1, G2, G3 and G4 are enabled and the state of the Q output of each
flip-flop is passed through the D-input of the following flipflop. When a clock pulse arrives, the data
are shifted one place to the right.
When RIGHT/LEFT = 0, gates G5, G6, G7 and G8 are enabled and the state of the Q output of each
flipflop is passed through the D input of the preceding flip-flop. When clock pulse arrives, the data
are shifted one place to the left.
The 4 bit type used for the input and output of the shifter is declared in package shift_types. This
package is used by entity shifter to declare ports DIN and DOUT. Port CLK , LOAD and LEFT_RIGHT
are STD_LOGIC signals used to control the functions of the shifter.
3.94 Digital Principles and System Design
Right/
Left
Data in G3 G7 G4 G8
G1 G5 G2 G6
D Q3
D D D
Q0 Q1 Q2
3 4
1 2
Q0
CLK
Fig. 3.96 : 4-bit bi-directional Shift Register
The VHDL program for bi-directional shift register is given. In this program two processes are
used:
current process
nxt process
(i) Current Process:
Process current is used to keep track of the current value of the shifter. It is a process that has a
single WAIT statement and a single signal assignment statement. When the CLK signal has a rising
edge occur, the signal assignment statement is activated and the next calculated value of shifter
(SHIFT_VAL) is written to the signal that holds the current state of the shift register (DOUT).
(ii) nxt Process:
Process nxt is used to calculate the next value of SHIFT_VAL to be written into DOUT. LOAD is
the highest priority input and if equal to ‘1’ causes SHIFT_VAL to receive the value of DIN. Otherwise,
signal LEFT_RIGHT is tested to see of the shift register is shifting left or right.
library IEEE;
use IEEE . Std_logic_1164 . all;
package SHIFT_TYPES is
subtype BIT 4 is STD_LOGIC_VECTOR (3 downto 0);
end SHIFT_TYPES;
Synchronous Sequential Logic 3.95
use WORK . shift_types.all;
library IEEE;
use IEEE . Std_logic_1164.all;
entity shifter is
port (DIN : in BIT 4;
CLK, LOAD, LEFT_RIGHT : in STD_LOGIC;
DOUT : inout BIT 4);
end shifter;
architecture synth of shifter is
signal SHIFT-VAL : BIT 4;
begin
NXT: Process (LOAD, LEFT_RIGHT, DIN, DOUT)
begin
if (LOAD = ‘1’) then
SHIFT_VAL < = }> DIN;
elseif (LEFT_RIGHT = ‘0’) THEN
SHIFT_VAL (2 downto 0) <= DOUT (3 downto 1);
SHIFT_VAL (3) < = ‘0’;
else
SHIFT_VAL (3 downto 1) < = DOUT (2 downto 0);
SHIFT_VAL (0) < = ‘0’;
end if
end process;
CURRENT : Process
begin
wait until CLK’ event and CLK = ‘1’;
DOUT < = SHIFT_VAL;
end process;
end Synth;
3.96 Digital Principles and System Design
3.29.5 COUNTERSS
The most popular MSI counter is the 74163, a synchronous 4-bit binary counter. A logic symbol
is shown in Figure 3.97 and the logic diagram is shown in Figure 3.98.
This counter can be synchronously present to any 4-bit binary number by applying the proper
levels to the parallel dat ainputs. When a LOW is applied to the LOAD input, the counter will assume
the state of the data inputs on the next clock pulse. Thus, the counter sequence can be started with any
4-bit binary number. The state table for this counter is given in Table 3.53.
Also, there is an active_LOW clear input (CLR), which synchronously resets all flip-flops in the
counter. There are two enable inputs, ENP and ENT. These inputs must be HIGH for the counter to
sequence through its binary states. When at least one input is LOW, the counter is disabled. The ripple
clock output (RCO) goes HIGH, when the counter reaches a terminal count of 15 (TC = 15).
Inputs
A B C D
CLR
LOAD
74163 TC = 15 RCO
ENT
ENP
CLK
QA QB QC QD
Outputs
Fig. 3.97 : Logic Symbol for 74163
Synchronous Sequential Logic 3.97
Fig. 3.98 : 4 bit Synchronous binary counter-Logic diagram
3.98 Digital Principles and System Design
TABLE 3.53 : State Table for 4 bit binary counter
Inputs Current State Next State
CLR LOAD ENT ENP QD QC QB QA QDN QCN QBN QAN
0 X X X X X X X 0 0 0 0
1 0 X X X X X X D C B A
1 1 0 X X X X X QD QC QB QA
1 1 X 0 X X X X QD QC QB QA
1 1 1 1 0 0 0 0 0 0 0 1
1 1 1 1 0 0 0 1 0 0 1 0
1 1 1 1 0 0 1 0 0 0 1 1
1 1 1 1 0 0 1 1 0 1 0 0
1 1 1 1 0 1 0 0 0 1 0 1
1 1 1 1 0 1 0 1 0 1 1 0
1 1 1 1 0 1 1 0 0 1 1 1
1 1 1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 0 0 1 0 0 1
1 1 1 1 1 0 0 1 1 0 1 0
1 1 1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 1 1 1 1 0 0
1 1 1 1 1 1 0 0 1 1 0 1
1 1 1 1 1 1 0 1 1 1 1 0
1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0
Each D input is driven by a 2-input multiplexer consisting of an OR gate and two AND gates. The
multiplexer output is 0 if the CLR input is asserted. Otherwise the top AND gate passes the data input
(A, B, C or D) to the output if LOAD is asserted. If neither CLR nor LOAD is asserted, the bottom
AND gate passes the output of an XNOR gate to the multiplexer output.
The XNOR gates perform the counting function. One input of each XNOR is the corresponding
count bit (QA, QB, QC or QD); the other input is ‘1’, which complements the count bit, if and only if
both enables ENP and ENT are asserted and all of the lower-order count bits are 1. The ripple carry
out (RCO) signals indicates a carry from the msb position and is 1 when all of the count bits are 1 and
ENT is asserted.
Synchronous Sequential Logic 3.99
The VHDL program for 4-bit synchronous binary counter is given below. this program uses the
IEEE.Std_logic_arith.all library, which includes the UNSIGNED type. This library includes
definitions of ‘+’ and ‘’ operators that perform unsigned addition and subtraction on UNSIGNED
operands. In this program an internal signal IQ to hold the counter value.
library IEEE;
use IEEE . Std_logic_1164 . all;
use IEEE . Std_logic_arith . all;
entity counter is
port (CLK CLR_L, LOAD_, ENP, ENT : in STD_LOGIC;
D : in UNSIGNED (3 downto 0);
Q : out UNSIGNED (3 downto 0);
RCO : out STD_LOGIC);
end counter;
architecture behave of counter is
signal IQ : UNSIGNED (3 downto 0);
begin
process (CLK, ENT, IQ)
begin
if (CLK’ event and CLK = ‘1’) then
if CLR_L = ‘0’ then IQ < = (others = > ‘0’);
elsif LOAD_L = ‘0’ the IQ < = D;
elsif (ENT and ENP) = ‘1’ then IQ < = }> IQ + 1;
end if;
end if;
if (IQ => 15) and (ENT = ‘1’) then RCO < = ‘1’;
else RCO < = ‘0’ ;
end if;
Q < = IQ ;
end process
end behave;
3.100 Digital Principles and System Design
TWO MARK QUESTIONS
1. What are the classifications of sequential circuits?
On the basis of timing of their signals 1) Synchronous sequential circuit. 2) Asynchronous
sequential circuit.
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until
directed by an input signal to change its state.
3. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are,
RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
4. What is the operation of RS flip-flop?
When R input is low and S input is high the Q output of flip-flop is set.
When R input is high and S input is low the Q output of flip-flop is reset.
When both the inputs R and S are low the output does not change
When both the inputs R and S are high the output is unpredictable.
5. What is the operation of SR flip-flop?
When R input is low and S input is high the Q output of flip-flop is set.
When R input is high and S input is low the Q output of flip-flop is reset.
When both the inputs R and S are low the output does not change.
When both the inputs R and S are high the output is unpredictable.
6. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the
output is reset.
7. What is the operation of JK flip-flop?
When K input is low and J input is high the Q output of flip-flop is set.
When K input is high and J input is low the Q output of flip-flop is reset.
Synchronous Sequential Logic 3.101
When both the inputs K and J are low the output does not change
When both the inputs K and J are high it is possible to set or reset the Flip-flop (ie) the output
toggle on the next positive clock edge.
8. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
When T=0 there is no change in the output.
When T=1 the output switch to the complement state (ie) the output toggles.
9. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change in the output results change in
the input. Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously. This condition is called race around condition’.
10. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge
triggering means that the flip-flop changes state either at the positive edge or negative edge of
the clock pulse and it is sensitive to its inputs only at this transition of the clock.
11. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the
other as a slave.
12. Explain the flip-flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to the next state.
They are,
_0_0 transition: This can happen either when R=S=0 or when R=1 and S=0.
_0_1 transition: This can happen only when S=1 and R=0.
_1_0 transition: This can happen only when S=0 and R=1.
_1_1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
13. Explain the flip-flop excitation tables for JK flip-flop
In JK flip-flop also there are four possible transitions from present state to next state. They are,
_0_0 transition: This can happen when J=0 and K=1 or K=0.
_0_1 transition: This can happen either when J=1 and K=0 or when J=K=1.
3.102 Digital Principles and System Design
_1_0 transition: This can happen either when J=0 and K=1 or when J=K=1.
_1_1 transition: This can happen when K=0 and J=0 or J=1.
14. Explain the flip-flop excitation tables for D flip-flop
In D flip-flop the next state is always equal to the D input and it is independent of the present
state. Therefore D must be 0 if Qn+1 has to 0, and if Qn+1 has to be 1 regardless the value of
Qn.
15. Explain the flip-flop excitation tables for T flip-flop
When input T=1 the state of the flip-flop is complemented; when T=0, the state of the Flip-flop
remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0_1 and 1_0
transitions must be 1.
16. Define sequential circuit?
In sequential circuits the output variables dependent not only on the present input variables but
they also depend up on the past history of these input variables.
17. Give the comparison between combinational circuits and sequential circuits.
Combinational circuits Sequential circuits Memory unit is not required Memory unity is
required. Parallel adder is a combinational circuit Serial adder is a sequential circuit
18. What do you mean by present state?
The information stored in the memory elements at any given time defines the present state of the
sequential circuit.
19. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the
sequential circuit.
20. State the types of sequential circuits?
1. Synchronous sequential circuits
2. Asynchronous sequential circuits
21. Define synchronous sequential circuit
In synchronous sequential circuits, signals can affect the memory elements only at discrete
instant of time.
Synchronous Sequential Logic 3.103
22. Define Asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memory element at any
instant of time.
23. Give the comparison between synchronous & Asynchronous sequential circuits?
24. What is race around condition?
In the JK latch, the output is feedback to the input, and therefore changes in the output results change
in the input. Due to this in the positive half of the clock pulse if J and K are both high then output
toggles continuously. This condition is known as race around condition
25. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering
means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse
and it is sensitive to its inputs only at this transition of the clock.
3.104 Digital Principles and System Design
MCQ QUESTIONS
1. An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate
each. If both S and R inputs are set to one, the outputs will be
a. Q and Q' both 1
b. No change in circuit output
c. Q and Q' both 0
d. Q and Q' complementary to each other
Answer: c. Q and Q' both 0
2. You are having a D flip-flop, which you want to use as a J-K flip-flop. The input of the D flip-
flop in terms of external inputs J and K can be written as (Consider Qn is the output of the D
flip-flop)
a. D = JQn + KQn
b. D = J’Qn + K’Qn
c. D = JQ’n + K’Qn
d. D = JQ’n + KQ’n
Answer: c. D = JQ’n + K’Qn
3. You are having a D flip-flop, which you want to use as a S-R flip-flop. The input of the D flip-
flop in terms of external inputs S and R can be written as (Consider Qn is the output of the D
flip-flop)
a. D = S + RQn
b. D = S + R’Qn
c. D = S’ + RQn
d. D = S’ + R’Qn
Answer: b. D = S + R’Qn
Synchronous Sequential Logic 3.103
4. Which of the following statements is NOT correct?
a. Race around condition occurs in a JK latch when both the inputs are one.
b. A flip flop is used to store one bit information.
c. A transparent latch is D-type flip-flop with enable (level triggered) in place of a clock.
d. Master-slave configuration is used in flip-flop to store two bits information.
Answer: d. Master-slave configuration is used in flip-flop to store two bits information.
5. The logic function depicting the behavior of the complementary output of T flip-flop is given
by
a. Q’ = T XOR Q
b. Q’ = T XNOR Q
c. Q’ = T OR Q
d. Q’ = T NOR Q
Answer: b. Q’ = T XNOR Q
6. To operate correctly, starting a ring shift counter requires:
a. clearing all the flip-flops
b. presetting one flip-flop and clearing all others
c. clearing one flip-flop and presetting all others
d. presetting all the flip-flops
Answer: b. presetting one flip-flop and clearing all others
7. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On
the sixth clock pulse, the sequence is ________.
a. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
b. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
c. Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
d. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
Answer: c. Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
3.104 Digital Principles and System Design
8. How many clock pulses will be required to completely load serially a 5-bit shift register?
a. 2
b. 3
c. 4
d. 5
Answer: d. 5
9. How is a J-K flip-flop made to toggle?
a. J = 0, K = 0
b. J = 1, K = 0
c. J = 0, K = 1
d. J = 1, K = 1
Answer: d. J=1, K=1
10. On a master-slave flip-flop, when is the master enabled?
a. when the gate is LOW
b. when the gate is HIGH
c. both of the above
d. neither of the above
Answer: b. when the gate is HIGH
11. How many flip-flops are required to make a MOD-32 binary counter?
a. 3
b. 4
c. 5
d. 6
Answer: c. 5
Synchronous Sequential Logic 3.105
12. The terminal count of a modulus-11 binary counter is ________.
a. 1010
b. 1000
c. 1001
d. 1100
Answer: a.1010
13. Synchronous counters eliminate the delay problems encountered with asynchronous counters
because the:
a. input clock pulses are applied only to the first and last stages
b. input clock pulses are applied only to the last stage
c. input clock pulses are not used to activate any of the counter stages
d. input clock pulses are applied simultaneously to each stage
Answer: d. input clock pulses are applied simultaneously to each stage
14. What is the difference between combinational logic and sequential logic?
a. Combinational circuits are not triggered by timing pulses, sequential circuits are triggered
by timing pulses.
b. Combinational and sequential circuits are both triggered by timing pulses.
c. Neither circuit is triggered by timing pulses.
d. None of the above
Answer: a. Combinational circuits are not triggered by timing pulses, sequential circuits
are triggered by timing pulses.
15. How many different states does a 3-bit asynchronous counter have?
a. 2
b. 4
c. 8
d. 16
Answer: c. 8
3.106 Digital Principles and System Design
16. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state
does the counter go on the next clock pulse?
a. 1101
b. 1011
c. 1111
d. 0000
Answer: b. 1011
17. The terminal count of a 3-bit binary counter in the DOWN mode is ________.
a. 000
b. 111
c. 101
d. 010
Answer: a. 000
18. A 4-bit counter has a maximum modulus of ________.
a. 3
b. 6
c. 8
d. 16
Answer: d. 16
19. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a. If both inputs are HIGH, the output will toggle.
b. The output will follow the input on the leading edge of the clock.
c. When both inputs are LOW, an invalid state exists.
d. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock.
Answer: b. The output will follow the input on the leading edge of the clock.
Synchronous Sequential Logic 3.107
20. What is one disadvantage of an S-R flip-flop?
a. It has no enable input.
b. It has an invalid state.
c. It has no clock input.
d. It has only a single output.
Answer: b. It has an invalid state.
21. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal
shift features, called?
a. tristate
b. end around
c. universal
d. conversion
Answer: c. universal
22. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble
1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift
register is storing ________.
a. 1101
b. 0111
c. 0001
d. 1110
Answer: b. 0111
23. How can parallel data be taken out of a shift register simultaneously?
a. Use the Q output of the first FF.
b. Use the Q output of the last FF.
c. Tie all of the Q outputs together.
d. Use the Q output of each FF.
Answer: d. Use the Q output of each FF.
3.108 Digital Principles and System Design
24. A modulus-12 ring counter requires a minimum of ________.
a. 10 flip-flops
b. 12 flip-flops
c. 6 flip-flops
d. 2 flip-flops
Answer: b. 12 flip-flops
25. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock
pulse?
a. 11101011
b. 00010111
c. 11110000
d. 00000000
Answer: a. 11101011
Synchronous Sequential Logic 3.109
REVIEW QUESTIONS
1) Explain the synchronous counter design procedure and also design Mod-7 counter using JK flip
flop.
2) (i) Implement JK flip flop using D flip flop.
(ii) How the race condition can be avoided in a flip flop?
3) Design a sequence detector that detects a sequence of three or more consecutive 1’s in a string
of bits coming through an input line and produces an output whenever this sequence is detected.
4) Design a binary counter using T flip flops to count in the following sequences:
(i) 000,001,010,011,100,101,111,000 (ii) 000,100, 111, 010, 011, 000
5) Explain the operation of JK, SR, T and D Flip flops with a neat diagram. Also discuss their
characteristic equation and excitation table.
6) Design a MOD-10 synchronous counter using JK flip flops. Write the execution table and state
table.
7) Design and implement mod-5 synchronous counter using JK flip flop and also draw the timing
diagram.
8) Implement T-flip flop and JK flip flop using D flip flop.
9) A sequential circuit with 2 D-flip-flops A and B and input X and output Y is specified by the
following next state and output equations. A(t+1)=AX+BX; B(t+1)=A′X ; Y=(A+B)X′;
i)Draw the logic diagram of the circuit. ii) Derive the state table. iii) Derive the state diagram.
10) A sequential circuit with 2 D-flip-flops A and B and input X and output Z is specified by the
following next state and output equations. A(t+1)=A’+B; B(t+1)=B′X ; Z=A+B′;
i)Draw the logic diagram of the circuit. ii) Derive the state table. iii) Derive the state diagram.
11) Design a synchronous sequential circuit using JK for the given state diagram.
3.110 Digital Principles and System Design
12) Design a synchronous sequential circuit using JK for the given state diagram.
13) Design a synchronous decade counter using D flip flop.
14) Design a three bit synchronous counter with T flip flop and draw the diagram.
15) Consider the design of 4-bit BCD counter that counts in the following way:
0000, 0001, 0010,…., 1001 and back to 0000. Draw the logic diagram of this circuit.
16) Draw and explain the operation of various shift registers in detail.
Asynchronous Sequential Logic 4.1
UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC
4.1 INTRODUCTION
In synchronous sequential circuits, memory elements are clocked flipflops. In asynchronous
sequential circuits, memory elements are either unclocked flipflops (latches) or time delay elements.
Asynchronous means without a synchronizing clock to control the state transitions of a sequential
circuit. The inputs and present state change after the internal delay of the circuit elements. Because no
synchronizing clock is used, asynchronous circuits are usually faster than synchronous circuits. The
comparison between synchronous and asynchronous sequential circuits is given in Table 4.1.
TABlE 4.1: Comparison between Synchronous and Asynchronous Sequential Circuits
Sl. No. Synchronous Sequential Circuits Asynchronous Sequential Circuits
1. Memory elements are clocked Memory elements are either unclocked
flipflops. flipflops or time delay elements.
2. The operating speed of clock depends Because of absence of clock, it can
on time delays involved. operate faster than asynchronous
Therefore synchronous circuits sequential circuits.
can operate slower than asynchronous.
3. The change in input signals can affect The change in inputs signals can affect
memory elements upon activation of memory elements at any instant of time.
clock signal.
4. Easier to design. More difficult to design.
4.2 TYPES OF ASYNCHRONOUS SEQUENTIAL CIRCUITS
Asynchronous Sequential Circuits are typically classified into two main groups:
Fundamental Mode Asynchronous Sequential Circuits
Pulse Mode Asynchronous Sequential Circuits
4.2.1 Fundamental Mode
In the fundamental mode, only one input is allowed to change at a time and the inputs are considered
to be levels, (0 or 1). Input level changes can occur no faster than allowed by the slowest propagation
path in the circuit.
4.2 Digital Principles and System Designs
4.2.2 Pulse Mode
In the pulse mode, only one input is allowed to change at a time and inputs are considered to pulse
(false-true-false) and the input pulses must be long enough to initiate a state change but not so wide
that the input is still true after a new state is reached.
The input signals i.e., level inputs for fundamental mode and pulse inputs for pulse mode are
shown in Figure 4.1.
Fig. 4.1: Level and Pulse inputs
4.3 TRANSITION TABLE
A state table with binary assignment is called transition table. Transition table of asynchronous
sequential circuits similar to the state table used for synchronous sequential circuits. It is constructed
which shows the next states of the flipflops as a function of the present state and inputs.
4.4 FLOW TABLE
During the design of asynchronous sequential circuits, it is more convenient to name the states by
letter symbols without making specific reference to their binary values. Such a table is called flow table.
A flow table is similar to a transition table except that the internal states are symbolized with
letters rather than binary numbers. The flow table also includes the output values of the circuit for
each state table.
Asynchronous Sequential Logic 4.3
4.5 PRIMITIVE FLOW TABLE
A primitive flow table is a special case of flow table. It is defined as a flow table which has exactly
one stable state for each row in the table.
4.6 ANALYSIS OF FUNDAMENTAL MODE ASYNCHRONOUS
Sequential Circuits
The analysis of asynchronous sequential circuits consists of obtaining a table or a diagram that
describes the sequence of internal states and outputs as a function of changes in the input variables.
Analysis Procedure
The procedure for obtaining a transition table from the given circuit diagram is as follows:
1. Determine all feedback loops in the circuit.
2. Designate the output of each feedback loop with variable Y1 and its corresponding inputs
y1, y2, ..., yk, where k is the number of feedback loops in the circuit.
3. Derive the Boolean functions of all Y’s as a function of the external inputs and the y’s.
4. Plot each Y function in a map, using y variables for the rows and the external inputs for the
columns.
5. Combine all the maps into one table showing the value of Y = Y1, Y2, ... Yk inside each square.
6. Circle all stable states where Y = y. The resulting map is then the transition table.
Example 4.1: Derive the transition table and primitive flow table for the fundamental mode
asynchronous sequential circuit shown in Figure 4.2.
y1
x Y1
y2
Y2
Fig. 4.2: Fundamental mode sequential circuit
Solution: (i) Boolean Expressions: Boolean expressions for the logic diagram are:
Y x y xy
Y x y xy
4.4 Digital Principles and System Design
where Y 1, Y 2 = Excitation variables = Next State
y1, y2 = Secondary variables = Present State
(ii) Maps for Y1 and Y2
TABLE 4.2: Next-State Table
x y1 y2 xy1 xy 2 xy 1 Y 1 = xy 1 xy 2 Y 2 = x y 1 xy 2
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 1 0 0 0 0 0 0
0 1 1 0 1 0 1 1
1 0 0 0 0 1 0 1
1 0 1 0 0 1 0 1
1 1 0 1 0 0 1 0
1 1 1 1 0 0 1 0
y2 y2
xy1 0 1 xy1 0 1
00 0 1 00 0 1
01 0 1 01 0 1
11 1 1 11 0 0
10 0 0 10 1 1
(a) Map for Y 1 = xy 1 x y 2 (b) Map for Y 2 = x y 1 xy2
Fig. 4.3: Maps for y1 and y2
(iii) Transition Table: The transition table shown in Table 4.3 is obtained from the maps by combining
the binary values in corresponding squares. i.e., Y = Y1Y2. The first bit of Y is obtained from the
value of Y1 and the second bit of Y is obtained from the value of Y2 in the same square position.
For a state to be stable, the value of Y must be the same as that of y = y1y2. Those entries in the
transition table where Y = y are circled to indicate a stable condition. An uncircled entry represents
an unstable state.
TABLE 4.3 : Transition Table
y2
xy1 0 1
00 00 01
01 11 01
unstable state 11 11 10
stable state
10 00 10
Asynchronous Sequential Logic 4.5
(iv) Primitive Flow Table
A flow table is similar to a transition table except that the internal states are symbolized with
letters like a, b, c, S1, S2, etc. rather than binary numbers. In this example, we assign the following
binary values to the states:
a = 00
b = 01
c = 11
d = 10
A primitive flow table is shown in Table 4.4; it has only one stable state in each row.
TABLE 4.4 : Primitive flow table
y2
xy1 0 1
a a b
b c b
c c d
d a d
Example 4.2: Derive the transition table and primitive flow table for the given circuit shown in
Figure 4.4.
Fig. 4.4 : Sequential circuit
Solution:
Excitation variables (Next State) = X0, X1
Secondary variables (Present State) = I0, I1 ; Output = Z
4.6 Digital Principles and System Design
Boolean Expressions
X t X I X I I X X I
X t X I I X
Z X I
Table 4.5 illustrates the present state, next state and output variables.
TABLE 4.5 : Next State Table
X1 X0 X1 I0 X1 (t + 1) = X0 I1 + I0 X1 X0 (t + 1) = X I I0+ X X 0 I 0 + X 0 I1 Z = X0I1
0 0 0 0 0 0 0
0 0 0 1 0 1 0
0 0 1 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 0 1 0 1 0
0 1 1 0 1 1 1
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 0
1 0 1 1 1 0 0
1 1 0 0 0 0 0
1 1 0 1 1 0 0
1 1 1 0 1 1 1
1 1 1 1 1 1 1
Map for X1(t + 1) Map for X0(t + 1)
I1 I0 I1 I0
X1X0 00 01 11 10 X1X0 00 01 11 10
00 0 0 0 0 00 0 1 0 0
01 0 0 1 1 01 0 1 1 1
11 0 1 1 1 11 0 0 1 1
10 0 1 1 0 10 0 0 0 0
Asynchronous Sequential Logic 4.7
Transition Table:
TABLE 4.6 : Transition Stable
I1 I0
00 01 11 10
X1X0
00 00 01 00 00
01 00 01 11 11
11 00 10 11 11
10 00 10 10 00
Primitive Flow Table:
TABLE 4.7 : Primitive Flow Table
I 1 I0
X1X0 00 01 11 10
a a b a a
b a b c c
c a d c c
d a d d a
4.7 ANALYSIS OF PULSE MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS
Pulse mode asynchronous sequential circuits relay on input pulses rather than levels. They allow
only one input variable to change at a time. They can be implemented by employing a basic flip-flop
commonly referred to as an SR Latch. We will first explain the operation of the SR latch with NOR
gates and NAND gates. We will then proceed to give examples of analysis of pulse mode asynchronous
sequential circuits that employ SR latches.
The SR latch has two inputs S and R and two cross-coupled NOR gates or two cross-coupled
NAND gates. The SR latch with NOR gates is shown in Figure 4.5. In order to analyze the circuit by
the transition-table method, redraw the circuit, as shown in Figure 4.6.
4.8 Digital Principles and System Design
Fig. 4.5 : SR latch
Fig. 4.6 : Circuit Showing feedback
The Boolean function for the output is,
Y= S y R
= (S + y) R
= SR + Ry
TABLE 4.8 : Output Values
S R y SR Ry Y = SR+ Ry
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 0 0 0 0
1 1 1 0 0 0
Asynchronous Sequential Logic 4.9
TABLE 4.9 : Transition table
y
SR 0 1
00 0 1
01 0 0
11 0 0
10 1 1
S R S R S R R = S
S R S when SR = 0
Y S R Ry S Ry
The SR latch with NAND gates is shown in Figure 4.7(a) and (b).
(a) Cross coupled circuit (b) Circuit showing feedback
Fig. 4.7: SR Latch
Output Y R y S R y S with S R
The values of output Y are shown in Table 4.10 and the transition table is shown in Table 4.11.
TABLE 4.10: Output Values TABLE 4.11 : Transition Table
S R y Ry Y RyS
y
0 1 0 1 1 SR 0 1
0 0 1 0 1 00 1 1
0 1 0 0 1 01 1 1
0 1 1 1 1 11 0 1
1 0 0 0 0 10 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
4.10 Digital Principles and System Design
SR latch using NOR gates, Y = S Ry with SR = 0
SR latch using NAND gates, Y = S R y with S R
Example 4.3: Derive the transition table for the pulse mode asynchronous sequential circuit shown in
Figure 4.8.
Fig. 4.8 : Pulse Mode sequential circuit
Solution:
Procedure
1. Derive the Boolean functions for S1 , R1 , S2 and R2 inputs.
2. Check whether SR = 0 for each NOR latch or whether S R for each NAND latch. If this
condition is not satisfied, there is a possibility that the circuit may not operate properly.
3. Evaluate Y S Ry for each NOR latch or
Y S R y for each NAND latch.
4. Construct maps for Y and Y2 .
5. Plot the value of Y = Y1Y2 in the map. Circle all stable states where Y = y. The resulting map is
the transition table.
Step 1: Boolean functions for S and R inputs in each table:
S x y R x y
S x x R x y
Asynchronous Sequential Logic 4.11
Step 2: Check whether the condition SR = 0 is satisfied to ensure proper operator of NOR latches.
S R x y x x x x y x x x
S R x y x y x x x y x x
Step 3: Evaluate Y1 and Y 2 .
Y S R y
x y x x y x y x y y
x y x y x y
Y S R y
x x x y y
x x x y y
x x x y y y
TABLE 4.12
x1 x2 y1 y2 x1y2 x1y1 x2y1 x1x2 x2y 2 y1y2 Y1 Y2
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 1 1 0 1
0 1 1 0 0 0 1 0 0 0 1 0
0 1 1 1 0 0 1 0 1 0 1 1
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 1 1 1
1 0 1 0 0 1 0 0 0 0 1 0
1 0 1 1 1 1 0 0 0 0 1 0
1 1 0 0 0 0 0 1 0 0 0 1
1 1 0 1 1 0 0 1 1 1 1 1
1 1 1 0 0 1 1 1 0 0 1 1
1 1 1 1 1 1 1 1 1 0 1 1
4.12 Digital Principles and System Design
Step 4: Maps for Y1 and Y2
Y1Y 2 Y1Y2
x1x2 00 01 11 10 x1x2 00 01 11 10
00 0 0 0 0 00 0 1 0 0
01 0 0 1 1 01 0 1 1 0
11 0 1 1 1 11 1 1 1 1
10 0 1 1 1 10 0 1 0 0
Map for Y1 Map for Y2
Fig. 4.9: K map simplification
Step 5: Transition Table
TABLE 4.13 : Transition Table
Y1Y 2
x1x2 00 01 11 10
00 00 01 00 00
01 00 01 11 10
11 01 11 11 11
10 00 11 10 10
4.8 RACES
Races exist in asynchronous sequential circuits when two or more binary state variables change
during a state transition.
Races are classified as:
(i) Non-critical races
(ii) Critical races.
4.8.1 Non-Critical Races
If the final stable state that the circuit reaches does not depend on the order in which the state
variables change, the race is called a non-critical race.
If a circuit, whose transition table is shown in Figure 4.10, starts in stable state 000 (y1y2x) and
then change the input from 0 to 1. The state variable must change from 00 to 11, which defines a race
condition. The possible transitions are:
Asynchronous Sequential Logic 4.13
00 11
1
00 01 11
1
00 10 11
1
In all cases the final stable state (y1y2 x = 111) is the same, which results in a non-critical race
condition.
X
Y1Y2 0 1
00 00 11
01 11 00 11
1
11 11 00 01 11
1
10 11 00 10 11
1
Fig. 4.10 : Non-critical race
4.8.2 Critical Race
A race becomes critical if the correct next state is not reached during a state transiton. If it is
possible to end up in two or more different stable states, depending on the order in which the state
variables change, then it is a critical race. For proper operation, critical races must be avoided.
The transition table for Figure 4.11 illustrate critical race condition. It starts in stable state y1 y2 x =
000 and then change the input from 0 to 1. The state variables must change from 00 to 11. If they
change simultaneously, the final total stable state is 111. If y2 changes to 1 before y1because of unequal
propagation delay, then the circuit goes to the total stable state 011 and remains there. On the other
hand, if y1 changes first, the internal state becomes 10 and the circuit will remain in the stable total
state 101. Hence the race is critical because the circuit goes to different stable states depending on the
order in which the state variables change.
x
y1y2 0 1
00 00 11
01 01
11 11
10 10
Possible Transitions Final State
00 11
1 111
00 01 011
00 10 101
Fig. 4.11 : Critical race
4.14 Digital Principles and System Design
4.9 CYCLES
Races can be avoided by directing the circuit through intermediate unstable states with a unique
state-variable change. When a circuit goes through a unique sequence of unstable states, it is said to
have a cycle.
Figure 4.12 illustrates the occurrence of cycles. The state variable starts with y1y2 = 00 and then
change the input from 0 to 1. The transition table Figure 4.12(a) gives a unique sequence that terminates
in a total stable state 101. The transition table Figure 4.12(b) shows that even though the state variables
change from 00 to 11, the cycle provides a unique transition from 00 to 01 and then to 11. The cycle
should terminate with a stable state. If the cycle does not terminate with a stable state, the circuit will
keep going from one unstable state to another, making the entire circuit unstable. This is illustrated in
Figure 4.12(c).
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
00 00 01 00 00 01 00 00 01
01 11 01 11 01 11
11 10 11 11 11 10
10 10 10 10 10 01
(a) State transition (b) State transition (c) Unstable state
00 01 11 1 10 00 01 11 1 00 11 10
Fig. 4.12 : Cycles
4.10 RACE FREE STATE ASSIGNMENT
Critical Races may be avoided by making a proper binary assignment to the state variables. The
state variables must be assigned binary numbers in such a way that only one stable variable can
change at any one time when a state transition occurs in the flow table.
Three techniques are commonly used for making a critical-race free state assignment:
1. Shared row State assignment
2. Multiple row State assignment
3. One Hot State assignment
4.10.1 Shared Row State Assigment
In shared row state assignment, an extra row is introduced in a flow table that is shared between
two stable states.
Figure 4.13 shows a transition diagram. It shows that there is a transition from state ‘a’ to state ‘b’
and transition from state ‘a’ to state ‘c’. The state ‘a’ is assigned binary value 00 and b = 01, c = 11.
Asynchronous Sequential Logic 4.15
This assignment will cause a critical race during the transition from ‘a’ to ‘c’, because there are two
changes in the binary state variable.
00 01 11
1
Fig. 4.13 : Transition Diagram
TABLE 4.14: Random State Assignment
State State Variable
F2 F1
a 0 0
b 0 1
c 1 1
A race free assignment can be obtained by introducing extra row in a flow Table. This extra state
is shared between two stable states. The flow table is shown in Table 4.15.
TABLE 4.15: Flow Table
State F2 F1
a 0 0
b 0 1
c 1 1
d 1 0
The transition diagram with addition binary state (d = 10) is shown in Figure 4.14. State ‘d’ is
adjacent to both ‘a’ and ‘c’. Now the transition from a to c will go through ‘d’. This causes the binary
variables to change from 00 10 11, which satisfy the condition that only one binary variable
changes during each state transition, thus avoiding the critical race.
Fig. 4.14 : Modified Transition diagram
4.16 Digital Principles and System Design
4.10.2 Multiple Row State Assignment
The multiple row state assignment technique specifies that each row in the original flow table be
replaced with two rows. Each new row or total state is equivalent to the original state before splitting;
for instance, state a = a1 = a2. Row ‘a’ existed in a flow table is replaced by rows a1 and a2. The binary
assignment for state a1(000) is the complement of binary assignment for state a1(111).
Table 4.16 shows the original flow table and Table 4.17 shows the multiple row state assignment.
State ‘a’ is replaced by two equivalent states a1 = 000 and a2 = 111
State ‘b’ is replaced by two equivalent states b1 = 001 and b2 = 110
State ‘c’ is replaced by two equivalent states c1 = 011 and c2 = 100
State ‘d’ is replaced by two equivalent states d1 = 010 and d2 = 101
The output values, not shown here, must be same in a1 and a2, b1 and b2, c1 and c2, d1 and d2.
Table 4.16 Flow Table Table 4.17 : Multiple row state assignment
00 01 11 10 00 01 11 10
a b a d a a1 = 000 b1 a1 d1 a1
b b d b a a2 = 111 b2 a2 d2 a2
c c a b c b1 = 001 b1 d2 b1 a1
d c d d c b2 = 110 b2 d1 b2 a2
c1 = 011 c1 a2 b1 c1
c2 = 100 c2 a1 b2 c2
d1 = 010 c1 d1 d1 c1
d2 = 101 c2 d2 d2 c2
Asynchronous Sequential Logic 4.17
In the multiple row assignment, the change from one stable state to another will always cause a
change of only one binary state variable. Each stable state has two binary assignments with exactly
the same output. At any given time, only one of the assignments is in use. For example, if we start
with state a1 and input 01 and then change the input to 11, 01, 00 and back to 01, the sequence of
internal states will be a1, d1, c1 and a2. Although the circuit starts in state a1 and terminates in states a2,
as far as the input-output relationship is concerned, the two states a1 and a2 are equivalent to state “a”
of the original flow table.
4.10.3 One Hot State Assignment
One hot state assignments are made so that only one variable is active or “HOT” for each row in
the original flow table. It requires as many state variables as there are rows in a flow table. Additional
rows are introduced to provide single variable changes between internal state transitions.
Consider the flow table given in Table 4.18. 4 state variables (a, b, c, d) are used to represent the
four rows in the table. Each row is represented by a case where only one of the four state variables is
a1. A transition from state ‘a’ to state ‘b’ requires two state variable changes. By introducing a new
row, one whose state assignment contains is where both states ‘a’ and ‘b’ have 1s, permits the transition
between ‘a’ and ‘b’ without a race. The complete one hot state assignment flow table is shown in
Table 4.19.
The transition from state ‘b’ to state ‘a’ is accomplished by passing through dummy state Q. If the
machine is in state ‘b’ and a 00 input is received then the machine will change state to Q and then to
‘a’, without any further change in the inputs. State ‘a’ is replaced by Q in the ‘b’ row.
Row c with a state assignment of 0100 makes a change to state ‘a’ when the input is 00. State ‘a’
has an assignment of 0001. By passing through state R, on the way from c to a, races are eliminated.
The state transition path is C(0100) R(0101) a(0001).
TABLE 4.18 : Flow table
State Variables Inputs (XY)
State
F4 F3 F2 F1 00 01 11 10
0 0 0 1 a a b c c
0 0 1 0 b a b c d
0 1 0 0 c a b c c
1 0 0 0 d d b c d
4.18 Digital Principles and System Design
TABLE 4.19 : One hot state assignment flow table
State Variables Inputs (XY)
State
F4 F3 F2 F1 00 01 11 10
0 0 0 1 a a Q R R
0 0 1 0 b Q b S T
0 1 0 0 c R S c c
1 0 0 0 d d T U d
0 0 1 1 Q a b
0 1 0 1 R a c c
0 1 1 0 S b c
1 0 1 0 T b d
1 1 0 0 U c
4.11 MINIMIZATION OF PRIMITIVE FLOW TABLE
The minimization of primitive flow table means that reduction of the primitive flow table to a
minimum number of rows. This reduction will reduce the number of state variables requires to realize
the table. This will make it easier to complete the design of the network and will reduce the amount of
logic required.
The minimization of primitive flow table is done by eliminating redundant stable states. To do
this, we must find equivalent stable states. Two stable states are equivalent iff they have the same
inputs and the associated internal states are equivalent. Thus two stable states are equivalent if
(i) their inputs are the same.(ii) their outputs are the same.(iii) their next states are equivalent for
each possible next input.
Consider the primitive flow table given in Table 4.20. From the first column (input 00) states 2, 6
and 8 have the same outputs (01). From the second column (input 01) 5 and 12 have the same outputs
(11). From the third column (input 11) 3 and 10 have the same outputs (10) and from the last column
(input 10) 4 and 11 have the same outputs (00). Therefore the sets of potentially equivalent states are:
(2, 6, 8) (5, 12) (3, 10) (4, 11)
Asynchronous Sequential Logic 4.19
(i) Next we examine the next states of the states in each group. With input 01, the next states of 2
and 6 are 5 and 7. Since 5 7, 2 6 . Similarly the next states of 6 and are 7 and 12. Since
7 12 , 6 8 . However for 2 and 8, with input 01 the next states are 5 and 12 and with input
10 both next states are 4.
(ii) For 5 and 12, both next states are 6 for input 00 and both next states are 9 for input 11.
(iii) For 3 and 10, both next states are 7 for input 01.
(iv) For 4 and 11, the next states are 2 and 8 for input 00 and 3 and 10 for input 11.
Since we have found no additional non-equivalent states, the remaining sets of equivalent states
are: (2, 8) (5, 12) (3, 10) (4, 11)
Therefore we can eliminate one equivalent state from the sets. After eliminating redundant states
8, 10, 11 and 12, the reduced primitive flow table is given by Table 4.21.
TABLE: 4.20: Primitive flow table to be reduced
Inputs (XY)
States Output
00 01 11 10
1 1 7 4 11
2 2 5 4 01
3 7 3 11 10
4 2 3 4 00
5 6 5 9 11
6 6 7 11 01
7 1 7 14 10
8 8 12 4 01
9 7 9 13 01
10 7 10 4 10
11 8 10 11 00
12 6 12 9 11
13 8 14 13 11
14 12 14 11 00
4.20 Digital Principles and System Design
TABLE: 4.21: Primitive flow table
Inputs (XY)
States Output
00 01 11 10
1 1 7 4 11
2 2 5 4 01
3 7 3 4 10
4 2 3 4 00
5 6 5 9 11
6 6 7 4 01
7 1 7 14 10
9 7 9 13 01
13 2 14 13 11
14 5 14 4 00
Example 4.4: Minimize the primitive flow table of Table 4.22.
TABLE: 4.22 : Primitive flow table
Inputs (XY)
States Output
00 01 11 10
1 1 2 3 4 0
2 8 2 7 9 1
3 1 2 3 9 0
4 1 6 7 4 1
5 5 6 7 4 0
6 5 6 3 4 1
7 8 2 7 9 0
8 8 2 3 4 0
9 5 10 3 9 1
10 1 10 7 9 0
11 5 10 11 4 0
Asynchronous Sequential Logic 4.21
Solution: The sets of stable states which have same inputs and output are shown in Table 4.23. The
states in each set are potentially equivalent.
(1, 5, 8) (2, 6) (3, 7, 11) (4, 9)
TABLE: 4.23: Potentially equivalent states
Inputs (XY)
States Output
00 01 11 10
1 1 2 3 4
5 5 6 7 4 0
8 8 2 3 4
2 8 2 7 9
6 5 6 3 4 1
3 1 2 3 9
7 8 2 7 9 0
11 5 10 11 4
4 1 6 7 4 1
9 5 10 3 9
Now examine the same next states of the states in each group. 1 8 , since both states have the
same next state for input 01.
3 7 , since both states have same next state for input 10.
Therefore eliminating the redundant states 7 and 8 from the original primitive flow table. The
reduced primitive flow table is shown in Table 4.24.
TABLE 4.24: Reduced Primitive Flow Table
Inputs (XY)
State Output
00 01 11 10
1 1 2 3 4 0
2 1 2 3 9 1
3 1 2 3 9 0
4 1 6 3 4 1
5 5 6 3 4 0
6 5 6 3 4 1
9 5 10 3 9 1
10 1 10 3 9 0
11 5 10 11 4 0
4.22 Digital Principles and System Design
4.12 DESIGN OF FUNDAMENTAL MODE ASYNCHRONOUS SEQUENTIAL
CIRCUITS
Example 4.5: Design a fundamental mode asynchronous sequential circuit with the following
behaviour. The circuit has two external inputs. A and B and one output Z. The state diagram is shown
in Figure 4.15.
Fig. 4.15: State Diagram
Solution: For this design one does not need to obtain a primitive flow table, merger diagram, reduced
primitive flow table, transition diagram since, Figure 4.15cannot be reduced to less than two states.
For two states, one state variable is required which will be called y. Assigning the state code 0 to state
`a’ and state code 1 to state `b’ and output Z = y. The K-map for the next state and external outputs can
be drawn using the state diagram. The logic diagram is shown in Figure 4.16.
TABLE 4.25
AB inputs
Present Next State Output
State 00 01 11 10 Z
a a a b a 0
b b a b b 1
a0
b1
TABLE: 4.26: State Table
Next State
Present Output
State 00 01 11 10 Z
0 0 0 1 0 0
1 1 0 1 1 1
Asynchronous Sequential Logic 4.23
AB
y 00 01 11 10
0 0 0 1 0
1 1 0 1 1
Y A B y A yB
Fig. 4.16: Logic Diagram
Example 4.6: Obtain the primitive flow table for a fundamental mode asynchronous sequential circuit
that has two inputs x1 and x2 and a single output z.
The inputs x1 and x2 never change simultaneously.
The outputs is always to be 0 when x1 = 0, independent of the value of x2.
The output is to become 1 if x2 changes while x1 = 1 and is to remain 1 until x1 becomes 0 again.
Solution:
Table 4.27: Primitive flow table
Present Next State Output (z)
State Input state (x1x2) Input state (x1x2)
00 01 10 11 00 01 10 11
A A B C 0
B B 0
C C 0
Stable State A
When the input state x1x2 = 00, the output must be 0 for stable state A , since x=0 when x1 = 0.
4.24 Digital Principles and System Design
When the input state is changed from x1x2 = 00 to x1x2 = 01, the circuit must become unstable,
since only one stable state is permitted in each row of a primitive flo table and eventually reach an
other stable state, say B . In the next state section of the primitive flow table an uncircled B is placed
in the first row, second column and a circled B is placed in the second row, second column. The
output z = 0 for stable state B , since x1 = 0.
When the input state is changed from x1x2 = 00 to x1x2 = 10, another row of C is needed. An
uncircled C is placed in the first row, third column and the circled C is placed in the third row, third
column of the next-state section. The output z = 0, since z = 1 if x2 changes while x1 = 1.
When the input state is changed from x1x2 = 00 to x1x2 = 11, a dash () is placed in the first row,
fourth column of the next section, since the inputs x1x2 never change simultaneously. Now the primitive
flow table appears as shown in Table 4.27.
Table 4.28: Primitive Flow Table
Present Next state Output (z)
state Input state (x1x2) Input state (x1x2)
00 01 10 11 00 01 10 11
A A B C 0
B A B D 0
C C 0
D D 0
Stable State B
Whe the input state is x1x2 = 01, the output must be 0 for stable state B , since x1 = 0.
When the input state is changed from x1x2 = 01 to x1x2 = 00, the circuit must first become unstable
and then reach a stable state. Since stable state A is already exists in the first column of the next-state
section, an uncircled A is placed in the second row, first column.
When the input state is changed from x1x2 = 01 to x1x2 = 11, a stable state must appear in the fourth
column of the next-state section of the primitive flow table. Thus, an internal change to a stable state
D is needed. The output z = 0 for stable state D , since x2 did not change but remained at the value
x2 = 1.
When the input state is changed from x1x2 = 10, a dash () is placed in the second row, third
column of the next-state section, since both input variable x1, x2 cannot change simultaneously. Now
the primitive flow table appears as shown in Table 4.28.
Asynchronous Sequential Logic 4.25
Table 4.29: Primitive flow table
Present Next state Output (z)
State Input state (x1x2) Input state (x1x2)
00 01 10 11 00 01 10 11
A A B C 0
B A B D 0
C A C E 0
D D 0
E E 1
Stable State C
When the input state is changed from x1x2 = 10 to x1x2 = 11, then a stable state with a 1 output must
be reached in the fourth column of the next- state section of the primitive flow table. This cannot be
state D , since the output is to become 1 when x2 changes while x1 = 1. Thus a stable state with a 1
output in the fourth column is needed. This necessitates a fifth row for present state E to be added in
the primitive flow table. The uncircled E is placed in the third row, fourth column and circled E is
placed in the fifth row, fourth column. The output z = 1 for stable state E .
When the input is changed from x1x2 = 10 to x1x2 = 00 the circuit must first become unstable and
thenr each a stable state. Since stable state A is already exists in the first column of the next-state
section, an uncircled A is placed in the third row, first column.
When the input is changed from x1x2 = 10 to x1x2 = 01, a dash () is placed in the third row, second
column, since both inputs x1x2 never change simultaneously. Now the primitive flow table appears
shown in Table 4.29.
Table 4.30: Primtive Flow Table
Present Next State Output (z)
State Input state (x1x2) Input state (x1x2)
00 01 10 11 00 01 10 11
A A B C 0
B A B D 0
C A C E 0
D B F D 0
E E 1
F F 1
4.26 Digital Principles and System Design
Stable State D
When the input state is changed from x1x2 = 11 to x1x2 = 10, then a stable state with a 1 output must
be reached in the third column of the next-state section of the primitive flow table. Since the only
stable state in the third column thus far has a 0 output, another row is added to the table for a stable
state F along with its 1 output.
When the input state is changed from x1x2 = 11 to x1x2 = 01, an uncircled B is placed in the fourth
row, second column.
When the input is changed from x1x2 = 11 to x1x2 = 00, a dash (–) a placed in the fourth row, first
column, since both inputs x1x2 never change simultaneously. Now the primitive flow table appears as
shown in Table 4.30.
The remaining entries in the last two rows are determined by similar reasons as mentioned above.
The completed primitive flow table is shown in Table 4.31.
Table 4.31: Primitive Flow Table
Present Next State Output (z)
State Input state (x1x2) Input state (x1x2)
00 01 10 11 00 01 10 11
A A B C 0
B A B D 0
C A C E 0
D B F D 0
E B F E 1
F A F E 1
Example 4.7
Obtain the primitive flow table for an asynchronous sequential circuit that has two inputs x, y and
one output z. The inputs x and y never change or are 1 simultaneously. An output z = 1 is to occur only
during the input state xy = 01 and then if and only if the input state xy = 01 is preceded by the input
sequences xy = 01, 00, 10, 00, 10, 00. (Nov. 2004)
Solution
Input Sequence Stable State
01 A
00 B
10 C
00 D
10 E
00 F
Asynchronous Sequential Logic 4.27
Stable state A is placed in the first row, second column of the next-state section of the primitive
flow table for the input state xy = 01, assumed that the output z = 0.
When the input state is changed from xy = 01 to xy = 00, a second row must be added for stable
state B . An uncircled B is placed in the first row, first column and a circled B is placed in the
second row, first column.
The input states xy = 10 and xy = 11 cannot follow the input state xy = 01, since the inputs xy never
change or are 1 simultaneously.
Next in input state of xy = 10 results in the circuit entering stable state C . This state signifies that
the input sequence xy = 01, 00, 10 has been applied.
Next an input state of xy = 00 results in the circuit entering stable state D . This state signifies that
the input sequence is xy = 01, 00, 10, 00.
Similarly, stable state E and F are placed in the primitive flow table as shown in Table 4.32.
Stable state G is introduced with an associated 1 output.
Table 4.32: Primitive Flow Table
Present Next State Output (z)
State Input state (xy) Input state (xy)
00 01 10 11 00 01 10 11
A B A 0
B B C 0
C D C 0
D D E 0
E F E 0
F F G 0
G G 1
This asynchronous sequential circuit has the following requirements:
1. The inputs x and y never change simultaneously i.e., only one input variable is allowed to
change value at a time.
2. The inputs x and y are never 1 simultaneously.
These requirements imply that only dashes (–) can appear in the fourth column and other some
entries in the next-state section of the primitive flow table as shown in the Table 4.33.
The unstable states A are entered in the second and fourth rows of the second column of the next
section of the primitive flow table since the sequence to be recognized is broken by the input state
xy = 01 and hence the recognition process must be restarted.
4.28 Digital Principles and System Design
Table 4.33: Primitive Flow Table
Present Next State Output (z)
State Input state (xy) Input state (xy)
00 01 10 11 00 01 10 11
A B A 0
B B C 0
C D C 0
D D E 0
E F E 0
F F G 1
G G 1
The unstable states B is entered in the seventh row, first column, since the input state for the
stable state in that row can serve both as the first xy = 01 input of a new sequence as well as the last
input of the recognized sequence.
Finally two additional stable states H and I must be added to handle the situation that the input
state xy = 01, which defines the beginning and end of the input sequence to be recognized. In the last
row an unstable state A indicates the first input state of the sequence to be recognized is applied and
an unstable state A indicates the first input state of the sequence to be recognized is applied and an
unstable state H provides for the network to wait for the beginning of the specified input sequence
that is to be recognized. The complete primitive flow table is shown in Table 4.34.
Table 4.34: Primitive flow table
Present Next state Output (z)
State Input state (xy) Input state (xy)
00 01 10 11 00 01 10 11
A B A 0
B B A C 0
C D C 0
D D A E 0
E F E 0
F F G H 0
G B G 1
H 1 H 0
I 1 A H 0
Asynchronous Sequential Logic 4.29
4.13 DESIGN OF PULSE MODE ASYNCHRONOUS SEQUENTIAL
CIRCUITS
The pulse mode asynchronous sequential circuit input signal restrictions can be stated by the
following rules:
Rule 1: Only one input signal pulse is allowed to occur at one time.
Rule 2: Before the next pulse is allowed to occur, the circuit must be given time to reach a new stable
state via a single state change.
Rule 3: Each applied input pulse has a minimum pulse width that is determined by the time it takes to
change the slowest flipflop in the circuit to a new stable state.
Rule 4: The maximum pulse width of an applied input pulse must be sufficiently narrow so that it is
no longer present when the new present state output signals become available.
Example 4.8: Design a pulse mode asynchronous sequential circuit, that has two inputs X1 and X2,
one Mealy output Z1 and one Moore output Z2. The Mealy output is coincident with the third consecutive
pulse on input X2 and the Moore output occurs after the third consecutive pulse on input X2 or after
any pulse that occurs on input X1.
Solution: The state diagram for the circuit based on the given problem is shown in Figure 4.17.
Fig. 4.17: State Diagram
The flow table can be obtained from the state diagram as shown in Table 4.35.
The input conditions X1 X2 = 00, 01, 11 and 10 that are normally shown in flow table for either a
synchronous or fundamental mode asynchronous design, do not appear in a pulse mode design. In a
pulse mode circuit, the presence of a pulse at an input causes the circuit to change its state; however,
the absence of a pulse causes no change in the circuit and hence represents unimportant information.
To present the presence of a pulse in a pulse mode circuit, only the name of the pulse is listed; X1
represents input condition 10 and X2 represents input condition 01. Input condition 00 is not represented
in the flow table because this is unimportant information, and input condition 11 is not represented in
the flow table, because this violates the restriction imposed by Rule 1.
4.30 Digital Principles and System Design
TABLE 4.35: Flow Table
Present Next State/Output Z1 Output Z2
State X1 X2
a a, 0 b, 0 1
b a, 0 c, 0 0
c a, 0 a, Z1 0
The transition table with state assignment is shown in Table 4.36. For race- free state assignment,
an extra state ‘d’ is added. The binary code assignment for the states as follows: a 00, b 01,
c 11, d 10
TABLE 4.36: Transition Table
Present State Next State/Output Z1 Output Z2
y1 y2 X1 X2 Z2
0 0 00, 0 01, 0 1
0 1 00, 0 11, 0 0
1 1 00, 0 00, 1 0
1 0 00, 0 00, 0 0
Two state variables are reqired and y 1 and y2 are choosen. For these two state variables, two
memory storage devices are required. J-K flipflops can be used as T flipflops for the memory storage
devices.
The composite excitation inputs T1 and T 2 are obtained by using excitation table for T flipflop
from the transition table of Table 4.36.
Remember the excitation table for T flipflops as shown in Table 4.37. By using the present state
and reset state, flipflop inputs T1 and T4 are obtained as shown in Table 4.38.
TABLE 4.37: Excitation Table
Q(t) Q(t + 1) T
0 0 0
0 1 1
1 0 1
1 1 0
Asynchronous Sequential Logic 4.31
TABLE 4.38: Excitation Inputs
Present State Next State Flipflop Inputs
Y1 Y2 X1 X2 T1, T2 T1, T2
0 0 00 01 00 01
0 1 00 11 01 10
1 1 00 00 11 11
1 0 00 00 10 10
Using the K-map, logic hazard-free equations for T 1, T2, Z1 and Z2 can be obtained as shown in
Figure 4.18.
(i) Map for T1
Y1 Y2 X1 X2
00 0 0
01 0 1
11 1 1
10 1 1
T y x y x y x
(ii) Map for T2
X1 X2
y1 y2
00 0 1
01 1 0
11 1 1
10 0 0
T y x y y x y y x y y x (hazard free equation)
(iii) Map for Z1
y1 y2 X1 X2
00 0 0
01 0 0
11 0 1
10 0 0 Z y y x
Fig. 4.18: K map simplications
4.32 Digital Principles and System Design
The logic diagram for pulse mode asynchronous sequential circuit using positive edge triggered T
flipflops is drawn by using of the following equations:
T y x y x y x , T y x y y x y y x
Z y y x , Z y y
Fig. 4.19: Pulse Mode Sequential Circuit
Example 4.9: Design a pulse mode asynchronous sequential circuit for the automatic toll collecting
machine in a road. Suppose the toll is Rupees 9 and the machine accepts Rupees 2 and rupees 5 coins
and generate pulses X2 and X5 respectively. The sequential circuit should produce a level output
whenever the amount received by the toll machine is rupees 9 or more. After a vehicle has passed, a
reset pulse Xr is automatically produced, which makes output zero and resets the sequential circuit to
its initial state.
Solution: The state table for the given problem is shown in Table 4.39.
TABLE 4.39: State Table
Toll Present Next State Output
in Rupees State X2 X5 Xr Z
0 A B D A 0
2 B C F A 0
4 C E H A 0
5 D F H A 0
6 E G H A 0
7 F H H A 0
8 G H H A 0
9 or more H H H A 1
Asynchronous Sequential Logic 4.33
3
This state table shows there are eight states, hence 3 flipflops (2 = 8) are needed. Table 4.42
shows the state assignments and derivation of S-R flipflop inputs with the help of SR flipflop excitation
table, shown in Table 4.40.
TABLE 4.40: Excitation Table
Q(t) Q(t + 1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
TABLE 4.41: State assignment and excitation tables
Present Next States Flip-flop inputs
States X2 X5 Xr
PQR X2 X5 Xr S1R1 S2R2 S3R3 S1R1 S2R2 S3R3 S1R1 S2R2 S3R3
A 000 001 011 000 0 X 0X 1 0 0 X 1 0 1 0 0 X 0 X 0 X
B 001 010 101 000 0 X 1 0 0 1 1 0 0 X X 0 0 X 0 X 0 1
C 010 100 111 000 1 0 0 1 0 X 1 0 X 0 1 0 0 X 0 1 0 X
D 011 101 111 000 1 0 0 1 X 0 1 0 X 0 X 0 0 X 0 1 0 1
E 100 110 111 000 X 0 0 1 0 X X 0 1 0 1 0 0 1 0 X 0 X
F 101 111 111 000 X 0 1 0 X 0 X 0 1 0 X 0 0 1 0 X 0 1
G 110 111 111 000 X 0 X 0 1 0 X 0 X 0 1 0 0 1 0 1 0 X
H 111 111 111 000 X 0 X 0 X 0 X 0 X 0 X 0 0 1 0 1 0 1
For S1
X2 X5 Xr
QR QR QR
P 00 01 11 10 P 00 01 11 10 P 00 01 11 10
0 0 0 1 1 0 0 1 1 1 0 0 0 0 0
1 X X X X 1 X X X X 1 0 0 0 0
S X Q X R Q
4.34 Digital Principles and System Design
For R1:
X2 X5 Xr
QR QR QR
00 01 11 10 P 00 01 11 10 P 00 01 11 10
P
0 X X 0 0 0 X 0 0 0 0 X X X X
1 0 0 0 0 1 0 0 0 0 1 1 1 1 1
R X
For S2
X2 X5 Xr
QR QR QR
P 00 01 11 10 00 01 11 10 P 00 01 11 10
P
0 0 1 0 0 0 1 0 X X 0 0 0 0 0
1 0 1 X X 1 1 1 X X 1 0 0 0 0
S X QR X P R
For R2:
X2 X5 Xr
QR QR
QR
P 00 01 11 10 00 01 11 10 P 00 01 11 10
P
0 X 1 1 1 0 0 X 0 0 0 X X 1 1
1 1 0 0 0 1 0 0 0 0 1 X X 1 1
R X Q R PQ X r
For S3:
X2 X5 Xr
QR QR QR
P 00 01 11 10 00 01 11 10 00 01 11 10
P P
0 1 0 X 0 0 1 X X 1 0 0 0 0 0
1 0 X X 1 1 1 X X 1 1 0 0 0 0
S X P Q R P Q X
Asynchronous Sequential Logic 4.35
For R3:
X2 X5 Xr
QR QR QR
00 01 11 10 P 00 01 11 10 P 00 01 11 10
P
0 0 1 0 X 0 0 0 0 0 0 X 1 1 X
1 X 0 0 0 1 0 0 0 0 1 X 1 1 X
R X PQR Xr
Fig. 4.20: K map simplification
Figure 4.20shows the K-map simplification for SR flipflop inputs. The input equations are:
S X Q X R Q R X r
S X QR X P R R X Q R PQ X r
S X PQ R P Q X R X P Q R X r
The output equation is, Z = PQR.
The logic diagram for pulse mode asynchronous sequential circuit using S-R flipflops is shown in
Figure 4.21.
Fig. 4.21: Pulse Mode Sequential Circuit
4.36 Digital Principles and System Design
4.14 HAZARDS
Hazard is an unwanted transient i.e., spike or glitch that occurs due to unequal path or unequal
path or unequal propagation delays through a combinational circuit.
Types of hazards:
There are three types of hazards:
Static hazard, Dynamic hazard, Essential hazard.
4.14.1 Static Hazards
Static hazard is a condition which results in a single momentary incorrect output due to change in
a single input variable when the output is expected to remain in the same state. The two types of static
hazard are:
Static-0 hazard,
Static-1 hazard.
Static-0 hazard: When the output is to remain at the value 0 and a momentary 1 output is possible
during the transition between the two input states, then the hazard is called a static-0 hazard.
Static-1 hazard: When the output is to remain at the value 1 and q momentary 0 output is possible
during the transition between the two input states, then the hazard is called a static-1 hazard.
(a) Static-0 hazard (b) Static-1 hazard
(c) Dynamic hazard
Fig. 4.22: Types of hazards
Asynchronous Sequential Logic 4.37
4.14.2 Dynamic Hazard
Dynamic hazards occur when the output of a network is to change between its two logic states,
but a momentary false output signal occurs during the transient behaviour.
A dynamic hazard is defined as a transient change occurring 3 or more times at an output terminal
of a logic network when the output is supposed to change only once during a transition between two
input states differing in the value of one variable.
4.14.3 Essential Hazard
Essential hazard is a type of hazard that exists only in asynchronous sequential circuits with two
or more feedbacks. An essential hazard is caused by unequal delays along two or more paths that
originate from the same input. An excessive delay through an inverter circuit in comparison to the
delay associated with the feedback path may cause essential hazard.
4.15 HAZARDS ELIMINATION
To design a hazard-free switching circuit, all adjacent input combinations having same output
occur within some sub cube of the corresponding function. In other words, every pair of adjacent 1
cells or 0 cells in the K-map of a switching function should be covered by at least one sub cube.
4.15.1 Static Hazard
A static hazard can be removed by covering the adjacent cells with a redundant grouping that
overlaps both groupings. In the K-map shown in Figure 4.23(a), static hazard can be eliminated by
covering adjacent cells corresponding to 000 and 010 as shown by dotted subcube. This leads to
redundant grouping that overlaps both A B and B C groupings. The redundant term is AC and the
modified circuit is shown in Figure 4.23(c). Now, when the input (ABC) changes from 000 to 010,
the output will remain at ‘1’ state (for both 010 and 000 inputs) because of high output at the newly
added lower AND gate.
C
0 1
AB
00 1 1
01 1 0 f A B BC ; f = A B BC AC
11 1 0
10 0 0
(a) K-map for the function f = (0, 1, 2, 6)
4.38 Digital Principles and System Design
f A B BC
(b) Logic circuit with static hazard
(c) Logic circuit without static hazard
Fig. 4.23
4.15.2 Dynamic Hazards Elimination
Dynamic hazard can also be eliminated in a similar manner as that of static hazard elimination by
covering every pair of 1 cells and every pair of ‘0’ cells in the K-map by at least one sub cube.
4.15.3 Essential Hazards Elimination
Essential hazard can be eliminated by adding redundant gates as in static hazards. They can be
eliminated by adjusting the amount of delay in the affected path. For this, each feedback loop must be
designed with extra care to ensure that the delayin the feedback path is long enough compared tothe
delay of other signals that originate from the input terminals.
Example 4.10: Design a logic hazard-free circuit to implement the following function:
F(A, B, C, D) = m (0, 2, 4, 5, 6, 7, 8, 10, 11, 15)
.
Asynchronous Sequential Logic 4.39
Solution: Fig. 4.24(a) shows the K-map with minimum covering of 1’s of the function. The adjacent
1s at minterm locations (1, 4), (2, 6), (7, 15) and (10, 11) are not covered in the same sub-cube.
Adding product terms to cover these adjacent 1s results in a logic hazard-free function as shown in
Fig. 4.24(b).
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 1 00 1 1
01 1 1 1 1 01 1 1 1 1
11 1 11 1
10 1 1 1 10 1 1 1
F AB B D ACD ACD
F AB B D ACD AC D BCD A B C
Fig. 4.24: K map simplifications
For hazard-free circuit,
F AB B D ACD ACD AC D BCD A B C
Example 4.11: Implement the switching function f x1 ,x2 ,x3 x1 x2 x 2 x3 by a static hazard free 2
level AND-OR gate network. (Nov. 2004)
Solution: The K-map and AND-OR circuit are shown in Fig. 4.25for the switching function
F x1 x2 x 2 x3 with hazards.
x2x3
00 01 11 10
x1
0 1
1 1 1 1
F x1 x2 x 2 x3 AND-OR circuit
Fig. 4.25: Circuit with hazard
4.40 Digital Principles and System Design
Hazards in combinational circuits can be removed by covering anytwo minterms that may produce
a hazard with product term common to both. The removal of hazards requires the addition of redundant
gates to the circuit. The hazard free circuit obtained by adding extra gate in the circuit generates the
product terms x1x3 as shown in Fig. 4.26.
x2x3
00 01 11 10
x1
0 1
1 1 1 1
F x1 x2 x 2 x3 AND-OR circuit
Fig. 4.26: Circuit with hazard
Example 4.12: Find a static and dynamic hazard free realization for the following function uisng
(i) NAND gates
(ii) NOR gates.
f(a, b, c, d) = m(1, 5, 7, 14, 15)
Solution:
cd
ab 00 01 11 10
00 1
01 1 1
11 1 1
10
Hazard free expression
F = a’c’d + a’bd + bcd + abc
Asynchronous Sequential Logic 4.41
a
b
c
a’
c’
F
d
a’
b
c’
b
c
d
Using NAND gate
a
b
c
a’
c’
F
d
a’
b
c’
b
c
d
Using NOR Gate
a
b
c
a’
c’
d F
a’
b
c’
b
c
d
4.42 Digital Principles and System Design
Example 4.13: Implement the switching function F = m(1, 3, 5, 7, 8, 9, 14, 15) by a static hazard free
2 level AND-OR gate network.
Solution:
CD
AB 00 01 11 10
A
00 1 1
B
01 1 1 F
C
11 1 1
D
10 1 1
F AD ABC ABC
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1
F AD ABC ABC BCD
Asynchronous Sequential Logic 4.43
B
F
C
Fig: 4.27 Hazard free circuit
4.44 Digital Principles and System Design
TWO MARK QUESTIONS
1. What is fundamental mode sequential circuit?
Input variables changes if the circuit is stable
Inputs are levels, not pulses
Only one input can change at a given time
2 What is pulse mode circuit?
Inputs are pulses
Widths of pulses are long for circuit to respond to the input
Pulse width must not be so long that it is still present after the new state is reached
3. When does race condition occur?
Two or more binary state variables change their value in response to the change in I/p Variable
4. What is non critical race?
Final stable state does not depend on the order in which the state variable changes race condition
is not harmful
5. What is critical race?
Final stable state depends on the order in which the state variable changes -race condition is
harmful
6. When does a cycle occur?
Asynchronous circuit makes a transition through a series of unstable state
7. What is hazard?
Unwanted switching transients
8. What is static 1 hazard?
Output goes momentarily 0 when it should remain at 1
9. What are static 0 hazards?
Output goes momentarily 1 when it should remain at 0
10. What is dynamic hazard?
Output changes 3 or more times when it changes from 1 to 0 or 0 to 1
11. What is the cause for essential hazards?
Unequal delays along 2 or more path from same input
Asynchronous Sequential Logic 4.45
12. What is state equivalence theorem?
Two states SA and SB, are equivalent if and only if for every possible input X sequence, the
outputs are the same and the next states are equivalent i.e.,
if SA (t + 1) = SB (t + 1) and ZA = ZB then SA = SB.
13. What do you mean by distinguishing sequences?
Two states, SA and SB of sequential machine are distinguishable if and only if their exists at
least one finite input sequence. Which, when applied to sequential machine causes different
output sequences depending on whether SA or SB is the initial state.
14. Prove that the equivalence partition is unique
Consider that there are two equivalence partitions exist: PA and PB, and PA) PB. This states
that, there exist 2 states Si & Sj which are in the same block of one partition and not in the same
block of the other. If Si & Sj are in different blocks of say PB, there exists at least on input
sequence which distinguishes Si & Sj and therefore, they cannot be in the same block of PA.
15. Define compatibility.
States Si and Sj said to be compatible states, if and only if for every input sequence that affects
the two states, the same output sequence, occurs whenever both outputs are specified and
regardless of whether Si on Sj is the initial state.
16. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the state table
contains states. A line drawn between the two state vertices indicates each compatible state pair.
It two states are incompatible no connecting line is drawn.
17. Define incompatibility
The states are said to be incompatible if no line is drawn in between them. If implied states are
incompatible, they are crossed & the corresponding line is ignored
18. Define state table.
For the design of sequential counters we have to relate present states and next states. The table,
which represents the relationship between present states and next states, is called state table.
4.46 Digital Principles and System Design
19. What are the steps for the design of asynchronous sequential circuit?
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state Reduction
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.
20. Define primitive flow table.
It is defined as a flow table which has exactly one stable state for each row in the table. The
design process begins with the construction of primitive flow table.
21. What are the types of asynchronous circuits?
1. Fundamental mode circuits
2. Pulse mode circuits
22. What are races?
When 2 or more binary state variables change their value in response to a change in an input
variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a
race condition may cause the state variables to change in an unpredictable manner.
23. Define non critical race.
If the final stable state that the circuit reaches does not depend on the order in which the state
variable changes, the race condition is not harmful and it is called a non critical race.
24. Define critical race?
If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.
25. What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series of unstable
states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to
another, until the inputs are changed.
26. List the different techniques used for state assignment.
1. Shared row state assignment
2. One hot state assignment.
Asynchronous Sequential Logic 4.47
27. Write a short note on fundamental mode asynchronous circuit.
Fundamental mode circuit assumes that. The input variables change only when the circuit is
stable. Only one input variable can change at a given time and inputs are levels and not pulses.
28. Write a short note on pulse mode circuit.
Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the
pulses is long enough for the circuit to respond to the input and the pulse width must not be so
long that it is still present after the new state is reached.
4.48 Digital Principles and System Design
MCQ QUESTIONS
1. The race in which the stable state depends on an order is called
a)critical race
b)non-critical race
c)identical race
d)defined race
Answer: a. critical race
2. Asynchronous circuits are useful in application where the input signals may
a)change at any time
b)never change
c)both (a) & (b)
d)continuously change
Answer: c. both (a) & (b)
3. The table that is not a part of the asynchronous analysis procedure is
a)transition table
b)state table
c)flow table
d)excitation table
Answer: d. excitation table
4. In all the cases final stable state is----
a)changed
b)same
c)inverted
d)undefined
Answer: b. same
Asynchronous Sequential Logic 4.49
5. A condition occurs when an asynchronous sequential circuit changes two or more binary state
variables is known as---
a)deadlock condition
b)running condition
c)race condition
d)livelock
Answer: c. race condition
6. Time delay device is the memory element of
a)unclocked flipflops
b)clocked flipflops
c)synchronous circuits
d)asynchronous circuits
Answer: d. asynchronous circuits
7. Naming the state is done in---
a)transition table
b)state table
c)flow table
d)excitation table
Answer: c. flow table
8. The delay elements provide---
a)large memory
b)clock pulses
c)outputs
d)short term memory
Answer: d. short term memory
9. In the design procedure of the asynchronous circuit, the flow of the table
a)increased to maximum states
4.50 Digital Principles and System Design
b)reduced to minimum states
c)changed
d)remain same
Answer: b. reduced to minimum states
10. The race in which the stable state does not depend on an order is called
a)critical race
b)non-critical race
c)identical race
d)defined race
Answer: b. non-critical race
11. Asynchronous sequential logic circuits are used when a primary need is
a)time
b)pressure
c)speed
d)accuracy
Answer: c. speed
12. Internal state and input values together are called
a)full state
b)initial state
c)total state
d)output state
Answer: c. total state
13. The table having one stable state in each row is called
a)transition table
b)state table
Asynchronous Sequential Logic 4.51
c)flow table
d)primitive flow table
Answer: d. primitive flow table
14. The next states of asynchronous circuits are also called
a)secondary variables
b)primary variables
c)excitation variables
d)short term memory
Answer: c. excitation variables
15. Asynchronous sequential logic circuits usually perform operations in
a)identical mode
b)fundamental mode
c)reserved mode
d)reset mode
Answer: b. fundamental mode
16. In fundamental mode, the circuit is assumed to be in
a)unstable state
b)stable state
c)clear state
d)reset state
Answer: b. stable state
17. Which mechanism allocates the binary value to the states in order to reduce the cost of the
combinational circuits?
a. State Reduction
b. State Minimization
4.52 Digital Principles and System Design
c. State Assignment
d. State Evaluation
Answer: c. State Assignment
18. The dynamic hazard problem occurs in
a) Combinational circuit alone
b) Sequential circuit only
c) Both (a) and (b)
d) None of these
Answer: c. Both (a) and (b)
19. Which one is not the type of hazard
a) Static-0 Hazard
b) Static-1 Hazard
c) Dynamic Hazard
d) None of the above
Answer: d. None of the above
20. Which statement is suitable to explain glitch?
a) A glitch is produce in a logic circuit when a circuit output may produce a short pulse.
b) A glitch is produce in a logic circuit when circuits output never produce short pulses.
c) A glitch is produce in a logic circuit when a circuit output may produce a high pulse.
d)A glitch is produce in a logic circuit when circuits output never produce High pulses.
Answer: a. A glitch is produce in a logic circuit when a circuit output may produce a
short pulse.
21. Which one is the suitable to detect the hazard in circuit?
a) Karnaugh map
b) Boolean expression
c) Logic gates
Asynchronous Sequential Logic 4.53
d)None of these
Answer: a. Karnaugh map
22. Which circuit hazards must be eliminated?
a) Combinational circuit
b) Sequential circuit
c) Multiprocessor
d) Decoder
Answer: b. Sequential circuit
23. Which of the following does not constitute a static hazard?
a) the output goes to 0, then temporarily moves to 1, and then again back to 0
b) the output goes to 0, then temporarily moves to 1, and then to 0, and then to 1
c) the output goes to 1, then temporarily moves to 0, and then again back to 1
d) None of these
Answer: b. the output goes to 0, then temporarily moves to 1, and then to 0, and then to
1
24. Which of the following constitutes a dynamic hazard?
a) the output goes to 0, then temporarily moves to 1, and then to 0,before stabilizing to 1
b) the output goes to 0, then temporarily moves to 1, and then again back to 0
c) the output goes to 1, then temporarily moves to 0, and then to 1,before stabilizing to 0
d) both a & c
Answer: d. both a & c
25. To make the 2-level realization of the function=A’B+AC free from static-1 logic hazard,what
should you do?
a)Implement the function in multi-level form
b)Add a product term BC to F, and implement accordingly
4.54 Digital Principles and System Design
c) Add a product term B’C to F, and implement accordingly
d) None of these
Answer: b. Add a product term BC to F, and implement accordingly
26. Two states are said to be equal if they have the same
a)inputs
b)next state
c)output
d)mid state
Answer: c. output
27. Two states of an incompletely specified FA are compatible if
a)Both of the states have identical outputs for same input
b)Both of the states have identical output and compatible next states for same inputs
c)both of the states have compatible next states for all inputs
d)None of the above
Answer: b. Both of the states have identical output and compatible next states for same
inputs
28. Compatible pairs are obtained from
a)Merger graph
b)Compatability graph
c)Testing table
d)Testing graph
Answer: a. Merger graph
29. Which of the following is/are not true for an asynchronous sequential circuit?
a)The speed of the circuit dependson the delay of the flipflops
b)the number of flipflops required is more than that for a synchronous sequential circuit.
Asynchronous Sequential Logic 4.55
c)Both a & b
d)None of the above
Answer: c. Both a & b
30. An asynchronous sequential circuit is said to have reached a stable state when
a) All the inputs of the delay elements have appeared on the outputs of the delay elements
b) Atleast one of the input of the delay elements have appeared on the outputs of the delay
elements
c)The inputs of the delay elements have stabilized
d)None of these
Answer: a. All the inputs of the delay elements have appeared on the outputs of the
delay element
4.56 Digital Principles and System Design
REVIEW QUESTIONS
1) Implement the switching function F=∑(1,3,5,7,8,9,14,15) & G=∑(0,1,3,4,8-12) by a static
hazard free two level AND-OR gate network
2) Explain the race-free state assignment procedure in detail.
3) Discuss in detail the procedure for reducing the flow table with an example.
4) Reduce the number of states in the following state diagram. Tabulate the reduced state table and
draw the reduced state diagram.
Present Next State Output
state X=0 X=1 X=0 X=1
A a B 0 0
B c D 0 0
C a D 0 0
D e F 0 1
E a F 0 1
F g F 0 1
G a F 0 1
5) Construct a circuit with inputs A and B to give an output Z=1 when AB=11 but only if A
becomes 1 before B, by drawing total state diagram, primitive flow table and output map in
which transient state is included.
6) Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output z.
When x1= 0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output
Z to be 1. The output Z will remain until X 1 returns to zero
Asynchronous Sequential Logic 4.57
7).An asynchronous network has two inputs and one output. The input sequence X1X2 =00,
01,11causes the output to become 1.The next input change then causes the output to return to
0. No other input sequence will produce a 1 output. Construct the state diagram using primitive
flow table
8).Design a circuit with inputs A and B to give an output Z equal to 1 when AB=11 but only
if A becomes 1 before B, by drawing total state Diagram, primitive flow table and output
map in which transient state is Included.
Memory and Programmable Logic 5.1
UNIT V
MEMORY AND PROGRAMMABLE LOGIC
5.1 INTRODUCTION
A memory unit is a collection of storage cells with associated circuits needed to transfer information
in and out of the device. A memory unit stores binary information in group of bits called words. A
word in memory is an entity of bits that move in and out of storage as a unit. A word is a group of 1’s
and 0’s and may represent a number, an instruction, one or more alphanumeric characters or any other
binary-coded information. A group of 8 bits is called a byte. The byte can be split into two 4-bit units
that are called nibbles. The capacity of a memory unit is the total number of bytes that can be stored.
Suppose the memory capacity is 1024 8, it means that the number of words is 1024 and the number
of bits per word is 8.
Each word stored in a memory location is represented by an address.
5.2 MEMORY UNIT
The communication between a memory and its environment is achieved through data input/output
lines, address selection lines and control lines that specify the direction of transfer. A block diagram
of the memory unit is shown in Figure 5.1. The ‘n’ data input lines provide the information to be
stored in memory and the ‘n’ data output lines supply the information coming out of memory. The ‘K’
address lines specify the particular word chosen among the many variable. The two control inputs
(read and write) specify the direction of transfer desired. The write input causes binary data to be
transferred into the memory and the read input causes binary data to be transferred out of memory.
Fig. 5.1: Block diagram of a memory unit
5 . 2 Digital Principles and System Design
Data units go into the memory and come out of the memory on a set of lines called data bus. The
data bus is bi-directional, which means that data can go in either direction. For a write or a read
operation, an address is selected by placing a binary code representing the desired address on a set of
lines called the address bus. The address code is decoded internally and the appropriate address is
selected. The number of lines in the address bus depends on the capacity of the memory. For example,
a 16 bit address code can select 65536 locations (216) in the memory. The block diagram of memory
operation is shown in Figure 5.2.
Address Memory
Address Decoder Data
Bus Array Bus
n:2n
Enable R/W
Fig. 5.2: Block diagram of memory operation
5.3 WRITE OPERATION
During write operation, the binary data are stored in a specified memory location. When
R / W control input is low, write operation is performed. The following steps are followed to write a
content in the memory:
1. The address decoder decodes the address for specified memory location based on the given
input of the decoder.
2. Data is placed on the data bus.
3. The data is written in above specified location when the memory chip receives the write signal.
The write operation is explained in the Figure 5.3.
1. Address code 100
is placed on the
address bus and
address 4 is
selected.
2. Data byte is placed
on the data bus.
3. Write command
causes the data
byte to be stored in
address 4, repla-
cing previous data.
Fig. 5.3: Write Operation
Memory and Programmable Logic 5.3
5.4 READ OPERATION
During read operation, the required contents are read from the specific memory location. When
the R / W control input is high, the read operation is performed. The following steps are followed
during the read operation:
1. The address decoder decodes the specified memory location based on the input of the decoder.
2. The read command is sent to memory.
3. The content of specified memory location is placed on the data bus.
The read operation is illustrated in Figure 5.4.
Fig. 5.4 : Read Operation
1. Address code 101 is placed on the address bus and address 5 is selected.
2. Read command is applied.
3. The contents of address 5 is placed on the data bus and shifted into data register.
5.5 CLASSIFICATION OF MEMORIES
Memories are usually classified as either bipolar or metal oxide semiconductor (MOS) or
complementary MOS (CMOS) according to the type of transistor used to construct the memory cells.
The operation of bipolar memories is fast but greater packing density. MOS and CMOS memories are
cheap and small in size and require low power.
5 . 4 Digital Principles and System Design
Memory
RAM ROM
Random Access Read-Only
Memory Memory
SRAM DRAM
Static RAM Dynamic RAM
Bipolar MOS MOS
PROM EPROM EEPROM
Programmable Erasable Electrically
ROM PROM Erasable PROM
Bipolar MOS MOS MOS
Fig. 5.5: Classification of Memories
The two general categories of memory, RAM and ROM can be further divided as illustrated in Figure 5.5.
5.5.1 RAM
Random Access Memory is a volatile chip memory in which both read and write operations can
be performed. RAMS are volatile because the stored data will be lost once the d.c. power applied to
the flip-flops is removed.
Random access means a bit (0 or 1) can be written (stored) in any cell or read (detected) from any
cell. A control signal (Enable) is used to enable or disable the chip. In the read mode, data from the
selected memory cells is made available at the output. In the write mode, information at the data input
is written into the selected memory cells. The address lines determine the cells written into or read
from. A typical RAM chip is shown in Figure 5.6.
Fig. 5.6 : RAM Chip
Memory and Programmable Logic 5.5
5.5.2 STATIC RAM
Static RAMs use flipflops as storage elements and can therefore store data indefinitely as long as
d.c. power is applied. SRAMs can be of either Bipolar or MOS technology.
5.5.3 Dynamic RAM
Dynamic RAMs use capacitors as storage elements and cannot retain data very long without the
capacitors being recharged by a process called refreshing. DRAMs can store much more data than
SRAMs. DRAMs are available in only MOS technology.
5.5.4 ROM
Read Only Memory (ROM) is a semi conductor memory device used to store the information
permanently. It performs only read operation and does not have a write operation. A ROM stores data
that are used repeatedly in system applications, such as tables, conversions or programmed instructions
for system initialization and the user cannot alter its function.
5.5.5 PROM
The PROM, Programmable ROM is the type in which the data are electrically stroed by the user
with the aid of specialized equipment but cannot be reprogrammed. PROMs are available in both
bipolar and MOS technologies.
5.5.6 EPROM
A PROM device that can be erased and reprogrammed is called Erasable PROM (EPROM). It is
strictly a MOS device.
To program a new data, all cells in the EPROM must be erased. This is done by illuminating cells
by a strong ultraviolet (UV) light. EPROMS are provided with a transparent quartz window on the
top of the chip to allow UV rays for erasing the data. Changes in the selected memory locations
cannot be made in the reprogramming. The entire memory should be erased before reprogramming.
5.5.7 EEPROM
Electrically Erasable PROM (EEPROM) can be erased and programmed by the application of
controlled electric pulses to the IC in the circuit. The changes can be made in the selected memory
locations without disturbing the correct data in other memory locations.
5.6 RAM ORGANIZATION
Figure 5.7 shows the organization of a typical 16K 1 SRAM. The memory cell array is arranged
in 128 rows and 128 columns. The chip select, CS must be low for the memory to operate. Seven of
the 14 address lines are decoded by the row decoder to select one of the 128 rows. Seven of the 14
address lines are decoded by the column decoder to select one of the 128 columns.
5 . 6 Digital Principles and System Design
If CS and R / W are low, then it is a write operation. In write operation, data on the Din input is
written into the addressed cell while the output will remain in the high impedance state. For read
operation CS signal must be low and R / W signal must be high. In read operation, data from addressed
cell appears at the output while the input buffer is disabled.
When CS is high both input and output buffers are disabled and the chip is electrically
disconnected. This makes the IC to operate in power down mode.
Fig. 5.7 : RAM organization (16K 1)
5.7 STATIC RAM CELL
The cell is a single storage element in the memory. The cell is selected by high values on the row
and column lines. The input data bit (0 or 1) is written into the cell by setting the flip-flop for a 1 and
resetting the flip-flop for a 0 when R / W line is low. When R / W line is high, the flip-flop is unaffected.
Memory and Programmable Logic 5.7
It means that the stored bit (data) is gated to the Data out line. The logic diagram of a static RAM cell
is shown in Figure 5.8. The flip-flop is static RAM cell can be constructed using BJT (Bipolar
technology) and MOSFET (MOS technology).
Fig. 5.8 : Logic diagram of a static RAM cell
5.8 BIPOLAR RAM CELL
The Bipolar memory cell is implemented using TTL (Transistor-Transistor-Logic) multiple emitter
technology. It stores 1 bit information. It is nothing but a flip-flop. It can store either 0 or 1 as long as
power is applied and it can set or reset to store either 1 or 0, respectively. In a bipolar static RAM cell
shown in Figure 5.9, two BJTs Q1 and Q2 are cross coupled to form a flip-flop. Each transistor has
three emitters, namely Row select input, Column select input and Write input. To select the cell, both
the row and column select lines must be held high. When selected a data bit can be stored in the cell
(Write operation) or the content of the cell can be read (Read operation). If either row or column
select line is low, then the memory cell is disabled.
The Row select line and Column select line select a cell from matrix. The Q1 and Q2 are cross
coupled, hence one is always OFF while the other is ON. A ‘1’ is stored in the cell if Q1 is conducting
and Q2 is OFF. A ‘0’ is stored in the cell if Q2 is conducting and Q1 is OFF. The state of the cell is
changed to ‘0’ by pulsing a high on the Q1 (write input) emitter. This turns OFF Q1. When Q1 is turned
OFF, Q2 is turned ON. As long as Q2 is ON, its collector is low and Q1 is held OFF.
5 . 8 Digital Principles and System Design
Fig. 5.9 : Bipolar SRAM cell
A 1 can be rewritten by pulsing the Q2 (write input) emitter high. Large number of these memory
cells are organized on a row and column basis to form a memory chip.
5.9 MOSFET RAM CELL
Each cell of static RAM is constructed by using flipflops. The number of flipflops is equal to the
number of cells in a memory. Since the number of cells is usually very large, so it is required to use
minimum devices per cell to occupy minimum chip area per cell in order to have more number of cells
per chip. This reduces cost, shortens access time etc. Therefore these flip-flops are constructed using
MOSFETs.
If the MOSFET T1 is turned ON then the output Q is low, which means that MOSFET T2 is cut
OFF. Since T2 is cut off, the output is high, ensuring that T1 is turned ON. Thus we have a static
situation as long as the bias voltage +VCC is applied to the circuit. The MOSFETs TA and TB are
connect the memory cell to the normal and complementary data lines (Data and Data ). The MOSFETss
T3 and T4 are act as load resistors.
When the bit select line is LOW, both TA and TB are cut off and the memory cell is isolated. The
data stored in the cell remain stored as long as power is applied to the cell. When the bit select line is
HIGH, the memory cell is connected to the data lines so that the data in the cell can be read or new
data can be written into the cell. The MOS RAM cell is shown in Figure 5.10.
Memory and Programmable Logic 5.9
Fig. 5.10 : MOS RAM cell
5.10 DYNAMIC RAM CELL
The dynamic RAM (DRAM) stores its binary information in the form of electric charges on
capacitors. The basic storage device in DRAM is not a flip-flop but a simple MOSFET and a capacitor.
The advantage of DRAM is that it is very simple, thus allowing very large memory arrays to be
constructed on a chip at a lower cost per bit. The disadvantage of DRAM is that the storage capacitor
cannot hold its charge over an extended period of time and will lose the stored data bit unless its
charge is refreshed periodically.
Column line
Row line
CS
Fig. 5.11 : DRAM cell
5 .1 0 Digital Principles and System Design
In DRAM memory cell, a bit of data is stored as charge on storage capacitor, where the presence
or absence of charge determines the value of the stored bit 1 or 0. The DRAM cell includes a MOSFET
and a storage capacitor (Cs) as shown in Figure 5.11. When column line and row line go high, the
MOSFET conducts and charges the capacitor. When column and row lines go low, the MOSFET
opens and the capacitor retains its charge. In this way it stores 1 bit.
5.10.1 Operation
The DRAM cell consists of 3 tri-state buffers: Input buffer, Output buffer and Refresh buffer.
Input and output buffers are enabled and disabled by controlling R/W line. When R/W = 0 , input
buffer is enabled and output buffer is disabled. When R/W = 1, input buffer is disabled and output
buffer is enabled.
(i) Write Operation
The write operation is illustrated in Figure 5.12. To enable write operation R/W line is made
low, which enables input buffer and disables output buffer. To write a 1 into the cell, the DIN line is
high and MOSFET is turned ON by a high on the Row line. This allows the capacitor to charge to a
positive voltage. When 0 is to be stored, a low is applied to the DIN line. The capacitor remains
uncharged or if it is storing a 1, it discharges. When the Row line is made Low, the transistor turns
OFF and disconnects the capacitor from the data line, thus storing the charge (1 or 0) on the capacitor.
Fig. 5.12 : Writing a 1 into the memory cell
(ii) Read Operation: To read data from the cell, the R/W line is made high, which enables output
buffer and disables input buffer. Then Row line is made high. It turns MOSFET ON and connects the
capacitor to the DOUT line through output buffer. Read operation is shown in Figure 5.13.
Memory and Programmable Logic 5.11
Fig. 5.13 : Reading a 1 from the memory cell
(iii) Refresh Operation: To enable refresh operation, R/W line, Row line and Refresh line are made
high. This turns ON MOSFET and connects capacitor to column line. As R/W is high, output buffer
is enabled and the stored data bit is applied to the input of refresh buffer. The enabled refresh buffer
then produces a voltage on column line corresponding to the stored bit and thus replenishing the
capacitor. This refresh operation is illustrated in Figure 5.14.
Fig. 5.14 : Refreshing a stored 1
5.10.2 DRAM Organization
In DRAM address multiplexing is used to reduce the number of address lines. The block diagram
of 16K DRAM is shown in Figure 5.15. 16K = 16 1024 = 16384 bits = 214, therefore 14 bit address
is applied to address inputs. First, the seven-bit Row address has to be applied and RAS (Row Address
Strobe) line latches the seven bits into the Row address latch.
Next, the seven bit column address is applied to the address inputs and CAS (Column Address
Strobe) latches the remaining 7 bits into the column address latch. Then the 7 bit Row address and the
5 .1 2 Digital Principles and System Design
7 bit column address are decoded to select the appropriate memory cell in the 128 128 dynamic
memory array for a Read or Write operation.
Row Row
Address Address
Latch Decoder
Column Column
Address Address
Latch Decoder
Fig. 5.15 : Block diagram of 16K DRAM
5.11 ROM
It is a Read Only Memory. ROM is a memory device in which permanent binary information is
stored. The binary information must be specified by the designer and is then embedded in the unit to
form the required interconnection pattern. Once the pattern is established, it stays within the unit even
when power is turned off and on again, i.e., it is non- volatile memory. The ROMs are classified as
follows:
(i) Masked ROM or ROM
(ii) Programmed ROM (PROM)
(iii) Erasable PROM (EPROM)
(iv) Electrically Erasable PROM (EEPROM)
5.12 ROM CELL
5.12.1 Diode ROM
The presence of a connection from a row line to the anode of the diode represents a 1 at that
location because when the row line is taken HIGH, all diodes are turn ON and connect the HIGH (1)
to the associated column lines. The ROM cell using diode is shown in Figure 5.16.
Memory and Programmable Logic 5.13
Fig. 5.16 : ROM cell using diode
5.12.2 Bipolar ROM
The presence of a connection from a row line to the base of a transistor represents a 1 at that
location because, when the row line is taken HIGH, all transistors with base connection to that row
line turn ON and connect the high (1) to the associated column lines. When there are no base connection
at row or column, the column lines remain low (0) when the row is addressed.
Fig. 5.17 : Bipolar ROM cell
5.12.3 MOS ROM
The presence of a connection from a row line to the gate of a MOSFET represents a 1 at that
location because when the row line is taken high, all MOSFETs with a gate connection to that row
line turn ON and connect the high (1) to the associated column lines. At row/column junctions where
there are no gate connections, the column lines remain low (0) when the row is addressed. The MOS
cells are shown in Figure 5.18.
Column Column
Row Row
+ VCC + VCC
Storing a 1 Storing a 0
Fig. 5.18 : MOS ROM cell
5 .1 4 Digital Principles and System Design
5.13 ROM ORGANIZATION
A simple ROM organization is shown in Figure 5.19. The dark squares represent ROM cells
stored 1s and the light squares represent ROM cells stored Os. When a 4-bit binary address is applied
to the address inputs, the corresponding row line become high. This high is connected to the column
lines through the transistors at each junction (cell) where a 1 is stored. At each cell where a 0 is stored,
the column line stays low because of the terminating resistor. The column lines form the data output.
Thus the 8 data bits stored in the selected row appear on the output lines.
A 16 8 ROM organization is shown in Figure 5.19. It is organized into 16 addresses, each of
which stores 8 data bits. Its total capacity is 128 bits (16 bytes).
Fig. 5.19 : 16 8 ROM
A typical TTL ROM IC 74187 is shown in Figure 5.20. It is a 16 pin, 1024 bits, 256 words of 4
bits each ROM. The memory cells are organized in a 32 32 matrix. Five of the eight address lines
(A0 A4 ) are decoded by the row decoder to select one of the 32 rows. Three of the eight address
lines (A5 A7) are decoded by the column decoder to select four of the 32 columns. The result of this
structure is that when an 8 bit address code (A0 A7) is applied, a 4 bit data word appears on the data
outputs when the chip enable lines ( E 0 and E 1 ) are LOW to enable the output buffers.
Memory and Programmable Logic 5.15
Fig. 5.20 : 1024 bit ROM
5.14 PROM
Programmable ROM (PROM) can be programmed electrically by the user but cannot be
reprogrammed. A PROM uses some type of fusing process to store bits, in which a memory link is
burned open on left intact to represent a 0 or a 1. The using process is irreversible; once a PROM is
programmed, it cannot be changed.
The fusible links are manufactured into the PROM between the cathode of each diode and its
column line as shown in Figure 5.21. In the programming process, a sufficient current is injected
through the fusible link to burn it open to create a stored 0. The link is left intact for a stored 1.
Fig. 5.21 : PROM cell using diodes
In Bipolar PROM, the fusible links are connected between the emitter of each cell’s BJT and its
column line as shown in Figure 5.22.
5 .1 6 Digital Principles and System Design
Fig. 5.22 : Bipolar PROM cell
In MOS PROM, the fusible links are connected between the source of each cell’s MOSFET and
its column line as shown in Figure 5.23.
Fig. 5.23 : PROM using MOSFET
A PROM is normally programmed by inserting it into a special instrument called a PROM
programmer. An address is selected by the electronic switches on the address lines and then a pulse
is applied to those output lines corresponding to bit locations where 0s are to be stored (the PROM
starts out with all 1s). These pulses blow the fusible links, thus creating the desired bit pattern. The
next address is then selected and the process is repeated. This sequence is automatically done by a
software-driven PROM programmer.
5.14.1 Fuse Technologies
The fuse technologies used in PROMs are metal links, silicon links and P-N junctions. A brief
description of each of these follows:
(i) Metal links are made by Nichrome. Each bit in the memory array is represented by a separate
link. During programming, the link is either blown open or left intact. This is done by forcing a
sufficient amount of current through the link to cause it to open.
(ii) Silicon links are formed by narrow, notched strips of polycrystalline silicon. Programming of
these fuses requires melting of the links by passing a sufficient amount of current through them.
This current causes a high temperature at the fuse location that oxidizes the silicon and forms an
insulation around the new-open link.
Memory and Programmable Logic 5.17
(iii) Shorted junction or avalanche-induced migration technology consists basically of two p-n
junctions arranged back-to-back. During programming, one of the diode junctions is avalanched
and the resulting voltage and heat short the junction. The remaining junction is then used as a
forward biased diode to represent a data bit.
Fig. 5.24 : PROM with fusible links
5.15 EPROM
An EPROM is an erasable PROM. EPROMs can be reprogrammed by the user with a special
EPROM programmer. We can erase the stored data in EPROM.
An EPROM uses an array of N-channel enhancement type MOSFET with an isolated gate structure.
The isolated transistor gate (floating gate) has no electrical connections and can store an electrical
charge for indefinite periods of time. The data bits in this type of array are represented by the presence
or absence of a stored gate charge. Erasure of a data bit is a process that removes the gate charge.
Figure 5.25 shows the basic structure and symbol of a typcial EPROM cell.
Consider the programming of an EPROM with 1s as initial values in all the cells. To program or
store a 0 in a such a cell, the floating gate must be charged. For this, a high voltage of about 16 to 20
volts is applied between the source and drain, and a voltage of about 25 to 50 volts is applied to the
control gate for a specified amount of time (50 ms per address location). Due to high electric field
established by the positive control gate voltage, the high energy electrons penetrate the thin insulating
SiO2 and reach the floating gate. Thus the charge is stored on the floating gate. Since more negative
charge accumulates on the floating gate, the electric field strength is reduced and thereby further
accumulation is inhibited. Programming actually involves selecting the desired cell gates and repeatedly
5 .1 8 Digital Principles and System Design
injecting charge onto the floating gate until a sufficient amount of charge is trapped. Since the gate is
surrounded by SiO2, there is no discharge path available. Therefore, the charge remains trapped on
the floating gate for an indefinite period of time. Now the cell is programmed for a logic 0.
(a) Structure (b) Symbol
Fig. 5.25 : EPROM cell
To program a different data, all cells in the EPROM must be erased. This is done by electrically or
ultraviolet light.
Thus EPROMs are classified as: Ultraviolet Erasable PROM (UV PROM)
Electrically Erasable PROM (EE PROM)
5.16 UV EPROM
The UVPROM has a transparent quartz lid on the
package. The stored data is erased by exposure of the
memory arry chip to high-intensity ultraviolet radiation
through the quartz window on top of the package for 15
to 20 minutes. The positive charge stored on the gate is
neutralized after several minutes of exposure time.
It is not possible to erase selective information, when
erased the entire information is lost. The chip can be
reprogrammed many times.
Fig. 5.26 : UV EPROM Chip
5.17 EEPROM
EEPROM (Electrically Erasable PROM) can be both erased and programmed by the application
of controlled electric pulses to the IC in the circuit and thereby changes can be made in the selected
memory locations without disturbing the correct data in other memory locations. EEPROM is non-
volatile memory.
Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the
device. The insulating layer is made very thin. Therefore, a voltage as low as 20 to 25 volts can be
used to move charges accross the thin barrier in either direction for programming or erasing.
EEPROMs are small in size and flexible. With EEPROM, the programs can be altered remotely.
Memory and Programmable Logic 5.19
5.18 MEMORY CYCLES AND TIMING WAVE FORMS
5.18.1 Read Cycle
The timing wave form for SRAM read cycle is shown in Figure 5.27. The timing wave form and
timing parameters for SRAM read cycle are identical to ROM read cycle. The timing parameters for
read operation in a static RAM are given below:
tAA Access time from address. Assuming that OE and CS are already asserted, or will be soon
enough not to make a difference, this is how long it takes to get stable output data after a change
in address.
tACS Access time from chip select. Assuming that the address and OE are already stable, or will be
soon enough not to make a difference, this is how long it takes to get stable output data after CS
is asserted. Often this parameter is identical to tAA, but sometimes it’s longer is SRAMs with a
“power-down” mode and shorter in SRAMs without one.
tOE Output-enable time. This is how long it takes for the three-stage output buffers to leave the
high-impedance state when OE and CS are both asserted. This parameter is normally less than
tACS, so it is possible for the RAM to start accessing data internally before OE is asserted
tOZ Output-disable time. This is how long it takes for the three-state outut buffers to enter the high-
impedance state after OE or CS is negated.
tOH Output-hold time. This parameter specifies how long the output data remains valid after a
change in the address inputs.
Fig. 5.27: Read cycle ( WE = High)
5.18.2 Write Cycle
The timing parameters for write cycle are shown in Figure 5.28 and are described below:
tAS Address setup time before write. All of the address inputs must be stable at this time before
both CS and WE are asserted. Otherwise, the data stored at unpredictable locations may be
corrupted.
5 .2 0 Digital Principles and System Design
tAH Address hold time after write. Analogous to tAS, all address inputs must be held stable unit this
time after CS or WE is negated.
tCSW Chip-select setup before end of write. CS must be asserted at least this long before the end of
the write cycle in order to select a cell.
tWP Write-pulse width. WE must be asserted at least this long to reliably latch data into the selected
cell.
tDS Data setup time before end of write. All of the data inputs must be stable at this time before
the write cycle ends. Otherwise, the data may not be latched.
tDH Data hold time after end of write. Analogous to tDS, all data inputs must be held stable until
this time after the write cycle ends.
tAH
Fig. 5.28 : Write cycle ( WE = low)
5.19 MEMORY DECODING
In addition to the storage components in a memory unit, there is a need for decoding circuits to
select the memory word specified by the input address. In addition to internal decoders, a memory
unit may also need external decoders. This happens when RAM ICs are connected in a multichip
memory configuration. The use of an external decoder to provide a large capacity memory.
Microprocessor system includes memory devices and I/O devices. Microprocessor can
communicate (read/write) with only one device at a time, since the data, address and control buses are
common for all the devices. In order to communicate with memory or I/O devices, it is necessary to
decode the address from the microprocessor. Due to this, memory or I/O device can be accessed
independently. The decoding techniques are
Absolute Decoding
Linear Decoding
Absolute decoding is normally used in large memory systems. In this technique, all the higher
address lines are decoded to select the memory chip and the memory chip is selected only for the
specified logic levels on these high-order address lines; no other logic levels can select the chip.
Memory and Programmable Logic 5.21
For the design of memory decoder, each memory IC used in the system should be assigned with a
range of addresses according to its capacity. The address range assigned to a particular memory IC
should not be assigned to some other memory IC in the same digital system.
For example, to select an EPROM and a RAM of 1 K byte capacity each, kept the address
assignment in non-overlapped manner. Let the address assigned to EPROM and RAM are as follows:
EPROM (1 K byte) : 0000 H 03FF H
RAM (1 K byte) : 2000 H 23FF H
It means that the starting address of the EPROM is 0000 H and the end address is 03FF H while
the starting address for RAM is 2000 H and the end address is 23FF H. The range of addresses can be
written in binary form as given in Table 5.1.
TABLE 5.1 : Address Assignment
Memory Address A15 A14 A13 A12 A11 A10 A9 A 8 A 7 A 6 A5 A4 A3 A2 A 1 A 0
(Hex)
EPROM
Starting 0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
address
EPROM
End 03FF H 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
address
RAM
Starting 2000 H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
address
RAM
End 23FF H 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1
address
The memory decoder for the given address assignment can be designed for the given address
assignment can be designed using a 3 to 8 decoder IC 74LS138 as shown in Figure 5.29.
Linear decoding or partial decoding technique is used in small memory systems. In this decoding,
address line A15 is directly connected to CS of EPROM and after inversion using a NOT gate, it is
connected to CS of RAM. Therefore, when the status of A15 line is 0, EPROM gets selected, otherwise
RAM gets selected. The status of other address lines is not considered. Let the address assigned to
EPROM and RAM are
EPROM (1 K byte) : 0000 H 03FF H
RAM (1 K byte) : 8000 H 83FF H
5 .2 2 Digital Principles and System Design
A12 A11
Fig. 5.29 : Absolute decoding technique
5.20 MEMORY EXPANSION
Available memory can be expanded to increase the word length (number of bits in each address)
or the word capacity (number of different addresses) or both. Memory expansion is accomplished by
adding an appropriate number of memory chips to the address, data and control buses.
5.20.1 Word Length Expansion
To increase the word length of a memory, the number of bits in the data bus must be increased. An
8-bit word length can be achieved by using two memories, each with 4 bit words as shown in Figure
5.30. The 16 bit address bus of 64 K ROM is commonly connected to both ROMs so that the
combination memory still has the same number of addresses (216 = 65536) as each individual memory.
The 4 bit data buses from the two memories are combined to form an 8 bit data bus. Now when an
address is a selected, 8 bits are produced on the data bus - four from each ROM.
Memory and Programmable Logic 5.23
64K x 8
16 bits 16 bits
Address Bus Address Bus
4 bits 4 bits
ROM ROM
64K x 4 Data
1
Control Bus Control
Bus
Bus
Data
8 bits Bus
16 bits
Address Bus
ROM 4 bits 16 bits ROM
64K x 4 2 4 bits
Data
Control Bus
Bus
(a) Two separate 64 K 4 ROMs (b) One 64 K 8 ROM
Fig. 5.30 : 64 K 4 ROMs into 64 K 8 ROM
Figure 5.30(b) is explained with address bus (A0A15 ), control but ( E ) and data bus (O0 O7 ) is
illustrated in Figure 5.31.
Fig. 5.31: 64 K 4 ROMs to 64 K 8 ROM
5 .2 4 Digital Principles and System Design
Example 5.1: Form 64 K 16 ROM using 64 K 4 ROM.
Solution
Fig. 5.32: 64 K 4 ROMs into a 64 K 16 ROM
5.20.2 Word-Capacity Expansion
When memories are expanded to increase the word capacity, the number of addresses is increased.
To achieve this increase, the number of address bits must be increased. Two 1M 8 RAMs are
expanded to form a 2M 8 RAM is shown in Figure 5.33. The twenty first address bit is used to
enable the appropriate memory chip. The data bus for the expanded memory remains eight bits wide.
20 bits 20 bits
Address Bus Address Bus
8 bits
RAM EN RAM 1 8 bits
1M x 8 Data
1Mx8
Control Bus Control
Bus
Bus
Data
20 bits 8 bits Bus
20 bits
Address Bus
RAM 8 bits RAM 2
1Mx8 1 M x 8 8 bits
Data
Control Bus
Bus
(a) Two separate 1M 8 RAM (b) 2M 8 RAM
Fig. 5.33: Word Capacity Expansion
Example 5.2: Use 512K 4 RAMs to implement a 1M 4 RAM.
Solution: The expanded addressing is achieved by connecting the chip enable ( E 0 ) input to the 20th
bit (A19).
When A19 ( E 0 ) = 0 , RAM 1 is selected; RAM 2 is disabled; (A0A18 ) access each of the address
in RAM 1.
When A19 ( E 0 ) = 1 , RAM 2 is enabled using a NOT gate; RAM 1 is disabled; (A0 A18) access
each of the RAM 2 address.
Input E 1 is used as an enable input common to both memories.
Memory and Programmable Logic 5.25
The 1M 4 RAM implementation is shown in Figure 5.34.
A0 RAM 1
20 bit 512 K x 4
Address
bus
A18
E0
A19
& EN D0
E1
D2
D3
RAM 2
512 K x 4
Control & EN
Bus
Fig. 5.34: 1M 4 RAM using 512 K 4 RAM
5.21 ADVANTAGES OF RAM
RAM has the following advantages: 1. Fast operating speed. ( < 150 nS), 2. Low power
dissipation ( < 1 mW), 3. Economy, 4. Compatibility, 5. Non-destructive read-out.
5.22 ADVANTAGES OF ROM
ROM has the following advantages:
Ease and speed of design.
Faster than MSI devices PLD and FPGA.
The program that generates the ROM contents can easily be structured to handle unusual
or undefined cases.
A ROM’s function is easily modified just by changing the stored pattern, usually without
changing any external connections.
More economical.
5.23 DISADVANTAGES OF ROM
For functions more than 20 inputs, a ROM based circuit is impractical because of the limit on
ROM sizes that are available.
For simple to moderately complex functions, ROM based circuit may costly; consume more
power; run slower.
5 .2 6 Digital Principles and System Design
5.24 COMPARISON BETWEEN RAM AND ROM
RAM ROM
RAMs have both read and write ROMs have only read operation
capability.
RAMs are volatile memories. ROMs are non-volatile memories.
They lose stored data when They retain stored data even if
the power is turned off power is turned off
RAMs are available in both bipolar ROMs are available in both bipolar
and MOS technologies and MOS technologies
Types: SRAM, DRAM, EEPROM Types: PROM, EPROM
5.25 COMPARISON BETWEEN SRAM AND DRAM
Static RAM Dynamic RAM
SRAM consists of flipflops. DRAM stores the data as charge on
Each flipflop stores one bit. the capacitor. It consists of MOSFET
and the capacitor for each cell.
SRAM contains less memory DRAM contains more memory cells per
cells per unit area. unit area.
Its access time is less, hence Its access time is greater than SRAM.
faster memories.
Cost is more. Cost is less.
Refreshing circuitry is not required. Refreshing circuitry is required.
5.26 COMPARISON OF TYPES OF MEMORIES:
Memory Non-Volatile High Density One-Transistor In-system
type cell writability
SRAM No No No Yes
DRAM No Yes Yes Yes
ROM Yes Yes Yes No
EPROM Yes Yes Yes No
EEPROM Yes No No Yes
Memory and Programmable Logic 5.27
5.27 IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUITS USING ROM
Example 5.3: Draw 4 2 ROM with AND-OR gates.
Solution
A0
2x4
Decoder
A1
F1 F2
Fig. 5.35 : 4 2 ROM
Example 5.4: Draw the logic construction of 32 4 ROM.
Solution
A0 0
A1 1
A2 5 x 32 2
Decoder
A3
A4 31
128 Fuses
F1 F2 F3 F4
Fig. 5.36 : 32 4 ROM
Example 5.5: Implement the following Boolean functions using ROM
F1 (A1 , A0 ) = (1 , 2)
F2 (A1 , A0 ) = (0 , 1 , 3)
5 .2 8 Digital Principles and System Design
Solution: A0
2x4
Decoder
A1
F1 F2
Fig. 5.37 : ROM circuit
Example 5.6: Design a combinational circuit for 3 bit binary to excess-3 code converter using ROM.
Solution: Truth Table for Binary to Excess 3 code converter.
Inputs Outputs
A2 A1 A0 B3 B2 B1 B0
0 0 0 0 0 1 1
0 0 1 0 1 0 0
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 0 1 1 1
1 0 1 1 0 0 0
1 1 0 1 0 0 1
1 1 1 1 0 1 0
A0
A1 3x8
Decoder
A2
B3 B2 B1 B0
Fig. 5.38 : Binary to Excess 3 code converter
Memory and Programmable Logic 5.29
Example 5.7: Implement the following Boolean function using ROM (PROM)
F1 = m (1, 2, 3) ; F2 = m (0, 1, 3).
A B
F1 F2
Fig. 5.39 : PROM circuit
5.28 PROGRAMMABLE LOGIC DEVICES
A programmable logic device (PLD) is an integrated circuit with internal logic gates that are connected
through electronic fuses. Programming the device involves the blowing of internal fuses to achieve a
desired logic function. The initial state of PLD has all the fuses intact as shown in Figure 5.56(a).
All PLD consist of programmable arrays. A programmable array is essentially a grid of conductors
that form rows and columns with a fusible link at each cross point. Arrays can be either fixed or
programmable. The gates in a PLD are divided into an AND array and an OR array that are connected
together to provide an AND-OR implementation.
Figure 5.56(b) shows an OR array consists of OR gates connected to a programmable matrix
with fusible links at each cross point of a row and column. The array can be programmed by blowing
fuses to eliminate selected variables from the output functions as shown in Figure 5.56(b).
A A B B A A B B
Fusible link
Y1 Y1=A+B
Y2 Y2=A+B
Y3 Y3=A+B
(a) Unprogrammed (b) Programmed
Fig. 5.40 : Programmable OR array
5 .3 0 Digital Principles and System Design
Figure 5.57(a) shows an AND array consists of AND gates connected to a programmable matrix
with fusible links at each cross point of a row and column. The array can be programmed by blowing
fuses to eliminate variables from the output function as shown in Figure 5.41(b).
A A B B A A B B
Fusible link
Y1 Y1=AB
Y2 Y2=AB
Y3 Y3=AB
(a) Unprogrammed (b) Programmed
Fig. 5.41 : Programmable AND array
5.29 CLASSIFICATION OF PLDs
The classification of PLDs are as follows:
1. Simple Programmable Logic Devices (SPLD)
(i) Programmable ROM (PROM) (ii) Programmable Logic Array (PLA)
(iii) Programmable Array Logic (PAL) (iv) Generic Array Logic (GAL)
2. Complex Programmable Logic Devices (CPLD)
3. Field Programmable Gate Array (FPGA).
5.29.1 PROM
The PROM has a fixed (non-programmable) AND array and programmable fuses for the output
OR gates. The PROM implements Boolean function in sum of minterms.
Fixed Fuses Fused
Inputs AND Programmable Outputs
array OR array
Fig. 5.42 : PROM
5.29.2 Programmable Array Logic (PAL)
The PAL has a fused programmable AND array and a fixed OR array as shown in Figure 5.43.
The AND gates are programmed to provide the product terms for the Boolean functions that are
logically summed in each OR gate.
Memory and Programmable Logic 5.31
Fuses Fused Fixed
Inputs Programmable OR Outputs
AND array array
Fig. 5.43 : PAL
5.29.3 Programmable Logic Array (PLA)
The PLA has a programmable AND array and a programmable OR array as shown in Figure 5.44.
The product terms in the AND array may be shared by any OR gate to provide the required sum of
products implementation. The PLA may be mask programmable or field programmable.
(i) Mask Programmable Logic Array
With a mask PLA, the customer must submit a PLA program table to the manufacturer. This table
is used by the vendor to produce a custom-made PLA that has the required internal paths between
inputs and outputs.
(ii) Field Programmable Logic Array (FPLA)
The FPLA can be programmed by the user by means of certain recommended procedures.
Commercial hardware programmer units are available for use in conjunction with certain FPLAs.
Fuses Fused Fuses Fused
Inputs Programmable Programmable Outputs
AND array OR array
Fig. 5.44: PLA
5.29.4 Field Programmable Gate Array (FPGA)
The FPGA consists of an array of logic blocks with programmable row and column interconnecting
channels surrounded by programmable I/O blocks.
Types of PLDs
Device AND-array OR-array
PROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed
PLDs have hundreds of gates interconnected through hundreds of electronic fuses. It is sometimes
convenient to draw the internal logic of such devices in a compact form referred to as Array Logic.
5 .3 2 Digital Principles and System Design
Figure 5.45 shows the convenient and array logic symbols for multiple-input AND gate and NOT
gate.
(a) Conventional Symbol (b) Array Logic Symbol
Fig. 5.45 : Array Logic Symbols
5.30 PROGRAMMABLE ROM (PROM)
PROMs are used for code conversions, generating bit patterns for characters and as look-up tables
for arithmetic functions.
As a PLD, PROM consists of an fixed AND-array and a programmable OR array. The AND array
is really an n-to-2n decoder and the OR array is simply a collection of programmable OR gates. The
OR array is also called the memory array. The decoder serves as a minterm generator. The n-variable
minterms appear on the 2n lines at the decoder output. The 2n outputs are connected to each of the `m’
gates in the OR array via programmable fusible links. Figure 5.46 illustrates a 2n m PROM.
2n word lines
n
n-to-2
‘n’ input Programmable ‘m’ output
Decoder
lines OR array lines
(AND array)
Fig. 5.46 : 2n m PROM
Memory and Programmable Logic 5.33
Example 5.8: Design a logic circuit for the following Boolean expressions using (PROM).
f1 x, y,z m 0,1,2,5,7
f 2 x, y,z m 1,2 , 4,6
Solution: Truth Table
x y z f1 f2
0 0 0 1 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 0 1
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0
PROM Logic Design
Fig. 5.47 : PROM circuit
5 .3 4 Digital Principles and System Design
5.31 PROGRAMMABLE LOGIC ARRAY
PLA is used in logic design where the number of don’t care conditions is excessive, since it is
more economical. In the PLA, the decoder (in ROM) is replaced by a group of AND gates, each of
which can be programmed to generate a product term of the input variables. The AND and OR gates
inside the PLA are initially fabricated with fuses among them. The specific Boolean functions are
implemented in sum of products form by blowing appropriate fuses and leaving the desired connections.
The block diagram of the PLA is shown in Figure 5.48. It consists of ‘n’ inputs, ‘m’ outputs, ‘k’
product terms and ‘m’ sum terms. The product terms constitute a group of ‘k’ AND gates and the sum
terms constitute a group of ‘m’ OR gates. Fuses are inserted between all ‘n’ inputs and their complement
values to each of the AND gates. Fuses are also provided between the outputs of the AND gates and
the inputs of the OR gates. Another set of fuses in the output inverters allow the output function to be
generated either in the AND-OR form or in the AND-OR- INVERT form. With the inverter fuse in
place, the inverter is bypassed, giving an AND-OR implementation. With the fuse blown, the inverter
becomes part of the circuit and the function is implemented in the AND-OR-INVERT form.
Fig. 5.48 : PLA block diagram
This PLA design is explained with the following example.
Example 5.9: Implement the combinational circuit for the functions
F1 = m (4, 5, 7) ; F2 = m (3, 5, 7)
Solution: The steps required in PLA implementation are:
Step 1: Truth Table for given functions
Step 2: K-map simplification
Step 3: PLA program table
Step 4: PLA diagram
Step 1: Truth Table:
A B C F1 F2
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1
Memory and Programmable Logic 5.35
Step 2: K map Simplification:
BC
A 00 01 11 10
0 0 1 3 2
1 1 1 1
4 5 7 6
F1 AB AC
BC
A 00 01 11 10
1
0 0 1 3 2
1 1
1 4 5 7 6
F2 AC BC
Step 3: PLA Program Table:
Product Inputs Outputs
Term A B C F1 F2
AB 1 1 0 1
AC 2 1 1 1 1
BC 3 1 1 1
T T T/C
In the PLA program table, first column lists the product terms numerically as 1, 2, 3. The second
column (Inputs) specifies the required paths between AND gates and inputs. For each product term,
the inputs are marked with 1, 0 or (dash). If a variable in the product term appears in its normal form
(unprimed), the corresponding input variable is marked with a 1. If it appears complemented (primed),
the corresponding input variable is marked with a 0. If the variable is absent in the product term, it is
marked with a dash.
The third column (outputs) specifies the paths between the AND gates and the OR gates. The output
variables the marked with 1’s for all those product terms that formulate the function. For example,
F1 AB AC
5 .3 6 Digital Principles and System Design
So F1 is marked with 1’s for product terms 1 and 2 and with a dash for product term 3. Each
product term that has a 1 in the output column requires a path from the corresponding AND gate to the
output OR gate. Those marked with a dash specify no connection.
Under each output variable, write T or C. The T (true) specifies that the fuse across the output
inverter remains intact and a C (complement) specifies that the corresponding fuse be blown. The
PLA circuit is shown in Figure 5.49.
Inputs (A, B, C) n=2
Product terms (1, 2, 3) k=3
Outputs (F1, F2) m=2
Fig. 5.49 : PLA circuit
5.32 IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUIT USING PLA
Example 5.10: Implement the following functions using PLA. (Dec. 2005)
F1 = m (1, 2, 4, 6) ; F2 = m (0, 1, 6, 7)
F3 = m (2 , 6)
Solution: Step 1: Truth Table for given functions:
A B C F1 F2 F3
0 0 0 0 1 0
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 0 1 0
Memory and Programmable Logic 5.37
Step 2: K map Simplification:
BC
A 00 01 11 10
0 1 1
0 1 3 2
1 1 1
4 5 7 6
F1 ABC AC BC
BC
00 01 11 10
A
1 1
0
0 1 3 2
1 1
1
4 5 7 6
F2 A B AB
BC
A 00 01 11 10
0 1
0 1 3 2
1 1
4 5 7 6
F3 = BC
Step 3: PLA Program Table:
Product Inputs Outputs
Term A B C F1 F2 F3
ABC 1 0 0 1 1
AC 2 1 0 1
BC 3 1 0 1 1
AB 4 0 0 1
AB 5 1 1 1
T T T T/C
5 .3 8 Digital Principles and System Design
Step 4: Draw the PLA circuit with
3 inputs
5 product terms
3 outputs
Fig. 5.50 : PLA circuit
Example 5.11: Implement the combinational circuit with a PLA having 3 inputs, 4 product terms and
2 outputs for the functions:
F1 = (3 , 5 , 6 , 7), F2 = (0, 2, 4, 7) (Dec. 2005)
Solution: Step 1: Truth Table for Boolean Functions:
A B C F1 F2
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Memory and Programmable Logic 5.39
Step 2: K map Simplification:
BC
A 00 01 11 10
0 1
1 1 1 1 F1 AC AB BC
BC
A 00 01 11 10
0 1 1
1 1 1 F 2 B C AC ABC
With this simplification, the total number of product terms is 6. But we require only 4 product
terms. Therefore find out the K map simplification for F 1 and F 2 .
BC
A 00 01 11 10
0 0 0 0
1 0 F 1 B C AC A B
BC
A 00 01 11 10
0 0 0
1 0 0 F 2 AC BC ABC
Now select the functions F 1 and F 2 , since the common product terms are BC , AC , AB , ABC
Step 3: PLA Program Table:
Product Inputs Outputs
Term A B C F1 F2
BC 1 0 0 1 1
AC 2 0 0 1 1
AB 3 0 0 1
ABC 4 1 1 1 1
C T T/C
F1 B C A C A B ; F2 B C A C ABC
5 .4 0 Digital Principles and System Design
Step 4: Draw the PLA circuit with
3 inputs, 4 product terms and 2 outputs.
Fig. 5.51 : PLA circuit
It should be noted that F 1 really occurs at one of the outputs of the OR-array. By programming
the corresponding EX-OR gate fuse, F 1 F1 appears at the output of thePLA.
Example 5.12: A combinational logic circuit has 4 inputs and 2 outputs. The output 1 gives high
output when the input combinational is greater than or equal to 1001 and the output 2 gives high
output when the input combinational is les than 1001. Implement the circuit with PLA.
Solution: Step 1: Truth Table for given problem:
A B C D F1 F2
0 0 0 0 0 1
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0
1 1 0 0 1 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 0
Memory and Programmable Logic 5.41
Step 2: K map Simplification:
CD
AB 00 01 11 10
00
01
11 1 1 1 1
10 1 1 1 F1 = AB + AD + AC
CD
AB 00 01 11 10
00 1 1 1 1
01 1 1 1 1
11
10 1 F2 A BC D
Step 3: PLA Program Table:
Product Term Inputs Outputs
A B C D F1 F2
AB 1 1 1 1
AC 2 1 1 1
AD 3 1 1 1
A 4 0 1
BC D 5 0 0 0 1
T T T/C
Step 4: Draw the PLA circuit with 4 inputs, 5 product terms and 2 outputs.
Fig. 5.52 : PLA circuit
5 .4 2 Digital Principles and System Design
Example 5.13: Design a BCD-to-Excess 3 code converter with PLA circuit. (May 2006)
Solution: Step 1: Truth Table for BCD to XS-3 code converter:
Decimal BCD Code Excess-3 Code
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Step 2: K map Simplification:
For E3
B1B0
B3B2 00 01 11 10
00
01 1 1 1
11 X X X X
10 1 1 X X
E3 = B3 + B2 B0 + B2 B1
For E2
B1B0
00 01 11 10
B3B2
00 1 1 1
01 1
11 X X X X
10 1 X X
E2 B2 B1 B 0 B 2 B0 B 2 B1
Memory and Programmable Logic 5.43
For E1
B1B0
B3B2 00 01 11 10
00 1 1
01 1 1
11 X X X X
10 1 X X
E1 B1 B 0 B1 B0
For E0
B1B0
B3B2 00 01 11 10
00 1 1
01 1 1
11 X X X X
10 1 X X X
E0 B 0
Step 3: PLA Program Table
Product terms Inputs Outputs
B3 B2 B1 B0 E3 E2 E1 E0
B3 1 1 1
B2B0 2 1 1 1
B2B1 3 1 1 1
B2 B1 B 0 4 1 0 0 1
B 2 B0 5 0 1 1
B 2 B1 6 0 1 1
5 .4 4 Digital Principles and System Design
B1 B 0 7 0 0 1 1
B1 B 0 8 1 1 1
B0 9 1 0 1
T T T T T/C
Step 4: Draw the PLA circuit with 4 inputs, 9 product terms and 4 outputs.
Fig. 5.53 : PLA circuit
Memory and Programmable Logic 5.45
Example 5.14: Implement the switching function. (May 2013)
Z1 abde abcde bc de
Z2 a ce
Z3 bc de cde bd
Z4 ace ce using 5 x 8 x 4 PLA
Solution:
PLA Program Table
Product Terms Inputs Outputs
a b c d e Z1 Z2 Z3 Z4
abde 1 1 0 0 1 1
abcde 2 0 0 0 0 0 1
bc 3 1 1 1 1
de 4 1 1 1 1
ace 5 0 0 1 1 1
cde 6 0 0 0 1
bd 7 1 1 1
ce 8 1 1 1
5 .4 6 Digital Principles and System Design
abde a bcde bc de ace cde bd ce
1 2 3 4 5 6 7 8
z1
z2
z3
z4
5.33 PROGRAMMABLE ARRAY LOGIC (PAL)
The PAL consists of a programmable array of AND gates that connects to a fixed array of OR
gates. This structure allows any sum-of-products (SOP) logic expression with a defined number of
variables to be implemented.
Example 5.15: Implement the circuit with PAL for the function Y AB AB AB .
Solution:
Fig. 5.54 : PAL circuit
Memory and Programmable Logic 5.47
5.34 IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUIT USING PAL
Example 5.16: Draw the PAL diagram for the following Boolean functions:
Y3 ABCD ABC D ABCD ABC D
Y2 ABC D ABCD ABCD
Y1 ABC ABC AC ABC
Y0 ABCD
Solution: (Nov. 2004)
Fig. 5.55 : PAL circuit
Example 5.17: Implement the following Boolean functions using PAL.
W A,B,C,D 0 ,2 ,6 ,7 ,8,9,12,13
X A,B,C,D 0 , 2 ,6 ,7 ,8,9 ,12 ,13,14
Y A,B,C,D 2 ,3,8,9 ,10 ,12,13
Z A,B,C,D 1,3, 4 ,6 ,9,12,14
5 .4 8 Digital Principles and System Design
Solution:
1. Simplifying the given Boolean functions to a minimum number of terms using K-map.
For W
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1
W ABD ABC AC
For X
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1 1
10 1 1
X ABD ABC AC BC D W BC D
For Y
CD
00 01 11 10
AB
00 1 1
01
11 1 1
10 1 1 1
Y ABC BC D AC
For Z
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1
Z ABD BCD BD
Memory and Programmable Logic 5.49
II. PAL Program Table
AND Inputs
Product Term Outputs
A B C D W
ABD 1 0 0 0
ABC 2 0 1 1 W
AC 3 1 0
W 4 1
BC D 5 1 1 0 X
6
ABC 7 0 0 1
BC D 8 0 1 0 Y
AC 9 1 0
ABD 10 0 0 1
BCD 11 0 0 1 Z
BD 12 1 0
w
III. PAL Diagram
Fig. 5.56 : PAL circuit
5 .5 0 Digital Principles and System Design
Example 5.18: Implement the given function using PAL
A = (0, 2 , 6 , 7 , 8, 9, 12, 13)
B = (0, 2, 6, 7, 8, 9, 12, 13, 14)
C = (1, 3, 4, 6, 10, 12, 13)
D = (1, 3, 4, 6, 9, 12, 14)
Solution: I. K map Simplification:
For A
YZ
WX 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1
A W Y X Y Z W XY WY Z
For B
YZ
WX 00 01 11 10
00 1 1
01 1 1
11 1 1 1
10 1 1
B W Y X Y Z W XY WY Z XY Z A XY Z
For C
YZ
WX 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1
C X Y Z WX Y W X Z W X Z W X Z W XY Z
Memory and Programmable Logic 5.51
For D
YZ
WX 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1
D X Z X YZ W X Z
II. PAL Program Table:
Product Inputs Outputs
Term W X Y Z A
WY 1 1 0
XYZ 2 0 0 0 A
W XY 3 0 1 1
WY Z 4 0 1 0
A 5 1
XY Z 6 1 1 0 B
XYZ 7 1 0 0
WX Y 8 1 1 0
WX Z 9 0 1 0 C
W XZ 10 0 0 1
W XY Z 11 1 0 1 0
XZ 12 1 0
XYZ 13 0 0 1 D
W XZ 14 0 0 1
5 .5 2 Digital Principles and System Design
III. PAL Diagram
W W X X Y Y Z Z A A
Fig. 5.57 : PAL circuit
5.35 FIELD PROGRAMMABLE GATE ARRAYS (FPGA)
The FPGA basically consists of an array of logic blocks with programmable row and column
interconnecting channels surrounded by programmable I/O blocks as shown in Figure 5.58. Many
FPGA architectures are based on a type of memory called LUT (look-up table) rather than on AND/
OR arrays. Another approach is the use of multiplexers to generate logic functons. FPGA is a single
VLSI (Very Large Scale Integrated) circuit constructed on a single piece of silicon.
Memory and Programmable Logic 5.53
Fig. 5.58 : Basic Block Diagram of an FPGA
The module shown in Figure 5.59 consists of 3 number of interconnected 2-to-1 multiplexer and
an OR gate whose output selects the MUX 3.
Fig. 5.59 : FPGA module
5 .5 4 Digital Principles and System Design
Logic expression for MUX 1, X X 0 S X X 1S X
Logic expression for MUX 2, Y Y0 S Y Y1SY
By connecting the input of this module in different ways, the module can be programmed as a
variety of 2 or 3 or 4 input gates. For example, by connecting X0, X1, Y0 and S1 to 0, the expression for
output Z becomes Z Y1 SY S0 and now this module acts like a 3 input positive logic AND gate. Similarly
by connecting different inputs to high and low, the module acts like different gates. The logic circuit
design procedure using FPGA involves the following steps:
1. Capture the logic circuit to be implemented with a suitable software package, using a library of
logic elements which are various configuration of basic modules available in FPGA. In addition,
many FPGA libraries also contain predesigned circuits for multiplexers, encoders, adders and
so on. Predesigned circuits make design much easier.
2. Functional simulation simulates the circuit to determine whether it is function properly.
3. Configure and interconnect the modules of the FPGA to produce the desired logic circuit. This
may be done automatically by a routing software called routes. Once the routing is over, it is
now possible to determine the actual circuit delays which can now be introduced into the
simulation model. Now an accurate simulation of the circuit can be available.
4. Programming is done by the FPGA interconnections. The routing of the devices determined in
the previous step is now made into a fuse map. Then this fuse map is used in conjunction with
a device programmer to make the internal device connections.
5. After programming, it must be tested. If the designed function is not fulfiled, it must be
reprogrammed. With careful simulation, reprogramming can be minimized.
5.36 COMPARISON BETWEEN PROM, PLA AND PAL
Sl.No. PROM PLA PAL
1. Fixed AND array Programmable AND and Programmable AND and
Programmable OR arrayProgrammable OR arrayFixed OR array
2. A11 minterms are decoded AND array can be programmed AND array can be
to get desired minterms. programmed to get
desired minterms.
3. Only Boolean functions is Any Boolean functions Any Boolean functions in
standard SOP form can be in SOP form can be SOP form can be
implemented. implemented implemented
4. Cheaper Costlier than PAL and Cheaper
PROM
5. Simple to use Complex than PAL and Simple to use
PROM
5.37 EAPROM:
EAPROM stands for Electronically Alterable Programmable Read-Only Memory. It is a type of PROM whose
contents can be changed. It acts as a non-volatile storage device, and its individual bits can be re-programmed
during the course of system operation.
5.55 Digital Principles and System Design
TWO MARK QUESTIONS
1. Explain ROM
A read only memory (ROM) is a device that includes both the decoder and the OR gates within a
single IC package. It consists of n input lines and m output lines. Each bit Combination of the
input variables is called an address. Each bit combination that comes out of the output lines is
called a word. The number of distinct addresses possible with n input variables is 2n.
2. What are the types of ROM?
1. PROM
2. EPROM
3. EEPROM
3. Explain PROM.
PROM (Programmable Read Only Memory) it allows user to store data or program. PROMs use
the fuses with material like nichrome and polycrystalline. The user can blow these fuses by pass
in around 20 to 50 mA of current for the period 5 to 20 μs. The blowing of fuses is called
programming of ROM. The PROMs are one time programmable. Once programmed, the
information is stored permanent.
4. Explain EPROM.
EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store
1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in
the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes.
It is not possible to erase selective information. The chip can be reprogrammed.
5. Explain EEPROM.
EEPROM (Electrically Erasable Programmable Read Only Memory). EEPROM also use MOS
circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate
in the device. EEPROM allows selective erasing at the register level rather than erasing all the
information since the information can be changed by using electrical signals.
6. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bit combination
that comes out of the output lines is called a word.
Memory and Programmable Logic 5.56
7. What are the types of ROM.?
1. Masked ROM.
2. Programmable Read only Memory
3. Erasable Programmable Read only memory.
4. Electrically Erasable Programmable Read only Memory.
8. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a
second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it
does not provide full decoding of the variables and does not generates all the min terms as in the
ROM.
9. What is mask - programmable?
With a mask programmable PLA, the user must submit a PLA program table to the
manufacturer.
10. What is field programmable logic array?
The second type of PLA is called a field programmable logic array. The user by means of certain
recommended procedures can program the EPLA.
11. List the major differences between PLA and PAL
PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL
PAL : AND arrays are programmable OR arrays are fixed Cheaper and Simpler
12. Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR gates that Can be
programmed to achieve specific logic functions.
13. Give the classification of PLDs.
PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array
(PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL)
14. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates Connected
to a decoder and a programmable OR array.
5.57 Digital Principles and System Design
15. Define PLA.
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a Programmable
AND array and a programmable OR array.
16. Define PAL.
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR
array with output logic.
16. Why was PAL developed?
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays
due to additional fusible links that result from using two programmable arrays and more circuit
complexity.
17. Define GAL.
GAL is Generic Array Logic. GAL consists of a programmable AND array and a fixed OR array
with output logic.
18. Why the input variables to a PAL are buffered
The input variables to a PAL are buffered to prevent loading by the large number of AND gate
inputs to which available or its complement can be connected.
19. What is CPLD?
CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a
centralized internal interconnect matrix used to connect the device macro cells together.
20. Define bit, byte and word.
The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte. A complete
unit of information is called a word which consists of one or more bytes.
21. How many words can a 16x8 memory can store?
A 16x8 memory can store 16,384 words of eight bits each
22. What is Read and Write operation?
The Write operation stores data into a specified address into the memory and the Read operation
takes data out of a specified address in the memory.
Memory and Programmable Logic 5.58
23. Why RAMs are called as Volatile?
RAMs are called as Volatile memories because RAMs lose stored data when the power is turned
OFF.
24. Define ROM.
ROM is a type of memory in which data are stored permanently or semi permanently. Data can be
read from a ROM, but there is no write operation.
25. Define RAM.
RAM is Random Access Memory. It is a random access read/write memory. The data can be
read or written into from any selected address in any sequence.
26. Define Static RAM and dynamic RAM.
Static RAM use flip flops as storage elements and therefore store data indefinitely as long as dc
power is applied. Dynamic RAMs use capacitors as storage elements and cannot retain data very
long without capacitors being recharged by a process called refreshing.
27. List the two types of SRAM.
Asynchronous SRAMs and Synchronous Burst SRAMs
28. List the basic types of DRAMs.
Fast Page Mode DRAM, Extended Data Out DRAM (EDO DRAM),Burst EDO DRAM and
Synchronous DRAM.
29. Define a bus.
A bus is a set of conductive paths that serve to interconnect two or more functional components
of a system or several diverse systems.
30. Define Cache memory.
It is a relatively small, high-speed memory that can store the most recently used instructions or
data from larger but slower main memory.
31. What is the technique adopted by DRAMs.
DRAMs use a technique called address multiplexing to reduce the number of address lines.
32. Give the feature of UV EPROM.
UV EPROM is electrically programmable by the user, but the store data must be erased by
exposure to ultra violet light over a period of several minutes.
5.59 Digital Principles and System Design
33. Give the feature of flash memory.
The ideal memory has high storage capacity, non-volatility; in-system read and write capability,
comparatively fast operation. The traditional memory technologies such as ROM, PROM,
EEPROM individually exhibits one of these characteristics, but no single technology has all of
them except the flash memory.
34. What are Flash memories?
They are high density read/write memories that are non-volatile, which means data can be stored
indefinitely with out power.
35. List the three major operations in a flash memory.
Programming, Read and Erase operation
36. List basic types of programmable logic devices.
1. Read only memory
2. Programmable logic Array
3. Programmable Array Logic
37. Define address and word.
In a ROM, each bit combination of the input variable is called on address. Each bit combination
that comes out of the output lines is called a word.
38. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a
second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it
does not provide full decoding of the variables and does not generates all the min terms as in the
ROM.
39. What is mask - programmable?
With a mask programmable PLA, the user must submit a PLA PLA program table to the
manufacturer.
40. Mention the classification of saturated bipolar logic families.
The bipolar logic family is classified as follows:
RTL- Resistor Transistor Logic
DTL- Diode Transistor logic
Memory and Programmable Logic 5.60
I2L- Integrated Injection Logic
TTL- Transistor Transistor Logic
ECL- Emitter Coupled Logic
41. Mention the important characteristics of digital IC’s?
Fan out, Power dissipation, Propagation Delay, Noise Margin, Fan In, Operating temperature,
Power supply requirements
42. Define Fan-out?
Fan out specifies the number of standard loads that the output of the gate can drive without
impairment of its normal operation.
43. Define power dissipation?
Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
44. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to
output when the signals change in value. It is expressed in ns.
45. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause
an undesirable change in the circuit output. It is expressed in volts.
46. Define fan in?
Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
47. What are the types of TTL logic?
1. Open collector output 2. Totem-Pole Output 3. Tri-state output.
48. Mention the characteristics of MOS transistor?
1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned of if its gate- to- source voltage is zero.
49. List the different versions of TTL
TTL (Std.TTL)
LTTL (Low PowerTTL)
HTTL (High Speed TTL)
5.61 Digital Principles and System Design
STTL (Schottky TTL)
LSTTL (Low power Schottky TTL)
50. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce
excessive current and may result in damage to the devices.
51. State advantages and disadvantages of TTL
Adv: Easily compatible with other ICs Low output impedance
Disadv: Wired output capability is possible only with tristate and open collector types Special
circuits in Circuit layout and system design are required.
Memory and Programmable Logic 5.62
MCQ QUESTIONS
1. A PLA is similar to a ROM in concept except that ____________
a) It hasn’t capability to read only
b) It hasn’t capability to read or write operation
c) It doesn’t provide full decoding to the variables
d) It hasn’t capability to write only
Answer: c. It doesn’t provide full decoding to the variables
2. PLA is used to implement ____________
a) A complex sequential circuit
b) A simple sequential circuit
c) A complex combinational circuit
d) A simple combinational circuit
Answer: c. A complex combinational circuit
3. PLA contains ____________
a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays
Answer: a. AND and OR arrays
4. The complex programmable logic device contains several PLD blocks and __________
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches
Answer: c. Global interconnection matrix
5.63 Digital Principles and System Design
5. The difference between a PAL & a PLA is ____________
a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only
has a programmable AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only
has a programmable AND plane
d) The PAL has more possible product terms than the PLA
Answer: b. The PLA has a programmable OR plane and a programmable AND plane,
while the PAL only has a programmable AND plane
6. If a PAL has been programmed once ____________
a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
Answer: d. It cannot be reprogrammed
7. What is memory decoding?
a) The process of Memory IC used in a digital system is overloaded with data
b) The process of Memory IC used in a digital system is selected for the range of address
assigned
c) The process of Memory IC used in a digital system is selected for the range of data assigned
d) The process of Memory IC used in a digital system is overloaded with data allocated in
memory cell
Answer: b. The process of Memory IC used in a digital system is selected for the range of
address assigned
Memory and Programmable Logic 5.64
8. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word
length of 8 bits?
a) 2
b) 4
c) 6
d) 8
Answer: d. 8
9. The advantages of RAMs are __________
a) Non destructive read out
b) Fast operating speed
c) Low power dissipation
d) All of the Mentioned
Answer: d. All of the Mentioned
10. The DRAM stores its binary information on __________
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
Answer: c. Capacitor
11. The memory which is used for storing programs and data currently being processed by the CPU
is called __________
a) PROM
b) Main Memory
c) Non-volatile memory
d) Mass memory
Answer: a. PROM
5.65 Digital Principles and System Design
12. Dynamic RAM is more preferable than static RAM, why?
a) DRAM is of the lowest cost, lowest density
b) DRAM is of the highest cost, reduced size
c) DRAM is of the lowest cost, highest density
d) DRAM is more flexible and lowest storage capacity
Answer: c. DRAM is of the lowest cost, highest density
13. DRAM uses of integrated MOS capacitors as _______ instead of a flip-flop.
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
Answer: b. Memory cell
14. What is the disadvantage of MOS capacitor in DRAM?
a) It can’t hold the data till a long period
b) It doesn’t holds the charge till a long period
c) It is highly densed
d) It is not flexible
Answer: b. It doesn’t holds the charge till a long period
15. Why do a DRAM employ address multiplexing technique?
a) To reduce the number of memory locations
b) To increase the number of memory locations
c) To reduce the number of address lines
d) To increase the number of address lines
Answer: c. To reduce the number of address lines
Memory and Programmable Logic 5.66
16. What is a sense amplifier?
a) It is an amplifier which converts ac current into dc current
b) It is an amplifier which lowers the input voltage
c) It is an amplifier which increases the input voltage
d) It is an amplifier which converts the low voltage to a sufficient voltage
Answer: d. It is an amplifier which converts the low voltage to a sufficient voltage
17. What is access time?
a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
Answer: c. The time taken to read a stored word after applying the address bits
18. Which programming is done during manufacturing process?
a) Mask Programming
b) PROM
c) Both PROM and mask programming
d) EPROM
Answer: a. Mask Programming
19. Which of the following best describes EPROMs?
a) EPROMs can be programmed only once
b) EPROMs can be erased by UV
c) EPROMs can be erased by shorting all inputs to the ground
d) EPROMs can be erased electrically
Answer: b. EPROMs can be erased by UV
5.67 Digital Principles and System Design
20. Which ROM can be erased by an electrical signal?
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
Answer: d. EEPROM
21. What does the term “random access” mean in terms of memory?
a) Any address can be accessed in systematic order
b) Any address can be accessed in any order
c) Addresses must be accessed in a specific order
d) Any address can be accessed in reverse order
Answer: b. Any address can be accessed in any order
22. A major disadvantage of the mask ROM is that ____________
a) It is time consuming to change the stored data when system requirements change
b) It is very expensive to change the stored data when system requirements change
c) It cannot be reprogrammed if stored data needs to be changed
d) It has an extremely short life expectancy and requires frequent replacement
Answer: c. It cannot be reprogrammed if stored data needs to be changed
23. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
Answer: b. ROM
24. Why are ROMs called non-volatile memory?
a) They lose memory when power is removed
Memory and Programmable Logic 5.68
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied
Answer: b. They do not lose memory when power is removed
25. Static memory holds data as long as __________
a) AC power is applied
b) DC power is applied
c) Capacitor is fully charged
d) High Conductivity
Answer: b. DC power is applied
26. PLDs with programmable AND and fixed OR arrays are called __________
a) PAL
b) PLA
c) APL
d) PPL
Answer: a. PAL
27. When both the AND and OR are programmable, such PLDs are known as __________
a) PAL
b) PPL
c) PLA
d) APL
Answer: c. PLA
5.69 Digital Principles and System Design
28. The difference between FPGA and PLD is that __________
a) FPGA is slower than PLD
b) FPGA has high power dissipation
c) FPGA incorporates logic blocks
d) All of the Mentioned
Answer: c. FPGA incorporates logic blocks
29. A dynamic memory is one in which __________
a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always
Answer: d. Memory is dynamic always
30. What is a fusing process?
a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
Answer: c. It is a process by which programs are burnout to the diode/transistors
Memory and Programmable Logic 5.70
REVIEW QUESTIONS
1. Explain in detail about the programmable Logic Array and Programmable Array Logic.
2. Design a 16-bit RAM array (4X4 RAM) and explain the operation.
3. Explain Field Programmable Gate Array (FPGA).
4. Design a switching circuit that converts a 4-bit binary code into a 4-bit gray code using
ROM array.
5. Implement the following using PLA A(x,y,z)=∑(1,2,4,6); B(x,y,z)=∑(0,1,6,7);
C(x,y,z)=∑(2,6)
6. A combinational logic circuit is defined by the following function f1(a,b,c)=∑(0,1,6,7)
f2(a,b,c)=∑(2,3,5,7). Implement the circuit with a PAL having three inputs, three product
terms and two outputs.
7. The following messages have been coded in even parity hamming code and transmitted
through a noisy channel. Decode the messages, assuming that at most a single error has
occurred in each code word. (i) 1001001; (ii) 0111001
8. Write a detailed note on sequential programmable devices.
9. Design and implement 3-bit binary to gray code converter using PLA.
10. Illustrate with neat sketch and describe the categories of RAM.
11. Explain about error detection and correction using hamming codes.
12. Implement the following function using PAL F1(A,B,C)=∑(1,2,4,6);
F2(A,B,C)=∑(0,1,6,7); F3(A,B,C)=∑(1,2,3,5,7)
13. Design a combinational circuit using ROM that accepts a three bit binary number and
output is a binary number equal to the square of the input number.
14. The hamming code 101101101 is received. Correct it if any errors. There are four parity
bits and odd parity is used.
15. Define Memory and discuss the operation & types of RAM and ROM.
16. Elaborate the construction of sequential programmable devices in detail.
17. Explain ASIC in detail.
5.71 Digital Principles and System Design
18. Implement following function using PLA
Z1= ab‘d’e+a’b’c’d’e’+bc+de
Z2=a’c’e
Z3=bc+de+c’d’e+bd
Z4=a’c’e+ce using 5x8x4 PLA
19. Implement the two following Boolean function using 8x2 PROM.
F1(x,y,z) = F2(x,y,z)=
Discuss the operation of memory decoding and elaborate its application as address multiplexing
and coincident decoding circuit.
Appendix 2 9
REFERENCES
1. Morris Mano.M, Digital Design, Prentice Hall of India Pvt. Ltd., New Delhi, 2003.
2. John.M.Yarbrough, Digital Logic Applications and Design, Thomson-Vikas Publishing House,
New Delhi, 2002.
3. John.F.Wakerly, Digital Design Principles and Practices, 3rd Edition, Pearson Education, New
Delhi, 2002.
4. Thomas.L.Floyd, Digital Fundamentals, 8th Edition, Pearson Education, Inc, New Delhi, 2003.
5. Richard.S.Sandige, Modern Digital Design, McGRAW-HILL Publishing Company, 1990.
6. Charles.H.Roth, Jr, Fundamentals of Logic Design, 4th edition, Jaico Publishing House, 2002.
7. Donald.P.Leach, Albert Paul Malvino, Digital Principles and Applications, 5th Edition, Tata
McGraw-Hill, 2003.
8. Taub.H, Schilling.D, Digital Integrated Electronics, McGraw Hill, 1977.
9. Millman.J, Jalkias.C.C, Integrated Electronics, McGraw Hill, 1972.
10. Fletcher.W.I, An Engineering Approach to Digital Design, Prentice Hall, 1996.
11. Jain. R.P, Modern Digital Electronics, Tata McGraw Hill, 2003.
12. Sedha.R.S, Digital Electronics, S.Chand & Company Ltd, 2004.
13. Salivahanan.S, Arivazhagan.S, Digital Circuits and Design, Vikas Publishing House Pvt. Ltd.,
2004.
14. Bhasker.J, Verilog HDL Synthesis, BS Publications, 2001.
15. Millman.J, Taub.H, Pulse, Digital and Switching Waveforms, McGraww Hill, 1965.
16. Hall.D.V, Micro Processor and Digital Systems, McGraw Hill, 1980.
17. Gothmann.W.H, Digital Electronics-Introduction Theory and Practice, PHI, 1992.
18. Theodore, F, Bogart. JR, Introduction to Digital Circuits, McGraw-Hill, 1992.
19. Donald D. Givone, Digital Principles and Design, Tata McGraw-Hill, 2003.
20. National Semi-Conductor, Data Book, 1976.
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