FPGA Training

Phucvg – 249090
Ban Công nghệ Bán dẫn - Viettel

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 Vivado IDE
• Interactive design and analysis
• Timing analysis, connectivity, resource utilization,
timing constraint analysis, and entry
• RTL Development and analysis
• Elaboration of HDL
• Hierarchical exploration
• Schematic generation
• xsim simulation integration
• Synthesis and implementation
• I/O pin planning

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 Vivado Design Flow

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 Vivado Design Flow

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 Vivado GUI
• Started Page
• Quick Start:
• Previous projects can quickly open
• Links to create new or example project
• Tasks:
• IP management, hardware manager,
Vivado Store
• Learning Center:
• Documentation and Tutorials
• Quick Take Videos
• Release Notes Guide
• TCL console for command line access
• Recent Projects

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 Vivado GUI
• Five types of Projects:
• RTL project
• Front-to-back end
• Post-synthesis Project
• EDIF and NGC
• I/O planning Project
• For early pin testing
• No design source
• Imported Project
• Imports existing project from Synplify, XST or ISE
• Example Project

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 Vivado GUI
• Project creation flow:
• Defines the project name and location
• Select types of Project
• Add source file
• Design file in RTL (*.v, *.vhd, …)
• Post-synthesized netlist (*.edf,
*.edif, *.vm, …)
• IP file (*.xci)
• Add constraints files
• Top level and IP level
• create clocks, assign I/O pin, …
• Select target device or pre-defined
board
• Project Summary and Finish

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 Vivado GUI
• Project Navigator
• Used to manage sources, customize IP,
implement design flow, ...
• Flow Navigator
• Sources View
• Project Summary
• Give detail information of project:
Settings, Synthesis, Implementation,
Timing, Utilization, …
• Tcl Console, Messages, Log, Report,
Design Runs

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 Vivado GUI
• Flow Navigator
• Project Manager
• Setting
• Add source file, constraints files, simulation files, …
• Language Templates
• IP Catalog
• IP Integrator
• Create, open and generate block design
• Simulation
• Xsim simulator
• Behavioral, post-synthesis, post-implementation simulation
• RTL analysis
• Loads the elaborated RTL design

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 Vivado GUI
• Flow Navigator (continue)
• Synthesis
• Synthesis design
• Load synthesized design
• Implementation
• link, opt, power_opt, place, phys_opt and route design
• Load implemented design
• Program and Debug
• Generate Bitstream
• Open Hardware manager to program the FPGA

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 Vivado GUI
• Project Setting

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 Vivado Example
• Create new project
• Type: RTL Project
• Do not specify sources at this time
• Target device: Board kit ZCU102

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 Vivado Example
• Add source:
• Create Verilog file and edit
• Counter 8 bit
• Set as Top for top module file
• Create Testbench file and edit
• Used for simulation
• Set as Top for Testbench file

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 Vivado Example
• Simulation
• Run behavioral Simulation
• Check error and warning in
TCL Console
• Check waveform

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 Vivado Example
• RTL Analysis
• Elaborated Design is representation of
design before synthesis
• Interconnected netlist of hierarchical
and generic technology cells
• Instances of modules/entries
• Generic technology representation of
hardware components (AND, OR,
buffer, adder, …)
• Open Elaborated Design
• Check Schematic

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 Vivado Example
• RTL Analysis
• Elaborated Design is representation of
design before synthesis
• Interconnected netlist of hierarchical
and generic technology cells
• Instances of modules/entries
• Generic technology representation of
hardware components (AND, OR,
buffer, adder, …)
• Open Elaborated Design
• Check Schematic

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 Vivado Example
• RTL Analysis
• Elaborated Design is representation of
design before synthesis
• Interconnected netlist of hierarchical
and generic technology cells
• Instances of modules/entries
• Generic technology representation of
hardware components (AND, OR,
buffer, adder, …)
• Open Elaborated Design
• Check Schematic

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 Vivado Example
• RTL Analysis
• Elaborated Design is representation of
design before synthesis
• Interconnected netlist of hierarchical
and generic technology cells
• Instances of modules/entries
• Generic technology representation of
hardware components (AND, OR,
buffer, adder, …)
• Open Elaborated Design
• Check Schematic

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 Vivado Example
• RTL Analysis (continue)
• Report DRC (Design Rule Check)

• Need assignment for clk, rst, enable, counter[7:0]

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 Vivado Example
• Create clock for the design:
• Use IP Clock Wizard to create an HDL file that contains a clocking circuit customized to the user’s clocking
• IP Catalog
• Search: clock wizard

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 Vivado Example
• Create clock for the design (continue)
• Use IP Clock Wizard
• Customized IP
• Use user si570 sysclk for CLK_IN1
• Set frequency clk_out1 = 100MHz
• Uncheck reset and locked option

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 Vivado Example
• Create clock for the design (continue)
• Use IP Clock Wizard
• Generate Clock Wizard IP
• Integrate Clock Wizard IP to source file
by using IP’s instantiation template

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 Vivado Example
• RTL Analysis
• Schematic

• Report DRC

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 Vivado Example
• Assign I/O of the Design to Board using constraint file
• Create Constraint file and edit
• Set as Target Constraint File for top constraint file
• Use ZCU102 Evaluation Board User Guide to assign pin

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 Vivado Example
• Synthesis
• Synthesized Design is representation of the design after
synthesis
• Interconnected netlist of hierarchical and Basic
Elements (BELs)
• Instances of modules/entries
• BELS:
• LUTs, Flip-Flops, Carry chain, Mux
• Block Rams, DSP
• Clock elements: BUFG, MMCM, …
• I/O elements: IBUF, OBUF, …
• Run Synthesis
• Open Synthesized Design

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 Vivado Example
• Synthesis
• Schematic

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 Vivado Example
• Synthesis (continue)
• Schematic
• Clock Elements

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 Vivado Example
• Synthesis (continue)
• Schematic
• LUTs, FDCE

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 Vivado Example
• Synthesis (continue)
• Schematic
• LUTs, FDCE

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 Vivado Example
• Synthesis (continue)
• Schematic
• IBUF, OBUF

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 Vivado Example
• Synthesis (continue)
• Schematic
• IBUF, OBUF

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 Vivado Example
• Synthesis (continue)
• Schematic
• IBUF, OBUF

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 Vivado Example
• Synthesis (continue)
• Report Timing Summary
• Timing analysis

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 Vivado Example
• Synthesis (continue)
• Report Clock Networks

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 Vivado Example
• Synthesis (continue)
• Report Clock Interaction
• Use the clock interaction report to identify interactions between clock domains

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 Vivado Example
• Synthesis (continue)
• Report Methodology
• Helps to streamline the design process and achieve better QoR using the UltraFast Design Methodology

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 Vivado Example
• Synthesis (continue)
• Report DRC
• Design Rule Check

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 Vivado Example
• Synthesis (continue)
• Report Noise
• Perform a simultaneous switching noise (SSN) analysis of the current design
• Predict how output switching affects interface noise margins

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 Vivado Example
• Synthesis (continue)
• Report Utilization
• Analyze the utilization of the design with different resources

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 Vivado Example
• Synthesis (continue)
• Report Power
• Report details of power consumption based on the current operating conditions of the device and the switching
rates of the design

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 Vivado Example
• Implementation
• Implemented Design is representation of the
design after implementation
• Structurally similar to the Synthesizer Design
• Cells have locations, and nets are mapped to
specific routing channel
• Run Implementation
• Open Implemented Design

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 Vivado Example
• Implementation (continue)
• Report Timing Summary

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 Vivado Example
• Implementation (continue)
• Report Timing Summary

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 Vivado Example
• Program And Debug
• Generate Bitstream
• Open Hardware Manager
• Programming and/or debugging your design in hardware

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 Vivado Example
• Debugger
• VIO (Virtual Input/Output)
• A customizable core that can both monitor and drive internal FPGA signals in real time

• ILA (Integrated Logic Analyzer)

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 Vivado Example
• Debugger (continue)
• Customize IP and Generate IP
• VIO

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 Vivado Example
• Debugger (continue)
• Customize IP and Generate IP
• ILA

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 Vivado Example
• Debugger (continue)
• Generate VIO IP and ILA IP
• Integrate VIO IP and ILA IP to source file
by using IP’s instantiation template
• Rerun Synthesis
• Rerun Implementation
• Rerun Generate Bitstream

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 Vivado Example
• Implementation
• Schematic

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 Vivado Example
• Implementation (continue)
• Report Clock Network

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 Vivado Example
• Implementation (continue)
• Report Clock Interaction

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 Vivado Example
• Implementation (continue)
• Report Utilization
• Analyze the utilization of the design with different resources

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 Vivado Example
• Implementation (continue)
• Report Timing Summary

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 Vivado Example
• Device

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 Zynq-FPGA (SoC-FPGA) Example
• Vivado
• Create Block Design
• Add Zynq UltraScale+ MPSoC IP

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 Zynq-FPGA Example
• Vivado (continue)
• Customize Zynq IP
• Run Block Automation

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 Zynq-FPGA Example
• Vivado (continue)
• Customize Zynq IP

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 Zynq-FPGA Example
• Vivado (continue)
• Add and Customize IP AXI GPIO

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 Zynq-FPGA Example
• Vivado (continue)
• Add and Customize IP AXI GPIO

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 Zynq-FPGA Example
• Vivado (continue)
• Run Connection Automation

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 Zynq-FPGA Example
• Vivado (continue)
• Run Connection Automation

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 Zynq-FPGA Example
• Vivado (continue)
• Check Address Editor

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 Zynq-FPGA Example
• Vivado (continue)
• Create HDl Wrapper...

• Generate Bitstream

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 Zynq-FPGA Example
• Vivado (continue)
• Export file xsa
• File => Export => Export Hardware

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 Zynq-FPGA Example
• Vivado (continue)
• Export file xsa
• File => Export => Export Hardware

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 Zynq-FPGA Example
• Vitis
• Select a directory as workspace

• Create Application Project

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 Zynq-FPGA Example
• Vitis
• Select a directory as workspace

• Create Application Project

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 Zynq-FPGA Example
• Vitis
• Create a new platform from hardware XSA
• Select the *.xsa file generated from Vivado
• Target processor to create FSBL: psu_cortexa53_0

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 Zynq-FPGA Example
• Vitis
• Specify the application project name and its system project properties
• Select a domain for your project or create a new domain
• Select a template to create your project

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 Zynq-FPGA Example
• Vitis

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 Zynq-FPGA Example
• Vitis
• Platform Project

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 Zynq-FPGA Example
• Vitis
• Application Project

• Clean and Build Project

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 Zynq-FPGA Example
• Vitis
• Use the API function declared in file xil_io.h to read and write the register of AXI GPIO through AXI Bus
• Check and use address of IP defined in file xprameters.h
xil_io.h

xparameters.h

Address
assigned
to AXI
GPIO IP

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 Zynq-FPGA Example
• Vitis
• Check register address of AXI GPIO IP

• Edit source code

• Clean and Build Project

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 Zynq-FPGA Example
• Vitis
• Run As => Run Configurations => Single Application Debug
• Run (if board is connected to PC through USB-JTAG cable)

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 IP packager
• Create new project
• Type: RTL Project
• Do not specify sources at this time
• Target device: Board kit ZCU102
• Add source:
• Create Verilog file and edit
• Convert binary code to gray code
• Set as Top for top module file

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 IP packager
• Tool => Create and Package New IP…

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 IP packager
• Tool => Create and Package New IP…

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 IP packager
• Edit IP

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 IP packager
• Add IP repo
• Setting => IP => Add => Select the folder including the file IP-XACT (file *.xml)
• Use this IP in IP catalog or Block Design

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 AXI IP packager
• Tool => Create and Package New IP…

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 AXI IP packager
• Tool => Create and Package New IP…

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 AXI IP packager
• Add source file
• Add bin2gray.v to edit project
• Edit template file: *_S00_AXI.v

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 AXI IP packager
• Add source file
• Edit top module file

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 AXI IP packager
• Add source file
• Edit top module file

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 AXI IP packager
• Add source file
• Merge changes and Re-Package IP

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