rifle

Effitis brain of minecompute

It is a single chip which is capable

of processing data memory

It controls all components
210
Extend devices
St executes sequence of instructions

UP fetches decades executes the instructions

Internal architecture of MP is complex
 Etntemicopmassis
First Generation 1939 1954 Vaccum Tubes
Second Generation 1959 1959 Transistors
Third Generation 1959 1971 IC
Fourth Generation 1971 present Miaopuelessor

MP is scaling from 4004 to pentium 4

up is identified with Word size data
of

4 bit processors
INTEL 4004 INTEL 4090

8 bit processors

8008 8080 8085 MOTOROLA 6800 176800

16 bit processors
8086 8088 21109 28001 80186 80286

32 bit processors x86 64 bit processors

INTEL 80386,80387,10486 INTEL CORE2100

INTEL PENTIUM PENTIUM PRO CORE 17 15 13

PENTIUM I II II
DUAL CORE
 VaccumTube
RStrigger
Transistor

IC in your
Sim card

Microprocessors typically consist of

locationfor
temp storage

arithmetic
Acy performs
f
Arithmetic Logi Unit logical
operations

Timing canted circuit

keeps all other parts of sys reg ALO
memory4110 working together in

right time sequence

 Microprocessor

FI

O
Newiletsmareinto808 mf
 tITaepenaattnnct'and
gutqghi.it
units
y Bus gnterface Unit
Execution Unit
i
y
L

memory

writethe data to ports

Read data from pants

3 functional parts
Instruction Pointer IP

Segment Registers
Instruction Queue
 i
Keeps address of memory

instruction to be executed

Segment Registers hold the address of segments

inthe memory
In BIU they are of size 16bits

7
i
4 Stack segment Ss

Note 8086 does not workthe whole IMB memoryatany

given time However it works onlywithfour 64KB
segments within the whole IMB memory We can
position a particular 64 KB segment anywhere in
the memory
 Gustuene
The EU is supposed to decode or execute an

instruction
When EU is busy in decodingand executing an
instruction the BIU fetches up to 6 instruction
bytes for the next instructions
These bytes are called pre fetched bytes and
they are stored in a FIFO register set which is called
as a queue Timerequiredfor execution oftwo
K instructions without pipelining
Sequential F D E Fa Da Ez
phases
Time saved

BIV F Fa F

Her D E Da Ez Dz E
Overlapping
phases
Time requiredforexecutionof
two instr becauseofpipelining
 fontrol
Bus

Function
Register
Ax Accumulator Register
for arithmetic logic datatransferoperation
Base Register
BX also known used as addressregister
CX count Register
usedforloopcounter shift rotatebits
Dx DataRegister
used in division multiplication 1 0operations
 painter
IT
I 16 I
Accumulator

at

Data Titi
4
I

jjjpp.se Base Pointer

me
J
gym

extra segment
TG size
bit
ALU 16 bit size
Can perform Arithmetic Logical Operations
8 bit as well as 16 bit

Flagstaff distfthestatus upbased on

of
O the following values in theflagregister

I 8 iii is
TRAI
y

i
 9ft unused

AuxiliaryCary Zend

I
t.am flag Carey

3 controlflag
flag Direction Gy t

Trap
Controlunit
Timing of EU

Directs all internal operations also

responsiblefor generation of control signals
painMODE
1stup in 4o MIEDE

Pit
É
Collector
t
00
040

8
 MemorySegmentation

Total memory divided into4segments

ÉÉf
a
starting
paddies code segment 364k
bitsaved Address

Wigston II.IE
Ii zmBDSYa
gq5E
Data segment your
m.fm
Physical

gg.y y
Es
i Eta
ÉÉ7 segment Your

Data Bus 16b

Address Bus obitsf.i IIB 220Bytes

20
O II
Do
3
register
Faint
data
DS 222240
e.gg
BIT appends to of address
Base addness ofDS becomes22220 H
 Logical address
t2 001

valued d offset displacement

Calculate EA of memory BIU uses formula as

aim
e

The contents
of following registers are

i
IP 67214 Bx 78654 DI 12354 BP 78214

address bytesin CS DS Es SS

x
18619 101 offsetadd
tqfg.gs 61 h X
K t
19h
17830in
632in
IP 11 01
LA of IS CS 12980 11 IOB
nee
104 DI
ISH
PAGES ji
129801 t 12354 13BB

LA El ES DI
of
E 12984 1235 H
PA of Ss
stIISPBE
FI
16
Tide 678904
ssxente
678904 18214
31 FOBI
PA of DS
DS X 10N T SI BX SI is
not
given
DJ IoT By 0 10 OA lo A
11 OB 11 B
56785 75654 2 12 OC iz c
13 OD 13 D
4 OE 14 E
g M
15 OF 15 F
f
16 10
7
8 17 IT
9 18 12
13
 É
_stamina
instruction
size in leases CAC
operands are easily fetched
CI
e MOV CL 124 0001001000110100
g 15 BX
MOV BX 12344
2
Igistiantgaffenfusing register
instruction size decreases

operands can't be identified fetched directly

e
g MOV CL DL

MOV AX BX
3
I.is
jt ti aintiyspeibiediie
instruction
e
g nor earnp moist'd'atta
from4321minds
memorylocation offset into PA
I CL to 4321H
DS 43204
MOV Ix 432K
DS 42214
4 Indirect Addressing Mode

1 BE w tI j aema ei.I
Or any of the two index registers SI DI
ftp.detheoffstddnsstorthe
data type
eg nor cc
Bx I
b Regist Reativaddressing Mode
Operand address is calculated using 1 ofthe base

registers a 8 bit or a 16 bit displacement

eg Mov El
Bjp moves a byte from address
painted by 1244 in Dstocc

IYjuaindeqd.es iaseitgister gndergista

e
g Mov cc By ftp.mouesa bytefrom theaddress
CL
pointed by BX SI in DS to
Bets PA D BISH
SEH

1 Bogitigjitimatiiatiittisutsnaexresista
8 bit on 16 bit displacement

eg OU
TEIDE ZI
5
Yptidasaddissifeittnotspecipediatne instruction

eg STC sets the Cary Flay

CLD Clears the DirectionFlag
LC Clear the Cary Fey

Typesoffustructions

1 Data Transfer Instructions

2 Arithmetic Instructions
3 Instructions
Logical
4 Branch and Program Control Instructions

Movgustruction

see Copies the contents from

gtion Ima to detain
M R reflagged
R R
Me I
ÉÉ
MOV AX Bx Register
MOV
Axton Lad
MOV AXIM Direct MOV ALBY ReistIndinect
 Baserelative plus indexed Instruction
MOV AX BASIT 10
Format
3
o

p Th
Memo
BYt bits
Register

opcode field 6
RegistadinectionICD EEÉRII
IORIMERED
Fasidith q FEIT
IF MOV AL BI
REG SIRE TIEN DI
MOV
IF REG DESTINATION TIEN DI AYY
1 ASSEMBLY BINARY

2 BINARY ASSEMBLY
8 BEC h
8 BEC or 8 SBE
e.g Becky metadeeing

nogf.FM
tt assI
destination

i g
9 101 REG Bp
iii

Tnt yo
MOV EEG RAI
me to
ay MoD 00,01
 R N DS SI

PDF
Pg I
o
loop
I at

7 represents
MOD Function memory
moral

IIisement
extended displacement Mov Al 2247

10 Fit signed displacement now Al fattoood

no memory or
off IIisaregist
codes
displacement

Opcode Direction Width MoD Destination Source

I t 2 8 bits
3
8bits CASE OF
ONLY IN
mid
Eff
000
it
AL AX
pincode
000
addressing

Ds
16 bit

001 001 DS BX DI
o s
011 SS CBP DI

If
01 I

i
BL
Ds is 5
101 CH I 101 DS DI
110 110 ss Ep Pointer
I1 I DS BI

REG when MOD 11 REFER THIS TABLE 01 10

ONLY IF MOD 00
Destination
i REG 101
RLM too Sage novB
AnotherExample

1
810
ÉÉÉjÉÉ moral

IY.nybfgyfggi.fidness of 2ndoperand some

Estes it intstand destine

Unlike MeV LEA stores cmedaddiess staget

LEA
egistYEE
IOU BY
.Y.IE
BAI loads the

leads data stored at memorylocation

was

É DI BX

Q Can we use the Mov instruction to leadth offset

address insteadoftadingthedata
saaksmtndonmEEB
Xiggging.int
DFFSETworks with simple operands
s CazbetlIT
theyYhy
I
doweneed

not with DI LIST SI dictate

a list of 4bytes
451,85 102 20,10 with values 10,20 30 40

µ Data
Byte
 QA OAh
10 Of a hexadecimal

Io 0 1 I List
50 OXIE Ith Databyte
To 0 2 5 28h