Delta modulation and demodulation
Delta modulation and demodulation
Preliminary discussion
Despite its cryptic name, delta modulation (or –modulation) is a pulse
modulation scheme. Other examples of pulse modulation schemes that you may have
learnt more about using the Emona Telecoms-Trainer 101 include: pulse amplitude
modulation (PAM), pulse code modulation (PCM) and pulse-width modulation (PWM).
Delta modulation is like PWM in that it samples the analog input signal and
converts it directly into a serial stream of 1s and 0s without the need for a discrete
analog-to-digital conversion process. As such, delta modulation is also like PWM in that
the digital signal on the delta modulator’s digital output is a complex waveform that
includes a component at the message frequency.
Despite the similarity between delta modulation and PWM, it’s actually more
useful to describe its operation by comparing it to that of PCM. PCM samples the analog
input signal at fixed intervals and the samples are converted to fixed length sequential
binary numbers. Importantly, these binary numbers are directly (or, in some cases,
mathematically) proportional to the samples’ size.
Delta modulation effectively samples the analog input signal at regular fixed
intervals also. However, it then compares the present sample to the previous one and
outputs a 1-bit data word to indicate whether the new sample is smaller or larger than
the previous one.
The block diagram of a basic delta modulation system is shown in Figure 1 below.
+ D elt a mod.
I nput L imit er S ampler
signal out
-
Clock
I nt egr at or
Figure 1
As the delta modulation system in Figure 1 is a feedback loop, a mathematical
analysis of its operation is complicated and not attempted here. For the purpose of this
exercise, think of its operation in the following way.
The Sampler’s output (which is also the modulator’s output) is a bi-polar pulse
train. That is, instead of using 0V and 5V for the two logic states, positive and negative
voltages are used (eg ±2.5V). This is done so that the Integrator produces a ramp
voltage that changes direction in response to changes in logic state on the Sampler’s
output.
The Integrator’s output is subtracted from the message using a Summing circuit
to produce an error signal. The polarity of the error signal is a function of the relative
absolute voltages of the analog input (the message) and Integrator’s output. So, if the
Integrator’s output is greater than the message, the error signal is one polarity. If the
Integrator’s output is smaller than the message the error signal is the opposite polarity.
This allows the modulator to “know” which of the two signals is bigger (though this
information is captured only at the moment of sampling – see below) and this is essential
for achieving an Integrator output that approximates the message. Specifically, the
Integrator’s output “hunts” the analog input voltage and so its positive or negative going
ramp voltages produce a sawtooth waveform that tracks the message signal’s shape
(and this can be seen in Figure 2 on the next page).
The Limiter continuously converts the status of the relative sizes of the sawtooth
and message waveforms to a logic state. That is, one logic state indicates when the
sawtooth waveform is bigger than the message but reverses the moment that it is
smaller. The Sampler samples this information to convert it to clocked data and level
translates it to the corresponding positive or negative voltage (mentioned above).
Importantly, by definition, sampling is a periodic process and so the Sampler’s output
only reflects the relative sizes of the sawtooth and message waveforms at the sampling
moment.
Now let’s put this together. At switch-on, the Sampler’s output starts at either a
positive or negative voltage which commences a ramp on the Integrator’s output. Now,
suppose that the Integrator’s output is smaller than the message (a likely proposition)
but travelling in the same direction. This produces an error signal on the Summer’s
output with a particular polarity that is immediately converted to a particular logic state
by the Limiter. This logic state is captured on sampling and a decision is made by the
Sampler to maintain its output voltage. In other words, nothing changes.
These conditions are maintained for every sample until such time as the absolute
ramp voltage exceeds absolute message voltage (either because the ramp catches up
with the message or the message reverses direction). Once this happens, the polarity of
the error signal reverses which immediately causes the logic state on the Limiter’s
output to reverse. This new logic state is sampled and captured by the Sampler forcing to
reverse its output voltage, in turn causing the Integrator’s ramp to reverse direction.
These new conditions are now maintained for every sample until such time as the ramp
returns to an absolute voltage that is smaller than the absolute message voltage.
Figure 2
Finally, Figure 1 shows a discrete amplifier section between the Sampler and the
Integrator to control the loop gain. In practice the amplification can be incorporated into
the Integrator or Summer circuits.
Procedure
2. Locate the Adder module and set its G and g controls to the middle of their travel
(which should have the arrowheads pointing to the 12 o’clock position).
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC TIFIER S ER IA L TO
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 3
This set-up can be represented by the block diagram in Figure 4 on the next page.
The Master Signals module’s 2kHz SINE output models the message. The remaining
blocks implement the delta modulator.
2 kH z A X1 D elt a mod
S/ P out put
IN
B CL K
10 0 kH z
M ast er
RC L PF
S ignals
Figure 4
Relating this functional block diagram to the generic block diagram of a delta
modulator in the preliminary discussion (Figure 1), the Utilities module’s RC LPF models
the Integrator, the Adder module implements the Summer, the Utilities module’s
Comparator implements the Limiter, and the Serial-to-Parallel Converter module models
the Sampler. Loop gain is provided and controlled by the Adder module.
A few important points should be made here before you continue with the
experiment. First, as the Telecoms-Trainer 101 doesn’t have a Sampler, the Serial-to-
Parallel Converter module is used in its place. Although this module is designed primarily
for another purpose, it has a bipolar output and provides a clocked version of the data on
its input which are the two key functions required of the Sampler in a delta modulator.
Second, the modulator’s sampling and data rate correspond with a 50kHz clock and not
the 100kHz clock connected to the Serial-to-Parallel Converter module. This is because
the module sends the data to alternate outputs on every clock pulse so the data rate of
each output corresponds with a 50kHz clock. Third, the accumulated phase shifts around
the loop return a signal to the Adder module’s B input that is inverted relative to the
message. This facilitates the delta modulator’s requirement for a subtraction of the
Integrator’s output from the message using the Adder module (in the same way that
adding a negative number to a positive number results in a subtraction of the two).
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L T O
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 5
Note: Ensure that the scope’s Trigger Source control is set to the CH 1 (or INT)
position.
6. Adjust the scope’s Timebase control to view two or so cycles of the message.
N OIS E
GEN ER ATOR
0 dB
-6 dB
-2 0 dB
B U F FER
GA IN
IN OU T
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L T O
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 6
9. Use the Buffer module’s GAIN control to set its output to the same amplitude that
you measured at Step 7.
N OIS E
GEN ER ATOR
0 dB
-6 dB
-2 0 dB
B U FFER
GA IN
IN OU T
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L TO
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 7
The scope’s connections to the set-up can be represented by the block diagram in
Figure 8 on the next page. Notice that the Buffer module isn’t shown. This is because it’s
not contributing to the implementation of delta modulation. Instead, it’s being used to
invert the message so that it’s in phase with the Integrator’s output and the two signals
can be conveniently compared.
Figure 8
M essage
T o CH 1
A X1 D elt a mod
S/ P out put
2 kH z IN
B CL K
I nt egr at or ' s
out put
10 0 kH z
T o CH 2
11 Check that the scope’s two Vertical Attenuation controls are on the same setting
. (the 1V/div position is probably best).
Note: Remember that the RC LPF is being used to model the Integrator.
13 Overlay the two signals and you should see that the RC LPF’s output tracks the
. message in much the same way as theoretically predicted in Figure 2 (in the
preliminary discussion).
Note 2: If the RC LPF’s output isn’t similar to the Integrator’s output in Figure 2,
you’ll need to double-check your wiring.
N OIS E
GEN ER ATOR
0 dB
-6 dB
-2 0 dB
B U F FER
GA IN
IN OU T
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L T O
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 9
The new scope connection to the set-up can be represented by the block diagram in
Figure 10 on the next page.
A X1 D elt a mod
S/ P out put
2 kH z IN
T o CH 2
B CL K
10 0 kH z
Figure 10
Question 1
The digital signal on the delta modulator’s output is a serial stream of 1-bit
numbers. What do these numbers represent?
Question 2
The digital signal on the delta modulator’s output is a complex waveform (that is,
it’s made up of many sinewaves). State the frequency of one of these sinewaves.
Tip: No calculations are needed to answer this question.
Question 3
What’s the significance of this sinewave?
There are several factors that the affect closeness of the Integrator’s output to
the message and these include: the integration rate, the loop gain and the sampling
15 Return the scope’s Channel 2 input to the RC LPF’s output as shown in Figure 11
. below.
N OIS E
GEN ER ATOR
0 dB
-6 dB
-2 0 dB
B U F FER
GA IN
IN OU T
X DC
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L T O
1 0 0 kH z G P A R A L L EL
C OS
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L RC LP F
2 kH z g
S IN E
B GA +gB CLK X2
Figure 11
16 Set the scope’s two Input Coupling controls to the GND position.
.
17 Align the traces then return the Input Coupling controls to the AC position.
.
Note: This overlays the RC LPF’s output with the message so that their centre
lines are aligned.
18 Look closely at the two signals and note when the sawtooth waveform changes
. back and forth across the message and when it doesn’t.
Figure 12
19 Slowly increase the voltage gain of the Adder module’s B input by turning its g
. control clockwise and observe the effect on the RC LPF’s output.
Note: This increases the loop gain, in turn increasing the Integrator’s step size.
20. Stop increasing the voltage gain of the Adder module’s B input when its g control
is at the 3 o’clock position.
21 Reduce the Buffer module’s gain but stop the moment the Integrator’s sawtooth
. waveform crosses the message every time it changes direction.
Note: When the Buffer’s gain is the correct level, the two signals should look
similar to Figure 13 below.
Figure 13
Notice that the Integrator’s output now has several more “teeth” during the time
that the message signal changes quickly (at the sinewave’s zero crossing points) than it
did when the Integrator’s step size was smaller. With the bigger step size the Integrator’s
output can better track the message and so the slope overload is reduced.
However, a price has been paid. Notice now that the teeth in the Integrator’s
output at the time that the message signal changes slowly (at the sinewave’s peaks)
deviate further from the message on one side than they did previously. This is a
quantisation error problem which contributes to quantisation noise or granularity on the
demodulator’s output. Thus, obtaining an appropriate step size for the Integrator is a
compromise between overload distortion and granularity.
Question 4
Which is worst when the Integrator’s step size is relatively small?
Slope overload
distortion
Granularity
Question 5
Which is worst when the Integrator’s step size is relatively large?
Slope overload
distortion
Granularit
y
An alternative to managing the compromise between slope overload distortion
and granularity involves increasing the sampling rate. This allows the step size to be
The sampling rate can be increased here by replacing the Master Signals
module’s 100kHz DIGITAL output with the VCO module’s DIGITAL output and setting the
VCO module’s output frequency to maximum. However, as the VCO module’s output and
Master Signals module’s 2kHz SINE output are not synchronised, the Integrator’s output
signal will be unstable on the scope’s display rendering the improvement difficult to
observe. This can be overcome by capturing one sweep of the display using a storage
scope if one is available.
22. Locate the Tuneable Low-pass Filter module and set its Gain control to the middle
of its travel.
23. Turn the Tuneable Low-pass Filter module’s Cut-off Frequency Adjust control fully
clockwise.
X DC f C x1 0 0
1 0 0 kH z IN OU T Y DC kX Y
S IN E R EC T IFIER S ER IA L T O
1 0 0 kH z G P A R A L L EL
C OS fC
1 0 0 kH z A GN D S/ P
D IGITA L D IOD E & R C L P F
8 kH z
D IGITA L
2 kH z S ER IA L X1
D IGITA L GA IN
RC LP F
2 kH z g
S IN E
B GA +gB CLK X2 IN OU T
Figure 14
The entire set-up including the modification in Figure 14 can be represented by
the block diagram in Figure 15 below. The Tuneable Low-pass Filter module is used to
demodulate the delta signal and recover the 2kHz message.
A X1 Recover ed
S/ P message
2 kH z IN
T o CH 2
B CL K
10 0 kH z
Figure 15
25. Slowly reduce the Tuneable Low-pass Filter module’s cut-off frequency until the
message has been recovered (ignoring phase shift).
Question 6
What change to the delta modulator can be made to allow simpler filters to be
used by the demodulator without introducing more noise and distortion?