UNIT – V

Basic Processing Unit

Fundamental Concepts

 Processor fetches one instruction at a time and

perform the operation specified.
 Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
 Program Counter (PC)
 Instruction Register (IR)
Executing an Instruction
 Fetch Phase:
 Fetch the contents of the memory location pointed to by the
PC. The contents of this location are loaded into the IR (fetch
phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable, increment the
contents of the PC by 4 (fetch phase).
PC ← [PC] + 4

 Execution Phase:
 Carry out the actions specified by the instruction in the IR
 Processor Organization Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Constant 4 R0

Select MUX

Add
A B
Datapath
ALU Sub R  n - 1 
control ALU
lines
Carry-in
XOR TEMP

Fig. 1: Single-bus organization of the datapath inside a processor

Internal organization of the processor
 Data Path:
 The registers, ALU, and interconnecting bus are collectively called
the data path
 The arithmetic and logic unit (ALU) and all the registers are
interconnected via a single common bus.
 This bus is internal to the processor
 ALU
 Registers for temporary storage
 Various digital circuits for executing different micro-operations
(gates, MUX, decoders, counters)
 Internal path for movement of data between ALU and registers
 Driver circuits for transmitting signals to external units
 Receiver circuits for incoming signals from external units
PC:
 Keeps track of execution of a program
 Contains the memory address of the next instruction to be
fetched and executed.
MAR:
 Holds the address of the location to be accessed.
 I/P of MAR is connected to Internal bus and an O/p to external
bus.
MDR:
 Contains data to be written into or read out of the addressed
location.
 IT has 2 inputs and 2 Outputs.
 Data can be loaded into MDR either from memory bus or from
internal processor bus
The data and address lines are connected to the
internal bus via MDR and MAR
Registers:
 The processor registers R0 to Rn-1 vary considerably from one
processor to another.
 Registers are provided for general-purpose use by the
programmer.
 Special purpose registers-index & stack registers.
 Registers Y, Z & TEMP are temporary registers - used by the
processor during the execution of some instruction.
Multiplexer:
 Select either the output of the register Y or a constant value 4
to be provided as input A of the ALU.
 Constant 4 is used by the processor to increment the contents
of PC.
Operations in executing an Instruction

 To execute an instruction:
1. Transfer a word of data from one processor register to another
register or the ALU
2. Perform an arithmetic or a logic operation and store the result in a
processor register
3. Fetch the contents of a given memory location and load them into
a processor register e.g. mov [R1], R2
4. Store a word of data from a processor register into a given memory
location e.g. mov R1, [R2]
 Internal processor
b us

R i in

R i

R i out

1.Register Transfers
in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
1. Register Transfers (contd…)

 The input and output for register

Ri are connected to the bus via
switches controlled by the signals
Riin and Riout .
 Riin Is set to 1 – data available on
bus are loaded into Ri.
 Riout is set to1 – the contents of
register are placed on the bus.
 Riout Is set to 0 – the bus can be
used for transferring data from
other registers
Data transfer between two registers

EX:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by
setting R1𝑜𝑢𝑡=1. This places
the contents of R1 on the
processor bus.
2. Enable input of register R4 by
setting R4𝑖𝑛=1. This loads the
data from the processor bus
into register R4.
Register Transfers

 The control signals that govern a particular transfer are asserted at

the start of the clock cycle.
 In our example, R1𝑂𝑈𝑇 and R4in are set to 1
 The registers consist of edge-triggered flip-flops. Hence, at the
next active edge of the clock, the flip-flops that constitute R4 will
load the data present at their inputs.
 At the same time, the control signals R1𝑂𝑈𝑇 and R4in will return to 0
Register Transfers
 All operations and data transfers are controlled by the processor
clock. Bus

D Q
1
Q
Riout

Ri in
Clock

Fig. 3. Input and output gating for one register bit.

Register Transfers
 A two-input multiplexer is used to select the data applied to the input
of an edge-triggered D flip-flop
 When the control input Riin is equal to 1, the multiplexer selects the
data on the bus
 This data will be loaded into the flip-flop at the rising edge of the
clock
 When Riin is equal to 0, the multiplexer feeds back the value currently
stored in the flip-flop.
 The Q output of the flip-flop is connected to the bus via a tri-state
gate.
 When Ri0 is equal to 0, the gate's output is in the high-impedance
(electrically disconnected) state. This corresponds to the open-circuit
state of a switch
2.Performing an Arithmetic or Logic
Operation R i in
Internal processor
bus

Ri
 The ALU is a combinational circuit
that has no internal storage. R i out

 ALU gets the two operands from Y in

MUX and bus. The result is

temporarily stored in register Z. Y
Constant 4
 What is the sequence of
operations to add the contents ofSelect MUX

register R1 to those of R2 and A B

store the result in R3? ALU

1. R1out, Yin Z in

2. R2out, SelectY, Add, Zin Z

3. Zout, R3in
Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 2.Performing an Arithmetic or Logic
Operation
Step 1: Output of the register R1 and input of the register Y are
enabled, causing the contents of R1 to be transferred to Y.
Step 2: The multiplexer’s select signal is set to select Y causing
the multiplexer to gate the contents of register Y
to input A of the ALU. The contents of register R2 are gated onto the
bus and, hence, to input B.
Step 3: The output of the arithmetic operation is loaded into memory
The contents of Z are transferred to the destination register R3
Fetching a Word from Memory
 Address into MAR; issue Read operation; data into MDR.

Memory-b us Internal processor

data lines MDRoutE MDRout bus

MDR

MDRinE MDRin

Fig. 4. Connection and control signals for register MDR.

3.Fetching a Word from Memory

 The response time of each memory access varies (cache

miss, memory-mapped I/O,…).
 To accommodate this, the processor waits until it receives
an indication that the requested operation has been
completed (Memory-Function-Completed, MFC).
 Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
 Step 1 2 3

Timing Clock

MAR in

Assume MAR Address

is always available
on the address lines Read
of the memory bus.
MR

 Move (R1), R2 MDR inE

1. R1out, MARin, Read

Data
2. MDRinE, WMFC
MFC
3. MDRout, R2in

MDR out

Figure 7.5. Timing of a memory Read operation.

4.Storing a word in memory

 Address is loaded into MAR

 Data to be written loaded into MDR.
 Write command is issued.
 Example:Move R2,(R1)
1. R1out,MARin
2. R2out,MDRin,Write
3. MDRoutE, WMFC
Execution of a Complete Instruction

 Add (R3), R1
1. Fetch the instruction: Fetching an instruction is the process of reading an
operation code from memory and storing it in the instruction register (IR).
2. Fetch the first operand (the contents of the memory location pointed to by
R3)
3. Perform the addition
4. Load the result into R1
 Execution of a Complete Instruction
Internal processor
bus
Control signals

Add (R3), R1 PC

Instruction
Address
Step Action lines
decoder and
MAR control logic

Memory
bus
1 PCout , MAR in , Read, Select4,Add, Zin
MDR
Data
2 Zout , PCin , Y in , WMF C lines IR

3 MDR out , IR in Y

Constant 4 R0
4 R3out , MAR in , Read
Select
5 R1out , Y in , WMF C MUX

6 MDR out , SelectY, Add, Zin Add

A B
ALU Sub R n - 1
control
7 Zout , R1in , End lines
ALU
Carry-in
XOR TEMP

Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.

Figure 7.1. Single-bus organization of the datapath inside a processor.
Execution of Branch Instructions

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Add, Z in
5 Z out , PC in , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Execution of Branch Instructions

 A branch instruction replaces the contents of PC with the branch target

address, which is usually obtained by adding an offset X given in the branch
instruction.
 The offset X is usually the difference between the branch target address and
the address immediately following the branch instruction.
 UnConditional branch
Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

• Allow the contents of two

PC

Re gister
different registers to be
file
accessed simultaneously and
Constant 4
have their contents placed on
buses A and B.
MUX

ALU R

B
• Allow the data on bus C to
be loaded into a third register
during the same clock cycle.
Instruction
decoder

IR
• Incrementer unit.
MDR
• ALU simply passes one of
MAR its two input operands
unmodified to bus C
Memory b us Address
data lines lines

 control signal: R=A or R=B

Figure 7.8. Three-b us or g anization of the datapath.
 General purpose registers are combined into a single block called
registers.
 3 ports,2 output ports –access two different registers and have their
contents on buses A and B
 Third port allows data on bus c during same clock cycle.
 Bus A & B are used to transfer the source operands to A & B inputs of the
ALU.
 ALU operation is performed.
 The result is transferred to the destination over the bus C.
 ALU may simply pass one of its 2 input operands
unmodified to bus C.
 The ALU control signals for such an operation R=A
or R=B.
 Incrementer unit is used to increment the PC by 4.
 Using the incrementer eliminates the need to add
the constant value 4 to the PC using the main ALU.
 The source for the constant 4 at the ALU input
multiplexer can be used to increment other address
such as loadmultiple & storemultiple
Multiple-Bus Organization
 Add R4, R5, R6

Step Action

1 PC out, R=B, MAR in , Read, IncPC

2 WMF C
3 MDR outB , R=B, IR in

4 R4 outA , R5 outB , SelectA, Add, R6 in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
 Step 1:The contents of PC are passed
through the ALU using R=B control signal & loaded into MAR to start a
memory read operation
At the same time PC is incrementer by 4
 Step 2:The processor waits for MFC
 Step 3: Loads the data ,received into MDR ,then transfers them to IR.
 Step 4: The execution phase of the instruction requires only one control
step to complete.
Exercise
Internal processor
bus

Control signals

 What is the control sequence for PC

execution of the instruction Instruction
Address
decoder and
Add R1, R2 lines
MAR control logic

including the instruction fetch

Memory
bus

phase? (Assume single bus Data

MDR

architecture) lines IR

Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines
Carry-in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

Overview

 To execute instructions, the processor must have some means of generating

the control signals needed in the proper sequence.
 Two categories: hardwired control and microprogrammed control
 Hardwired system can operate at high speed; but with little flexibility.
Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Generating Zin

 Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Generating End
 End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

A Complete Processor

Instruction Integer Floating-point

unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System b
us

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor

.
Microprogrammed Control
 Control signals are generated by a program similar to machine
language programs.
 Control Word (CW); microroutine; microinstruction: Textbook page430

MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

Overview

Textbook page 421

Step Action

1 PCout , MAR in , Read, Select4,Add, Zin

2 Zout , PCin , Y in , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1in , End

Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.

Basic organization of a
microprogrammed control unit
 Control store
Starting
IR address
generator One function
cannot be carried
out by this simple
organization.

Clock PC

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

Conditional branch
 The previous organization cannot handle the situation when the
control unit is required to check the status of the condition codes or
external inputs to choose between alternative courses of action.
 Use conditional branch microinstruction.

Address Microinstruction

0 PC out , MAR in , Read, Select4, Add, Z in

1 Z out , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Z out , PC in , End

Figure 7.17. Microroutine for the instruction Branch<0.

Microprogrammed Control
External
inputs
Starting and
branch address Condition
IR codes
generator

Clock PC

Control
store CW

Fig. 18 organization of the control unit to allow

conditional branching in the microprogram.
Thank You