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AXI_Protocols_Overview_July9_2020

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9 views

AXI_Protocols_Overview_July9_2020

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kaya46003
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Section : AXI Protocol Overview

1. AXI Introduction
2. Types of AXI Bus
3. Channels on AXI
4. Main general AXI IP
5. AXI Interconnect
6. Example Design: VIVADO
AXI Protocols-Overview
Popular SoC Bus Protocol
• Core Connect
• PLB/OPB/..
• Whishbone
• Used by OpenCores IPs
• AXI
• Advanced Extensible Interface, developed by ARM
• Xilinx use ARM on its all of the FPGA Chip architecture
• While many Xilinx SoC chip also consists of “ARM CPU Core”.
• And Xilinx also have own Microblaze Architecture which also works on AXI
interface protocol.
Reference: Mohammad Sadri
What is AXI?
• AXI is part of ARM AMBA, a family of micro controller buses first
introduced in 1996. The first version of AXI was first included in AMBA
3.0, released in 2003. AMBA 4.0, released in 2010, includes the
second version of AXI, AXI4.
• There are three types of AXI4 interfaces:
➢AXI4—for high-performance memory-mapped requirements.
➢AXI4-Lite—for simple, low-throughput memory-mapped communication (for
example, to and from control and status registers).
➢AXI4-Stream—for high-speed streaming data.

Reference: UG1037, Xilinx


Summary of AXI4 Benefits

Reference: UG1037, Xilinx


AXI Channels
Both AXI4 and AXI4-Lite interfaces
consist of five different channels:
• Read Address Channel
• Write Address Channel
• Read Data Channel
• Write Data Channel
• Write Response Channel

Reference: UG761, Xilinx


AXI Master vs. Slave
• AXI master and salve IP transact the data from one point in hardware
to another point.
• Master IP can initiates the transaction
• Salve IP respond to the initiated transaction

Reference: Mohammad Sadri


Control Channels with AXI Master and Slave
1. Read Address Channel
2. Write Address Channel
3. Read Data Channel
4. Write Data Channel
5. Write Response Channel

Reference: Mohammad Sadri


AXI Infrastructure IP:
Some Examples:
• AXI Interconnect
1.
• Processing 2.
System Reset 3.
• AXI GPIO 4.

5.
6.

Reference: UG1037, Xilinx


AXI Interconnect IP
1. AXI Interconnect help us to
➢ Can connect different number
of master and different number
of slave IP or ports of IP.
➢ Example1 : Connect one AXI
Master with multiple Slaves
➢ Example 2: Multiple AXI Master
need to communicate to one
AXI Slave.
2. It can also
❖Do Width conversion
❖AXI3 to AXI4 conversion
❖Clock Domain Transformation
❖Provide register slice, FIFOs

Reference: UG761, Xilinx


AXI Interconnect Core Use Models
• The AXI Interconnect IP core connects one or more AXI memory-
mapped master devices to one or more memory-mapped slave
devices.
• The following subsections describe the possible use cases:
1. Conversion Only
2. N-to-1 Interconnect
3. 1-to-N Interconnect
4. N-to-M Interconnect (Sparse Crossbar Mode)
Example of AXI Interconnect in connection

Reference: Mohammad Sadri


How the communication via interconnect work?
Addressing the Slave IP
Port/Registers
General Rules:
1. The address of one
slave should not
overlap to another one.
2. Address region must be
separated completely.

Reference: Mohammad Sadri


Address Decoding by AXI Interconnect
• For sending and receiving data to/from master/slave

Reference: Mohammad Sadri


Address Alignment Rule
• This rule is for interconnecting
high address range based
address with the low address
range based address.
• We cant give address to new
IP from the last address of
another one.

• Though VIVADO have “Auto


Assign” option on Address
Editor which works very well.
How AXI Interconnect allow to change clock
domains?
• Example➔

Reference: Mohammadsadegh Sadri


Hierarchical AXI Interconnects
❖This type of connection needed when:
1. There is limited number of AXI interconnect port
limited. When number of slave is larger then the
AXI interconnect ports.
2. Creating the design expandable when needed, so
that the number of slaves can be added on the
design later when needed.
3. With separate cluster, we can also create
“Hierarchy of group of IP” which help to group and
work on design.

❖In the design, the AXI Master 1 and DMA can access
any of AXI slave IP while CPU2 can only access UART,
ETH and USB.

Reference: Mohammadsadegh Sadri


AXI SmartConnect
• AXI SmartConnect is a drop-in replacement for the AXI Interconnect
v2 core.
• AXI SmartConnect is more tightly integrated into the Vivado design
environment to automatically configure and adapt to connected AXI
master and slave IP with minimal user intervention.
AXI Data Transfer Methods
Memory Mapped vs Stream Data Transfer
• Number of channel on Memory
Mapped are 5 [3 channel for write
transaction and 2 channel for read
transaction].
• Number of channel needed for
Streaming mode is just 1.
Figure: Memory Mapped
Interface

Figure: Streaming Channel details


Figure: Streaming Interface
Reference: Mohammadsadegh Sadri
Thank You!

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