Chapter 1
Chapter 1
Unit I
By
Ms. Ruchira Muchhal
REGISTER TRANSFER AND MICROOPERATIONS
• Register Transfer
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers
MICROOPERATIONS (1)
R f(R, R)
- Microoperations set
MAR
– Registers may also be represented showing the bits of data they contain
DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
REGISTER TRANSFER
R2 R1
– In this case the contents of register R2 are copied (loaded) into register R1
– A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are not altered by
copying (loading) them to R2
REGISTER TRANSFER
R3 R5
– the data lines from the source register (R5) to the destination register
(R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action
CONTROL FUNCTIONS
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called
a control function
– If the signal is 1, the action takes place
• This is represented as:
P: R2 R1
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function
and the destination register (Reason: Page 51)
• Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS
P: R3 R5, MAR IR
Bus lines
B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
TRANSFER FROM BUS TO A DESTINATION REGISTER
Bus lines
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D0 D1 D2 D 3
Select z 2x4 E (enable)
w
Decoder
S0 0
Select 1
S1 2
Enable 3
BUS TRANSFER IN RTL
M
Memory Read
AR
unit
Write
M[MAR] R1
C4 S3 S2 S1 S0
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
FA FA FA FA
C4 S3 S2 S1 S0
Binary Incrementer A 3 A 2 A 1 A 0 1
x y x y x y x y
H A H A H A H A
C S C S C S C S
C 4 S 3 S 2 S 1 S 0
ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1
Ai
0
Bi
1
4X1 Fi
MUX
2
3 Select
S1
S0
Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F=AB OR
1 0 F=AB XOR
1 1 F = A’ Complement
References
• M. Morris Mano, Computer System Architecture, 3rd Edition, Pearson.
• William Stallings, Computer Organization and Architecture, 8th Edition, Pearson.