MCA 103 Operating System
Unit I
Register Transfer Language and
Microinstructions
By
Ms. Ruchira Muchhal
REGISTER TRANSFER AND MICROOPERATIONS
• Register Transfer Language
• Register Transfer
• Bus and Memory Transfers
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
• Arithmetic Logic Shift Unit
SIMPLE DIGITAL SYSTEMS
• Combinational and sequential circuits can be used to create simple digital
systems.
• These are the low-level building blocks of a digital computer.
• Simple digital systems are frequently characterized in terms of
– the registers they contain, and
– the operations that they perform.
• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers
MICROOPERATIONS (1)
• The operations on the data in registers are called
microoperations.
• The functions built into registers are examples of
microoperations
– Shift
– Load
– Clear
– Increment
– …
MICROOPERATION (2)
An elementary operation performed (during one clock pulse),
on the information stored in one or more registers
Registers ALU 1 clock cycle
(R) (f)
R f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
ORGANIZATION OF A DIGITAL SYSTEM
• Definition of the (internal) organization of a computer
- Set of registers and their functions
- Microoperations set
Set of allowable microoperations provided
by the organization of the computer
- Control signals that initiate the sequence of
microoperations (to perform the functions)
REGISTER TRANSFER LEVEL
• Viewing a computer, or any digital system, in this way is
called the register transfer level
• This is because we’re focusing on
– The system’s registers
– The data transformations in them, and
– The data transfers between them.
REGISTER TRANSFER LANGUAGE
• Rather than specifying a digital system in words, a specific
notation is used, register transfer language
• For any function of the computer, the register transfer language
can be used to describe the (sequence of) microoperations
• Register transfer language
– A symbolic language
– A convenient tool for describing the internal organization of digital
computers
– Can also be used to facilitate the design process of digital systems.
DESIGNATION OF REGISTERS
• Registers are designated by capital letters, sometimes
followed by numbers (e.g., A, R13, IR)
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register
• Registers and their contents can be viewed and represented in
various ways
– A register can be viewed as a single entity:
MAR
– Registers may also be represented showing the bits of data they contain
DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register
• Common ways of drawing the block diagram of a register
Register Showing individual bits
R1 7 6 5 4 3 2 1 0
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
REGISTER TRANSFER
• Copying the contents of one register to another is a register
transfer
• A register transfer is indicated as
R2 R1
– In this case the contents of register R2 are copied (loaded) into register R1
– A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are not altered by
copying (loading) them to R2
REGISTER TRANSFER
• A register transfer such as
R3 R5
Implies that the digital system has
– the data lines from the source register (R5) to the destination register
(R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action
CONTROL FUNCTIONS
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called
a control function
– If the signal is 1, the action takes place
• This is represented as:
P: R2 R1
Which means “if P = 1, then load the contents of register R1 into
register R2”, i.e., if (P = 1) then (R2 R1)
HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS
Implementation of controlled transfer
P: R2 R1
Block diagram Control P Load
R2 Clock
Circuit
n
R1
Timing diagram t t+1
Clock
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function
and the destination register (Reason: Page 51)
• Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS
• If two or more operations are to occur simultaneously,
they are separated with commas
P: R3 R5, MAR IR
• Here, if the control function P = 1, load the contents of R5
into R3, and at the same time (clock), load the contents of
register IR into register MAR
BASIC SYMBOLS FOR REGISTER TRANSFERS
Symbols Description Examples
Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow Denotes transfer of information R2 R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A B, B A
CONNECTING REGISTRS
• In a digital system with many registers, it is impractical to
have data and control lines to directly allow each register to
be loaded with the contents of every possible other registers
• To completely connect n registers n(n-1) lines
• O(n2) cost
– This is not a realistic approach to use in a large digital system
• Instead, take a different approach
• Have one centralized set of circuits for data transfer – the bus
• Have control circuits to select which register is the source,
and which is the destination
BUS AND BUS TRANSFER
Bus is a path(of a group of wires) over which information is transferred, from any
of several sources to any of several destinations.
From a register to bus: BUS R
Register A Register B Register C Register D
Bus lines
Register A Register B Register C Register D
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
TRANSFER FROM BUS TO A DESTINATION REGISTER
Bus lines
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D0 D1 D2 D 3
Select z 2x4 E (enable)
w
Decoder
Three-State Bus Buffers
Output Y=A if C=1
Normal input A
High-impedence if C=0
Control input C
Bus line with three-state buffers
Bus line for bit 0
A0
B0
C0
D0
S0 0
Select 1
S1 2
Enable 3
BUS TRANSFER IN RTL
• Depending on whether the bus is to be mentioned
explicitly or not, register transfer can be indicated as
either
R2 R1
or
BUS R1, R2 BUS
• In the former case the bus is implicit, but in the latter, it is
explicitly indicated
MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits
containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2m words. It needs the
following
– n data input lines data input lines
– n data output lines
n
– m address lines
– A Read control line address lines
– A Write control line m RAM
Read
unit
Write
n
data output lines
MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as a device,
M.
• Since it contains multiple locations, we must specify which
address in memory we will be using
• This is done by indexing memory references
• Memory is usually accessed in computer systems by putting
the desired address in a special register, the Memory Address
Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get sent to
the memory unit’s address lines
M
Memory Read
AR
unit
Write
Data out Data in
MEMORY READ
• To read a value from a location in memory and load it into a register,
the register transfer language notation looks like this:
R1 M[MAR]
• This causes the following to occur
– The contents of the MAR get sent to the memory address lines
– A Read (= 1) gets sent to the memory unit
– The contents of the specified address are put on the memory’s output data
lines
– These get sent over the bus to be loaded into register R1
MEMORY WRITE
• To write a value from a register to a location in memory looks
like this in register transfer language:
M[MAR] R1
• This causes the following to occur
– The contents of the MAR get sent to the memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus to the data input lines
of the memory
– The values get loaded into the specified address in the memory
SUMMARY OF R. TRANSFER MICROOPERATIONS
A B Transfer content of reg. B into reg. A
AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A constant Transfer a binary constant into reg. A
ABUS R1, Transfer content of R1 into bus A and, at the same time,
R2 ABUS transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR M Memory read operation: transfers content of
memory word specified by AR into DR
M DR Memory write operation: transfers content of
DR into memory word specified by AR
MICROOPERATIONS
• Computer system microoperations are of four types:
- Register transfer microoperations
- Arithmetic microoperations
- Logic microoperations
- Shift microoperations
ARITHMETIC MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement
• The additional arithmetic microoperations are
– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …
Summary of Typical Arithmetic Micro-Operations
R3 R1 + R2 Contents of R1 plus R2 transferred to R3
R3 R1 - R2 Contents of R1 minus R2 transferred to R3
R2 R2’ Complement the contents of R2
R2 R2’+ 1 2's complement the contents of R2 (negate)
R3 R1 + R2’+ 1 subtraction
R1 R1 + 1 Increment
R1 R1 - 1 Decrement
BINARY ADDER / SUBTRACTOR / INCREMENTER
B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder
FA C3 FA C2 FA C1 FA
C0
C4 S3 S2 S1 S0
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
FA FA FA FA
C4 S3 S2 S1 S0
Binary Incrementer A 3 A 2 A 1 A 0 1
x y x y x y x y
H A H A H A H A
C S C S C S C S
C 4 S 3 S 2 S 1 S 0
ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1
S1 S0 Cin Y Output Microoperation
0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
LOGIC MICROOPERATIONS
• Specify binary operations on the strings of bits in registers
– Logic microoperations are bit-wise operations, i.e., they work on the individual
bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can
be defined over two binary input variables
A B F0 F1 F2 … F13 F14 F15
0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1
• However, most systems only implement four of these
– AND (), OR (), XOR (), Complement/NOT
• The others can be created from combination of these
LIST OF LOGIC MICROOPERATIONS
• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
- n binary vars → 2 2 n functions
• Truth tables for 16 functions of 2 variables and the
corresponding 16 logic micro-operations
x 0011 Boolean Micro-
Name
y 0101 Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F A B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F A’ B
0101 F5 = y FB Transfer B
0110 F6 = x y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F A B)’ NOR
1001 F9 = (x y)' F (A B)’ Exclusive-NOR
1010 F10 = y' F B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F A’ Complement A
1101 F13 = x' + y F A’ B
1110 F14 = (xy)' F (A B)’ NAND
1111 F15 = 1 F all 1's Set to all 1's
What are Logic Micro-Operations?
Logic Microoperations are a set of binary operations
that are performed on registers that contain strings of
bits. These operations treat each bit of the register
separately and consider them as binary variables. As a
result, there are 16 different logic operations that could
be performed. These are-
HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS
Ai
0
Bi
1
4X1 Fi
MUX
2
3 Select
S1
S0
Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F=AB OR
1 0 F=AB XOR
1 1 F = A’ Complement
References
• M. Morris Mano, Computer System Architecture, 3rd Edition, Pearson.
• William Stallings, Computer Organization and Architecture, 8th Edition, Pearson.