Scribd
Upload
4 views

VLSI-Assignment

Important assignment for vlsi final year

Uploaded by

mohammedsufyaan440
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
4 views

VLSI-Assignment

Important assignment for vlsi final year

Uploaded by

mohammedsufyaan440
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 11

Department of Electronics & Communication Engineering

Bengaluru

Assignment I
“Carry Adders (skip , save & select)”
Subject: Advanced VLSI [21EC71]

Submitted by: Submitted to:


Hemang Gehlot Ms. Gouri M S
1TJ21EC005 Assistant Professor
Department of ECE, TJIT Department of ECE, TJIT
1. AIM : Carry-skip adder (also Ripple carry adder).

THEORY : A Carry Skip Adder is an adder that improves the performance of addition by
skipping over the carry propagation for certain conditions. It is typically used in situations
where the addition of numbers involves several bits, and the carry propagation takes too long.
By skipping certain carry propagations, the overall speed of the addition is improved.
 Carry Skip Adder works by dividing the bit addition into segments and attempting to
skip over the carry propagation when it is not necessary.
 The key idea is to use a condition (like a generate signal) to check if the carry for a
group of bits will propagate. If no carry propagation occurs, the adder skips over that
group and performs the addition on the next group of bits.
 It is a combination of a Ripple Carry Adder and Carry Lookahead Adder where carry
is "skipped" if the condition is met, speeding up the addition process.

CIRCUIT :
CODE :
module carry_skip_adder_4bit(A [3:0], B[3:0], Cin, Sum[3:0], Cout );
wire [3:0] G;
wire [3:0] P;
wire [3:0] C;

assign G = A & B;
assign P = A ^ B;
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & C[1]);
assign C[3] = G[2] | (P[2] & C[2]);
assign Sum = P ^ C[3:0];
assign Cout = G[3] | (P[3] & C[3]);
endmodule

Testbench:
module tb_carry_skip_adder_4bit;
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire [3:0] Sum;
wire Cout;

carry_skip_adder_4bit uut (.A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout );

initial begin
$monitor("A = %b, B = %b, Cin = %b, Sum = %b, Cout = %b", A, B, Cin, Sum, Cout);
A = 4'b0011; B = 4'b0101; Cin = 1'b0; #10;
A = 4'b1100; B = 4'b1010; Cin = 1'b0; #10;
A = 4'b1111; B = 4'b1111; Cin = 1'b1; #10;
A = 4'b1001; B = 4'b0110; Cin = 1'b1; #10;
A = 4'b0000; B = 4'b0000; Cin = 1'b0; #10;
A = 4'b1111; B = 4'b0001; Cin = 1'b0; #10;

$finish;
end
endmodule

OUTPUT :

2. AIM: Carry-save adder (CSA).


THEORY: A 4-bit Carry Save Adder is a type of adder used to add multiple operands in
parallel without immediately propagating the carry, which reduces the time needed to
compute the final result.
Working Principle:
 A 4-bit CSA takes two 4-bit numbers and generates a partial sum and carry.
 Each bit pair from the operands is added with the carry from the previous stage, and
instead of propagating the carry, the carry is "saved" to be processed in the next
stage.
 The final sum and carry are generated in additional stages of computation.
4-Bit Carry Save Adder (CSA) Logic:
For two 4-bit operands A=A3A2A1A0A = A_3 A_2 A_1 A_0A=A3A2A1A0 and
B=B3B2B1B0B = B_3 B_2 B_1 B_0B=B3B2B1B0, the adder computes:
1. Partial Sum (S) for each bit:

o S0=A0⊕B0S_0 = A_0 \oplus B_0S0=A0⊕B0

o S1=A1⊕B1S_1 = A_1 \oplus B_1S1=A1⊕B1

o S2=A2⊕B2S_2 = A_2 \oplus B_2S2=A2⊕B2

o S3=A3⊕B3S_3 = A_3 \oplus B_3S3=A3⊕B3

2. Carry (C) for each bit:


o C0=A0&B0C_0 = A_0 \& B_0C0=A0&B0

o C1=A1&B1C_1 = A_1 \& B_1C1=A1&B1

o C2=A2&B2C_2 = A_2 \& B_2C2=A2&B2

o C3=A3&B3C_3 = A_3 \& B_3C3=A3&B3

Then, these results are combined in further stages (if multiple operands are involved).
CIRCUIT:
CODE:
module fulladder(input a,b,cin,output sum,carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule

module CSA(input [3:0] x,y,z,output [4:0] s,output cout);


wire [3:0] c1,s1,c2;
fulladder fa_inst10(x[0],y[0],z[0],s1[0],c1[0]);
fulladder fa_inst11(x[1],y[1],z[1],s1[1],c1[1]);
fulladder fa_inst12(x[2],y[2],z[2],s1[2],c1[2]);
fulladder fa_inst13(x[3],y[3],z[3],s1[3],c1[3]);
fulladder fa_inst20(s1[1],c1[0],1'b0,s[1],c2[1]);
fulladder fa_inst21(s1[2],c1[1],c2[1],s[2],c2[2]);
fulladder fa_inst22(s1[3],c1[2],c2[2],s[3],c2[3]);
fulladder fa_inst23(1'b0,c1[3],c2[3],s[4],cout);
assign s[0] = s1[0];
endmodule

Testbench:
module tb_adder;
reg [3:0] x,y,z;
wire [4:0] s;
wire cout;
integer i,j,k,error;
CSA uut(x,y,z,s,cout);
initial begin
x = 0;
y = 0;
z = 0;
error = 0;
for(i=0;i<16;i=i+1) begin
for(j=0;j<16;j=j+1) begin
for(k=0;k<16;k=k+1) begin
x = i;
y = j;
z = k;
#10;
if({cout,s} != (i+j+k))
error <= error + 1;
end
end
end
end
endmodule

OUTPUT:
3. AIM: Carry select Adder

THEORY: The Carry Select Adder is a fast adder used for binary addition, designed to speed
up the computation by reducing the time delay of carry propagation.The Carry Select Adder
works by calculating the sum of two binary numbers in parallel, considering both possible
values of the carry-in: 0 and 1. It then selects the correct sum and carry-out based on the
actual carry-in.
The key idea behind the carry select adder is to use multiple Ripple Carry Adders to calculate
the sum of the two input numbers for both possible carry-in values, and then select the correct
result using multiplexers.

CIRCUIT:
CODE:
module fulladder(input a,b,cin,output sum,carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule

module carry_select_adder(input [3:0] A,B,input cin,output [3:0] S,output cout);


wire [3:0] temp0,temp1,carry0,carry1;
fulladder fa00(A[0],B[0],1'b0,temp0[0],carry0[0]);
fulladder fa01(A[1],B[1],carry0[0],temp0[1],carry0[1]);
fulladder fa02(A[2],B[2],carry0[1],temp0[2],carry0[2]);
fulladder fa03(A[3],B[3],carry0[2],temp0[3],carry0[3]);
fulladder fa10(A[0],B[0],1'b1,temp1[0],carry1[0]);
fulladder fa11(A[1],B[1],carry1[0],temp1[1],carry1[1]);
fulladder fa12(A[2],B[2],carry1[1],temp1[2],carry1[2]);
fulladder fa13(A[3],B[3],carry1[2],temp1[3],carry1[3]);
multiplexer2 mux_carry(carry0[3],carry1[3],cin,cout);
multiplexer2 mux_sum0(temp0[0],temp1[0],cin,S[0]);
multiplexer2 mux_sum1(temp0[1],temp1[1],cin,S[1]);
multiplexer2 mux_sum2(temp0[2],temp1[2],cin,S[2]);
multiplexer2 mux_sum3(temp0[3],temp1[3],cin,S[3]);
endmodule

module multiplexer2(input i0,i1,sel,output reg bitout);


always@(i0,i1,sel)
begin
if(sel == 0)
bitout = i0;
else
bitout = i1;
end
endmodule

Testbench:
module tb_adder;
reg [3:0] A,B;
reg cin;
wire [3:0] S;
wire cout;
integer i,j,error;
carry_select_adder uut(.A(A),.B(B),.cin(cin),.S(S),.cout(cout));
initial begin
A = 0;
B = 0;
error = 0;
cin = 0;
for(i=0;i<16;i=i+1) begin
for(j=0;j<16;j=j+1) begin
A = i;
B = j;
#10;
if({cout,S} != (i+j))
error <= error + 1;
end
end
cin = 1;
for(i=0;i<16;i=i+1) begin
for(j=0;j<16;j=j+1) begin
A = i;
B = j;
#10;
if({cout,S} != (i+j+1))
error <= error + 1;
end
end
end
endmodule

OUTPUT:

You might also like