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Lec2

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Markhor Gaming
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8 views

Lec2

Uploaded by

Markhor Gaming
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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// gate level

module gate (o, a, b);


// I/O ports

and a1 (o, a, b);


endmodule

// da flow level
module dflow (o, a, b);
// I/O ports

assign o = a && b; // && is logical


// !, ~, + , -, %, /, *, **,

endmodule

module dff (d, q, clk, rst);

output reg q;

always @(negedge clk or posedge rst)


begin
if (rst)
q =0;
else
q =d;
end

endmodule

module ha (s, c, a, b);

// IO
assign s = a ^ b;
assign c = a & b;
endmodule

module fa (s, c, a, b, cin);

// IO
wire s1, c1, c2;
ha ha1 (s1_reg, c1, a, b);
ha ha2 (.a(s1_reg), .b(cin), .s(s) , .c(c2) );

assign c = c1 || c2;
endmodule
// Instantiate the module
led instance_name (
.out(out),
.in(in)
);

module mux (out, a, b, c, d, sel)


// IO
input [1:0] sel;
always@(*)
case(sel)
2'b00: out =a ;
2'b01: out =b ;
2'b10: out =c ;
2'b11: out =d ;
default: out = 1'b0 ;
endcase
endmodule

module inst_rom #(parameter N=32, DEPTH=32)


(input [N-1:0]address, output reg [N-1:0] instruction);

reg [N-1:0] memory [DEPTH-1:0];

initial begin
memory [0] = 32'b000000_00001_00010_00011_000000_00010; //add $1, $2,
$3
memory [1] = 32'd45;
memory [2] = 32'd6969;
end

always@(address)
instruction <= memory [address];

endmodule

module data_mem #(parameter N=32, DEPTH=32)


(input [N-1:0]address, input [N-1:0]data_in, output reg [N-1:0] data_out, input
clk, input we);

reg [N-1:0] memory [DEPTH-1:0];

initial begin
memory [0] = 32'b000000_00001_00010_00011_000000_00010; //add $1, $2,
$3
memory [1] = 32'd45;
memory [2] = 32'd6969;
end

//always@(address)
// data <= memory [address];
assign data_out = memory [address];

always @(posedge clk)


if (we)
memory [address] <= data_in;

endmodule

data_mem mem1 (.data_in(din), .... );

//// Hints for reg file

module reg_file (rdata1, rdata2, rs1, rs2, rd, write_data, rst, clk, mem_write);

reg [N-1:0] memory [DEPTH-1:0];

assign rdata1 = memory [rs1]; // 32 bits


assign rdata2 = memory [rs2]; // 32 bits

always @(posedge clk)


if (mem_write)
memory [rd] <= write_data; // N=32 bits

endcase

module PC (jump_address, pc_out, jump, clk, rst);

parameter N = 32;

input clk, rst, jump;


input [N-1:0] jump_address;
output reg [N-1:0] pc_out;

always @(posedge clk or posedge rst)


begin
if (rst)
pc_out <=0;
else begin
if (jump) pc_out <= jump_address;

else
pc_out <= pc_out + 1;
end // ???
end

endmodule

data 16 bit variable ... signed

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