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7 views

Ack

Uploaded by

Nandhini Sundaram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ACKNOWLEDGEMENT

First and foremost, we would like to thank our guide, Mrs. S. Jayanthi,
Assistant Professor, Department of Electronics and Communication
Engineering, for the valuable guidance and advice. She inspired us greatly to
work on this project. Her ability to inspire us has made an enormous
contribution to our project.

We thank our project coordinator Dr. N. Saranya, Assistant Professor,


Department of Electronics and Communication Engineering, for her endless
support and guidance.

We would like to take this opportunity to express our deepest gratitude


to Dr. P. Raja, Professor and Head of the Department, Electronics and
Communication Engineering, for giving us valuable suggestions. He has always
been a source of inspiration and encouragement towards the project.

We would like to take this opportunity to thank our respected Director


cum Principal, Dr. V. S. K. Venkatachalapathy and our Management for
providing us the best ambience to complete this project.

We would like to thank all the Electronics and Communication


Engineering Department Teaching Staff and Technical Staff for their support to
complete this project.

Finally, for the motivation and assistance in completing this mission, an


honorable mention goes to our families and friends. Without their support we
would have faced many challenges while doing this project.
ABSTRACT

The Semiconductor technology advances into the nanometer scale


conventional CMOS technology faces significant challenges including
increased power leakage, sub-threshold current, and reduced efficiency.
Static Random Access Memory (SRAM) a critical component in modern
semiconductor circuits is particularly affected by these limitations due to
its substantial area utilization and power consumption. These
shortcomings hinder the designing and analyzing of SRAM memory cell
using Carbon Nanotube Field Effect Transistors (CNTFETs) which offer
promising advantages over traditional CMOS technology. The SRAM
cell architecture leverages the superior gate control and reduced leakage
properties of CNTFETs to achieve enhanced performance metrics. The
mitigating issues such as sub-threshold leakage and gate-induced barrier
lowering while improving power efficiency and stability. The design aims
to provide a robust and high-performance solution suitable for modern
applications that demand low power and high-speed memory. The
implementation involves designing the SRAM cell using a 32 nm
CNTFET technology node. The HSPICE simulations will be performed
to validate the design under varying operating conditions such as a supply
voltage of 0.9V and different temperature ranges. The parameters
including power consumption, delay, and stability metrics like Read
Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM)
will be evaluated. The proposed design leverages the potential of
CNTFET technology to address the limitations of CMOS in memory cell
design offering a more power-efficient, speed and stable alternative.

Keywords: CNTFETs, SRAM, Low Power Design, Sub-threshold


Leakage, Read/Write Stability, HSPICE Simulations, nanometer
Technology Node.

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