ACKNOWLEDGEMENT

First and foremost, we would like to thank our guide, Mrs. S. Jayanthi,
Assistant Professor, Department of Electronics and Communication
Engineering, for the valuable guidance and advice. She inspired us greatly to
work on this project. Her ability to inspire us has made an enormous
contribution to our project.

We thank our project coordinator Dr. N. Saranya, Assistant Professor,

Department of Electronics and Communication Engineering, for her endless
support and guidance.

We would like to take this opportunity to express our deepest gratitude

to Dr. P. Raja, Professor and Head of the Department, Electronics and
Communication Engineering, for giving us valuable suggestions. He has always
been a source of inspiration and encouragement towards the project.

We would like to take this opportunity to thank our respected Director

cum Principal, Dr. V. S. K. Venkatachalapathy and our Management for
providing us the best ambience to complete this project.

We would like to thank all the Electronics and Communication

Engineering Department Teaching Staff and Technical Staff for their support to
complete this project.

Finally, for the motivation and assistance in completing this mission, an

honorable mention goes to our families and friends. Without their support we
would have faced many challenges while doing this project.
 ABSTRACT
The Semiconductor technology advances into the nanometer scale
conventional CMOS technology faces significant challenges including
increased power leakage, sub-threshold current, and reduced efficiency.
Static Random Access Memory (SRAM) a critical component in modern
semiconductor circuits is particularly affected by these limitations due to
its substantial area utilization and power consumption. These
shortcomings hinder the designing and analyzing of SRAM memory cell
using Carbon Nanotube Field Effect Transistors (CNTFETs) which offer
promising advantages over traditional CMOS technology. The SRAM
cell architecture leverages the superior gate control and reduced leakage
properties of CNTFETs to achieve enhanced performance metrics. The
mitigating issues such as sub-threshold leakage and gate-induced barrier
lowering while improving power efficiency and stability. The design
aims to provide a robust and high-performance solution suitable for
modern applications that demand low power and high-speed memory.
The implementation involves designing the SRAM cell using a 32 nm
CNTFET technology node. The HSPICE simulations will be performed
to validate the design under varying operating conditions such as a supply
voltage of 0.9V and different temperature ranges. The parameters
including power consumption, delay, and stability metrics like Read
Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM)
will be evaluated. The proposed design leverages the potential of
CNTFET technology to address the limitations of CMOS in memory cell
design offering a more power-efficient, speed and stable alternative.

Keywords: CNTFETs, SRAM, Low Power Design, Sub-threshold

Leakage, Read/Write Stability, HSPICE Simulations, nanometer
Technology Node.
 TABLE OF CONTENTS

CHAPTER PAGE
TITLE
NO. NO.
ABSTRACT
i
LIST OF FIGURES
ii
LIST OF TABLES
iii
LIST OF ABBREVIATIONS
iv

1 INTRODUCTION 1
1.1. OVERVIEW OF MEMORY 1
1.2. STATIC RANDOM ACCESS
MEMORY 2
(SRAM)
1.2.1. Features of Static Random Access
3
Memory
1.3. DYNAMIC RANDOM ACCESS
4
MEMORY (DRAM)
1.3.1. Applications of DRAM 5
1.4. CMOS- BASED SRAM CELL 6
1.5. CHALLENGES WITH
CONVENTIONAL CMOS 7
TECHNOLOGY
1.6. CARBON NANOTUBE FIELD EFFECT
8
TRANSISTOR (CNTFETs)
1.6.1. Structure of CNTFETs 10
1.6.2. Types of CNTFETs 11
1.6.3. Features of CNTFET 12
1.7. SCOPE OF THE PROJECT 14
1.8. OBJECTIVES OF THE PROJECT 14
1.9. ORGANIZATION OF THE THESIS 15
2 LITERATURE SURVEY 16
2.1. OVERVIEW 16
2.2. LITERATURE SURVEY 16
2.3. SUMMARY 26
3 PROPOSED SYSTEM 28
3.1. OVERVIEW OF THE PROPOSED
28
SYSTEM
3.2. EXISTING DESIGN OF FINFET BASED
28
SRAM
3.3. OPERATION OF FINFET BASED I2T
30
SRAM
3.3.1. Hold/Idle mode of Operation 30
3.3.2. Write Operation 31
3.3.3. Read Operation 32
3.5. ADVANTAGES OF THE CIRCUIT 34
3.6. SUMMARY 35

REFERENCES 36
 LIST OF FIGURES

FIGURE PAGE
TITLE
NO. NO.

1
1.1 Digital Memory
2
1.2 Static Random Access Memory Chip
4
1.3 Basic 6T Binary SRAM Cell
5
1.4 Dynamic Random Access Memory (DRAM)
6
1.5 CMOS based SRAM circuit
Carbon Nanotube Field Effect Transistor 9
1.6
(CNTFET)
Structure of Carbon Nanotube Field Effect 10
1.7
Transistor
Classification of Carbon Nanotube Field Effect 12
1.8
Transistors
29
3.1 Design of proposed 12T SRAM cell
31
3.2 Hold/Idle operation of 12T SRAM cell
32
3.3 Write operation of 12T SRAM
34
3.4 Read operation of 12T SRAM cell
LIST OFABBREVIATIONS

BL Bit Line
BLB Complementary Bit Line
CNT Carbon Nanotube
CNTFET Carbon Nanotube Field Effect Transistor
CMOS Complementary Metal-Oxide Semiconductor
DIBL Drain-Induced Barrier Lowering
DRAM Dynamic Random Access Memory
DVS Dynamic Voltage Scaling
EDP Energy Delay Product
FF Fast-Fast Process Corner
IoT Internet of Things
INDEP Independent Gate Control
LN Logic Node
MOSFET Metal-Oxide Semiconductor Field Effect Transistor
NMOS N-type Metal-Oxide Semiconductor
PDP Power Delay Product
PMOS P-type Metal-Oxide Semiconductor
RAM Random Access Memory
RBL Read Bit Line
RSNM Read Static Noise Margin
ROM Read-Only Memory
Schottky-Barrier Carbon Nanotube Field Effect
SB-CNTFET
Transistor
SNM Static Noise Margin
Simulation Program with Integrated Circuit
SPICE
Emphasis
SRAM Static Random Access Memory
SS Slow-Slow Process Corner
TT Typical-Typical Process Corner
VMIN Minimum Voltage
WL Word Line