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Modernize Design Pawan 4Yrs+

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0% found this document useful (0 votes)
10 views2 pages

Modernize Design Pawan 4Yrs+

Uploaded by

prasad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Pawan

Professional Summary:

I am working in VLSI Front end Design for 3+ Years To work in a creative and
challenging environment using cutting edge technologies, where I could constantly
learn and successfully deliver solutions to problems and provide an opportunity for my
professional advancement.

PROFESSIONAL OUTLINE:

 Design flow from RTL design to Netlist generation, validation and Timing
Analysis include Compile, Lint, CDC, Synthesis, LEC, Power Artist.
 Expertise in RTL Coding using VerilogHDL & VHDL.
 Developing RTL designs for ADC, DAC and Ethernet.
 Work Experience of STA, Timing Analysis, Timing Closure.
 Conducting system study; coordinating with team members for System
Design &integration and Application Maintenance.
 Delivering and implementing the project as per scheduled deadlines and
extending post-implementation and maintenance support.

Technical Skills:

 Hardware Languages : Verilog HDL, System verilog.


 Front End Design Tools : VCS, Design Compiler, Formality, Power Artist,
Spyglass, Xilinx ISE 14.7
 Industry Standard Protocols: AMBA AHB, APB.

Professional Experience:
Design Engineer, Modernize chip solutions From Nov 2021
Education:
B.Tech (ECE) Aryabhatta Knowledge University, Patna CGPA : 7.48/10

PROJECT DETAILS

IP Logic Design &SOC Integration

 Contributed to architecture/micro-architecture of Network On Chips (NOCs) for


subsystems of vision accelerator based SOCs. RTL design of Intel Ultra Path
Interconnect (UPI) Logical PHY IPs, ensuring timing convergence for multiple
operating speeds
 Analyzed NOC Performance, traffic congestion and routing algorithms to achieve
target bandwidth and latency for point to point and parallel workloads.
Automated NOC performance optimizations (buffer size, link/virtual-channel
width computations etc.)
 Identified timing critical paths in NOC using logic synthesis and static timing
analysis. Modified micro-architecture to reduce combinational logic depth by
adding pipeline stages to reduce path delays and met higher target frequencies to
enhance bandwidth
 Proposed a two NOC shared Re-Order Buffer (ROB) architecture where IP master
bridges on the first NOC share ROBs on a second NOC interfacing to DDR memory
controllers, this reduced the overall NOC area by 19 % while delivering equivalent
performance
 Performed Lint, CDC, LEC/FEV checks and logical/timing ECOs using
Cadence/Synopsys tools for all NOC subsystems

Digital Design Engineer | Ethernet PHY Team


 Developed architecture and micro-architecture for digital coarse calibration IPs of
mixed signal PLL synthesizer based chipsets. Proposed a lookup table based
calibration scheme with memory binary search to reduce successive re-calibration
time by tenfold
 Designed a ‘processor-like’ frequency ramp generator IP that generates
programmable frequency up/down-chirps; developed a custom instruction set,
dedicated arithmetic unit, controller to fetch instructions from memory and a
debug monitor for the IP
 Devised digital Design For Testability (DFT) architecture for ethernet PHY IPs to
ensure high test coverage, accelerated yield ramp and improved silicon quality
and reliability. Generated test patterns for various fault (stuck at, transition fault,
IDDQ) models
 Developed digital micro-architecture for a 10baseT/100baseTX ethernet PHY IP,
supported device bringup, validation and debug of scan/functional vectors on
automated test equipment. Contributed to automating assertion based verification
flow

PERSONAL ATTRIBUTES

Hard working & Punctual


Good Analytical Skills
Ability to work with minimal resources

PERSONAL DETAILS

DOB : 15th, November 1992


Gender : Male
Nationality : Indian
Language : English, Hindi, Bhojpuri
Address : Thori Pandey Pur, Murar, Buxar, Bihar, Pincode - 802127

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